diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/indirect-interleaves')
50 files changed, 2189 insertions, 2243 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp index 4dfe46446e..e4bfc0f6e4 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8.hpp @@ -170,7 +170,6 @@ void interleave_block<4, 16, VLType::None, false>( "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "12:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "x20", "x21", "x22", "x23" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp index 56ca49a36e..23800edf20 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_s8_s8_summing.hpp @@ -210,8 +210,8 @@ void interleave_block<4, 16, VLType::None, true>( "sadalp v22.4s, v26.8h\n" "sadalp v21.4s, v25.8h\n" "addp v24.4s, v24.4s, v23.4s\n" - "addp v23.4s, v22.4s, v21.4s\n" - "addp v24.4s, v24.4s, v23.4s\n" + "addp v16.4s, v22.4s, v21.4s\n" + "addp v24.4s, v24.4s, v16.4s\n" "add v24.4s, v24.4s, v20.4s\n" "str q24, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp index 4c7bb71fb2..15545c24db 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave4_block16_u8_u8_summing.hpp @@ -210,8 +210,8 @@ void interleave_block<4, 16, VLType::None, true>( "uadalp v22.4s, v26.8h\n" "uadalp v21.4s, v25.8h\n" "addp v24.4s, v24.4s, v23.4s\n" - "addp v23.4s, v22.4s, v21.4s\n" - "addp v24.4s, v24.4s, v23.4s\n" + "addp v16.4s, v22.4s, v21.4s\n" + "addp v24.4s, v24.4s, v16.4s\n" "add v24.4s, v24.4s, v20.4s\n" "str q24, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp index 2ba2aa854a..b900c330b7 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_bf16_fp32.hpp @@ -80,36 +80,36 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d28, [x28], #0x8\n" - "ldr d27, [x27], #0x8\n" - "shll v28.4s, v28.4h, #0x10\n" + "ldr d27, [x28], #0x8\n" + "ldr d26, [x27], #0x8\n" "shll v27.4s, v27.4h, #0x10\n" + "shll v26.4s, v26.4h, #0x10\n" "ldr d22, [x26], #0x8\n" "ldr d21, [x25], #0x8\n" "shll v22.4s, v22.4h, #0x10\n" "shll v21.4s, v21.4h, #0x10\n" - "ldr d26, [x24], #0x8\n" + "ldr d20, [x24], #0x8\n" "ldr d25, [x23], #0x8\n" - "shll v26.4s, v26.4h, #0x10\n" - "shll v25.4s, v25.4h, #0x10\n" - "ldr d20, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" "shll v20.4s, v20.4h, #0x10\n" + "shll v25.4s, v25.4h, #0x10\n" + "ldr d19, [x22], #0x8\n" + "ldr d16, [x21], #0x8\n" "shll v19.4s, v19.4h, #0x10\n" - "zip1 v24.4s, v28.4s, v22.4s\n" - "zip1 v23.4s, v27.4s, v21.4s\n" + "shll v16.4s, v16.4h, #0x10\n" + "zip1 v24.4s, v27.4s, v22.4s\n" + "zip1 v23.4s, v26.4s, v21.4s\n" "subs %x[width], %x[width], #0x4\n" "cmp %x[width], #0x4\n" - "zip1 v18.4s, v26.4s, v20.4s\n" - "zip1 v17.4s, v25.4s, v19.4s\n" + "zip1 v18.4s, v20.4s, v19.4s\n" + "zip1 v17.4s, v25.4s, v16.4s\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" + "zip2 v22.4s, v27.4s, v22.4s\n" + "zip2 v21.4s, v26.4s, v21.4s\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip2 v20.4s, v26.4s, v20.4s\n" - "zip2 v19.4s, v25.4s, v19.4s\n" + "zip2 v20.4s, v20.4s, v19.4s\n" + "zip2 v19.4s, v25.4s, v16.4s\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" "prfm pldl1keep, [x22, #0x70]\n" @@ -138,71 +138,70 @@ void interleave_block<8, 1, VLType::None, false>( "ldr s28, [x28], #0x4\n" "ldr s27, [x27], #0x4\n" "mov x20, #0x2\n" - "ldr s22, [x26], #0x4\n" - "ldr s21, [x25], #0x4\n" - "ldr s26, [x24], #0x4\n" - "ldr s25, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" + "ldr s26, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" + "ldr s24, [x24], #0x4\n" + "ldr s23, [x23], #0x4\n" + "ldr s22, [x22], #0x4\n" + "ldr s21, [x21], #0x4\n" "tbz %x[width], #0, 5f\n" "ld1 { v28.h }[2], [x28]\n" "ld1 { v27.h }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v22.h }[2], [x26]\n" - "ld1 { v21.h }[2], [x25]\n" - "ld1 { v26.h }[2], [x24]\n" - "ld1 { v25.h }[2], [x23]\n" - "ld1 { v20.h }[2], [x22]\n" - "ld1 { v19.h }[2], [x21]\n" + "ld1 { v26.h }[2], [x26]\n" + "ld1 { v25.h }[2], [x25]\n" + "ld1 { v24.h }[2], [x24]\n" + "ld1 { v23.h }[2], [x23]\n" + "ld1 { v22.h }[2], [x22]\n" + "ld1 { v21.h }[2], [x21]\n" "b 5f\n" "4:" // odd_loads_1_0 "ldr h28, [x28, #0x0]\n" "ldr h27, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h22, [x26, #0x0]\n" - "ldr h21, [x25, #0x0]\n" - "ldr h26, [x24, #0x0]\n" - "ldr h25, [x23, #0x0]\n" - "ldr h20, [x22, #0x0]\n" - "ldr h19, [x21, #0x0]\n" + "ldr h26, [x26, #0x0]\n" + "ldr h25, [x25, #0x0]\n" + "ldr h24, [x24, #0x0]\n" + "ldr h23, [x23, #0x0]\n" + "ldr h22, [x22, #0x0]\n" + "ldr h21, [x21, #0x0]\n" "5:" // Odd load end "shll v28.4s, v28.4h, #0x10\n" "shll v27.4s, v27.4h, #0x10\n" "subs x20, x20, #0x1\n" - "shll v22.4s, v22.4h, #0x10\n" - "shll v21.4s, v21.4h, #0x10\n" "shll v26.4s, v26.4h, #0x10\n" "shll v25.4s, v25.4h, #0x10\n" - "shll v20.4s, v20.4h, #0x10\n" - "shll v19.4s, v19.4h, #0x10\n" - "zip1 v24.4s, v28.4s, v22.4s\n" - "zip1 v23.4s, v27.4s, v21.4s\n" - "zip1 v18.4s, v26.4s, v20.4s\n" - "zip1 v17.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v24.4s, v23.4s\n" + "shll v24.4s, v24.4h, #0x10\n" + "shll v23.4s, v23.4h, #0x10\n" + "shll v22.4s, v22.4h, #0x10\n" + "shll v21.4s, v21.4h, #0x10\n" + "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v19.4s, v27.4s, v25.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" "subs x20, x20, #0x1\n" - "zip2 v16.4s, v24.4s, v23.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v17.4s, v18.4s, v17.4s\n" - "str q17, [%x[out_ptr], #0x10]\n" + "zip2 v16.4s, v18.4s, v17.4s\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" - "zip2 v20.4s, v26.4s, v20.4s\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v22.4s, v21.4s\n" + "zip2 v19.4s, v28.4s, v26.4s\n" + "zip2 v16.4s, v27.4s, v25.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v19.4s, v16.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v20.4s, v19.4s\n" - "str q18, [%x[out_ptr], #0x10]\n" + "zip1 v16.4s, v18.4s, v17.4s\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp index f55c2be4a4..e54b3b9f41 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp16.hpp @@ -80,33 +80,33 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q25, [x28], #0x10\n" - "ldr q30, [x27], #0x10\n" + "ldr q27, [x27], #0x10\n" "subs %x[width], %x[width], #0x8\n" "cmp %x[width], #0x8\n" - "ldr q29, [x26], #0x10\n" - "ldr q28, [x25], #0x10\n" + "ldr q26, [x26], #0x10\n" + "ldr q24, [x25], #0x10\n" "ldr q21, [x24], #0x10\n" - "ldr q27, [x23], #0x10\n" + "ldr q20, [x23], #0x10\n" "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v26.8h, v30.8h, v27.8h\n" - "ldr q20, [x22], #0x10\n" - "ldr q22, [x21], #0x10\n" - "zip1 v19.8h, v29.8h, v20.8h\n" - "zip1 v18.8h, v28.8h, v22.8h\n" + "zip1 v22.8h, v27.8h, v20.8h\n" + "ldr q17, [x22], #0x10\n" + "ldr q16, [x21], #0x10\n" + "zip1 v19.8h, v26.8h, v17.8h\n" + "zip1 v18.8h, v24.8h, v16.8h\n" "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v21.8h, v26.8h, v17.8h\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v22.8h\n" + "zip2 v20.8h, v27.8h, v20.8h\n" + "zip2 v16.8h, v24.8h, v16.8h\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" "zip1 v24.8h, v23.8h, v19.8h\n" - "zip1 v17.8h, v26.8h, v18.8h\n" + "zip1 v17.8h, v22.8h, v18.8h\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" "zip2 v23.8h, v23.8h, v19.8h\n" - "zip2 v19.8h, v26.8h, v18.8h\n" + "zip2 v19.8h, v22.8h, v18.8h\n" "prfm pldl1keep, [x22, #0x70]\n" "prfm pldl1keep, [x21, #0x70]\n" "zip1 v22.8h, v25.8h, v21.8h\n" @@ -134,132 +134,131 @@ void interleave_block<8, 1, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr d25, [x28], #0x8\n" - "ldr d30, [x27], #0x8\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" - "ldr d21, [x24], #0x8\n" - "ldr d27, [x23], #0x8\n" - "ldr d20, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d30, [x28], #0x8\n" + "ldr d29, [x27], #0x8\n" + "ldr d28, [x26], #0x8\n" + "ldr d27, [x25], #0x8\n" + "ldr d26, [x24], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ldr d24, [x22], #0x8\n" + "ldr d23, [x21], #0x8\n" "tbz %x[width], #1, 4f\n" - "ld1 { v25.s }[2], [x28], #0x4\n" - "ld1 { v30.s }[2], [x27], #0x4\n" + "ld1 { v30.s }[2], [x28], #0x4\n" + "ld1 { v29.s }[2], [x27], #0x4\n" "mov x20, #0x6\n" - "ld1 { v29.s }[2], [x26], #0x4\n" - "ld1 { v28.s }[2], [x25], #0x4\n" - "ld1 { v21.s }[2], [x24], #0x4\n" - "ld1 { v27.s }[2], [x23], #0x4\n" - "ld1 { v20.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v28.s }[2], [x26], #0x4\n" + "ld1 { v27.s }[2], [x25], #0x4\n" + "ld1 { v26.s }[2], [x24], #0x4\n" + "ld1 { v25.s }[2], [x23], #0x4\n" + "ld1 { v24.s }[2], [x22], #0x4\n" + "ld1 { v23.s }[2], [x21], #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.h }[6], [x28]\n" - "ld1 { v30.h }[6], [x27]\n" + "ld1 { v30.h }[6], [x28]\n" + "ld1 { v29.h }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.h }[6], [x26]\n" - "ld1 { v28.h }[6], [x25]\n" - "ld1 { v21.h }[6], [x24]\n" - "ld1 { v27.h }[6], [x23]\n" - "ld1 { v20.h }[6], [x22]\n" - "ld1 { v22.h }[6], [x21]\n" + "ld1 { v28.h }[6], [x26]\n" + "ld1 { v27.h }[6], [x25]\n" + "ld1 { v26.h }[6], [x24]\n" + "ld1 { v25.h }[6], [x23]\n" + "ld1 { v24.h }[6], [x22]\n" + "ld1 { v23.h }[6], [x21]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.h }[4], [x28]\n" - "ld1 { v30.h }[4], [x27]\n" + "ld1 { v30.h }[4], [x28]\n" + "ld1 { v29.h }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.h }[4], [x26]\n" - "ld1 { v28.h }[4], [x25]\n" - "ld1 { v21.h }[4], [x24]\n" - "ld1 { v27.h }[4], [x23]\n" - "ld1 { v20.h }[4], [x22]\n" - "ld1 { v22.h }[4], [x21]\n" + "ld1 { v28.h }[4], [x26]\n" + "ld1 { v27.h }[4], [x25]\n" + "ld1 { v26.h }[4], [x24]\n" + "ld1 { v25.h }[4], [x23]\n" + "ld1 { v24.h }[4], [x22]\n" + "ld1 { v23.h }[4], [x21]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr s25, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" "mov x20, #0x2\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s21, [x24], #0x4\n" - "ldr s27, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s24, [x22], #0x4\n" + "ldr s23, [x21], #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.h }[2], [x28]\n" - "ld1 { v30.h }[2], [x27]\n" + "ld1 { v30.h }[2], [x28]\n" + "ld1 { v29.h }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.h }[2], [x26]\n" - "ld1 { v28.h }[2], [x25]\n" - "ld1 { v21.h }[2], [x24]\n" - "ld1 { v27.h }[2], [x23]\n" - "ld1 { v20.h }[2], [x22]\n" - "ld1 { v22.h }[2], [x21]\n" + "ld1 { v28.h }[2], [x26]\n" + "ld1 { v27.h }[2], [x25]\n" + "ld1 { v26.h }[2], [x24]\n" + "ld1 { v25.h }[2], [x23]\n" + "ld1 { v24.h }[2], [x22]\n" + "ld1 { v23.h }[2], [x21]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr h25, [x28, #0x0]\n" - "ldr h30, [x27, #0x0]\n" + "ldr h30, [x28, #0x0]\n" + "ldr h29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h29, [x26, #0x0]\n" - "ldr h28, [x25, #0x0]\n" - "ldr h21, [x24, #0x0]\n" - "ldr h27, [x23, #0x0]\n" - "ldr h20, [x22, #0x0]\n" - "ldr h22, [x21, #0x0]\n" + "ldr h28, [x26, #0x0]\n" + "ldr h27, [x25, #0x0]\n" + "ldr h26, [x24, #0x0]\n" + "ldr h25, [x23, #0x0]\n" + "ldr h24, [x22, #0x0]\n" + "ldr h23, [x21, #0x0]\n" "7:" // Odd load end - "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v19.8h, v29.8h, v20.8h\n" + "zip1 v22.8h, v30.8h, v26.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip1 v26.8h, v30.8h, v27.8h\n" - "zip1 v18.8h, v28.8h, v22.8h\n" - "zip1 v24.8h, v23.8h, v19.8h\n" - "zip1 v17.8h, v26.8h, v18.8h\n" - "zip1 v16.8h, v24.8h, v17.8h\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v24.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v23.8h, v23.8h, v19.8h\n" - "zip2 v19.8h, v26.8h, v18.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" - "zip1 v17.8h, v23.8h, v19.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v23.8h, v19.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v22.8h\n" - "zip1 v22.8h, v25.8h, v21.8h\n" - "zip1 v18.8h, v20.8h, v16.8h\n" - "zip1 v19.8h, v22.8h, v18.8h\n" - "str q19, [%x[out_ptr], #0x0]\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v18.8h, v22.8h, v18.8h\n" - "str q18, [%x[out_ptr], #0x0]\n" + "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v21.8h, v25.8h, v21.8h\n" - "zip2 v20.8h, v20.8h, v16.8h\n" - "zip1 v17.8h, v21.8h, v20.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp index f64db0b476..3a5dcf4a6b 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp16_fp32.hpp @@ -79,36 +79,36 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr d28, [x28], #0x8\n" - "ldr d27, [x27], #0x8\n" - "fcvtl v28.4s, v28.4h\n" + "ldr d27, [x28], #0x8\n" + "ldr d26, [x27], #0x8\n" "fcvtl v27.4s, v27.4h\n" + "fcvtl v26.4s, v26.4h\n" "ldr d22, [x26], #0x8\n" "ldr d21, [x25], #0x8\n" "fcvtl v22.4s, v22.4h\n" "fcvtl v21.4s, v21.4h\n" - "ldr d26, [x24], #0x8\n" + "ldr d20, [x24], #0x8\n" "ldr d25, [x23], #0x8\n" - "fcvtl v26.4s, v26.4h\n" - "fcvtl v25.4s, v25.4h\n" - "ldr d20, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" "fcvtl v20.4s, v20.4h\n" + "fcvtl v25.4s, v25.4h\n" + "ldr d19, [x22], #0x8\n" + "ldr d16, [x21], #0x8\n" "fcvtl v19.4s, v19.4h\n" - "zip1 v24.4s, v28.4s, v22.4s\n" - "zip1 v23.4s, v27.4s, v21.4s\n" + "fcvtl v16.4s, v16.4h\n" + "zip1 v24.4s, v27.4s, v22.4s\n" + "zip1 v23.4s, v26.4s, v21.4s\n" "subs %x[width], %x[width], #0x4\n" "cmp %x[width], #0x4\n" - "zip1 v18.4s, v26.4s, v20.4s\n" - "zip1 v17.4s, v25.4s, v19.4s\n" + "zip1 v18.4s, v20.4s, v19.4s\n" + "zip1 v17.4s, v25.4s, v16.4s\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" + "zip2 v22.4s, v27.4s, v22.4s\n" + "zip2 v21.4s, v26.4s, v21.4s\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip2 v20.4s, v26.4s, v20.4s\n" - "zip2 v19.4s, v25.4s, v19.4s\n" + "zip2 v20.4s, v20.4s, v19.4s\n" + "zip2 v19.4s, v25.4s, v16.4s\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" "prfm pldl1keep, [x22, #0x70]\n" @@ -137,71 +137,70 @@ void interleave_block<8, 1, VLType::None, false>( "ldr s28, [x28], #0x4\n" "ldr s27, [x27], #0x4\n" "mov x20, #0x2\n" - "ldr s22, [x26], #0x4\n" - "ldr s21, [x25], #0x4\n" - "ldr s26, [x24], #0x4\n" - "ldr s25, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" + "ldr s26, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" + "ldr s24, [x24], #0x4\n" + "ldr s23, [x23], #0x4\n" + "ldr s22, [x22], #0x4\n" + "ldr s21, [x21], #0x4\n" "tbz %x[width], #0, 5f\n" "ld1 { v28.h }[2], [x28]\n" "ld1 { v27.h }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v22.h }[2], [x26]\n" - "ld1 { v21.h }[2], [x25]\n" - "ld1 { v26.h }[2], [x24]\n" - "ld1 { v25.h }[2], [x23]\n" - "ld1 { v20.h }[2], [x22]\n" - "ld1 { v19.h }[2], [x21]\n" + "ld1 { v26.h }[2], [x26]\n" + "ld1 { v25.h }[2], [x25]\n" + "ld1 { v24.h }[2], [x24]\n" + "ld1 { v23.h }[2], [x23]\n" + "ld1 { v22.h }[2], [x22]\n" + "ld1 { v21.h }[2], [x21]\n" "b 5f\n" "4:" // odd_loads_1_0 "ldr h28, [x28, #0x0]\n" "ldr h27, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h22, [x26, #0x0]\n" - "ldr h21, [x25, #0x0]\n" - "ldr h26, [x24, #0x0]\n" - "ldr h25, [x23, #0x0]\n" - "ldr h20, [x22, #0x0]\n" - "ldr h19, [x21, #0x0]\n" + "ldr h26, [x26, #0x0]\n" + "ldr h25, [x25, #0x0]\n" + "ldr h24, [x24, #0x0]\n" + "ldr h23, [x23, #0x0]\n" + "ldr h22, [x22, #0x0]\n" + "ldr h21, [x21, #0x0]\n" "5:" // Odd load end "fcvtl v28.4s, v28.4h\n" "fcvtl v27.4s, v27.4h\n" "subs x20, x20, #0x1\n" - "fcvtl v22.4s, v22.4h\n" - "fcvtl v21.4s, v21.4h\n" "fcvtl v26.4s, v26.4h\n" "fcvtl v25.4s, v25.4h\n" - "fcvtl v20.4s, v20.4h\n" - "fcvtl v19.4s, v19.4h\n" - "zip1 v24.4s, v28.4s, v22.4s\n" - "zip1 v23.4s, v27.4s, v21.4s\n" - "zip1 v18.4s, v26.4s, v20.4s\n" - "zip1 v17.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v24.4s, v23.4s\n" + "fcvtl v24.4s, v24.4h\n" + "fcvtl v23.4s, v23.4h\n" + "fcvtl v22.4s, v22.4h\n" + "fcvtl v21.4s, v21.4h\n" + "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v19.4s, v27.4s, v25.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" "subs x20, x20, #0x1\n" - "zip2 v16.4s, v24.4s, v23.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v17.4s, v18.4s, v17.4s\n" - "str q17, [%x[out_ptr], #0x10]\n" + "zip2 v16.4s, v18.4s, v17.4s\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" - "zip2 v20.4s, v26.4s, v20.4s\n" - "zip2 v19.4s, v25.4s, v19.4s\n" - "zip1 v16.4s, v22.4s, v21.4s\n" + "zip2 v19.4s, v28.4s, v26.4s\n" + "zip2 v16.4s, v27.4s, v25.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v19.4s, v16.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.4s, v20.4s, v19.4s\n" - "str q18, [%x[out_ptr], #0x10]\n" + "zip1 v16.4s, v18.4s, v17.4s\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp index 6c009b34b8..80c387db47 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_fp32_fp32.hpp @@ -79,29 +79,29 @@ void interleave_block<8, 1, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q28, [x28], #0x10\n" - "ldr q27, [x27], #0x10\n" + "ldr q20, [x28], #0x10\n" + "ldr q18, [x27], #0x10\n" "subs %x[width], %x[width], #0x4\n" "cmp %x[width], #0x4\n" - "ldr q22, [x26], #0x10\n" - "ldr q21, [x25], #0x10\n" - "zip1 v26.4s, v28.4s, v22.4s\n" - "zip1 v25.4s, v27.4s, v21.4s\n" - "ldr q24, [x24], #0x10\n" + "ldr q17, [x26], #0x10\n" + "ldr q16, [x25], #0x10\n" + "zip1 v25.4s, v20.4s, v17.4s\n" + "zip1 v24.4s, v18.4s, v16.4s\n" + "ldr q19, [x24], #0x10\n" "ldr q23, [x23], #0x10\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" - "ldr q19, [x22], #0x10\n" - "ldr q18, [x21], #0x10\n" - "zip1 v20.4s, v24.4s, v19.4s\n" - "zip1 v17.4s, v23.4s, v18.4s\n" - "zip2 v19.4s, v24.4s, v19.4s\n" - "zip2 v18.4s, v23.4s, v18.4s\n" + "zip2 v22.4s, v20.4s, v17.4s\n" + "zip2 v21.4s, v18.4s, v16.4s\n" + "ldr q18, [x22], #0x10\n" + "ldr q16, [x21], #0x10\n" + "zip1 v20.4s, v19.4s, v18.4s\n" + "zip1 v17.4s, v23.4s, v16.4s\n" + "zip2 v19.4s, v19.4s, v18.4s\n" + "zip2 v18.4s, v23.4s, v16.4s\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip1 v16.4s, v26.4s, v25.4s\n" + "zip1 v16.4s, v25.4s, v24.4s\n" "str q16, [%x[out_ptr], #0x0]\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" @@ -109,7 +109,7 @@ void interleave_block<8, 1, VLType::None, false>( "str q16, [%x[out_ptr], #0x10]\n" "prfm pldl1keep, [x22, #0x70]\n" "prfm pldl1keep, [x21, #0x70]\n" - "zip2 v16.4s, v26.4s, v25.4s\n" + "zip2 v16.4s, v25.4s, v24.4s\n" "str q16, [%x[out_ptr], #0x20]\n" "zip2 v16.4s, v20.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x30]\n" @@ -129,63 +129,62 @@ void interleave_block<8, 1, VLType::None, false>( "ldr d28, [x28], #0x8\n" "ldr d27, [x27], #0x8\n" "mov x20, #0x2\n" - "ldr d22, [x26], #0x8\n" - "ldr d21, [x25], #0x8\n" + "ldr d26, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" "ldr d24, [x24], #0x8\n" "ldr d23, [x23], #0x8\n" - "ldr d19, [x22], #0x8\n" - "ldr d18, [x21], #0x8\n" + "ldr d22, [x22], #0x8\n" + "ldr d21, [x21], #0x8\n" "tbz %x[width], #0, 5f\n" "ld1 { v28.s }[2], [x28]\n" "ld1 { v27.s }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v22.s }[2], [x26]\n" - "ld1 { v21.s }[2], [x25]\n" + "ld1 { v26.s }[2], [x26]\n" + "ld1 { v25.s }[2], [x25]\n" "ld1 { v24.s }[2], [x24]\n" "ld1 { v23.s }[2], [x23]\n" - "ld1 { v19.s }[2], [x22]\n" - "ld1 { v18.s }[2], [x21]\n" + "ld1 { v22.s }[2], [x22]\n" + "ld1 { v21.s }[2], [x21]\n" "b 5f\n" "4:" // odd_loads_1_0 "ldr s28, [x28, #0x0]\n" "ldr s27, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr s22, [x26, #0x0]\n" - "ldr s21, [x25, #0x0]\n" + "ldr s26, [x26, #0x0]\n" + "ldr s25, [x25, #0x0]\n" "ldr s24, [x24, #0x0]\n" "ldr s23, [x23, #0x0]\n" - "ldr s19, [x22, #0x0]\n" - "ldr s18, [x21, #0x0]\n" + "ldr s22, [x22, #0x0]\n" + "ldr s21, [x21, #0x0]\n" "5:" // Odd load end - "zip1 v26.4s, v28.4s, v22.4s\n" - "zip1 v25.4s, v27.4s, v21.4s\n" + "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v19.4s, v27.4s, v25.4s\n" "subs x20, x20, #0x1\n" - "zip1 v20.4s, v24.4s, v19.4s\n" - "zip1 v17.4s, v23.4s, v18.4s\n" - "zip1 v16.4s, v26.4s, v25.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v16.4s, v20.4s, v17.4s\n" + "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" "subs x20, x20, #0x1\n" - "zip2 v16.4s, v26.4s, v25.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.4s, v20.4s, v17.4s\n" + "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 6f\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" - "zip2 v19.4s, v24.4s, v19.4s\n" - "zip2 v18.4s, v23.4s, v18.4s\n" - "zip1 v16.4s, v22.4s, v21.4s\n" + "zip2 v19.4s, v28.4s, v26.4s\n" + "zip2 v16.4s, v27.4s, v25.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v19.4s, v16.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v16.4s, v19.4s, v18.4s\n" + "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "6:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp index 767d468ad1..8e06b7ecab 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16.hpp @@ -80,33 +80,33 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr q25, [x28], #0x10\n" - "ldr q30, [x27], #0x10\n" + "ldr q27, [x27], #0x10\n" "subs %x[width], %x[width], #0x8\n" "cmp %x[width], #0x8\n" - "ldr q29, [x26], #0x10\n" - "ldr q28, [x25], #0x10\n" + "ldr q26, [x26], #0x10\n" + "ldr q24, [x25], #0x10\n" "ldr q21, [x24], #0x10\n" - "ldr q27, [x23], #0x10\n" + "ldr q20, [x23], #0x10\n" "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v26.8h, v30.8h, v27.8h\n" - "ldr q20, [x22], #0x10\n" - "ldr q22, [x21], #0x10\n" - "zip1 v19.8h, v29.8h, v20.8h\n" - "zip1 v18.8h, v28.8h, v22.8h\n" + "zip1 v22.8h, v27.8h, v20.8h\n" + "ldr q17, [x22], #0x10\n" + "ldr q16, [x21], #0x10\n" + "zip1 v19.8h, v26.8h, v17.8h\n" + "zip1 v18.8h, v24.8h, v16.8h\n" "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v21.8h, v26.8h, v17.8h\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v22.8h\n" + "zip2 v20.8h, v27.8h, v20.8h\n" + "zip2 v16.8h, v24.8h, v16.8h\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" "zip1 v24.8h, v23.8h, v19.8h\n" - "zip1 v17.8h, v26.8h, v18.8h\n" + "zip1 v17.8h, v22.8h, v18.8h\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" "zip2 v23.8h, v23.8h, v19.8h\n" - "zip2 v19.8h, v26.8h, v18.8h\n" + "zip2 v19.8h, v22.8h, v18.8h\n" "prfm pldl1keep, [x22, #0x70]\n" "prfm pldl1keep, [x21, #0x70]\n" "zip1 v22.8h, v25.8h, v21.8h\n" @@ -134,132 +134,131 @@ void interleave_block<8, 1, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr d25, [x28], #0x8\n" - "ldr d30, [x27], #0x8\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" - "ldr d21, [x24], #0x8\n" - "ldr d27, [x23], #0x8\n" - "ldr d20, [x22], #0x8\n" - "ldr d22, [x21], #0x8\n" + "ldr d30, [x28], #0x8\n" + "ldr d29, [x27], #0x8\n" + "ldr d28, [x26], #0x8\n" + "ldr d27, [x25], #0x8\n" + "ldr d26, [x24], #0x8\n" + "ldr d25, [x23], #0x8\n" + "ldr d24, [x22], #0x8\n" + "ldr d23, [x21], #0x8\n" "tbz %x[width], #1, 4f\n" - "ld1 { v25.s }[2], [x28], #0x4\n" - "ld1 { v30.s }[2], [x27], #0x4\n" + "ld1 { v30.s }[2], [x28], #0x4\n" + "ld1 { v29.s }[2], [x27], #0x4\n" "mov x20, #0x6\n" - "ld1 { v29.s }[2], [x26], #0x4\n" - "ld1 { v28.s }[2], [x25], #0x4\n" - "ld1 { v21.s }[2], [x24], #0x4\n" - "ld1 { v27.s }[2], [x23], #0x4\n" - "ld1 { v20.s }[2], [x22], #0x4\n" - "ld1 { v22.s }[2], [x21], #0x4\n" + "ld1 { v28.s }[2], [x26], #0x4\n" + "ld1 { v27.s }[2], [x25], #0x4\n" + "ld1 { v26.s }[2], [x24], #0x4\n" + "ld1 { v25.s }[2], [x23], #0x4\n" + "ld1 { v24.s }[2], [x22], #0x4\n" + "ld1 { v23.s }[2], [x21], #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.h }[6], [x28]\n" - "ld1 { v30.h }[6], [x27]\n" + "ld1 { v30.h }[6], [x28]\n" + "ld1 { v29.h }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.h }[6], [x26]\n" - "ld1 { v28.h }[6], [x25]\n" - "ld1 { v21.h }[6], [x24]\n" - "ld1 { v27.h }[6], [x23]\n" - "ld1 { v20.h }[6], [x22]\n" - "ld1 { v22.h }[6], [x21]\n" + "ld1 { v28.h }[6], [x26]\n" + "ld1 { v27.h }[6], [x25]\n" + "ld1 { v26.h }[6], [x24]\n" + "ld1 { v25.h }[6], [x23]\n" + "ld1 { v24.h }[6], [x22]\n" + "ld1 { v23.h }[6], [x21]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.h }[4], [x28]\n" - "ld1 { v30.h }[4], [x27]\n" + "ld1 { v30.h }[4], [x28]\n" + "ld1 { v29.h }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.h }[4], [x26]\n" - "ld1 { v28.h }[4], [x25]\n" - "ld1 { v21.h }[4], [x24]\n" - "ld1 { v27.h }[4], [x23]\n" - "ld1 { v20.h }[4], [x22]\n" - "ld1 { v22.h }[4], [x21]\n" + "ld1 { v28.h }[4], [x26]\n" + "ld1 { v27.h }[4], [x25]\n" + "ld1 { v26.h }[4], [x24]\n" + "ld1 { v25.h }[4], [x23]\n" + "ld1 { v24.h }[4], [x22]\n" + "ld1 { v23.h }[4], [x21]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr s25, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" "mov x20, #0x2\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s21, [x24], #0x4\n" - "ldr s27, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s22, [x21], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s24, [x22], #0x4\n" + "ldr s23, [x21], #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.h }[2], [x28]\n" - "ld1 { v30.h }[2], [x27]\n" + "ld1 { v30.h }[2], [x28]\n" + "ld1 { v29.h }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.h }[2], [x26]\n" - "ld1 { v28.h }[2], [x25]\n" - "ld1 { v21.h }[2], [x24]\n" - "ld1 { v27.h }[2], [x23]\n" - "ld1 { v20.h }[2], [x22]\n" - "ld1 { v22.h }[2], [x21]\n" + "ld1 { v28.h }[2], [x26]\n" + "ld1 { v27.h }[2], [x25]\n" + "ld1 { v26.h }[2], [x24]\n" + "ld1 { v25.h }[2], [x23]\n" + "ld1 { v24.h }[2], [x22]\n" + "ld1 { v23.h }[2], [x21]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr h25, [x28, #0x0]\n" - "ldr h30, [x27, #0x0]\n" + "ldr h30, [x28, #0x0]\n" + "ldr h29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h29, [x26, #0x0]\n" - "ldr h28, [x25, #0x0]\n" - "ldr h21, [x24, #0x0]\n" - "ldr h27, [x23, #0x0]\n" - "ldr h20, [x22, #0x0]\n" - "ldr h22, [x21, #0x0]\n" + "ldr h28, [x26, #0x0]\n" + "ldr h27, [x25, #0x0]\n" + "ldr h26, [x24, #0x0]\n" + "ldr h25, [x23, #0x0]\n" + "ldr h24, [x22, #0x0]\n" + "ldr h23, [x21, #0x0]\n" "7:" // Odd load end - "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v19.8h, v29.8h, v20.8h\n" + "zip1 v22.8h, v30.8h, v26.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip1 v26.8h, v30.8h, v27.8h\n" - "zip1 v18.8h, v28.8h, v22.8h\n" - "zip1 v24.8h, v23.8h, v19.8h\n" - "zip1 v17.8h, v26.8h, v18.8h\n" - "zip1 v16.8h, v24.8h, v17.8h\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v24.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v23.8h, v23.8h, v19.8h\n" - "zip2 v19.8h, v26.8h, v18.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" - "zip1 v17.8h, v23.8h, v19.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v23.8h, v19.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v22.8h\n" - "zip1 v22.8h, v25.8h, v21.8h\n" - "zip1 v18.8h, v20.8h, v16.8h\n" - "zip1 v19.8h, v22.8h, v18.8h\n" - "str q19, [%x[out_ptr], #0x0]\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v18.8h, v22.8h, v18.8h\n" - "str q18, [%x[out_ptr], #0x0]\n" + "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v21.8h, v25.8h, v21.8h\n" - "zip2 v20.8h, v20.8h, v16.8h\n" - "zip1 v17.8h, v21.8h, v20.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp index a73792036a..b91ae8a948 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s16_s16_summing.hpp @@ -159,101 +159,101 @@ void interleave_block<8, 1, VLType::None, true>( "5:" // Main loop skip "cbz %x[width], 10f\n" "tbz %x[width], #2, 7f\n" - "ldr d31, [x28], #0x8\n" - "ldr d30, [x27], #0x8\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" - "ldr d27, [x24], #0x8\n" - "ldr d26, [x23], #0x8\n" + "ldr d30, [x28], #0x8\n" + "ldr d29, [x27], #0x8\n" + "ldr d28, [x26], #0x8\n" + "ldr d27, [x25], #0x8\n" + "ldr d26, [x24], #0x8\n" + "ldr d25, [x23], #0x8\n" "ldr d24, [x22], #0x8\n" "ldr d23, [x21], #0x8\n" "tbz %x[width], #1, 6f\n" - "ld1 { v31.s }[2], [x28], #0x4\n" - "ld1 { v30.s }[2], [x27], #0x4\n" + "ld1 { v30.s }[2], [x28], #0x4\n" + "ld1 { v29.s }[2], [x27], #0x4\n" "mov x20, #0x6\n" - "ld1 { v29.s }[2], [x26], #0x4\n" - "ld1 { v28.s }[2], [x25], #0x4\n" - "ld1 { v27.s }[2], [x24], #0x4\n" - "ld1 { v26.s }[2], [x23], #0x4\n" + "ld1 { v28.s }[2], [x26], #0x4\n" + "ld1 { v27.s }[2], [x25], #0x4\n" + "ld1 { v26.s }[2], [x24], #0x4\n" + "ld1 { v25.s }[2], [x23], #0x4\n" "ld1 { v24.s }[2], [x22], #0x4\n" "ld1 { v23.s }[2], [x21], #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.h }[6], [x28]\n" - "ld1 { v30.h }[6], [x27]\n" + "ld1 { v30.h }[6], [x28]\n" + "ld1 { v29.h }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.h }[6], [x26]\n" - "ld1 { v28.h }[6], [x25]\n" - "ld1 { v27.h }[6], [x24]\n" - "ld1 { v26.h }[6], [x23]\n" + "ld1 { v28.h }[6], [x26]\n" + "ld1 { v27.h }[6], [x25]\n" + "ld1 { v26.h }[6], [x24]\n" + "ld1 { v25.h }[6], [x23]\n" "ld1 { v24.h }[6], [x22]\n" "ld1 { v23.h }[6], [x21]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.h }[4], [x28]\n" - "ld1 { v30.h }[4], [x27]\n" + "ld1 { v30.h }[4], [x28]\n" + "ld1 { v29.h }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.h }[4], [x26]\n" - "ld1 { v28.h }[4], [x25]\n" - "ld1 { v27.h }[4], [x24]\n" - "ld1 { v26.h }[4], [x23]\n" + "ld1 { v28.h }[4], [x26]\n" + "ld1 { v27.h }[4], [x25]\n" + "ld1 { v26.h }[4], [x24]\n" + "ld1 { v25.h }[4], [x23]\n" "ld1 { v24.h }[4], [x22]\n" "ld1 { v23.h }[4], [x21]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" - "ldr s31, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" "mov x20, #0x2\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s27, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" "ldr s24, [x22], #0x4\n" "ldr s23, [x21], #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.h }[2], [x28]\n" - "ld1 { v30.h }[2], [x27]\n" + "ld1 { v30.h }[2], [x28]\n" + "ld1 { v29.h }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.h }[2], [x26]\n" - "ld1 { v28.h }[2], [x25]\n" - "ld1 { v27.h }[2], [x24]\n" - "ld1 { v26.h }[2], [x23]\n" + "ld1 { v28.h }[2], [x26]\n" + "ld1 { v27.h }[2], [x25]\n" + "ld1 { v26.h }[2], [x24]\n" + "ld1 { v25.h }[2], [x23]\n" "ld1 { v24.h }[2], [x22]\n" "ld1 { v23.h }[2], [x21]\n" "b 9f\n" "8:" // odd_loads_1_0 - "ldr h31, [x28, #0x0]\n" - "ldr h30, [x27, #0x0]\n" + "ldr h30, [x28, #0x0]\n" + "ldr h29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h29, [x26, #0x0]\n" - "ldr h28, [x25, #0x0]\n" - "ldr h27, [x24, #0x0]\n" - "ldr h26, [x23, #0x0]\n" + "ldr h28, [x26, #0x0]\n" + "ldr h27, [x25, #0x0]\n" + "ldr h26, [x24, #0x0]\n" + "ldr h25, [x23, #0x0]\n" "ldr h24, [x22, #0x0]\n" "ldr h23, [x21, #0x0]\n" "9:" // Odd load end - "zip1 v25.8h, v31.8h, v27.8h\n" - "zip1 v18.8h, v29.8h, v24.8h\n" - "subs x20, x20, #0x1\n" "zip1 v22.8h, v30.8h, v26.8h\n" - "zip1 v21.8h, v28.8h, v23.8h\n" - "zip1 v17.8h, v25.8h, v18.8h\n" - "zip1 v16.8h, v22.8h, v21.8h\n" - "zip1 v20.8h, v17.8h, v16.8h\n" - "str q20, [%x[out_ptr], #0x0]\n" - "add v2.8h, v2.8h, v20.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" + "subs x20, x20, #0x1\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" + "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v19.8h, v17.8h, v16.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "subs x20, x20, #0x1\n" - "str q19, [%x[out_ptr], #0x0]\n" - "add v2.8h, v2.8h, v19.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" + "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v25.8h, v18.8h\n" - "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -266,11 +266,11 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v22.8h, v31.8h, v27.8h\n" - "zip2 v21.8h, v29.8h, v24.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v26.8h\n" - "zip2 v19.8h, v28.8h, v23.8h\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" "zip1 v18.8h, v22.8h, v21.8h\n" "zip1 v17.8h, v20.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" @@ -284,9 +284,9 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v22.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp index 4a38187638..c41120c698 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16.hpp @@ -80,35 +80,35 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr d25, [x28], #0x8\n" - "ldr d30, [x27], #0x8\n" + "ldr d27, [x27], #0x8\n" "sshll v25.8h, v25.8b, #0x0\n" - "sshll v30.8h, v30.8b, #0x0\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" - "sshll v29.8h, v29.8b, #0x0\n" - "sshll v28.8h, v28.8b, #0x0\n" + "sshll v27.8h, v27.8b, #0x0\n" + "ldr d26, [x26], #0x8\n" + "ldr d24, [x25], #0x8\n" + "sshll v26.8h, v26.8b, #0x0\n" + "sshll v24.8h, v24.8b, #0x0\n" "ldr d21, [x24], #0x8\n" - "ldr d27, [x23], #0x8\n" + "ldr d20, [x23], #0x8\n" "sshll v21.8h, v21.8b, #0x0\n" - "sshll v27.8h, v27.8b, #0x0\n" - "ldr d20, [x22], #0x8\n" - "ldr d26, [x21], #0x8\n" "sshll v20.8h, v20.8b, #0x0\n" - "sshll v26.8h, v26.8b, #0x0\n" + "ldr d17, [x22], #0x8\n" + "ldr d16, [x21], #0x8\n" + "sshll v17.8h, v17.8b, #0x0\n" + "sshll v16.8h, v16.8b, #0x0\n" "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v22.8h, v29.8h, v20.8h\n" + "zip1 v22.8h, v26.8h, v17.8h\n" "subs %x[width], %x[width], #0x8\n" "cmp %x[width], #0x8\n" - "zip1 v19.8h, v30.8h, v27.8h\n" - "zip1 v18.8h, v28.8h, v26.8h\n" + "zip1 v19.8h, v27.8h, v20.8h\n" + "zip1 v18.8h, v24.8h, v16.8h\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v21.8h, v26.8h, v17.8h\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v26.8h\n" + "zip2 v20.8h, v27.8h, v20.8h\n" + "zip2 v16.8h, v24.8h, v16.8h\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" "zip1 v24.8h, v23.8h, v22.8h\n" @@ -142,140 +142,139 @@ void interleave_block<8, 1, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr s25, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s21, [x24], #0x4\n" - "ldr s27, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s24, [x22], #0x4\n" + "ldr s23, [x21], #0x4\n" "tbz %x[width], #1, 4f\n" - "ld1 { v25.h }[2], [x28], #0x2\n" - "ld1 { v30.h }[2], [x27], #0x2\n" + "ld1 { v30.h }[2], [x28], #0x2\n" + "ld1 { v29.h }[2], [x27], #0x2\n" "mov x20, #0x6\n" - "ld1 { v29.h }[2], [x26], #0x2\n" - "ld1 { v28.h }[2], [x25], #0x2\n" - "ld1 { v21.h }[2], [x24], #0x2\n" - "ld1 { v27.h }[2], [x23], #0x2\n" - "ld1 { v20.h }[2], [x22], #0x2\n" - "ld1 { v26.h }[2], [x21], #0x2\n" + "ld1 { v28.h }[2], [x26], #0x2\n" + "ld1 { v27.h }[2], [x25], #0x2\n" + "ld1 { v26.h }[2], [x24], #0x2\n" + "ld1 { v25.h }[2], [x23], #0x2\n" + "ld1 { v24.h }[2], [x22], #0x2\n" + "ld1 { v23.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.b }[6], [x28]\n" - "ld1 { v30.b }[6], [x27]\n" + "ld1 { v30.b }[6], [x28]\n" + "ld1 { v29.b }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.b }[6], [x26]\n" - "ld1 { v28.b }[6], [x25]\n" - "ld1 { v21.b }[6], [x24]\n" - "ld1 { v27.b }[6], [x23]\n" - "ld1 { v20.b }[6], [x22]\n" - "ld1 { v26.b }[6], [x21]\n" + "ld1 { v28.b }[6], [x26]\n" + "ld1 { v27.b }[6], [x25]\n" + "ld1 { v26.b }[6], [x24]\n" + "ld1 { v25.b }[6], [x23]\n" + "ld1 { v24.b }[6], [x22]\n" + "ld1 { v23.b }[6], [x21]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.b }[4], [x28]\n" - "ld1 { v30.b }[4], [x27]\n" + "ld1 { v30.b }[4], [x28]\n" + "ld1 { v29.b }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.b }[4], [x26]\n" - "ld1 { v28.b }[4], [x25]\n" - "ld1 { v21.b }[4], [x24]\n" - "ld1 { v27.b }[4], [x23]\n" - "ld1 { v20.b }[4], [x22]\n" - "ld1 { v26.b }[4], [x21]\n" + "ld1 { v28.b }[4], [x26]\n" + "ld1 { v27.b }[4], [x25]\n" + "ld1 { v26.b }[4], [x24]\n" + "ld1 { v25.b }[4], [x23]\n" + "ld1 { v24.b }[4], [x22]\n" + "ld1 { v23.b }[4], [x21]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr h25, [x28], #0x2\n" - "ldr h30, [x27], #0x2\n" + "ldr h30, [x28], #0x2\n" + "ldr h29, [x27], #0x2\n" "mov x20, #0x2\n" - "ldr h29, [x26], #0x2\n" - "ldr h28, [x25], #0x2\n" - "ldr h21, [x24], #0x2\n" - "ldr h27, [x23], #0x2\n" - "ldr h20, [x22], #0x2\n" - "ldr h26, [x21], #0x2\n" + "ldr h28, [x26], #0x2\n" + "ldr h27, [x25], #0x2\n" + "ldr h26, [x24], #0x2\n" + "ldr h25, [x23], #0x2\n" + "ldr h24, [x22], #0x2\n" + "ldr h23, [x21], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.b }[2], [x28]\n" - "ld1 { v30.b }[2], [x27]\n" + "ld1 { v30.b }[2], [x28]\n" + "ld1 { v29.b }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.b }[2], [x26]\n" - "ld1 { v28.b }[2], [x25]\n" - "ld1 { v21.b }[2], [x24]\n" - "ld1 { v27.b }[2], [x23]\n" - "ld1 { v20.b }[2], [x22]\n" - "ld1 { v26.b }[2], [x21]\n" + "ld1 { v28.b }[2], [x26]\n" + "ld1 { v27.b }[2], [x25]\n" + "ld1 { v26.b }[2], [x24]\n" + "ld1 { v25.b }[2], [x23]\n" + "ld1 { v24.b }[2], [x22]\n" + "ld1 { v23.b }[2], [x21]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr b25, [x28, #0x0]\n" - "ldr b30, [x27, #0x0]\n" + "ldr b30, [x28, #0x0]\n" + "ldr b29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b29, [x26, #0x0]\n" - "ldr b28, [x25, #0x0]\n" - "ldr b21, [x24, #0x0]\n" - "ldr b27, [x23, #0x0]\n" - "ldr b20, [x22, #0x0]\n" - "ldr b26, [x21, #0x0]\n" + "ldr b28, [x26, #0x0]\n" + "ldr b27, [x25, #0x0]\n" + "ldr b26, [x24, #0x0]\n" + "ldr b25, [x23, #0x0]\n" + "ldr b24, [x22, #0x0]\n" + "ldr b23, [x21, #0x0]\n" "7:" // Odd load end - "sshll v25.8h, v25.8b, #0x0\n" "sshll v30.8h, v30.8b, #0x0\n" - "subs x20, x20, #0x1\n" "sshll v29.8h, v29.8b, #0x0\n" + "subs x20, x20, #0x1\n" "sshll v28.8h, v28.8b, #0x0\n" - "sshll v21.8h, v21.8b, #0x0\n" "sshll v27.8h, v27.8b, #0x0\n" - "sshll v20.8h, v20.8b, #0x0\n" "sshll v26.8h, v26.8b, #0x0\n" - "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v22.8h, v29.8h, v20.8h\n" - "zip1 v19.8h, v30.8h, v27.8h\n" - "zip1 v18.8h, v28.8h, v26.8h\n" - "zip1 v24.8h, v23.8h, v22.8h\n" - "zip1 v17.8h, v19.8h, v18.8h\n" - "zip1 v16.8h, v24.8h, v17.8h\n" + "sshll v25.8h, v25.8b, #0x0\n" + "sshll v24.8h, v24.8b, #0x0\n" + "sshll v23.8h, v23.8b, #0x0\n" + "zip1 v22.8h, v30.8h, v26.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v24.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v23.8h, v23.8h, v22.8h\n" - "zip2 v19.8h, v19.8h, v18.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" - "zip1 v17.8h, v23.8h, v19.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v23.8h, v19.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v26.8h\n" - "zip1 v22.8h, v25.8h, v21.8h\n" - "zip1 v18.8h, v20.8h, v16.8h\n" - "zip1 v19.8h, v22.8h, v18.8h\n" - "str q19, [%x[out_ptr], #0x0]\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v18.8h, v22.8h, v18.8h\n" - "str q18, [%x[out_ptr], #0x0]\n" + "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v21.8h, v25.8h, v21.8h\n" - "zip2 v20.8h, v20.8h, v16.8h\n" - "zip1 v17.8h, v21.8h, v20.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp index 3ad103c8d4..9ac7053ad8 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_s8_s16_summing.hpp @@ -167,109 +167,109 @@ void interleave_block<8, 1, VLType::None, true>( "5:" // Main loop skip "cbz %x[width], 10f\n" "tbz %x[width], #2, 7f\n" - "ldr s31, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s27, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" - "ldr s24, [x21], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s24, [x22], #0x4\n" + "ldr s23, [x21], #0x4\n" "tbz %x[width], #1, 6f\n" - "ld1 { v31.h }[2], [x28], #0x2\n" - "ld1 { v30.h }[2], [x27], #0x2\n" + "ld1 { v30.h }[2], [x28], #0x2\n" + "ld1 { v29.h }[2], [x27], #0x2\n" "mov x20, #0x6\n" - "ld1 { v29.h }[2], [x26], #0x2\n" - "ld1 { v28.h }[2], [x25], #0x2\n" - "ld1 { v27.h }[2], [x24], #0x2\n" - "ld1 { v26.h }[2], [x23], #0x2\n" - "ld1 { v25.h }[2], [x22], #0x2\n" - "ld1 { v24.h }[2], [x21], #0x2\n" + "ld1 { v28.h }[2], [x26], #0x2\n" + "ld1 { v27.h }[2], [x25], #0x2\n" + "ld1 { v26.h }[2], [x24], #0x2\n" + "ld1 { v25.h }[2], [x23], #0x2\n" + "ld1 { v24.h }[2], [x22], #0x2\n" + "ld1 { v23.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.b }[6], [x28]\n" - "ld1 { v30.b }[6], [x27]\n" + "ld1 { v30.b }[6], [x28]\n" + "ld1 { v29.b }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.b }[6], [x26]\n" - "ld1 { v28.b }[6], [x25]\n" - "ld1 { v27.b }[6], [x24]\n" - "ld1 { v26.b }[6], [x23]\n" - "ld1 { v25.b }[6], [x22]\n" - "ld1 { v24.b }[6], [x21]\n" + "ld1 { v28.b }[6], [x26]\n" + "ld1 { v27.b }[6], [x25]\n" + "ld1 { v26.b }[6], [x24]\n" + "ld1 { v25.b }[6], [x23]\n" + "ld1 { v24.b }[6], [x22]\n" + "ld1 { v23.b }[6], [x21]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.b }[4], [x28]\n" - "ld1 { v30.b }[4], [x27]\n" + "ld1 { v30.b }[4], [x28]\n" + "ld1 { v29.b }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.b }[4], [x26]\n" - "ld1 { v28.b }[4], [x25]\n" - "ld1 { v27.b }[4], [x24]\n" - "ld1 { v26.b }[4], [x23]\n" - "ld1 { v25.b }[4], [x22]\n" - "ld1 { v24.b }[4], [x21]\n" + "ld1 { v28.b }[4], [x26]\n" + "ld1 { v27.b }[4], [x25]\n" + "ld1 { v26.b }[4], [x24]\n" + "ld1 { v25.b }[4], [x23]\n" + "ld1 { v24.b }[4], [x22]\n" + "ld1 { v23.b }[4], [x21]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" - "ldr h31, [x28], #0x2\n" - "ldr h30, [x27], #0x2\n" + "ldr h30, [x28], #0x2\n" + "ldr h29, [x27], #0x2\n" "mov x20, #0x2\n" - "ldr h29, [x26], #0x2\n" - "ldr h28, [x25], #0x2\n" - "ldr h27, [x24], #0x2\n" - "ldr h26, [x23], #0x2\n" - "ldr h25, [x22], #0x2\n" - "ldr h24, [x21], #0x2\n" + "ldr h28, [x26], #0x2\n" + "ldr h27, [x25], #0x2\n" + "ldr h26, [x24], #0x2\n" + "ldr h25, [x23], #0x2\n" + "ldr h24, [x22], #0x2\n" + "ldr h23, [x21], #0x2\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.b }[2], [x28]\n" - "ld1 { v30.b }[2], [x27]\n" + "ld1 { v30.b }[2], [x28]\n" + "ld1 { v29.b }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.b }[2], [x26]\n" - "ld1 { v28.b }[2], [x25]\n" - "ld1 { v27.b }[2], [x24]\n" - "ld1 { v26.b }[2], [x23]\n" - "ld1 { v25.b }[2], [x22]\n" - "ld1 { v24.b }[2], [x21]\n" + "ld1 { v28.b }[2], [x26]\n" + "ld1 { v27.b }[2], [x25]\n" + "ld1 { v26.b }[2], [x24]\n" + "ld1 { v25.b }[2], [x23]\n" + "ld1 { v24.b }[2], [x22]\n" + "ld1 { v23.b }[2], [x21]\n" "b 9f\n" "8:" // odd_loads_1_0 - "ldr b31, [x28, #0x0]\n" - "ldr b30, [x27, #0x0]\n" + "ldr b30, [x28, #0x0]\n" + "ldr b29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b29, [x26, #0x0]\n" - "ldr b28, [x25, #0x0]\n" - "ldr b27, [x24, #0x0]\n" - "ldr b26, [x23, #0x0]\n" - "ldr b25, [x22, #0x0]\n" - "ldr b24, [x21, #0x0]\n" + "ldr b28, [x26, #0x0]\n" + "ldr b27, [x25, #0x0]\n" + "ldr b26, [x24, #0x0]\n" + "ldr b25, [x23, #0x0]\n" + "ldr b24, [x22, #0x0]\n" + "ldr b23, [x21, #0x0]\n" "9:" // Odd load end - "sshll v31.8h, v31.8b, #0x0\n" "sshll v30.8h, v30.8b, #0x0\n" - "subs x20, x20, #0x1\n" "sshll v29.8h, v29.8b, #0x0\n" + "subs x20, x20, #0x1\n" "sshll v28.8h, v28.8b, #0x0\n" "sshll v27.8h, v27.8b, #0x0\n" "sshll v26.8h, v26.8b, #0x0\n" "sshll v25.8h, v25.8b, #0x0\n" "sshll v24.8h, v24.8b, #0x0\n" - "zip1 v23.8h, v31.8h, v27.8h\n" - "zip1 v22.8h, v29.8h, v25.8h\n" - "zip1 v21.8h, v30.8h, v26.8h\n" - "zip1 v20.8h, v28.8h, v24.8h\n" - "zip1 v18.8h, v23.8h, v22.8h\n" - "zip1 v17.8h, v21.8h, v20.8h\n" + "sshll v23.8h, v23.8b, #0x0\n" + "zip1 v22.8h, v30.8h, v26.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v19.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "subs x20, x20, #0x1\n" - "str q19, [%x[out_ptr], #0x0]\n" - "add v2.8h, v2.8h, v19.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" + "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v23.8h, v22.8h\n" - "zip2 v17.8h, v21.8h, v20.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -282,11 +282,11 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v22.8h, v31.8h, v27.8h\n" - "zip2 v21.8h, v29.8h, v25.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v26.8h\n" - "zip2 v19.8h, v28.8h, v24.8h\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" "zip1 v18.8h, v22.8h, v21.8h\n" "zip1 v17.8h, v20.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" @@ -300,9 +300,9 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v22.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp index de29d77a22..c01d980f49 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u16_u16_summing.hpp @@ -159,101 +159,101 @@ void interleave_block<8, 1, VLType::None, true>( "5:" // Main loop skip "cbz %x[width], 10f\n" "tbz %x[width], #2, 7f\n" - "ldr d31, [x28], #0x8\n" - "ldr d30, [x27], #0x8\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" - "ldr d27, [x24], #0x8\n" - "ldr d26, [x23], #0x8\n" + "ldr d30, [x28], #0x8\n" + "ldr d29, [x27], #0x8\n" + "ldr d28, [x26], #0x8\n" + "ldr d27, [x25], #0x8\n" + "ldr d26, [x24], #0x8\n" + "ldr d25, [x23], #0x8\n" "ldr d24, [x22], #0x8\n" "ldr d23, [x21], #0x8\n" "tbz %x[width], #1, 6f\n" - "ld1 { v31.s }[2], [x28], #0x4\n" - "ld1 { v30.s }[2], [x27], #0x4\n" + "ld1 { v30.s }[2], [x28], #0x4\n" + "ld1 { v29.s }[2], [x27], #0x4\n" "mov x20, #0x6\n" - "ld1 { v29.s }[2], [x26], #0x4\n" - "ld1 { v28.s }[2], [x25], #0x4\n" - "ld1 { v27.s }[2], [x24], #0x4\n" - "ld1 { v26.s }[2], [x23], #0x4\n" + "ld1 { v28.s }[2], [x26], #0x4\n" + "ld1 { v27.s }[2], [x25], #0x4\n" + "ld1 { v26.s }[2], [x24], #0x4\n" + "ld1 { v25.s }[2], [x23], #0x4\n" "ld1 { v24.s }[2], [x22], #0x4\n" "ld1 { v23.s }[2], [x21], #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.h }[6], [x28]\n" - "ld1 { v30.h }[6], [x27]\n" + "ld1 { v30.h }[6], [x28]\n" + "ld1 { v29.h }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.h }[6], [x26]\n" - "ld1 { v28.h }[6], [x25]\n" - "ld1 { v27.h }[6], [x24]\n" - "ld1 { v26.h }[6], [x23]\n" + "ld1 { v28.h }[6], [x26]\n" + "ld1 { v27.h }[6], [x25]\n" + "ld1 { v26.h }[6], [x24]\n" + "ld1 { v25.h }[6], [x23]\n" "ld1 { v24.h }[6], [x22]\n" "ld1 { v23.h }[6], [x21]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.h }[4], [x28]\n" - "ld1 { v30.h }[4], [x27]\n" + "ld1 { v30.h }[4], [x28]\n" + "ld1 { v29.h }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.h }[4], [x26]\n" - "ld1 { v28.h }[4], [x25]\n" - "ld1 { v27.h }[4], [x24]\n" - "ld1 { v26.h }[4], [x23]\n" + "ld1 { v28.h }[4], [x26]\n" + "ld1 { v27.h }[4], [x25]\n" + "ld1 { v26.h }[4], [x24]\n" + "ld1 { v25.h }[4], [x23]\n" "ld1 { v24.h }[4], [x22]\n" "ld1 { v23.h }[4], [x21]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" - "ldr s31, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" "mov x20, #0x2\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s27, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" "ldr s24, [x22], #0x4\n" "ldr s23, [x21], #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.h }[2], [x28]\n" - "ld1 { v30.h }[2], [x27]\n" + "ld1 { v30.h }[2], [x28]\n" + "ld1 { v29.h }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.h }[2], [x26]\n" - "ld1 { v28.h }[2], [x25]\n" - "ld1 { v27.h }[2], [x24]\n" - "ld1 { v26.h }[2], [x23]\n" + "ld1 { v28.h }[2], [x26]\n" + "ld1 { v27.h }[2], [x25]\n" + "ld1 { v26.h }[2], [x24]\n" + "ld1 { v25.h }[2], [x23]\n" "ld1 { v24.h }[2], [x22]\n" "ld1 { v23.h }[2], [x21]\n" "b 9f\n" "8:" // odd_loads_1_0 - "ldr h31, [x28, #0x0]\n" - "ldr h30, [x27, #0x0]\n" + "ldr h30, [x28, #0x0]\n" + "ldr h29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h29, [x26, #0x0]\n" - "ldr h28, [x25, #0x0]\n" - "ldr h27, [x24, #0x0]\n" - "ldr h26, [x23, #0x0]\n" + "ldr h28, [x26, #0x0]\n" + "ldr h27, [x25, #0x0]\n" + "ldr h26, [x24, #0x0]\n" + "ldr h25, [x23, #0x0]\n" "ldr h24, [x22, #0x0]\n" "ldr h23, [x21, #0x0]\n" "9:" // Odd load end - "zip1 v25.8h, v31.8h, v27.8h\n" - "zip1 v18.8h, v29.8h, v24.8h\n" - "subs x20, x20, #0x1\n" "zip1 v22.8h, v30.8h, v26.8h\n" - "zip1 v21.8h, v28.8h, v23.8h\n" - "zip1 v17.8h, v25.8h, v18.8h\n" - "zip1 v16.8h, v22.8h, v21.8h\n" - "zip1 v20.8h, v17.8h, v16.8h\n" - "str q20, [%x[out_ptr], #0x0]\n" - "add v2.8h, v2.8h, v20.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" + "subs x20, x20, #0x1\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" + "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v19.8h, v17.8h, v16.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "subs x20, x20, #0x1\n" - "str q19, [%x[out_ptr], #0x0]\n" - "add v2.8h, v2.8h, v19.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" + "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v25.8h, v18.8h\n" - "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -266,11 +266,11 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v22.8h, v31.8h, v27.8h\n" - "zip2 v21.8h, v29.8h, v24.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v26.8h\n" - "zip2 v19.8h, v28.8h, v23.8h\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" "zip1 v18.8h, v22.8h, v21.8h\n" "zip1 v17.8h, v20.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" @@ -284,9 +284,9 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v22.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp index 43a3a46801..d29a995b46 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16.hpp @@ -80,35 +80,35 @@ void interleave_block<8, 1, VLType::None, false>( "blt 3f\n" "2:" // Main loop head "ldr d25, [x28], #0x8\n" - "ldr d30, [x27], #0x8\n" + "ldr d27, [x27], #0x8\n" "ushll v25.8h, v25.8b, #0x0\n" - "ushll v30.8h, v30.8b, #0x0\n" - "ldr d29, [x26], #0x8\n" - "ldr d28, [x25], #0x8\n" - "ushll v29.8h, v29.8b, #0x0\n" - "ushll v28.8h, v28.8b, #0x0\n" + "ushll v27.8h, v27.8b, #0x0\n" + "ldr d26, [x26], #0x8\n" + "ldr d24, [x25], #0x8\n" + "ushll v26.8h, v26.8b, #0x0\n" + "ushll v24.8h, v24.8b, #0x0\n" "ldr d21, [x24], #0x8\n" - "ldr d27, [x23], #0x8\n" + "ldr d20, [x23], #0x8\n" "ushll v21.8h, v21.8b, #0x0\n" - "ushll v27.8h, v27.8b, #0x0\n" - "ldr d20, [x22], #0x8\n" - "ldr d26, [x21], #0x8\n" "ushll v20.8h, v20.8b, #0x0\n" - "ushll v26.8h, v26.8b, #0x0\n" + "ldr d17, [x22], #0x8\n" + "ldr d16, [x21], #0x8\n" + "ushll v17.8h, v17.8b, #0x0\n" + "ushll v16.8h, v16.8b, #0x0\n" "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v22.8h, v29.8h, v20.8h\n" + "zip1 v22.8h, v26.8h, v17.8h\n" "subs %x[width], %x[width], #0x8\n" "cmp %x[width], #0x8\n" - "zip1 v19.8h, v30.8h, v27.8h\n" - "zip1 v18.8h, v28.8h, v26.8h\n" + "zip1 v19.8h, v27.8h, v20.8h\n" + "zip1 v18.8h, v24.8h, v16.8h\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v21.8h, v26.8h, v17.8h\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v26.8h\n" + "zip2 v20.8h, v27.8h, v20.8h\n" + "zip2 v16.8h, v24.8h, v16.8h\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" "zip1 v24.8h, v23.8h, v22.8h\n" @@ -142,140 +142,139 @@ void interleave_block<8, 1, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr s25, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s21, [x24], #0x4\n" - "ldr s27, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s26, [x21], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s24, [x22], #0x4\n" + "ldr s23, [x21], #0x4\n" "tbz %x[width], #1, 4f\n" - "ld1 { v25.h }[2], [x28], #0x2\n" - "ld1 { v30.h }[2], [x27], #0x2\n" + "ld1 { v30.h }[2], [x28], #0x2\n" + "ld1 { v29.h }[2], [x27], #0x2\n" "mov x20, #0x6\n" - "ld1 { v29.h }[2], [x26], #0x2\n" - "ld1 { v28.h }[2], [x25], #0x2\n" - "ld1 { v21.h }[2], [x24], #0x2\n" - "ld1 { v27.h }[2], [x23], #0x2\n" - "ld1 { v20.h }[2], [x22], #0x2\n" - "ld1 { v26.h }[2], [x21], #0x2\n" + "ld1 { v28.h }[2], [x26], #0x2\n" + "ld1 { v27.h }[2], [x25], #0x2\n" + "ld1 { v26.h }[2], [x24], #0x2\n" + "ld1 { v25.h }[2], [x23], #0x2\n" + "ld1 { v24.h }[2], [x22], #0x2\n" + "ld1 { v23.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.b }[6], [x28]\n" - "ld1 { v30.b }[6], [x27]\n" + "ld1 { v30.b }[6], [x28]\n" + "ld1 { v29.b }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.b }[6], [x26]\n" - "ld1 { v28.b }[6], [x25]\n" - "ld1 { v21.b }[6], [x24]\n" - "ld1 { v27.b }[6], [x23]\n" - "ld1 { v20.b }[6], [x22]\n" - "ld1 { v26.b }[6], [x21]\n" + "ld1 { v28.b }[6], [x26]\n" + "ld1 { v27.b }[6], [x25]\n" + "ld1 { v26.b }[6], [x24]\n" + "ld1 { v25.b }[6], [x23]\n" + "ld1 { v24.b }[6], [x22]\n" + "ld1 { v23.b }[6], [x21]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.b }[4], [x28]\n" - "ld1 { v30.b }[4], [x27]\n" + "ld1 { v30.b }[4], [x28]\n" + "ld1 { v29.b }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.b }[4], [x26]\n" - "ld1 { v28.b }[4], [x25]\n" - "ld1 { v21.b }[4], [x24]\n" - "ld1 { v27.b }[4], [x23]\n" - "ld1 { v20.b }[4], [x22]\n" - "ld1 { v26.b }[4], [x21]\n" + "ld1 { v28.b }[4], [x26]\n" + "ld1 { v27.b }[4], [x25]\n" + "ld1 { v26.b }[4], [x24]\n" + "ld1 { v25.b }[4], [x23]\n" + "ld1 { v24.b }[4], [x22]\n" + "ld1 { v23.b }[4], [x21]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr h25, [x28], #0x2\n" - "ldr h30, [x27], #0x2\n" + "ldr h30, [x28], #0x2\n" + "ldr h29, [x27], #0x2\n" "mov x20, #0x2\n" - "ldr h29, [x26], #0x2\n" - "ldr h28, [x25], #0x2\n" - "ldr h21, [x24], #0x2\n" - "ldr h27, [x23], #0x2\n" - "ldr h20, [x22], #0x2\n" - "ldr h26, [x21], #0x2\n" + "ldr h28, [x26], #0x2\n" + "ldr h27, [x25], #0x2\n" + "ldr h26, [x24], #0x2\n" + "ldr h25, [x23], #0x2\n" + "ldr h24, [x22], #0x2\n" + "ldr h23, [x21], #0x2\n" "tbz %x[width], #0, 7f\n" - "ld1 { v25.b }[2], [x28]\n" - "ld1 { v30.b }[2], [x27]\n" + "ld1 { v30.b }[2], [x28]\n" + "ld1 { v29.b }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.b }[2], [x26]\n" - "ld1 { v28.b }[2], [x25]\n" - "ld1 { v21.b }[2], [x24]\n" - "ld1 { v27.b }[2], [x23]\n" - "ld1 { v20.b }[2], [x22]\n" - "ld1 { v26.b }[2], [x21]\n" + "ld1 { v28.b }[2], [x26]\n" + "ld1 { v27.b }[2], [x25]\n" + "ld1 { v26.b }[2], [x24]\n" + "ld1 { v25.b }[2], [x23]\n" + "ld1 { v24.b }[2], [x22]\n" + "ld1 { v23.b }[2], [x21]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr b25, [x28, #0x0]\n" - "ldr b30, [x27, #0x0]\n" + "ldr b30, [x28, #0x0]\n" + "ldr b29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b29, [x26, #0x0]\n" - "ldr b28, [x25, #0x0]\n" - "ldr b21, [x24, #0x0]\n" - "ldr b27, [x23, #0x0]\n" - "ldr b20, [x22, #0x0]\n" - "ldr b26, [x21, #0x0]\n" + "ldr b28, [x26, #0x0]\n" + "ldr b27, [x25, #0x0]\n" + "ldr b26, [x24, #0x0]\n" + "ldr b25, [x23, #0x0]\n" + "ldr b24, [x22, #0x0]\n" + "ldr b23, [x21, #0x0]\n" "7:" // Odd load end - "ushll v25.8h, v25.8b, #0x0\n" "ushll v30.8h, v30.8b, #0x0\n" - "subs x20, x20, #0x1\n" "ushll v29.8h, v29.8b, #0x0\n" + "subs x20, x20, #0x1\n" "ushll v28.8h, v28.8b, #0x0\n" - "ushll v21.8h, v21.8b, #0x0\n" "ushll v27.8h, v27.8b, #0x0\n" - "ushll v20.8h, v20.8b, #0x0\n" "ushll v26.8h, v26.8b, #0x0\n" - "zip1 v23.8h, v25.8h, v21.8h\n" - "zip1 v22.8h, v29.8h, v20.8h\n" - "zip1 v19.8h, v30.8h, v27.8h\n" - "zip1 v18.8h, v28.8h, v26.8h\n" - "zip1 v24.8h, v23.8h, v22.8h\n" - "zip1 v17.8h, v19.8h, v18.8h\n" - "zip1 v16.8h, v24.8h, v17.8h\n" + "ushll v25.8h, v25.8b, #0x0\n" + "ushll v24.8h, v24.8b, #0x0\n" + "ushll v23.8h, v23.8b, #0x0\n" + "zip1 v22.8h, v30.8h, v26.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v24.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v23.8h, v23.8h, v22.8h\n" - "zip2 v19.8h, v19.8h, v18.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" - "zip1 v17.8h, v23.8h, v19.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.8h, v23.8h, v19.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v25.8h, v25.8h, v21.8h\n" - "zip2 v21.8h, v29.8h, v20.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v27.8h\n" - "zip2 v16.8h, v28.8h, v26.8h\n" - "zip1 v22.8h, v25.8h, v21.8h\n" - "zip1 v18.8h, v20.8h, v16.8h\n" - "zip1 v19.8h, v22.8h, v18.8h\n" - "str q19, [%x[out_ptr], #0x0]\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v18.8h, v22.8h, v18.8h\n" - "str q18, [%x[out_ptr], #0x0]\n" + "zip2 v16.8h, v18.8h, v17.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 8f\n" - "zip2 v21.8h, v25.8h, v21.8h\n" - "zip2 v20.8h, v20.8h, v16.8h\n" - "zip1 v17.8h, v21.8h, v20.8h\n" - "str q17, [%x[out_ptr], #0x0]\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "8:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp index 3ab24365af..ae4bf9bf3b 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block1_u8_u16_summing.hpp @@ -167,109 +167,109 @@ void interleave_block<8, 1, VLType::None, true>( "5:" // Main loop skip "cbz %x[width], 10f\n" "tbz %x[width], #2, 7f\n" - "ldr s31, [x28], #0x4\n" - "ldr s30, [x27], #0x4\n" - "ldr s29, [x26], #0x4\n" - "ldr s28, [x25], #0x4\n" - "ldr s27, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" - "ldr s25, [x22], #0x4\n" - "ldr s24, [x21], #0x4\n" + "ldr s30, [x28], #0x4\n" + "ldr s29, [x27], #0x4\n" + "ldr s28, [x26], #0x4\n" + "ldr s27, [x25], #0x4\n" + "ldr s26, [x24], #0x4\n" + "ldr s25, [x23], #0x4\n" + "ldr s24, [x22], #0x4\n" + "ldr s23, [x21], #0x4\n" "tbz %x[width], #1, 6f\n" - "ld1 { v31.h }[2], [x28], #0x2\n" - "ld1 { v30.h }[2], [x27], #0x2\n" + "ld1 { v30.h }[2], [x28], #0x2\n" + "ld1 { v29.h }[2], [x27], #0x2\n" "mov x20, #0x6\n" - "ld1 { v29.h }[2], [x26], #0x2\n" - "ld1 { v28.h }[2], [x25], #0x2\n" - "ld1 { v27.h }[2], [x24], #0x2\n" - "ld1 { v26.h }[2], [x23], #0x2\n" - "ld1 { v25.h }[2], [x22], #0x2\n" - "ld1 { v24.h }[2], [x21], #0x2\n" + "ld1 { v28.h }[2], [x26], #0x2\n" + "ld1 { v27.h }[2], [x25], #0x2\n" + "ld1 { v26.h }[2], [x24], #0x2\n" + "ld1 { v25.h }[2], [x23], #0x2\n" + "ld1 { v24.h }[2], [x22], #0x2\n" + "ld1 { v23.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.b }[6], [x28]\n" - "ld1 { v30.b }[6], [x27]\n" + "ld1 { v30.b }[6], [x28]\n" + "ld1 { v29.b }[6], [x27]\n" "mov x20, #0x7\n" - "ld1 { v29.b }[6], [x26]\n" - "ld1 { v28.b }[6], [x25]\n" - "ld1 { v27.b }[6], [x24]\n" - "ld1 { v26.b }[6], [x23]\n" - "ld1 { v25.b }[6], [x22]\n" - "ld1 { v24.b }[6], [x21]\n" + "ld1 { v28.b }[6], [x26]\n" + "ld1 { v27.b }[6], [x25]\n" + "ld1 { v26.b }[6], [x24]\n" + "ld1 { v25.b }[6], [x23]\n" + "ld1 { v24.b }[6], [x22]\n" + "ld1 { v23.b }[6], [x21]\n" "b 9f\n" "6:" // odd_loads_1_4 "mov x20, #0x4\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.b }[4], [x28]\n" - "ld1 { v30.b }[4], [x27]\n" + "ld1 { v30.b }[4], [x28]\n" + "ld1 { v29.b }[4], [x27]\n" "mov x20, #0x5\n" - "ld1 { v29.b }[4], [x26]\n" - "ld1 { v28.b }[4], [x25]\n" - "ld1 { v27.b }[4], [x24]\n" - "ld1 { v26.b }[4], [x23]\n" - "ld1 { v25.b }[4], [x22]\n" - "ld1 { v24.b }[4], [x21]\n" + "ld1 { v28.b }[4], [x26]\n" + "ld1 { v27.b }[4], [x25]\n" + "ld1 { v26.b }[4], [x24]\n" + "ld1 { v25.b }[4], [x23]\n" + "ld1 { v24.b }[4], [x22]\n" + "ld1 { v23.b }[4], [x21]\n" "b 9f\n" "7:" // odd_loads_2_0 "tbz %x[width], #1, 8f\n" - "ldr h31, [x28], #0x2\n" - "ldr h30, [x27], #0x2\n" + "ldr h30, [x28], #0x2\n" + "ldr h29, [x27], #0x2\n" "mov x20, #0x2\n" - "ldr h29, [x26], #0x2\n" - "ldr h28, [x25], #0x2\n" - "ldr h27, [x24], #0x2\n" - "ldr h26, [x23], #0x2\n" - "ldr h25, [x22], #0x2\n" - "ldr h24, [x21], #0x2\n" + "ldr h28, [x26], #0x2\n" + "ldr h27, [x25], #0x2\n" + "ldr h26, [x24], #0x2\n" + "ldr h25, [x23], #0x2\n" + "ldr h24, [x22], #0x2\n" + "ldr h23, [x21], #0x2\n" "tbz %x[width], #0, 9f\n" - "ld1 { v31.b }[2], [x28]\n" - "ld1 { v30.b }[2], [x27]\n" + "ld1 { v30.b }[2], [x28]\n" + "ld1 { v29.b }[2], [x27]\n" "mov x20, #0x3\n" - "ld1 { v29.b }[2], [x26]\n" - "ld1 { v28.b }[2], [x25]\n" - "ld1 { v27.b }[2], [x24]\n" - "ld1 { v26.b }[2], [x23]\n" - "ld1 { v25.b }[2], [x22]\n" - "ld1 { v24.b }[2], [x21]\n" + "ld1 { v28.b }[2], [x26]\n" + "ld1 { v27.b }[2], [x25]\n" + "ld1 { v26.b }[2], [x24]\n" + "ld1 { v25.b }[2], [x23]\n" + "ld1 { v24.b }[2], [x22]\n" + "ld1 { v23.b }[2], [x21]\n" "b 9f\n" "8:" // odd_loads_1_0 - "ldr b31, [x28, #0x0]\n" - "ldr b30, [x27, #0x0]\n" + "ldr b30, [x28, #0x0]\n" + "ldr b29, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b29, [x26, #0x0]\n" - "ldr b28, [x25, #0x0]\n" - "ldr b27, [x24, #0x0]\n" - "ldr b26, [x23, #0x0]\n" - "ldr b25, [x22, #0x0]\n" - "ldr b24, [x21, #0x0]\n" + "ldr b28, [x26, #0x0]\n" + "ldr b27, [x25, #0x0]\n" + "ldr b26, [x24, #0x0]\n" + "ldr b25, [x23, #0x0]\n" + "ldr b24, [x22, #0x0]\n" + "ldr b23, [x21, #0x0]\n" "9:" // Odd load end - "ushll v31.8h, v31.8b, #0x0\n" "ushll v30.8h, v30.8b, #0x0\n" - "subs x20, x20, #0x1\n" "ushll v29.8h, v29.8b, #0x0\n" + "subs x20, x20, #0x1\n" "ushll v28.8h, v28.8b, #0x0\n" "ushll v27.8h, v27.8b, #0x0\n" "ushll v26.8h, v26.8b, #0x0\n" "ushll v25.8h, v25.8b, #0x0\n" "ushll v24.8h, v24.8b, #0x0\n" - "zip1 v23.8h, v31.8h, v27.8h\n" - "zip1 v22.8h, v29.8h, v25.8h\n" - "zip1 v21.8h, v30.8h, v26.8h\n" - "zip1 v20.8h, v28.8h, v24.8h\n" - "zip1 v18.8h, v23.8h, v22.8h\n" - "zip1 v17.8h, v21.8h, v20.8h\n" + "ushll v23.8h, v23.8b, #0x0\n" + "zip1 v22.8h, v30.8h, v26.8h\n" + "zip1 v21.8h, v28.8h, v24.8h\n" + "zip1 v20.8h, v29.8h, v25.8h\n" + "zip1 v19.8h, v27.8h, v23.8h\n" + "zip1 v18.8h, v22.8h, v21.8h\n" + "zip1 v17.8h, v20.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v19.8h, v18.8h, v17.8h\n" + "zip2 v16.8h, v18.8h, v17.8h\n" "subs x20, x20, #0x1\n" - "str q19, [%x[out_ptr], #0x0]\n" - "add v2.8h, v2.8h, v19.8h\n" + "str q16, [%x[out_ptr], #0x0]\n" + "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v23.8h, v22.8h\n" - "zip2 v17.8h, v21.8h, v20.8h\n" + "zip2 v18.8h, v22.8h, v21.8h\n" + "zip2 v17.8h, v20.8h, v19.8h\n" "subs x20, x20, #0x1\n" "zip1 v16.8h, v18.8h, v17.8h\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -282,11 +282,11 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v22.8h, v31.8h, v27.8h\n" - "zip2 v21.8h, v29.8h, v25.8h\n" + "zip2 v22.8h, v30.8h, v26.8h\n" + "zip2 v21.8h, v28.8h, v24.8h\n" "subs x20, x20, #0x1\n" - "zip2 v20.8h, v30.8h, v26.8h\n" - "zip2 v19.8h, v28.8h, v24.8h\n" + "zip2 v20.8h, v29.8h, v25.8h\n" + "zip2 v19.8h, v27.8h, v23.8h\n" "zip1 v18.8h, v22.8h, v21.8h\n" "zip1 v17.8h, v20.8h, v19.8h\n" "zip1 v16.8h, v18.8h, v17.8h\n" @@ -300,9 +300,9 @@ void interleave_block<8, 1, VLType::None, true>( "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" "beq 10f\n" - "zip2 v18.8h, v22.8h, v21.8h\n" - "zip2 v17.8h, v20.8h, v19.8h\n" - "zip1 v16.8h, v18.8h, v17.8h\n" + "zip2 v17.8h, v22.8h, v21.8h\n" + "zip2 v16.8h, v20.8h, v19.8h\n" + "zip1 v16.8h, v17.8h, v16.8h\n" "str q16, [%x[out_ptr], #0x0]\n" "add v2.8h, v2.8h, v16.8h\n" "add %x[out_ptr], %x[out_ptr], #0x10\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp index d4d150456f..43d9d20c10 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_bf16_bf16.hpp @@ -79,29 +79,29 @@ void interleave_block<8, 2, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q28, [x28], #0x10\n" - "ldr q27, [x27], #0x10\n" + "ldr q20, [x28], #0x10\n" + "ldr q18, [x27], #0x10\n" "subs %x[width], %x[width], #0x8\n" "cmp %x[width], #0x8\n" - "ldr q22, [x26], #0x10\n" - "ldr q21, [x25], #0x10\n" - "zip1 v26.4s, v28.4s, v22.4s\n" - "zip1 v25.4s, v27.4s, v21.4s\n" - "ldr q24, [x24], #0x10\n" + "ldr q17, [x26], #0x10\n" + "ldr q16, [x25], #0x10\n" + "zip1 v25.4s, v20.4s, v17.4s\n" + "zip1 v24.4s, v18.4s, v16.4s\n" + "ldr q19, [x24], #0x10\n" "ldr q23, [x23], #0x10\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" - "ldr q19, [x22], #0x10\n" - "ldr q18, [x21], #0x10\n" - "zip1 v20.4s, v24.4s, v19.4s\n" - "zip1 v17.4s, v23.4s, v18.4s\n" - "zip2 v19.4s, v24.4s, v19.4s\n" - "zip2 v18.4s, v23.4s, v18.4s\n" + "zip2 v22.4s, v20.4s, v17.4s\n" + "zip2 v21.4s, v18.4s, v16.4s\n" + "ldr q18, [x22], #0x10\n" + "ldr q16, [x21], #0x10\n" + "zip1 v20.4s, v19.4s, v18.4s\n" + "zip1 v17.4s, v23.4s, v16.4s\n" + "zip2 v19.4s, v19.4s, v18.4s\n" + "zip2 v18.4s, v23.4s, v16.4s\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip1 v16.4s, v26.4s, v25.4s\n" + "zip1 v16.4s, v25.4s, v24.4s\n" "str q16, [%x[out_ptr], #0x0]\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" @@ -109,7 +109,7 @@ void interleave_block<8, 2, VLType::None, false>( "str q16, [%x[out_ptr], #0x10]\n" "prfm pldl1keep, [x22, #0x70]\n" "prfm pldl1keep, [x21, #0x70]\n" - "zip2 v16.4s, v26.4s, v25.4s\n" + "zip2 v16.4s, v25.4s, v24.4s\n" "str q16, [%x[out_ptr], #0x20]\n" "zip2 v16.4s, v20.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x30]\n" @@ -128,32 +128,32 @@ void interleave_block<8, 2, VLType::None, false>( "tbz %x[width], #2, 5f\n" "ldr d28, [x28], #0x8\n" "ldr d27, [x27], #0x8\n" - "ldr d22, [x26], #0x8\n" - "ldr d21, [x25], #0x8\n" + "ldr d26, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" "ldr d24, [x24], #0x8\n" "ldr d23, [x23], #0x8\n" - "ldr d19, [x22], #0x8\n" - "ldr d18, [x21], #0x8\n" + "ldr d22, [x22], #0x8\n" + "ldr d21, [x21], #0x8\n" "tbz %x[width], #1, 4f\n" "ld1 { v28.s }[2], [x28], #0x4\n" "ld1 { v27.s }[2], [x27], #0x4\n" "mov x20, #0x3\n" - "ld1 { v22.s }[2], [x26], #0x4\n" - "ld1 { v21.s }[2], [x25], #0x4\n" + "ld1 { v26.s }[2], [x26], #0x4\n" + "ld1 { v25.s }[2], [x25], #0x4\n" "ld1 { v24.s }[2], [x24], #0x4\n" "ld1 { v23.s }[2], [x23], #0x4\n" - "ld1 { v19.s }[2], [x22], #0x4\n" - "ld1 { v18.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x22], #0x4\n" + "ld1 { v21.s }[2], [x21], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v28.h }[6], [x28]\n" "ld1 { v27.h }[6], [x27]\n" "mov x20, #0x4\n" - "ld1 { v22.h }[6], [x26]\n" - "ld1 { v21.h }[6], [x25]\n" + "ld1 { v26.h }[6], [x26]\n" + "ld1 { v25.h }[6], [x25]\n" "ld1 { v24.h }[6], [x24]\n" "ld1 { v23.h }[6], [x23]\n" - "ld1 { v19.h }[6], [x22]\n" - "ld1 { v18.h }[6], [x21]\n" + "ld1 { v22.h }[6], [x22]\n" + "ld1 { v21.h }[6], [x21]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x20, #0x2\n" @@ -161,82 +161,81 @@ void interleave_block<8, 2, VLType::None, false>( "ld1 { v28.h }[4], [x28]\n" "ld1 { v27.h }[4], [x27]\n" "mov x20, #0x3\n" - "ld1 { v22.h }[4], [x26]\n" - "ld1 { v21.h }[4], [x25]\n" + "ld1 { v26.h }[4], [x26]\n" + "ld1 { v25.h }[4], [x25]\n" "ld1 { v24.h }[4], [x24]\n" "ld1 { v23.h }[4], [x23]\n" - "ld1 { v19.h }[4], [x22]\n" - "ld1 { v18.h }[4], [x21]\n" + "ld1 { v22.h }[4], [x22]\n" + "ld1 { v21.h }[4], [x21]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" "ldr s28, [x28], #0x4\n" "ldr s27, [x27], #0x4\n" "mov x20, #0x1\n" - "ldr s22, [x26], #0x4\n" - "ldr s21, [x25], #0x4\n" + "ldr s26, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" "ldr s24, [x24], #0x4\n" "ldr s23, [x23], #0x4\n" - "ldr s19, [x22], #0x4\n" - "ldr s18, [x21], #0x4\n" + "ldr s22, [x22], #0x4\n" + "ldr s21, [x21], #0x4\n" "tbz %x[width], #0, 7f\n" "ld1 { v28.h }[2], [x28]\n" "ld1 { v27.h }[2], [x27]\n" "mov x20, #0x2\n" - "ld1 { v22.h }[2], [x26]\n" - "ld1 { v21.h }[2], [x25]\n" + "ld1 { v26.h }[2], [x26]\n" + "ld1 { v25.h }[2], [x25]\n" "ld1 { v24.h }[2], [x24]\n" "ld1 { v23.h }[2], [x23]\n" - "ld1 { v19.h }[2], [x22]\n" - "ld1 { v18.h }[2], [x21]\n" + "ld1 { v22.h }[2], [x22]\n" + "ld1 { v21.h }[2], [x21]\n" "b 7f\n" "6:" // odd_loads_1_0 "ldr h28, [x28, #0x0]\n" "ldr h27, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h22, [x26, #0x0]\n" - "ldr h21, [x25, #0x0]\n" + "ldr h26, [x26, #0x0]\n" + "ldr h25, [x25, #0x0]\n" "ldr h24, [x24, #0x0]\n" "ldr h23, [x23, #0x0]\n" - "ldr h19, [x22, #0x0]\n" - "ldr h18, [x21, #0x0]\n" + "ldr h22, [x22, #0x0]\n" + "ldr h21, [x21, #0x0]\n" "7:" // Odd load end - "zip1 v26.4s, v28.4s, v22.4s\n" - "zip1 v25.4s, v27.4s, v21.4s\n" + "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v19.4s, v27.4s, v25.4s\n" "subs x20, x20, #0x1\n" - "zip1 v20.4s, v24.4s, v19.4s\n" - "zip1 v17.4s, v23.4s, v18.4s\n" - "zip1 v16.4s, v26.4s, v25.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v16.4s, v20.4s, v17.4s\n" + "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 8f\n" "subs x20, x20, #0x1\n" - "zip2 v16.4s, v26.4s, v25.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.4s, v20.4s, v17.4s\n" + "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 8f\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" + "zip2 v20.4s, v28.4s, v26.4s\n" + "zip2 v19.4s, v27.4s, v25.4s\n" "subs x20, x20, #0x1\n" - "zip2 v19.4s, v24.4s, v19.4s\n" - "zip2 v18.4s, v23.4s, v18.4s\n" - "zip1 v16.4s, v22.4s, v21.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v16.4s, v19.4s, v18.4s\n" + "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 8f\n" - "zip2 v17.4s, v22.4s, v21.4s\n" - "str q17, [%x[out_ptr], #0x0]\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" + "str q16, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "8:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp index 358b83ad1b..3ec03370a0 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block2_fp32_fp32.hpp @@ -79,18 +79,18 @@ void interleave_block<8, 2, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q26, [x28], #0x10\n" - "ldr q21, [x27], #0x10\n" + "ldr q20, [x28], #0x10\n" + "ldr q19, [x27], #0x10\n" "subs %x[width], %x[width], #0x4\n" "cmp %x[width], #0x4\n" "ldr q25, [x26], #0x10\n" "ldr q24, [x25], #0x10\n" - "zip1 v16.2d, v26.2d, v21.2d\n" + "zip1 v16.2d, v20.2d, v19.2d\n" "zip1 v18.2d, v25.2d, v24.2d\n" "ldr q23, [x24], #0x10\n" "ldr q22, [x23], #0x10\n" "zip1 v17.2d, v23.2d, v22.2d\n" - "zip2 v21.2d, v26.2d, v21.2d\n" + "zip2 v21.2d, v20.2d, v19.2d\n" "ldr q20, [x22], #0x10\n" "ldr q19, [x21], #0x10\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -118,62 +118,61 @@ void interleave_block<8, 2, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 6f\n" "tbz %x[width], #1, 4f\n" - "ldr d26, [x28], #0x8\n" - "ldr d21, [x27], #0x8\n" + "ldr d25, [x28], #0x8\n" + "ldr d24, [x27], #0x8\n" "mov x20, #0x1\n" - "ldr d25, [x26], #0x8\n" - "ldr d24, [x25], #0x8\n" - "ldr d23, [x24], #0x8\n" - "ldr d22, [x23], #0x8\n" - "ldr d20, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" + "ldr d23, [x26], #0x8\n" + "ldr d22, [x25], #0x8\n" + "ldr d21, [x24], #0x8\n" + "ldr d20, [x23], #0x8\n" + "ldr d19, [x22], #0x8\n" + "ldr d18, [x21], #0x8\n" "tbz %x[width], #0, 5f\n" - "ld1 { v26.s }[2], [x28]\n" - "ld1 { v21.s }[2], [x27]\n" + "ld1 { v25.s }[2], [x28]\n" + "ld1 { v24.s }[2], [x27]\n" "mov x20, #0x2\n" - "ld1 { v25.s }[2], [x26]\n" - "ld1 { v24.s }[2], [x25]\n" - "ld1 { v23.s }[2], [x24]\n" - "ld1 { v22.s }[2], [x23]\n" - "ld1 { v20.s }[2], [x22]\n" - "ld1 { v19.s }[2], [x21]\n" + "ld1 { v23.s }[2], [x26]\n" + "ld1 { v22.s }[2], [x25]\n" + "ld1 { v21.s }[2], [x24]\n" + "ld1 { v20.s }[2], [x23]\n" + "ld1 { v19.s }[2], [x22]\n" + "ld1 { v18.s }[2], [x21]\n" "b 5f\n" "4:" // odd_loads_1_0 - "ldr s26, [x28, #0x0]\n" - "ldr s21, [x27, #0x0]\n" + "ldr s25, [x28, #0x0]\n" + "ldr s24, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr s25, [x26, #0x0]\n" - "ldr s24, [x25, #0x0]\n" - "ldr s23, [x24, #0x0]\n" - "ldr s22, [x23, #0x0]\n" - "ldr s20, [x22, #0x0]\n" - "ldr s19, [x21, #0x0]\n" + "ldr s23, [x26, #0x0]\n" + "ldr s22, [x25, #0x0]\n" + "ldr s21, [x24, #0x0]\n" + "ldr s20, [x23, #0x0]\n" + "ldr s19, [x22, #0x0]\n" + "ldr s18, [x21, #0x0]\n" "5:" // Odd load end "subs x20, x20, #0x1\n" - "zip1 v16.2d, v26.2d, v21.2d\n" + "zip1 v16.2d, v25.2d, v24.2d\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.2d, v25.2d, v24.2d\n" - "str q18, [%x[out_ptr], #0x10]\n" - "zip1 v17.2d, v23.2d, v22.2d\n" - "zip1 v16.2d, v20.2d, v19.2d\n" + "zip1 v16.2d, v23.2d, v22.2d\n" + "str q16, [%x[out_ptr], #0x10]\n" + "zip1 v17.2d, v21.2d, v20.2d\n" + "zip1 v16.2d, v19.2d, v18.2d\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 6f\n" - "zip2 v21.2d, v26.2d, v21.2d\n" - "str q21, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v25.2d, v24.2d\n" - "str q18, [%x[out_ptr], #0x10]\n" - "zip2 v17.2d, v23.2d, v22.2d\n" - "zip2 v16.2d, v20.2d, v19.2d\n" + "zip2 v16.2d, v25.2d, v24.2d\n" + "str q16, [%x[out_ptr], #0x0]\n" + "zip2 v16.2d, v23.2d, v22.2d\n" + "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v17.2d, v21.2d, v20.2d\n" + "zip2 v16.2d, v19.2d, v18.2d\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "6:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp index d606d5a5b6..e9799f87a9 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_bf16_bf16.hpp @@ -79,18 +79,18 @@ void interleave_block<8, 4, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q26, [x28], #0x10\n" - "ldr q21, [x27], #0x10\n" + "ldr q20, [x28], #0x10\n" + "ldr q19, [x27], #0x10\n" "subs %x[width], %x[width], #0x8\n" "cmp %x[width], #0x8\n" "ldr q25, [x26], #0x10\n" "ldr q24, [x25], #0x10\n" - "zip1 v16.2d, v26.2d, v21.2d\n" + "zip1 v16.2d, v20.2d, v19.2d\n" "zip1 v18.2d, v25.2d, v24.2d\n" "ldr q23, [x24], #0x10\n" "ldr q22, [x23], #0x10\n" "zip1 v17.2d, v23.2d, v22.2d\n" - "zip2 v21.2d, v26.2d, v21.2d\n" + "zip2 v21.2d, v20.2d, v19.2d\n" "ldr q20, [x22], #0x10\n" "ldr q19, [x21], #0x10\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -118,104 +118,103 @@ void interleave_block<8, 4, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 8f\n" "tbz %x[width], #2, 5f\n" - "ldr d26, [x28], #0x8\n" - "ldr d21, [x27], #0x8\n" - "ldr d25, [x26], #0x8\n" - "ldr d24, [x25], #0x8\n" - "ldr d23, [x24], #0x8\n" - "ldr d22, [x23], #0x8\n" - "ldr d20, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" + "ldr d25, [x28], #0x8\n" + "ldr d24, [x27], #0x8\n" + "ldr d23, [x26], #0x8\n" + "ldr d22, [x25], #0x8\n" + "ldr d21, [x24], #0x8\n" + "ldr d20, [x23], #0x8\n" + "ldr d19, [x22], #0x8\n" + "ldr d18, [x21], #0x8\n" "tbz %x[width], #1, 4f\n" - "ld1 { v26.s }[2], [x28], #0x4\n" - "ld1 { v21.s }[2], [x27], #0x4\n" + "ld1 { v25.s }[2], [x28], #0x4\n" + "ld1 { v24.s }[2], [x27], #0x4\n" "mov x20, #0x2\n" - "ld1 { v25.s }[2], [x26], #0x4\n" - "ld1 { v24.s }[2], [x25], #0x4\n" - "ld1 { v23.s }[2], [x24], #0x4\n" - "ld1 { v22.s }[2], [x23], #0x4\n" - "ld1 { v20.s }[2], [x22], #0x4\n" - "ld1 { v19.s }[2], [x21], #0x4\n" + "ld1 { v23.s }[2], [x26], #0x4\n" + "ld1 { v22.s }[2], [x25], #0x4\n" + "ld1 { v21.s }[2], [x24], #0x4\n" + "ld1 { v20.s }[2], [x23], #0x4\n" + "ld1 { v19.s }[2], [x22], #0x4\n" + "ld1 { v18.s }[2], [x21], #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v26.h }[6], [x28]\n" - "ld1 { v21.h }[6], [x27]\n" - "ld1 { v25.h }[6], [x26]\n" - "ld1 { v24.h }[6], [x25]\n" - "ld1 { v23.h }[6], [x24]\n" - "ld1 { v22.h }[6], [x23]\n" - "ld1 { v20.h }[6], [x22]\n" - "ld1 { v19.h }[6], [x21]\n" + "ld1 { v25.h }[6], [x28]\n" + "ld1 { v24.h }[6], [x27]\n" + "ld1 { v23.h }[6], [x26]\n" + "ld1 { v22.h }[6], [x25]\n" + "ld1 { v21.h }[6], [x24]\n" + "ld1 { v20.h }[6], [x23]\n" + "ld1 { v19.h }[6], [x22]\n" + "ld1 { v18.h }[6], [x21]\n" "b 7f\n" "4:" // odd_loads_1_4 "mov x20, #0x1\n" "tbz %x[width], #0, 7f\n" - "ld1 { v26.h }[4], [x28]\n" - "ld1 { v21.h }[4], [x27]\n" + "ld1 { v25.h }[4], [x28]\n" + "ld1 { v24.h }[4], [x27]\n" "mov x20, #0x2\n" - "ld1 { v25.h }[4], [x26]\n" - "ld1 { v24.h }[4], [x25]\n" - "ld1 { v23.h }[4], [x24]\n" - "ld1 { v22.h }[4], [x23]\n" - "ld1 { v20.h }[4], [x22]\n" - "ld1 { v19.h }[4], [x21]\n" + "ld1 { v23.h }[4], [x26]\n" + "ld1 { v22.h }[4], [x25]\n" + "ld1 { v21.h }[4], [x24]\n" + "ld1 { v20.h }[4], [x23]\n" + "ld1 { v19.h }[4], [x22]\n" + "ld1 { v18.h }[4], [x21]\n" "b 7f\n" "5:" // odd_loads_2_0 "tbz %x[width], #1, 6f\n" - "ldr s26, [x28], #0x4\n" - "ldr s21, [x27], #0x4\n" + "ldr s25, [x28], #0x4\n" + "ldr s24, [x27], #0x4\n" "mov x20, #0x1\n" - "ldr s25, [x26], #0x4\n" - "ldr s24, [x25], #0x4\n" - "ldr s23, [x24], #0x4\n" - "ldr s22, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" + "ldr s23, [x26], #0x4\n" + "ldr s22, [x25], #0x4\n" + "ldr s21, [x24], #0x4\n" + "ldr s20, [x23], #0x4\n" + "ldr s19, [x22], #0x4\n" + "ldr s18, [x21], #0x4\n" "tbz %x[width], #0, 7f\n" - "ld1 { v26.h }[2], [x28]\n" - "ld1 { v21.h }[2], [x27]\n" - "ld1 { v25.h }[2], [x26]\n" - "ld1 { v24.h }[2], [x25]\n" - "ld1 { v23.h }[2], [x24]\n" - "ld1 { v22.h }[2], [x23]\n" - "ld1 { v20.h }[2], [x22]\n" - "ld1 { v19.h }[2], [x21]\n" + "ld1 { v25.h }[2], [x28]\n" + "ld1 { v24.h }[2], [x27]\n" + "ld1 { v23.h }[2], [x26]\n" + "ld1 { v22.h }[2], [x25]\n" + "ld1 { v21.h }[2], [x24]\n" + "ld1 { v20.h }[2], [x23]\n" + "ld1 { v19.h }[2], [x22]\n" + "ld1 { v18.h }[2], [x21]\n" "b 7f\n" "6:" // odd_loads_1_0 - "ldr h26, [x28, #0x0]\n" - "ldr h21, [x27, #0x0]\n" + "ldr h25, [x28, #0x0]\n" + "ldr h24, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr h25, [x26, #0x0]\n" - "ldr h24, [x25, #0x0]\n" - "ldr h23, [x24, #0x0]\n" - "ldr h22, [x23, #0x0]\n" - "ldr h20, [x22, #0x0]\n" - "ldr h19, [x21, #0x0]\n" + "ldr h23, [x26, #0x0]\n" + "ldr h22, [x25, #0x0]\n" + "ldr h21, [x24, #0x0]\n" + "ldr h20, [x23, #0x0]\n" + "ldr h19, [x22, #0x0]\n" + "ldr h18, [x21, #0x0]\n" "7:" // Odd load end "subs x20, x20, #0x1\n" - "zip1 v16.2d, v26.2d, v21.2d\n" + "zip1 v16.2d, v25.2d, v24.2d\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.2d, v25.2d, v24.2d\n" - "str q18, [%x[out_ptr], #0x10]\n" - "zip1 v17.2d, v23.2d, v22.2d\n" - "zip1 v16.2d, v20.2d, v19.2d\n" + "zip1 v16.2d, v23.2d, v22.2d\n" + "str q16, [%x[out_ptr], #0x10]\n" + "zip1 v17.2d, v21.2d, v20.2d\n" + "zip1 v16.2d, v19.2d, v18.2d\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 8f\n" - "zip2 v21.2d, v26.2d, v21.2d\n" - "str q21, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v25.2d, v24.2d\n" - "str q18, [%x[out_ptr], #0x10]\n" - "zip2 v17.2d, v23.2d, v22.2d\n" - "zip2 v16.2d, v20.2d, v19.2d\n" + "zip2 v16.2d, v25.2d, v24.2d\n" + "str q16, [%x[out_ptr], #0x0]\n" + "zip2 v16.2d, v23.2d, v22.2d\n" + "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v17.2d, v21.2d, v20.2d\n" + "zip2 v16.2d, v19.2d, v18.2d\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "8:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_fp32_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_fp32_bf16.hpp index dfec14358b..730bfd6342 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_fp32_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_fp32_bf16.hpp @@ -79,14 +79,14 @@ void interleave_block<8, 4, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q23, [x28], #0x10\n" - "ldr q22, [x26], #0x10\n" - ".inst 0x0ea16af7 // bfcvtn v23.4h, v23.4s\n" - ".inst 0x0ea16ad6 // bfcvtn v22.4h, v22.4s\n" - "ldr q21, [x24], #0x10\n" - "ldr q20, [x22], #0x10\n" - ".inst 0x0ea16ab5 // bfcvtn v21.4h, v21.4s\n" - ".inst 0x0ea16a94 // bfcvtn v20.4h, v20.4s\n" + "ldr q17, [x28], #0x10\n" + "ldr q16, [x26], #0x10\n" + ".inst 0x0ea16a37 // bfcvtn v23.4h, v17.4s\n" + ".inst 0x0ea16a16 // bfcvtn v22.4h, v16.4s\n" + "ldr q17, [x24], #0x10\n" + "ldr q16, [x22], #0x10\n" + ".inst 0x0ea16a35 // bfcvtn v21.4h, v17.4s\n" + ".inst 0x0ea16a14 // bfcvtn v20.4h, v16.4s\n" "ldr q19, [x27], #0x10\n" "ldr q18, [x25], #0x10\n" "subs %x[width], %x[width], #0x4\n" @@ -114,51 +114,50 @@ void interleave_block<8, 4, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 6f\n" "tbz %x[width], #1, 4f\n" - "ldr d23, [x28], #0x8\n" - "ldr d19, [x27], #0x8\n" + "ldr d19, [x28], #0x8\n" + "ldr d23, [x27], #0x8\n" "mov x20, #0x1\n" - "ldr d22, [x26], #0x8\n" - "ldr d18, [x25], #0x8\n" - "ldr d21, [x24], #0x8\n" - "ldr d17, [x23], #0x8\n" - "ldr d20, [x22], #0x8\n" - "ldr d16, [x21], #0x8\n" + "ldr d18, [x26], #0x8\n" + "ldr d22, [x25], #0x8\n" + "ldr d17, [x24], #0x8\n" + "ldr d21, [x23], #0x8\n" + "ldr d16, [x22], #0x8\n" + "ldr d20, [x21], #0x8\n" "tbz %x[width], #0, 5f\n" - "ld1 { v23.s }[2], [x28]\n" - "ld1 { v19.s }[2], [x27]\n" - "ld1 { v22.s }[2], [x26]\n" - "ld1 { v18.s }[2], [x25]\n" - "ld1 { v21.s }[2], [x24]\n" - "ld1 { v17.s }[2], [x23]\n" - "ld1 { v20.s }[2], [x22]\n" - "ld1 { v16.s }[2], [x21]\n" + "ld1 { v19.s }[2], [x28]\n" + "ld1 { v23.s }[2], [x27]\n" + "ld1 { v18.s }[2], [x26]\n" + "ld1 { v22.s }[2], [x25]\n" + "ld1 { v17.s }[2], [x24]\n" + "ld1 { v21.s }[2], [x23]\n" + "ld1 { v16.s }[2], [x22]\n" + "ld1 { v20.s }[2], [x21]\n" "b 5f\n" "4:" // odd_loads_1_0 - "ldr s23, [x28, #0x0]\n" - "ldr s19, [x27, #0x0]\n" + "ldr s19, [x28, #0x0]\n" + "ldr s23, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr s22, [x26, #0x0]\n" - "ldr s18, [x25, #0x0]\n" - "ldr s21, [x24, #0x0]\n" - "ldr s17, [x23, #0x0]\n" - "ldr s20, [x22, #0x0]\n" - "ldr s16, [x21, #0x0]\n" + "ldr s18, [x26, #0x0]\n" + "ldr s22, [x25, #0x0]\n" + "ldr s17, [x24, #0x0]\n" + "ldr s21, [x23, #0x0]\n" + "ldr s16, [x22, #0x0]\n" + "ldr s20, [x21, #0x0]\n" "5:" // Odd load end - ".inst 0x0ea16af7 // bfcvtn v23.4h, v23.4s\n" - ".inst 0x0ea16ad6 // bfcvtn v22.4h, v22.4s\n" - ".inst 0x0ea16ab5 // bfcvtn v21.4h, v21.4s\n" - ".inst 0x0ea16a94 // bfcvtn v20.4h, v20.4s\n" - ".inst 0x4ea16a77 // bfcvtn2 v23.8h, v19.4s\n" - ".inst 0x4ea16a56 // bfcvtn2 v22.8h, v18.4s\n" - "str q23, [%x[out_ptr], #0x0]\n" - ".inst 0x4ea16a35 // bfcvtn2 v21.8h, v17.4s\n" - ".inst 0x4ea16a14 // bfcvtn2 v20.8h, v16.4s\n" - "str q22, [%x[out_ptr], #0x10]\n" - "str q21, [%x[out_ptr], #0x20]\n" - "str q20, [%x[out_ptr], #0x30]\n" + ".inst 0x0ea16a73 // bfcvtn v19.4h, v19.4s\n" + ".inst 0x0ea16a52 // bfcvtn v18.4h, v18.4s\n" + ".inst 0x0ea16a31 // bfcvtn v17.4h, v17.4s\n" + ".inst 0x0ea16a10 // bfcvtn v16.4h, v16.4s\n" + ".inst 0x4ea16af3 // bfcvtn2 v19.8h, v23.4s\n" + ".inst 0x4ea16ad2 // bfcvtn2 v18.8h, v22.4s\n" + "str q19, [%x[out_ptr], #0x0]\n" + ".inst 0x4ea16ab1 // bfcvtn2 v17.8h, v21.4s\n" + ".inst 0x4ea16a90 // bfcvtn2 v16.8h, v20.4s\n" + "str q18, [%x[out_ptr], #0x10]\n" + "str q17, [%x[out_ptr], #0x20]\n" + "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "6:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp index 54f15f8a5c..15d8ddbe53 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8.hpp @@ -79,29 +79,29 @@ void interleave_block<8, 4, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q28, [x28], #0x10\n" - "ldr q27, [x27], #0x10\n" + "ldr q20, [x28], #0x10\n" + "ldr q18, [x27], #0x10\n" "subs %x[width], %x[width], #0x10\n" "cmp %x[width], #0x10\n" - "ldr q22, [x26], #0x10\n" - "ldr q21, [x25], #0x10\n" - "zip1 v26.4s, v28.4s, v22.4s\n" - "zip1 v25.4s, v27.4s, v21.4s\n" - "ldr q24, [x24], #0x10\n" + "ldr q17, [x26], #0x10\n" + "ldr q16, [x25], #0x10\n" + "zip1 v25.4s, v20.4s, v17.4s\n" + "zip1 v24.4s, v18.4s, v16.4s\n" + "ldr q19, [x24], #0x10\n" "ldr q23, [x23], #0x10\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" - "ldr q19, [x22], #0x10\n" - "ldr q18, [x21], #0x10\n" - "zip1 v20.4s, v24.4s, v19.4s\n" - "zip1 v17.4s, v23.4s, v18.4s\n" - "zip2 v19.4s, v24.4s, v19.4s\n" - "zip2 v18.4s, v23.4s, v18.4s\n" + "zip2 v22.4s, v20.4s, v17.4s\n" + "zip2 v21.4s, v18.4s, v16.4s\n" + "ldr q18, [x22], #0x10\n" + "ldr q16, [x21], #0x10\n" + "zip1 v20.4s, v19.4s, v18.4s\n" + "zip1 v17.4s, v23.4s, v16.4s\n" + "zip2 v19.4s, v19.4s, v18.4s\n" + "zip2 v18.4s, v23.4s, v16.4s\n" "prfm pldl1keep, [x28, #0x70]\n" "prfm pldl1keep, [x27, #0x70]\n" "prfm pldl1keep, [x26, #0x70]\n" "prfm pldl1keep, [x25, #0x70]\n" - "zip1 v16.4s, v26.4s, v25.4s\n" + "zip1 v16.4s, v25.4s, v24.4s\n" "str q16, [%x[out_ptr], #0x0]\n" "prfm pldl1keep, [x24, #0x70]\n" "prfm pldl1keep, [x23, #0x70]\n" @@ -109,7 +109,7 @@ void interleave_block<8, 4, VLType::None, false>( "str q16, [%x[out_ptr], #0x10]\n" "prfm pldl1keep, [x22, #0x70]\n" "prfm pldl1keep, [x21, #0x70]\n" - "zip2 v16.4s, v26.4s, v25.4s\n" + "zip2 v16.4s, v25.4s, v24.4s\n" "str q16, [%x[out_ptr], #0x20]\n" "zip2 v16.4s, v20.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x30]\n" @@ -128,40 +128,40 @@ void interleave_block<8, 4, VLType::None, false>( "tbz %x[width], #3, 7f\n" "ldr d28, [x28], #0x8\n" "ldr d27, [x27], #0x8\n" - "ldr d22, [x26], #0x8\n" - "ldr d21, [x25], #0x8\n" + "ldr d26, [x26], #0x8\n" + "ldr d25, [x25], #0x8\n" "ldr d24, [x24], #0x8\n" "ldr d23, [x23], #0x8\n" - "ldr d19, [x22], #0x8\n" - "ldr d18, [x21], #0x8\n" + "ldr d22, [x22], #0x8\n" + "ldr d21, [x21], #0x8\n" "tbz %x[width], #2, 5f\n" "ld1 { v28.s }[2], [x28], #0x4\n" "ld1 { v27.s }[2], [x27], #0x4\n" - "ld1 { v22.s }[2], [x26], #0x4\n" - "ld1 { v21.s }[2], [x25], #0x4\n" + "ld1 { v26.s }[2], [x26], #0x4\n" + "ld1 { v25.s }[2], [x25], #0x4\n" "ld1 { v24.s }[2], [x24], #0x4\n" "ld1 { v23.s }[2], [x23], #0x4\n" - "ld1 { v19.s }[2], [x22], #0x4\n" - "ld1 { v18.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x22], #0x4\n" + "ld1 { v21.s }[2], [x21], #0x4\n" "tbz %x[width], #1, 4f\n" "ld1 { v28.h }[6], [x28], #0x2\n" "ld1 { v27.h }[6], [x27], #0x2\n" "mov x20, #0x4\n" - "ld1 { v22.h }[6], [x26], #0x2\n" - "ld1 { v21.h }[6], [x25], #0x2\n" + "ld1 { v26.h }[6], [x26], #0x2\n" + "ld1 { v25.h }[6], [x25], #0x2\n" "ld1 { v24.h }[6], [x24], #0x2\n" "ld1 { v23.h }[6], [x23], #0x2\n" - "ld1 { v19.h }[6], [x22], #0x2\n" - "ld1 { v18.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x22], #0x2\n" + "ld1 { v21.h }[6], [x21], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[14], [x28]\n" "ld1 { v27.b }[14], [x27]\n" - "ld1 { v22.b }[14], [x26]\n" - "ld1 { v21.b }[14], [x25]\n" + "ld1 { v26.b }[14], [x26]\n" + "ld1 { v25.b }[14], [x25]\n" "ld1 { v24.b }[14], [x24]\n" "ld1 { v23.b }[14], [x23]\n" - "ld1 { v19.b }[14], [x22]\n" - "ld1 { v18.b }[14], [x21]\n" + "ld1 { v22.b }[14], [x22]\n" + "ld1 { v21.b }[14], [x21]\n" "b 11f\n" "4:" // odd_loads_1_12 "mov x20, #0x3\n" @@ -169,33 +169,33 @@ void interleave_block<8, 4, VLType::None, false>( "ld1 { v28.b }[12], [x28]\n" "ld1 { v27.b }[12], [x27]\n" "mov x20, #0x4\n" - "ld1 { v22.b }[12], [x26]\n" - "ld1 { v21.b }[12], [x25]\n" + "ld1 { v26.b }[12], [x26]\n" + "ld1 { v25.b }[12], [x25]\n" "ld1 { v24.b }[12], [x24]\n" "ld1 { v23.b }[12], [x23]\n" - "ld1 { v19.b }[12], [x22]\n" - "ld1 { v18.b }[12], [x21]\n" + "ld1 { v22.b }[12], [x22]\n" + "ld1 { v21.b }[12], [x21]\n" "b 11f\n" "5:" // odd_loads_2_8 "tbz %x[width], #1, 6f\n" "ld1 { v28.h }[4], [x28], #0x2\n" "ld1 { v27.h }[4], [x27], #0x2\n" "mov x20, #0x3\n" - "ld1 { v22.h }[4], [x26], #0x2\n" - "ld1 { v21.h }[4], [x25], #0x2\n" + "ld1 { v26.h }[4], [x26], #0x2\n" + "ld1 { v25.h }[4], [x25], #0x2\n" "ld1 { v24.h }[4], [x24], #0x2\n" "ld1 { v23.h }[4], [x23], #0x2\n" - "ld1 { v19.h }[4], [x22], #0x2\n" - "ld1 { v18.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x22], #0x2\n" + "ld1 { v21.h }[4], [x21], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[10], [x28]\n" "ld1 { v27.b }[10], [x27]\n" - "ld1 { v22.b }[10], [x26]\n" - "ld1 { v21.b }[10], [x25]\n" + "ld1 { v26.b }[10], [x26]\n" + "ld1 { v25.b }[10], [x25]\n" "ld1 { v24.b }[10], [x24]\n" "ld1 { v23.b }[10], [x23]\n" - "ld1 { v19.b }[10], [x22]\n" - "ld1 { v18.b }[10], [x21]\n" + "ld1 { v22.b }[10], [x22]\n" + "ld1 { v21.b }[10], [x21]\n" "b 11f\n" "6:" // odd_loads_1_8 "mov x20, #0x2\n" @@ -203,42 +203,42 @@ void interleave_block<8, 4, VLType::None, false>( "ld1 { v28.b }[8], [x28]\n" "ld1 { v27.b }[8], [x27]\n" "mov x20, #0x3\n" - "ld1 { v22.b }[8], [x26]\n" - "ld1 { v21.b }[8], [x25]\n" + "ld1 { v26.b }[8], [x26]\n" + "ld1 { v25.b }[8], [x25]\n" "ld1 { v24.b }[8], [x24]\n" "ld1 { v23.b }[8], [x23]\n" - "ld1 { v19.b }[8], [x22]\n" - "ld1 { v18.b }[8], [x21]\n" + "ld1 { v22.b }[8], [x22]\n" + "ld1 { v21.b }[8], [x21]\n" "b 11f\n" "7:" // odd_loads_4_0 "tbz %x[width], #2, 9f\n" "ldr s28, [x28], #0x4\n" "ldr s27, [x27], #0x4\n" - "ldr s22, [x26], #0x4\n" - "ldr s21, [x25], #0x4\n" + "ldr s26, [x26], #0x4\n" + "ldr s25, [x25], #0x4\n" "ldr s24, [x24], #0x4\n" "ldr s23, [x23], #0x4\n" - "ldr s19, [x22], #0x4\n" - "ldr s18, [x21], #0x4\n" + "ldr s22, [x22], #0x4\n" + "ldr s21, [x21], #0x4\n" "tbz %x[width], #1, 8f\n" "ld1 { v28.h }[2], [x28], #0x2\n" "ld1 { v27.h }[2], [x27], #0x2\n" "mov x20, #0x2\n" - "ld1 { v22.h }[2], [x26], #0x2\n" - "ld1 { v21.h }[2], [x25], #0x2\n" + "ld1 { v26.h }[2], [x26], #0x2\n" + "ld1 { v25.h }[2], [x25], #0x2\n" "ld1 { v24.h }[2], [x24], #0x2\n" "ld1 { v23.h }[2], [x23], #0x2\n" - "ld1 { v19.h }[2], [x22], #0x2\n" - "ld1 { v18.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x22], #0x2\n" + "ld1 { v21.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[6], [x28]\n" "ld1 { v27.b }[6], [x27]\n" - "ld1 { v22.b }[6], [x26]\n" - "ld1 { v21.b }[6], [x25]\n" + "ld1 { v26.b }[6], [x26]\n" + "ld1 { v25.b }[6], [x25]\n" "ld1 { v24.b }[6], [x24]\n" "ld1 { v23.b }[6], [x23]\n" - "ld1 { v19.b }[6], [x22]\n" - "ld1 { v18.b }[6], [x21]\n" + "ld1 { v22.b }[6], [x22]\n" + "ld1 { v21.b }[6], [x21]\n" "b 11f\n" "8:" // odd_loads_1_4 "mov x20, #0x1\n" @@ -246,81 +246,80 @@ void interleave_block<8, 4, VLType::None, false>( "ld1 { v28.b }[4], [x28]\n" "ld1 { v27.b }[4], [x27]\n" "mov x20, #0x2\n" - "ld1 { v22.b }[4], [x26]\n" - "ld1 { v21.b }[4], [x25]\n" + "ld1 { v26.b }[4], [x26]\n" + "ld1 { v25.b }[4], [x25]\n" "ld1 { v24.b }[4], [x24]\n" "ld1 { v23.b }[4], [x23]\n" - "ld1 { v19.b }[4], [x22]\n" - "ld1 { v18.b }[4], [x21]\n" + "ld1 { v22.b }[4], [x22]\n" + "ld1 { v21.b }[4], [x21]\n" "b 11f\n" "9:" // odd_loads_2_0 "tbz %x[width], #1, 10f\n" "ldr h28, [x28], #0x2\n" "ldr h27, [x27], #0x2\n" "mov x20, #0x1\n" - "ldr h22, [x26], #0x2\n" - "ldr h21, [x25], #0x2\n" + "ldr h26, [x26], #0x2\n" + "ldr h25, [x25], #0x2\n" "ldr h24, [x24], #0x2\n" "ldr h23, [x23], #0x2\n" - "ldr h19, [x22], #0x2\n" - "ldr h18, [x21], #0x2\n" + "ldr h22, [x22], #0x2\n" + "ldr h21, [x21], #0x2\n" "tbz %x[width], #0, 11f\n" "ld1 { v28.b }[2], [x28]\n" "ld1 { v27.b }[2], [x27]\n" - "ld1 { v22.b }[2], [x26]\n" - "ld1 { v21.b }[2], [x25]\n" + "ld1 { v26.b }[2], [x26]\n" + "ld1 { v25.b }[2], [x25]\n" "ld1 { v24.b }[2], [x24]\n" "ld1 { v23.b }[2], [x23]\n" - "ld1 { v19.b }[2], [x22]\n" - "ld1 { v18.b }[2], [x21]\n" + "ld1 { v22.b }[2], [x22]\n" + "ld1 { v21.b }[2], [x21]\n" "b 11f\n" "10:" // odd_loads_1_0 "ldr b28, [x28, #0x0]\n" "ldr b27, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b22, [x26, #0x0]\n" - "ldr b21, [x25, #0x0]\n" + "ldr b26, [x26, #0x0]\n" + "ldr b25, [x25, #0x0]\n" "ldr b24, [x24, #0x0]\n" "ldr b23, [x23, #0x0]\n" - "ldr b19, [x22, #0x0]\n" - "ldr b18, [x21, #0x0]\n" + "ldr b22, [x22, #0x0]\n" + "ldr b21, [x21, #0x0]\n" "11:" // Odd load end - "zip1 v26.4s, v28.4s, v22.4s\n" - "zip1 v25.4s, v27.4s, v21.4s\n" + "zip1 v20.4s, v28.4s, v26.4s\n" + "zip1 v19.4s, v27.4s, v25.4s\n" "subs x20, x20, #0x1\n" - "zip1 v20.4s, v24.4s, v19.4s\n" - "zip1 v17.4s, v23.4s, v18.4s\n" - "zip1 v16.4s, v26.4s, v25.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v16.4s, v20.4s, v17.4s\n" + "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 12f\n" "subs x20, x20, #0x1\n" - "zip2 v16.4s, v26.4s, v25.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip2 v16.4s, v20.4s, v17.4s\n" + "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 12f\n" - "zip2 v22.4s, v28.4s, v22.4s\n" - "zip2 v21.4s, v27.4s, v21.4s\n" + "zip2 v20.4s, v28.4s, v26.4s\n" + "zip2 v19.4s, v27.4s, v25.4s\n" "subs x20, x20, #0x1\n" - "zip2 v19.4s, v24.4s, v19.4s\n" - "zip2 v18.4s, v23.4s, v18.4s\n" - "zip1 v16.4s, v22.4s, v21.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip2 v17.4s, v23.4s, v21.4s\n" + "zip1 v16.4s, v20.4s, v19.4s\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v16.4s, v19.4s, v18.4s\n" + "zip1 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 12f\n" - "zip2 v17.4s, v22.4s, v21.4s\n" - "str q17, [%x[out_ptr], #0x0]\n" - "zip2 v16.4s, v19.4s, v18.4s\n" + "zip2 v16.4s, v20.4s, v19.4s\n" + "str q16, [%x[out_ptr], #0x0]\n" + "zip2 v16.4s, v18.4s, v17.4s\n" "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "12:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp index 2db54126c0..6c41b5fdfb 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_s8_s8_summing.hpp @@ -153,202 +153,202 @@ void interleave_block<8, 4, VLType::None, true>( "5:" // Main loop skip "cbz %x[width], 14f\n" "tbz %x[width], #3, 9f\n" - "ldr d30, [x28], #0x8\n" - "ldr d29, [x27], #0x8\n" - "ldr d28, [x26], #0x8\n" - "ldr d27, [x25], #0x8\n" - "ldr d20, [x24], #0x8\n" - "ldr d26, [x23], #0x8\n" - "ldr d19, [x22], #0x8\n" - "ldr d18, [x21], #0x8\n" + "ldr d29, [x28], #0x8\n" + "ldr d28, [x27], #0x8\n" + "ldr d27, [x26], #0x8\n" + "ldr d26, [x25], #0x8\n" + "ldr d25, [x24], #0x8\n" + "ldr d24, [x23], #0x8\n" + "ldr d23, [x22], #0x8\n" + "ldr d22, [x21], #0x8\n" "tbz %x[width], #2, 7f\n" - "ld1 { v30.s }[2], [x28], #0x4\n" - "ld1 { v29.s }[2], [x27], #0x4\n" - "ld1 { v28.s }[2], [x26], #0x4\n" - "ld1 { v27.s }[2], [x25], #0x4\n" - "ld1 { v20.s }[2], [x24], #0x4\n" - "ld1 { v26.s }[2], [x23], #0x4\n" - "ld1 { v19.s }[2], [x22], #0x4\n" - "ld1 { v18.s }[2], [x21], #0x4\n" + "ld1 { v29.s }[2], [x28], #0x4\n" + "ld1 { v28.s }[2], [x27], #0x4\n" + "ld1 { v27.s }[2], [x26], #0x4\n" + "ld1 { v26.s }[2], [x25], #0x4\n" + "ld1 { v25.s }[2], [x24], #0x4\n" + "ld1 { v24.s }[2], [x23], #0x4\n" + "ld1 { v23.s }[2], [x22], #0x4\n" + "ld1 { v22.s }[2], [x21], #0x4\n" "tbz %x[width], #1, 6f\n" - "ld1 { v30.h }[6], [x28], #0x2\n" - "ld1 { v29.h }[6], [x27], #0x2\n" + "ld1 { v29.h }[6], [x28], #0x2\n" + "ld1 { v28.h }[6], [x27], #0x2\n" "mov x20, #0x4\n" - "ld1 { v28.h }[6], [x26], #0x2\n" - "ld1 { v27.h }[6], [x25], #0x2\n" - "ld1 { v20.h }[6], [x24], #0x2\n" - "ld1 { v26.h }[6], [x23], #0x2\n" - "ld1 { v19.h }[6], [x22], #0x2\n" - "ld1 { v18.h }[6], [x21], #0x2\n" + "ld1 { v27.h }[6], [x26], #0x2\n" + "ld1 { v26.h }[6], [x25], #0x2\n" + "ld1 { v25.h }[6], [x24], #0x2\n" + "ld1 { v24.h }[6], [x23], #0x2\n" + "ld1 { v23.h }[6], [x22], #0x2\n" + "ld1 { v22.h }[6], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[14], [x28]\n" - "ld1 { v29.b }[14], [x27]\n" - "ld1 { v28.b }[14], [x26]\n" - "ld1 { v27.b }[14], [x25]\n" - "ld1 { v20.b }[14], [x24]\n" - "ld1 { v26.b }[14], [x23]\n" - "ld1 { v19.b }[14], [x22]\n" - "ld1 { v18.b }[14], [x21]\n" + "ld1 { v29.b }[14], [x28]\n" + "ld1 { v28.b }[14], [x27]\n" + "ld1 { v27.b }[14], [x26]\n" + "ld1 { v26.b }[14], [x25]\n" + "ld1 { v25.b }[14], [x24]\n" + "ld1 { v24.b }[14], [x23]\n" + "ld1 { v23.b }[14], [x22]\n" + "ld1 { v22.b }[14], [x21]\n" "b 13f\n" "6:" // odd_loads_1_12 "mov x20, #0x3\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[12], [x28]\n" - "ld1 { v29.b }[12], [x27]\n" + "ld1 { v29.b }[12], [x28]\n" + "ld1 { v28.b }[12], [x27]\n" "mov x20, #0x4\n" - "ld1 { v28.b }[12], [x26]\n" - "ld1 { v27.b }[12], [x25]\n" - "ld1 { v20.b }[12], [x24]\n" - "ld1 { v26.b }[12], [x23]\n" - "ld1 { v19.b }[12], [x22]\n" - "ld1 { v18.b }[12], [x21]\n" + "ld1 { v27.b }[12], [x26]\n" + "ld1 { v26.b }[12], [x25]\n" + "ld1 { v25.b }[12], [x24]\n" + "ld1 { v24.b }[12], [x23]\n" + "ld1 { v23.b }[12], [x22]\n" + "ld1 { v22.b }[12], [x21]\n" "b 13f\n" "7:" // odd_loads_2_8 "tbz %x[width], #1, 8f\n" - "ld1 { v30.h }[4], [x28], #0x2\n" - "ld1 { v29.h }[4], [x27], #0x2\n" + "ld1 { v29.h }[4], [x28], #0x2\n" + "ld1 { v28.h }[4], [x27], #0x2\n" "mov x20, #0x3\n" - "ld1 { v28.h }[4], [x26], #0x2\n" - "ld1 { v27.h }[4], [x25], #0x2\n" - "ld1 { v20.h }[4], [x24], #0x2\n" - "ld1 { v26.h }[4], [x23], #0x2\n" - "ld1 { v19.h }[4], [x22], #0x2\n" - "ld1 { v18.h }[4], [x21], #0x2\n" + "ld1 { v27.h }[4], [x26], #0x2\n" + "ld1 { v26.h }[4], [x25], #0x2\n" + "ld1 { v25.h }[4], [x24], #0x2\n" + "ld1 { v24.h }[4], [x23], #0x2\n" + "ld1 { v23.h }[4], [x22], #0x2\n" + "ld1 { v22.h }[4], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[10], [x28]\n" - "ld1 { v29.b }[10], [x27]\n" - "ld1 { v28.b }[10], [x26]\n" - "ld1 { v27.b }[10], [x25]\n" - "ld1 { v20.b }[10], [x24]\n" - "ld1 { v26.b }[10], [x23]\n" - "ld1 { v19.b }[10], [x22]\n" - "ld1 { v18.b }[10], [x21]\n" + "ld1 { v29.b }[10], [x28]\n" + "ld1 { v28.b }[10], [x27]\n" + "ld1 { v27.b }[10], [x26]\n" + "ld1 { v26.b }[10], [x25]\n" + "ld1 { v25.b }[10], [x24]\n" + "ld1 { v24.b }[10], [x23]\n" + "ld1 { v23.b }[10], [x22]\n" + "ld1 { v22.b }[10], [x21]\n" "b 13f\n" "8:" // odd_loads_1_8 "mov x20, #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[8], [x28]\n" - "ld1 { v29.b }[8], [x27]\n" + "ld1 { v29.b }[8], [x28]\n" + "ld1 { v28.b }[8], [x27]\n" "mov x20, #0x3\n" - "ld1 { v28.b }[8], [x26]\n" - "ld1 { v27.b }[8], [x25]\n" - "ld1 { v20.b }[8], [x24]\n" - "ld1 { v26.b }[8], [x23]\n" - "ld1 { v19.b }[8], [x22]\n" - "ld1 { v18.b }[8], [x21]\n" + "ld1 { v27.b }[8], [x26]\n" + "ld1 { v26.b }[8], [x25]\n" + "ld1 { v25.b }[8], [x24]\n" + "ld1 { v24.b }[8], [x23]\n" + "ld1 { v23.b }[8], [x22]\n" + "ld1 { v22.b }[8], [x21]\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" - "ldr s30, [x28], #0x4\n" - "ldr s29, [x27], #0x4\n" - "ldr s28, [x26], #0x4\n" - "ldr s27, [x25], #0x4\n" - "ldr s20, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" - "ldr s19, [x22], #0x4\n" - "ldr s18, [x21], #0x4\n" + "ldr s29, [x28], #0x4\n" + "ldr s28, [x27], #0x4\n" + "ldr s27, [x26], #0x4\n" + "ldr s26, [x25], #0x4\n" + "ldr s25, [x24], #0x4\n" + "ldr s24, [x23], #0x4\n" + "ldr s23, [x22], #0x4\n" + "ldr s22, [x21], #0x4\n" "tbz %x[width], #1, 10f\n" - "ld1 { v30.h }[2], [x28], #0x2\n" - "ld1 { v29.h }[2], [x27], #0x2\n" + "ld1 { v29.h }[2], [x28], #0x2\n" + "ld1 { v28.h }[2], [x27], #0x2\n" "mov x20, #0x2\n" - "ld1 { v28.h }[2], [x26], #0x2\n" - "ld1 { v27.h }[2], [x25], #0x2\n" - "ld1 { v20.h }[2], [x24], #0x2\n" - "ld1 { v26.h }[2], [x23], #0x2\n" - "ld1 { v19.h }[2], [x22], #0x2\n" - "ld1 { v18.h }[2], [x21], #0x2\n" + "ld1 { v27.h }[2], [x26], #0x2\n" + "ld1 { v26.h }[2], [x25], #0x2\n" + "ld1 { v25.h }[2], [x24], #0x2\n" + "ld1 { v24.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x22], #0x2\n" + "ld1 { v22.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[6], [x28]\n" - "ld1 { v29.b }[6], [x27]\n" - "ld1 { v28.b }[6], [x26]\n" - "ld1 { v27.b }[6], [x25]\n" - "ld1 { v20.b }[6], [x24]\n" - "ld1 { v26.b }[6], [x23]\n" - "ld1 { v19.b }[6], [x22]\n" - "ld1 { v18.b }[6], [x21]\n" + "ld1 { v29.b }[6], [x28]\n" + "ld1 { v28.b }[6], [x27]\n" + "ld1 { v27.b }[6], [x26]\n" + "ld1 { v26.b }[6], [x25]\n" + "ld1 { v25.b }[6], [x24]\n" + "ld1 { v24.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x22]\n" + "ld1 { v22.b }[6], [x21]\n" "b 13f\n" "10:" // odd_loads_1_4 "mov x20, #0x1\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[4], [x28]\n" - "ld1 { v29.b }[4], [x27]\n" + "ld1 { v29.b }[4], [x28]\n" + "ld1 { v28.b }[4], [x27]\n" "mov x20, #0x2\n" - "ld1 { v28.b }[4], [x26]\n" - "ld1 { v27.b }[4], [x25]\n" - "ld1 { v20.b }[4], [x24]\n" - "ld1 { v26.b }[4], [x23]\n" - "ld1 { v19.b }[4], [x22]\n" - "ld1 { v18.b }[4], [x21]\n" + "ld1 { v27.b }[4], [x26]\n" + "ld1 { v26.b }[4], [x25]\n" + "ld1 { v25.b }[4], [x24]\n" + "ld1 { v24.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x22]\n" + "ld1 { v22.b }[4], [x21]\n" "b 13f\n" "11:" // odd_loads_2_0 "tbz %x[width], #1, 12f\n" - "ldr h30, [x28], #0x2\n" - "ldr h29, [x27], #0x2\n" + "ldr h29, [x28], #0x2\n" + "ldr h28, [x27], #0x2\n" "mov x20, #0x1\n" - "ldr h28, [x26], #0x2\n" - "ldr h27, [x25], #0x2\n" - "ldr h20, [x24], #0x2\n" - "ldr h26, [x23], #0x2\n" - "ldr h19, [x22], #0x2\n" - "ldr h18, [x21], #0x2\n" + "ldr h27, [x26], #0x2\n" + "ldr h26, [x25], #0x2\n" + "ldr h25, [x24], #0x2\n" + "ldr h24, [x23], #0x2\n" + "ldr h23, [x22], #0x2\n" + "ldr h22, [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[2], [x28]\n" - "ld1 { v29.b }[2], [x27]\n" - "ld1 { v28.b }[2], [x26]\n" - "ld1 { v27.b }[2], [x25]\n" - "ld1 { v20.b }[2], [x24]\n" - "ld1 { v26.b }[2], [x23]\n" - "ld1 { v19.b }[2], [x22]\n" - "ld1 { v18.b }[2], [x21]\n" + "ld1 { v29.b }[2], [x28]\n" + "ld1 { v28.b }[2], [x27]\n" + "ld1 { v27.b }[2], [x26]\n" + "ld1 { v26.b }[2], [x25]\n" + "ld1 { v25.b }[2], [x24]\n" + "ld1 { v24.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x22]\n" + "ld1 { v22.b }[2], [x21]\n" "b 13f\n" "12:" // odd_loads_1_0 - "ldr b30, [x28, #0x0]\n" - "ldr b29, [x27, #0x0]\n" + "ldr b29, [x28, #0x0]\n" + "ldr b28, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b28, [x26, #0x0]\n" - "ldr b27, [x25, #0x0]\n" - "ldr b20, [x24, #0x0]\n" - "ldr b26, [x23, #0x0]\n" - "ldr b19, [x22, #0x0]\n" - "ldr b18, [x21, #0x0]\n" + "ldr b27, [x26, #0x0]\n" + "ldr b26, [x25, #0x0]\n" + "ldr b25, [x24, #0x0]\n" + "ldr b24, [x23, #0x0]\n" + "ldr b23, [x22, #0x0]\n" + "ldr b22, [x21, #0x0]\n" "13:" // Odd load end - "zip1 v22.4s, v30.4s, v28.4s\n" "zip1 v21.4s, v29.4s, v27.4s\n" + "zip1 v20.4s, v28.4s, v26.4s\n" "subs x20, x20, #0x1\n" - "zip1 v17.4s, v20.4s, v19.4s\n" - "zip1 v16.4s, v26.4s, v18.4s\n" - "zip1 v25.4s, v22.4s, v21.4s\n" - "zip1 v24.4s, v17.4s, v16.4s\n" - "str q25, [%x[out_ptr], #0x0]\n" - "sadalp v2.8h, v25.16b\n" - "str q24, [%x[out_ptr], #0x10]\n" - "sadalp v1.8h, v24.16b\n" + "zip1 v19.4s, v25.4s, v23.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v21.4s, v20.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "sadalp v2.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x10]\n" + "sadalp v1.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v23.4s, v22.4s, v21.4s\n" - "zip2 v22.4s, v17.4s, v16.4s\n" + "zip2 v17.4s, v21.4s, v20.4s\n" + "zip2 v16.4s, v19.4s, v18.4s\n" "subs x20, x20, #0x1\n" - "str q23, [%x[out_ptr], #0x0]\n" - "sadalp v2.8h, v23.16b\n" - "str q22, [%x[out_ptr], #0x10]\n" - "sadalp v1.8h, v22.16b\n" + "str q17, [%x[out_ptr], #0x0]\n" + "sadalp v2.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x10]\n" + "sadalp v1.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v21.4s, v30.4s, v28.4s\n" - "zip2 v17.4s, v29.4s, v27.4s\n" + "zip2 v21.4s, v29.4s, v27.4s\n" + "zip2 v20.4s, v28.4s, v26.4s\n" "subs x20, x20, #0x1\n" - "zip2 v20.4s, v20.4s, v19.4s\n" - "zip2 v16.4s, v26.4s, v18.4s\n" - "zip1 v19.4s, v21.4s, v17.4s\n" - "zip1 v18.4s, v20.4s, v16.4s\n" - "str q19, [%x[out_ptr], #0x0]\n" - "sadalp v2.8h, v19.16b\n" - "str q18, [%x[out_ptr], #0x10]\n" - "sadalp v1.8h, v18.16b\n" + "zip2 v19.4s, v25.4s, v23.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v21.4s, v20.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "sadalp v2.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x10]\n" + "sadalp v1.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v17.4s, v21.4s, v17.4s\n" - "zip2 v16.4s, v20.4s, v16.4s\n" + "zip2 v17.4s, v21.4s, v20.4s\n" + "zip2 v16.4s, v19.4s, v18.4s\n" "str q17, [%x[out_ptr], #0x0]\n" "sadalp v2.8h, v17.16b\n" "str q16, [%x[out_ptr], #0x10]\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp index 44a79c0f0a..17eb7d5556 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block4_u8_u8_summing.hpp @@ -153,202 +153,202 @@ void interleave_block<8, 4, VLType::None, true>( "5:" // Main loop skip "cbz %x[width], 14f\n" "tbz %x[width], #3, 9f\n" - "ldr d30, [x28], #0x8\n" - "ldr d29, [x27], #0x8\n" - "ldr d28, [x26], #0x8\n" - "ldr d27, [x25], #0x8\n" - "ldr d20, [x24], #0x8\n" - "ldr d26, [x23], #0x8\n" - "ldr d19, [x22], #0x8\n" - "ldr d18, [x21], #0x8\n" + "ldr d29, [x28], #0x8\n" + "ldr d28, [x27], #0x8\n" + "ldr d27, [x26], #0x8\n" + "ldr d26, [x25], #0x8\n" + "ldr d25, [x24], #0x8\n" + "ldr d24, [x23], #0x8\n" + "ldr d23, [x22], #0x8\n" + "ldr d22, [x21], #0x8\n" "tbz %x[width], #2, 7f\n" - "ld1 { v30.s }[2], [x28], #0x4\n" - "ld1 { v29.s }[2], [x27], #0x4\n" - "ld1 { v28.s }[2], [x26], #0x4\n" - "ld1 { v27.s }[2], [x25], #0x4\n" - "ld1 { v20.s }[2], [x24], #0x4\n" - "ld1 { v26.s }[2], [x23], #0x4\n" - "ld1 { v19.s }[2], [x22], #0x4\n" - "ld1 { v18.s }[2], [x21], #0x4\n" + "ld1 { v29.s }[2], [x28], #0x4\n" + "ld1 { v28.s }[2], [x27], #0x4\n" + "ld1 { v27.s }[2], [x26], #0x4\n" + "ld1 { v26.s }[2], [x25], #0x4\n" + "ld1 { v25.s }[2], [x24], #0x4\n" + "ld1 { v24.s }[2], [x23], #0x4\n" + "ld1 { v23.s }[2], [x22], #0x4\n" + "ld1 { v22.s }[2], [x21], #0x4\n" "tbz %x[width], #1, 6f\n" - "ld1 { v30.h }[6], [x28], #0x2\n" - "ld1 { v29.h }[6], [x27], #0x2\n" + "ld1 { v29.h }[6], [x28], #0x2\n" + "ld1 { v28.h }[6], [x27], #0x2\n" "mov x20, #0x4\n" - "ld1 { v28.h }[6], [x26], #0x2\n" - "ld1 { v27.h }[6], [x25], #0x2\n" - "ld1 { v20.h }[6], [x24], #0x2\n" - "ld1 { v26.h }[6], [x23], #0x2\n" - "ld1 { v19.h }[6], [x22], #0x2\n" - "ld1 { v18.h }[6], [x21], #0x2\n" + "ld1 { v27.h }[6], [x26], #0x2\n" + "ld1 { v26.h }[6], [x25], #0x2\n" + "ld1 { v25.h }[6], [x24], #0x2\n" + "ld1 { v24.h }[6], [x23], #0x2\n" + "ld1 { v23.h }[6], [x22], #0x2\n" + "ld1 { v22.h }[6], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[14], [x28]\n" - "ld1 { v29.b }[14], [x27]\n" - "ld1 { v28.b }[14], [x26]\n" - "ld1 { v27.b }[14], [x25]\n" - "ld1 { v20.b }[14], [x24]\n" - "ld1 { v26.b }[14], [x23]\n" - "ld1 { v19.b }[14], [x22]\n" - "ld1 { v18.b }[14], [x21]\n" + "ld1 { v29.b }[14], [x28]\n" + "ld1 { v28.b }[14], [x27]\n" + "ld1 { v27.b }[14], [x26]\n" + "ld1 { v26.b }[14], [x25]\n" + "ld1 { v25.b }[14], [x24]\n" + "ld1 { v24.b }[14], [x23]\n" + "ld1 { v23.b }[14], [x22]\n" + "ld1 { v22.b }[14], [x21]\n" "b 13f\n" "6:" // odd_loads_1_12 "mov x20, #0x3\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[12], [x28]\n" - "ld1 { v29.b }[12], [x27]\n" + "ld1 { v29.b }[12], [x28]\n" + "ld1 { v28.b }[12], [x27]\n" "mov x20, #0x4\n" - "ld1 { v28.b }[12], [x26]\n" - "ld1 { v27.b }[12], [x25]\n" - "ld1 { v20.b }[12], [x24]\n" - "ld1 { v26.b }[12], [x23]\n" - "ld1 { v19.b }[12], [x22]\n" - "ld1 { v18.b }[12], [x21]\n" + "ld1 { v27.b }[12], [x26]\n" + "ld1 { v26.b }[12], [x25]\n" + "ld1 { v25.b }[12], [x24]\n" + "ld1 { v24.b }[12], [x23]\n" + "ld1 { v23.b }[12], [x22]\n" + "ld1 { v22.b }[12], [x21]\n" "b 13f\n" "7:" // odd_loads_2_8 "tbz %x[width], #1, 8f\n" - "ld1 { v30.h }[4], [x28], #0x2\n" - "ld1 { v29.h }[4], [x27], #0x2\n" + "ld1 { v29.h }[4], [x28], #0x2\n" + "ld1 { v28.h }[4], [x27], #0x2\n" "mov x20, #0x3\n" - "ld1 { v28.h }[4], [x26], #0x2\n" - "ld1 { v27.h }[4], [x25], #0x2\n" - "ld1 { v20.h }[4], [x24], #0x2\n" - "ld1 { v26.h }[4], [x23], #0x2\n" - "ld1 { v19.h }[4], [x22], #0x2\n" - "ld1 { v18.h }[4], [x21], #0x2\n" + "ld1 { v27.h }[4], [x26], #0x2\n" + "ld1 { v26.h }[4], [x25], #0x2\n" + "ld1 { v25.h }[4], [x24], #0x2\n" + "ld1 { v24.h }[4], [x23], #0x2\n" + "ld1 { v23.h }[4], [x22], #0x2\n" + "ld1 { v22.h }[4], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[10], [x28]\n" - "ld1 { v29.b }[10], [x27]\n" - "ld1 { v28.b }[10], [x26]\n" - "ld1 { v27.b }[10], [x25]\n" - "ld1 { v20.b }[10], [x24]\n" - "ld1 { v26.b }[10], [x23]\n" - "ld1 { v19.b }[10], [x22]\n" - "ld1 { v18.b }[10], [x21]\n" + "ld1 { v29.b }[10], [x28]\n" + "ld1 { v28.b }[10], [x27]\n" + "ld1 { v27.b }[10], [x26]\n" + "ld1 { v26.b }[10], [x25]\n" + "ld1 { v25.b }[10], [x24]\n" + "ld1 { v24.b }[10], [x23]\n" + "ld1 { v23.b }[10], [x22]\n" + "ld1 { v22.b }[10], [x21]\n" "b 13f\n" "8:" // odd_loads_1_8 "mov x20, #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[8], [x28]\n" - "ld1 { v29.b }[8], [x27]\n" + "ld1 { v29.b }[8], [x28]\n" + "ld1 { v28.b }[8], [x27]\n" "mov x20, #0x3\n" - "ld1 { v28.b }[8], [x26]\n" - "ld1 { v27.b }[8], [x25]\n" - "ld1 { v20.b }[8], [x24]\n" - "ld1 { v26.b }[8], [x23]\n" - "ld1 { v19.b }[8], [x22]\n" - "ld1 { v18.b }[8], [x21]\n" + "ld1 { v27.b }[8], [x26]\n" + "ld1 { v26.b }[8], [x25]\n" + "ld1 { v25.b }[8], [x24]\n" + "ld1 { v24.b }[8], [x23]\n" + "ld1 { v23.b }[8], [x22]\n" + "ld1 { v22.b }[8], [x21]\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" - "ldr s30, [x28], #0x4\n" - "ldr s29, [x27], #0x4\n" - "ldr s28, [x26], #0x4\n" - "ldr s27, [x25], #0x4\n" - "ldr s20, [x24], #0x4\n" - "ldr s26, [x23], #0x4\n" - "ldr s19, [x22], #0x4\n" - "ldr s18, [x21], #0x4\n" + "ldr s29, [x28], #0x4\n" + "ldr s28, [x27], #0x4\n" + "ldr s27, [x26], #0x4\n" + "ldr s26, [x25], #0x4\n" + "ldr s25, [x24], #0x4\n" + "ldr s24, [x23], #0x4\n" + "ldr s23, [x22], #0x4\n" + "ldr s22, [x21], #0x4\n" "tbz %x[width], #1, 10f\n" - "ld1 { v30.h }[2], [x28], #0x2\n" - "ld1 { v29.h }[2], [x27], #0x2\n" + "ld1 { v29.h }[2], [x28], #0x2\n" + "ld1 { v28.h }[2], [x27], #0x2\n" "mov x20, #0x2\n" - "ld1 { v28.h }[2], [x26], #0x2\n" - "ld1 { v27.h }[2], [x25], #0x2\n" - "ld1 { v20.h }[2], [x24], #0x2\n" - "ld1 { v26.h }[2], [x23], #0x2\n" - "ld1 { v19.h }[2], [x22], #0x2\n" - "ld1 { v18.h }[2], [x21], #0x2\n" + "ld1 { v27.h }[2], [x26], #0x2\n" + "ld1 { v26.h }[2], [x25], #0x2\n" + "ld1 { v25.h }[2], [x24], #0x2\n" + "ld1 { v24.h }[2], [x23], #0x2\n" + "ld1 { v23.h }[2], [x22], #0x2\n" + "ld1 { v22.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[6], [x28]\n" - "ld1 { v29.b }[6], [x27]\n" - "ld1 { v28.b }[6], [x26]\n" - "ld1 { v27.b }[6], [x25]\n" - "ld1 { v20.b }[6], [x24]\n" - "ld1 { v26.b }[6], [x23]\n" - "ld1 { v19.b }[6], [x22]\n" - "ld1 { v18.b }[6], [x21]\n" + "ld1 { v29.b }[6], [x28]\n" + "ld1 { v28.b }[6], [x27]\n" + "ld1 { v27.b }[6], [x26]\n" + "ld1 { v26.b }[6], [x25]\n" + "ld1 { v25.b }[6], [x24]\n" + "ld1 { v24.b }[6], [x23]\n" + "ld1 { v23.b }[6], [x22]\n" + "ld1 { v22.b }[6], [x21]\n" "b 13f\n" "10:" // odd_loads_1_4 "mov x20, #0x1\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[4], [x28]\n" - "ld1 { v29.b }[4], [x27]\n" + "ld1 { v29.b }[4], [x28]\n" + "ld1 { v28.b }[4], [x27]\n" "mov x20, #0x2\n" - "ld1 { v28.b }[4], [x26]\n" - "ld1 { v27.b }[4], [x25]\n" - "ld1 { v20.b }[4], [x24]\n" - "ld1 { v26.b }[4], [x23]\n" - "ld1 { v19.b }[4], [x22]\n" - "ld1 { v18.b }[4], [x21]\n" + "ld1 { v27.b }[4], [x26]\n" + "ld1 { v26.b }[4], [x25]\n" + "ld1 { v25.b }[4], [x24]\n" + "ld1 { v24.b }[4], [x23]\n" + "ld1 { v23.b }[4], [x22]\n" + "ld1 { v22.b }[4], [x21]\n" "b 13f\n" "11:" // odd_loads_2_0 "tbz %x[width], #1, 12f\n" - "ldr h30, [x28], #0x2\n" - "ldr h29, [x27], #0x2\n" + "ldr h29, [x28], #0x2\n" + "ldr h28, [x27], #0x2\n" "mov x20, #0x1\n" - "ldr h28, [x26], #0x2\n" - "ldr h27, [x25], #0x2\n" - "ldr h20, [x24], #0x2\n" - "ldr h26, [x23], #0x2\n" - "ldr h19, [x22], #0x2\n" - "ldr h18, [x21], #0x2\n" + "ldr h27, [x26], #0x2\n" + "ldr h26, [x25], #0x2\n" + "ldr h25, [x24], #0x2\n" + "ldr h24, [x23], #0x2\n" + "ldr h23, [x22], #0x2\n" + "ldr h22, [x21], #0x2\n" "tbz %x[width], #0, 13f\n" - "ld1 { v30.b }[2], [x28]\n" - "ld1 { v29.b }[2], [x27]\n" - "ld1 { v28.b }[2], [x26]\n" - "ld1 { v27.b }[2], [x25]\n" - "ld1 { v20.b }[2], [x24]\n" - "ld1 { v26.b }[2], [x23]\n" - "ld1 { v19.b }[2], [x22]\n" - "ld1 { v18.b }[2], [x21]\n" + "ld1 { v29.b }[2], [x28]\n" + "ld1 { v28.b }[2], [x27]\n" + "ld1 { v27.b }[2], [x26]\n" + "ld1 { v26.b }[2], [x25]\n" + "ld1 { v25.b }[2], [x24]\n" + "ld1 { v24.b }[2], [x23]\n" + "ld1 { v23.b }[2], [x22]\n" + "ld1 { v22.b }[2], [x21]\n" "b 13f\n" "12:" // odd_loads_1_0 - "ldr b30, [x28, #0x0]\n" - "ldr b29, [x27, #0x0]\n" + "ldr b29, [x28, #0x0]\n" + "ldr b28, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b28, [x26, #0x0]\n" - "ldr b27, [x25, #0x0]\n" - "ldr b20, [x24, #0x0]\n" - "ldr b26, [x23, #0x0]\n" - "ldr b19, [x22, #0x0]\n" - "ldr b18, [x21, #0x0]\n" + "ldr b27, [x26, #0x0]\n" + "ldr b26, [x25, #0x0]\n" + "ldr b25, [x24, #0x0]\n" + "ldr b24, [x23, #0x0]\n" + "ldr b23, [x22, #0x0]\n" + "ldr b22, [x21, #0x0]\n" "13:" // Odd load end - "zip1 v22.4s, v30.4s, v28.4s\n" "zip1 v21.4s, v29.4s, v27.4s\n" + "zip1 v20.4s, v28.4s, v26.4s\n" "subs x20, x20, #0x1\n" - "zip1 v17.4s, v20.4s, v19.4s\n" - "zip1 v16.4s, v26.4s, v18.4s\n" - "zip1 v25.4s, v22.4s, v21.4s\n" - "zip1 v24.4s, v17.4s, v16.4s\n" - "str q25, [%x[out_ptr], #0x0]\n" - "uadalp v2.8h, v25.16b\n" - "str q24, [%x[out_ptr], #0x10]\n" - "uadalp v1.8h, v24.16b\n" + "zip1 v19.4s, v25.4s, v23.4s\n" + "zip1 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v21.4s, v20.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "uadalp v2.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x10]\n" + "uadalp v1.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v23.4s, v22.4s, v21.4s\n" - "zip2 v22.4s, v17.4s, v16.4s\n" + "zip2 v17.4s, v21.4s, v20.4s\n" + "zip2 v16.4s, v19.4s, v18.4s\n" "subs x20, x20, #0x1\n" - "str q23, [%x[out_ptr], #0x0]\n" - "uadalp v2.8h, v23.16b\n" - "str q22, [%x[out_ptr], #0x10]\n" - "uadalp v1.8h, v22.16b\n" + "str q17, [%x[out_ptr], #0x0]\n" + "uadalp v2.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x10]\n" + "uadalp v1.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v21.4s, v30.4s, v28.4s\n" - "zip2 v17.4s, v29.4s, v27.4s\n" + "zip2 v21.4s, v29.4s, v27.4s\n" + "zip2 v20.4s, v28.4s, v26.4s\n" "subs x20, x20, #0x1\n" - "zip2 v20.4s, v20.4s, v19.4s\n" - "zip2 v16.4s, v26.4s, v18.4s\n" - "zip1 v19.4s, v21.4s, v17.4s\n" - "zip1 v18.4s, v20.4s, v16.4s\n" - "str q19, [%x[out_ptr], #0x0]\n" - "uadalp v2.8h, v19.16b\n" - "str q18, [%x[out_ptr], #0x10]\n" - "uadalp v1.8h, v18.16b\n" + "zip2 v19.4s, v25.4s, v23.4s\n" + "zip2 v18.4s, v24.4s, v22.4s\n" + "zip1 v17.4s, v21.4s, v20.4s\n" + "zip1 v16.4s, v19.4s, v18.4s\n" + "str q17, [%x[out_ptr], #0x0]\n" + "uadalp v2.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x10]\n" + "uadalp v1.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" "beq 14f\n" - "zip2 v17.4s, v21.4s, v17.4s\n" - "zip2 v16.4s, v20.4s, v16.4s\n" + "zip2 v17.4s, v21.4s, v20.4s\n" + "zip2 v16.4s, v19.4s, v18.4s\n" "str q17, [%x[out_ptr], #0x0]\n" "uadalp v2.8h, v17.16b\n" "str q16, [%x[out_ptr], #0x10]\n" diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp index 4bfb36082e..7b445ef3d4 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8.hpp @@ -79,18 +79,18 @@ void interleave_block<8, 8, VLType::None, false>( "prfm pldl1keep, [x21, #0x40]\n" "blt 3f\n" "2:" // Main loop head - "ldr q26, [x28], #0x10\n" - "ldr q21, [x27], #0x10\n" + "ldr q20, [x28], #0x10\n" + "ldr q19, [x27], #0x10\n" "subs %x[width], %x[width], #0x10\n" "cmp %x[width], #0x10\n" "ldr q25, [x26], #0x10\n" "ldr q24, [x25], #0x10\n" - "zip1 v16.2d, v26.2d, v21.2d\n" + "zip1 v16.2d, v20.2d, v19.2d\n" "zip1 v18.2d, v25.2d, v24.2d\n" "ldr q23, [x24], #0x10\n" "ldr q22, [x23], #0x10\n" "zip1 v17.2d, v23.2d, v22.2d\n" - "zip2 v21.2d, v26.2d, v21.2d\n" + "zip2 v21.2d, v20.2d, v19.2d\n" "ldr q20, [x22], #0x10\n" "ldr q19, [x21], #0x10\n" "str q16, [%x[out_ptr], #0x0]\n" @@ -118,188 +118,187 @@ void interleave_block<8, 8, VLType::None, false>( "3:" // Main loop skip "cbz %x[width], 12f\n" "tbz %x[width], #3, 7f\n" - "ldr d26, [x28], #0x8\n" - "ldr d21, [x27], #0x8\n" - "ldr d25, [x26], #0x8\n" - "ldr d24, [x25], #0x8\n" - "ldr d23, [x24], #0x8\n" - "ldr d22, [x23], #0x8\n" - "ldr d20, [x22], #0x8\n" - "ldr d19, [x21], #0x8\n" + "ldr d25, [x28], #0x8\n" + "ldr d24, [x27], #0x8\n" + "ldr d23, [x26], #0x8\n" + "ldr d22, [x25], #0x8\n" + "ldr d21, [x24], #0x8\n" + "ldr d20, [x23], #0x8\n" + "ldr d19, [x22], #0x8\n" + "ldr d18, [x21], #0x8\n" "tbz %x[width], #2, 5f\n" - "ld1 { v26.s }[2], [x28], #0x4\n" - "ld1 { v21.s }[2], [x27], #0x4\n" - "ld1 { v25.s }[2], [x26], #0x4\n" - "ld1 { v24.s }[2], [x25], #0x4\n" - "ld1 { v23.s }[2], [x24], #0x4\n" - "ld1 { v22.s }[2], [x23], #0x4\n" - "ld1 { v20.s }[2], [x22], #0x4\n" - "ld1 { v19.s }[2], [x21], #0x4\n" + "ld1 { v25.s }[2], [x28], #0x4\n" + "ld1 { v24.s }[2], [x27], #0x4\n" + "ld1 { v23.s }[2], [x26], #0x4\n" + "ld1 { v22.s }[2], [x25], #0x4\n" + "ld1 { v21.s }[2], [x24], #0x4\n" + "ld1 { v20.s }[2], [x23], #0x4\n" + "ld1 { v19.s }[2], [x22], #0x4\n" + "ld1 { v18.s }[2], [x21], #0x4\n" "tbz %x[width], #1, 4f\n" - "ld1 { v26.h }[6], [x28], #0x2\n" - "ld1 { v21.h }[6], [x27], #0x2\n" + "ld1 { v25.h }[6], [x28], #0x2\n" + "ld1 { v24.h }[6], [x27], #0x2\n" "mov x20, #0x2\n" - "ld1 { v25.h }[6], [x26], #0x2\n" - "ld1 { v24.h }[6], [x25], #0x2\n" - "ld1 { v23.h }[6], [x24], #0x2\n" - "ld1 { v22.h }[6], [x23], #0x2\n" - "ld1 { v20.h }[6], [x22], #0x2\n" - "ld1 { v19.h }[6], [x21], #0x2\n" + "ld1 { v23.h }[6], [x26], #0x2\n" + "ld1 { v22.h }[6], [x25], #0x2\n" + "ld1 { v21.h }[6], [x24], #0x2\n" + "ld1 { v20.h }[6], [x23], #0x2\n" + "ld1 { v19.h }[6], [x22], #0x2\n" + "ld1 { v18.h }[6], [x21], #0x2\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[14], [x28]\n" - "ld1 { v21.b }[14], [x27]\n" - "ld1 { v25.b }[14], [x26]\n" - "ld1 { v24.b }[14], [x25]\n" - "ld1 { v23.b }[14], [x24]\n" - "ld1 { v22.b }[14], [x23]\n" - "ld1 { v20.b }[14], [x22]\n" - "ld1 { v19.b }[14], [x21]\n" + "ld1 { v25.b }[14], [x28]\n" + "ld1 { v24.b }[14], [x27]\n" + "ld1 { v23.b }[14], [x26]\n" + "ld1 { v22.b }[14], [x25]\n" + "ld1 { v21.b }[14], [x24]\n" + "ld1 { v20.b }[14], [x23]\n" + "ld1 { v19.b }[14], [x22]\n" + "ld1 { v18.b }[14], [x21]\n" "b 11f\n" "4:" // odd_loads_1_12 "mov x20, #0x2\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[12], [x28]\n" - "ld1 { v21.b }[12], [x27]\n" - "ld1 { v25.b }[12], [x26]\n" - "ld1 { v24.b }[12], [x25]\n" - "ld1 { v23.b }[12], [x24]\n" - "ld1 { v22.b }[12], [x23]\n" - "ld1 { v20.b }[12], [x22]\n" - "ld1 { v19.b }[12], [x21]\n" + "ld1 { v25.b }[12], [x28]\n" + "ld1 { v24.b }[12], [x27]\n" + "ld1 { v23.b }[12], [x26]\n" + "ld1 { v22.b }[12], [x25]\n" + "ld1 { v21.b }[12], [x24]\n" + "ld1 { v20.b }[12], [x23]\n" + "ld1 { v19.b }[12], [x22]\n" + "ld1 { v18.b }[12], [x21]\n" "b 11f\n" "5:" // odd_loads_2_8 "tbz %x[width], #1, 6f\n" - "ld1 { v26.h }[4], [x28], #0x2\n" - "ld1 { v21.h }[4], [x27], #0x2\n" + "ld1 { v25.h }[4], [x28], #0x2\n" + "ld1 { v24.h }[4], [x27], #0x2\n" "mov x20, #0x2\n" - "ld1 { v25.h }[4], [x26], #0x2\n" - "ld1 { v24.h }[4], [x25], #0x2\n" - "ld1 { v23.h }[4], [x24], #0x2\n" - "ld1 { v22.h }[4], [x23], #0x2\n" - "ld1 { v20.h }[4], [x22], #0x2\n" - "ld1 { v19.h }[4], [x21], #0x2\n" + "ld1 { v23.h }[4], [x26], #0x2\n" + "ld1 { v22.h }[4], [x25], #0x2\n" + "ld1 { v21.h }[4], [x24], #0x2\n" + "ld1 { v20.h }[4], [x23], #0x2\n" + "ld1 { v19.h }[4], [x22], #0x2\n" + "ld1 { v18.h }[4], [x21], #0x2\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[10], [x28]\n" - "ld1 { v21.b }[10], [x27]\n" - "ld1 { v25.b }[10], [x26]\n" - "ld1 { v24.b }[10], [x25]\n" - "ld1 { v23.b }[10], [x24]\n" - "ld1 { v22.b }[10], [x23]\n" - "ld1 { v20.b }[10], [x22]\n" - "ld1 { v19.b }[10], [x21]\n" + "ld1 { v25.b }[10], [x28]\n" + "ld1 { v24.b }[10], [x27]\n" + "ld1 { v23.b }[10], [x26]\n" + "ld1 { v22.b }[10], [x25]\n" + "ld1 { v21.b }[10], [x24]\n" + "ld1 { v20.b }[10], [x23]\n" + "ld1 { v19.b }[10], [x22]\n" + "ld1 { v18.b }[10], [x21]\n" "b 11f\n" "6:" // odd_loads_1_8 "mov x20, #0x1\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[8], [x28]\n" - "ld1 { v21.b }[8], [x27]\n" + "ld1 { v25.b }[8], [x28]\n" + "ld1 { v24.b }[8], [x27]\n" "mov x20, #0x2\n" - "ld1 { v25.b }[8], [x26]\n" - "ld1 { v24.b }[8], [x25]\n" - "ld1 { v23.b }[8], [x24]\n" - "ld1 { v22.b }[8], [x23]\n" - "ld1 { v20.b }[8], [x22]\n" - "ld1 { v19.b }[8], [x21]\n" + "ld1 { v23.b }[8], [x26]\n" + "ld1 { v22.b }[8], [x25]\n" + "ld1 { v21.b }[8], [x24]\n" + "ld1 { v20.b }[8], [x23]\n" + "ld1 { v19.b }[8], [x22]\n" + "ld1 { v18.b }[8], [x21]\n" "b 11f\n" "7:" // odd_loads_4_0 "tbz %x[width], #2, 9f\n" - "ldr s26, [x28], #0x4\n" - "ldr s21, [x27], #0x4\n" - "ldr s25, [x26], #0x4\n" - "ldr s24, [x25], #0x4\n" - "ldr s23, [x24], #0x4\n" - "ldr s22, [x23], #0x4\n" - "ldr s20, [x22], #0x4\n" - "ldr s19, [x21], #0x4\n" + "ldr s25, [x28], #0x4\n" + "ldr s24, [x27], #0x4\n" + "ldr s23, [x26], #0x4\n" + "ldr s22, [x25], #0x4\n" + "ldr s21, [x24], #0x4\n" + "ldr s20, [x23], #0x4\n" + "ldr s19, [x22], #0x4\n" + "ldr s18, [x21], #0x4\n" "tbz %x[width], #1, 8f\n" - "ld1 { v26.h }[2], [x28], #0x2\n" - "ld1 { v21.h }[2], [x27], #0x2\n" + "ld1 { v25.h }[2], [x28], #0x2\n" + "ld1 { v24.h }[2], [x27], #0x2\n" "mov x20, #0x1\n" - "ld1 { v25.h }[2], [x26], #0x2\n" - "ld1 { v24.h }[2], [x25], #0x2\n" - "ld1 { v23.h }[2], [x24], #0x2\n" - "ld1 { v22.h }[2], [x23], #0x2\n" - "ld1 { v20.h }[2], [x22], #0x2\n" - "ld1 { v19.h }[2], [x21], #0x2\n" + "ld1 { v23.h }[2], [x26], #0x2\n" + "ld1 { v22.h }[2], [x25], #0x2\n" + "ld1 { v21.h }[2], [x24], #0x2\n" + "ld1 { v20.h }[2], [x23], #0x2\n" + "ld1 { v19.h }[2], [x22], #0x2\n" + "ld1 { v18.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[6], [x28]\n" - "ld1 { v21.b }[6], [x27]\n" - "ld1 { v25.b }[6], [x26]\n" - "ld1 { v24.b }[6], [x25]\n" - "ld1 { v23.b }[6], [x24]\n" - "ld1 { v22.b }[6], [x23]\n" - "ld1 { v20.b }[6], [x22]\n" - "ld1 { v19.b }[6], [x21]\n" + "ld1 { v25.b }[6], [x28]\n" + "ld1 { v24.b }[6], [x27]\n" + "ld1 { v23.b }[6], [x26]\n" + "ld1 { v22.b }[6], [x25]\n" + "ld1 { v21.b }[6], [x24]\n" + "ld1 { v20.b }[6], [x23]\n" + "ld1 { v19.b }[6], [x22]\n" + "ld1 { v18.b }[6], [x21]\n" "b 11f\n" "8:" // odd_loads_1_4 "mov x20, #0x1\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[4], [x28]\n" - "ld1 { v21.b }[4], [x27]\n" - "ld1 { v25.b }[4], [x26]\n" - "ld1 { v24.b }[4], [x25]\n" - "ld1 { v23.b }[4], [x24]\n" - "ld1 { v22.b }[4], [x23]\n" - "ld1 { v20.b }[4], [x22]\n" - "ld1 { v19.b }[4], [x21]\n" + "ld1 { v25.b }[4], [x28]\n" + "ld1 { v24.b }[4], [x27]\n" + "ld1 { v23.b }[4], [x26]\n" + "ld1 { v22.b }[4], [x25]\n" + "ld1 { v21.b }[4], [x24]\n" + "ld1 { v20.b }[4], [x23]\n" + "ld1 { v19.b }[4], [x22]\n" + "ld1 { v18.b }[4], [x21]\n" "b 11f\n" "9:" // odd_loads_2_0 "tbz %x[width], #1, 10f\n" - "ldr h26, [x28], #0x2\n" - "ldr h21, [x27], #0x2\n" + "ldr h25, [x28], #0x2\n" + "ldr h24, [x27], #0x2\n" "mov x20, #0x1\n" - "ldr h25, [x26], #0x2\n" - "ldr h24, [x25], #0x2\n" - "ldr h23, [x24], #0x2\n" - "ldr h22, [x23], #0x2\n" - "ldr h20, [x22], #0x2\n" - "ldr h19, [x21], #0x2\n" + "ldr h23, [x26], #0x2\n" + "ldr h22, [x25], #0x2\n" + "ldr h21, [x24], #0x2\n" + "ldr h20, [x23], #0x2\n" + "ldr h19, [x22], #0x2\n" + "ldr h18, [x21], #0x2\n" "tbz %x[width], #0, 11f\n" - "ld1 { v26.b }[2], [x28]\n" - "ld1 { v21.b }[2], [x27]\n" - "ld1 { v25.b }[2], [x26]\n" - "ld1 { v24.b }[2], [x25]\n" - "ld1 { v23.b }[2], [x24]\n" - "ld1 { v22.b }[2], [x23]\n" - "ld1 { v20.b }[2], [x22]\n" - "ld1 { v19.b }[2], [x21]\n" + "ld1 { v25.b }[2], [x28]\n" + "ld1 { v24.b }[2], [x27]\n" + "ld1 { v23.b }[2], [x26]\n" + "ld1 { v22.b }[2], [x25]\n" + "ld1 { v21.b }[2], [x24]\n" + "ld1 { v20.b }[2], [x23]\n" + "ld1 { v19.b }[2], [x22]\n" + "ld1 { v18.b }[2], [x21]\n" "b 11f\n" "10:" // odd_loads_1_0 - "ldr b26, [x28, #0x0]\n" - "ldr b21, [x27, #0x0]\n" + "ldr b25, [x28, #0x0]\n" + "ldr b24, [x27, #0x0]\n" "mov x20, #0x1\n" - "ldr b25, [x26, #0x0]\n" - "ldr b24, [x25, #0x0]\n" - "ldr b23, [x24, #0x0]\n" - "ldr b22, [x23, #0x0]\n" - "ldr b20, [x22, #0x0]\n" - "ldr b19, [x21, #0x0]\n" + "ldr b23, [x26, #0x0]\n" + "ldr b22, [x25, #0x0]\n" + "ldr b21, [x24, #0x0]\n" + "ldr b20, [x23, #0x0]\n" + "ldr b19, [x22, #0x0]\n" + "ldr b18, [x21, #0x0]\n" "11:" // Odd load end "subs x20, x20, #0x1\n" - "zip1 v16.2d, v26.2d, v21.2d\n" + "zip1 v16.2d, v25.2d, v24.2d\n" "str q16, [%x[out_ptr], #0x0]\n" - "zip1 v18.2d, v25.2d, v24.2d\n" - "str q18, [%x[out_ptr], #0x10]\n" - "zip1 v17.2d, v23.2d, v22.2d\n" - "zip1 v16.2d, v20.2d, v19.2d\n" + "zip1 v16.2d, v23.2d, v22.2d\n" + "str q16, [%x[out_ptr], #0x10]\n" + "zip1 v17.2d, v21.2d, v20.2d\n" + "zip1 v16.2d, v19.2d, v18.2d\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 12f\n" - "zip2 v21.2d, v26.2d, v21.2d\n" - "str q21, [%x[out_ptr], #0x0]\n" - "zip2 v18.2d, v25.2d, v24.2d\n" - "str q18, [%x[out_ptr], #0x10]\n" - "zip2 v17.2d, v23.2d, v22.2d\n" - "zip2 v16.2d, v20.2d, v19.2d\n" + "zip2 v16.2d, v25.2d, v24.2d\n" + "str q16, [%x[out_ptr], #0x0]\n" + "zip2 v16.2d, v23.2d, v22.2d\n" + "str q16, [%x[out_ptr], #0x10]\n" + "zip2 v17.2d, v21.2d, v20.2d\n" + "zip2 v16.2d, v19.2d, v18.2d\n" "str q17, [%x[out_ptr], #0x20]\n" "str q16, [%x[out_ptr], #0x30]\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "12:" // Odds skip - : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp index c6ad2949f5..a2288e8299 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_s8_s8_summing.hpp @@ -156,182 +156,182 @@ void interleave_block<8, 8, VLType::None, true>( "cbz %x[width], 14f\n" "tbz %x[width], #3, 9f\n" "ldr d27, [x28], #0x8\n" - "ldr d19, [x27], #0x8\n" + "ldr d26, [x27], #0x8\n" "ldr d25, [x26], #0x8\n" - "ldr d18, [x25], #0x8\n" + "ldr d24, [x25], #0x8\n" "ldr d23, [x24], #0x8\n" - "ldr d17, [x23], #0x8\n" + "ldr d22, [x23], #0x8\n" "ldr d21, [x22], #0x8\n" - "ldr d16, [x21], #0x8\n" + "ldr d20, [x21], #0x8\n" "tbz %x[width], #2, 7f\n" "ld1 { v27.s }[2], [x28], #0x4\n" - "ld1 { v19.s }[2], [x27], #0x4\n" + "ld1 { v26.s }[2], [x27], #0x4\n" "ld1 { v25.s }[2], [x26], #0x4\n" - "ld1 { v18.s }[2], [x25], #0x4\n" + "ld1 { v24.s }[2], [x25], #0x4\n" "ld1 { v23.s }[2], [x24], #0x4\n" - "ld1 { v17.s }[2], [x23], #0x4\n" + "ld1 { v22.s }[2], [x23], #0x4\n" "ld1 { v21.s }[2], [x22], #0x4\n" - "ld1 { v16.s }[2], [x21], #0x4\n" + "ld1 { v20.s }[2], [x21], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v27.h }[6], [x28], #0x2\n" - "ld1 { v19.h }[6], [x27], #0x2\n" + "ld1 { v26.h }[6], [x27], #0x2\n" "mov x20, #0x2\n" "ld1 { v25.h }[6], [x26], #0x2\n" - "ld1 { v18.h }[6], [x25], #0x2\n" + "ld1 { v24.h }[6], [x25], #0x2\n" "ld1 { v23.h }[6], [x24], #0x2\n" - "ld1 { v17.h }[6], [x23], #0x2\n" + "ld1 { v22.h }[6], [x23], #0x2\n" "ld1 { v21.h }[6], [x22], #0x2\n" - "ld1 { v16.h }[6], [x21], #0x2\n" + "ld1 { v20.h }[6], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[14], [x28]\n" - "ld1 { v19.b }[14], [x27]\n" + "ld1 { v26.b }[14], [x27]\n" "ld1 { v25.b }[14], [x26]\n" - "ld1 { v18.b }[14], [x25]\n" + "ld1 { v24.b }[14], [x25]\n" "ld1 { v23.b }[14], [x24]\n" - "ld1 { v17.b }[14], [x23]\n" + "ld1 { v22.b }[14], [x23]\n" "ld1 { v21.b }[14], [x22]\n" - "ld1 { v16.b }[14], [x21]\n" + "ld1 { v20.b }[14], [x21]\n" "b 13f\n" "6:" // odd_loads_1_12 "mov x20, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[12], [x28]\n" - "ld1 { v19.b }[12], [x27]\n" + "ld1 { v26.b }[12], [x27]\n" "ld1 { v25.b }[12], [x26]\n" - "ld1 { v18.b }[12], [x25]\n" + "ld1 { v24.b }[12], [x25]\n" "ld1 { v23.b }[12], [x24]\n" - "ld1 { v17.b }[12], [x23]\n" + "ld1 { v22.b }[12], [x23]\n" "ld1 { v21.b }[12], [x22]\n" - "ld1 { v16.b }[12], [x21]\n" + "ld1 { v20.b }[12], [x21]\n" "b 13f\n" "7:" // odd_loads_2_8 "tbz %x[width], #1, 8f\n" "ld1 { v27.h }[4], [x28], #0x2\n" - "ld1 { v19.h }[4], [x27], #0x2\n" + "ld1 { v26.h }[4], [x27], #0x2\n" "mov x20, #0x2\n" "ld1 { v25.h }[4], [x26], #0x2\n" - "ld1 { v18.h }[4], [x25], #0x2\n" + "ld1 { v24.h }[4], [x25], #0x2\n" "ld1 { v23.h }[4], [x24], #0x2\n" - "ld1 { v17.h }[4], [x23], #0x2\n" + "ld1 { v22.h }[4], [x23], #0x2\n" "ld1 { v21.h }[4], [x22], #0x2\n" - "ld1 { v16.h }[4], [x21], #0x2\n" + "ld1 { v20.h }[4], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[10], [x28]\n" - "ld1 { v19.b }[10], [x27]\n" + "ld1 { v26.b }[10], [x27]\n" "ld1 { v25.b }[10], [x26]\n" - "ld1 { v18.b }[10], [x25]\n" + "ld1 { v24.b }[10], [x25]\n" "ld1 { v23.b }[10], [x24]\n" - "ld1 { v17.b }[10], [x23]\n" + "ld1 { v22.b }[10], [x23]\n" "ld1 { v21.b }[10], [x22]\n" - "ld1 { v16.b }[10], [x21]\n" + "ld1 { v20.b }[10], [x21]\n" "b 13f\n" "8:" // odd_loads_1_8 "mov x20, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[8], [x28]\n" - "ld1 { v19.b }[8], [x27]\n" + "ld1 { v26.b }[8], [x27]\n" "mov x20, #0x2\n" "ld1 { v25.b }[8], [x26]\n" - "ld1 { v18.b }[8], [x25]\n" + "ld1 { v24.b }[8], [x25]\n" "ld1 { v23.b }[8], [x24]\n" - "ld1 { v17.b }[8], [x23]\n" + "ld1 { v22.b }[8], [x23]\n" "ld1 { v21.b }[8], [x22]\n" - "ld1 { v16.b }[8], [x21]\n" + "ld1 { v20.b }[8], [x21]\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" "ldr s27, [x28], #0x4\n" - "ldr s19, [x27], #0x4\n" + "ldr s26, [x27], #0x4\n" "ldr s25, [x26], #0x4\n" - "ldr s18, [x25], #0x4\n" + "ldr s24, [x25], #0x4\n" "ldr s23, [x24], #0x4\n" - "ldr s17, [x23], #0x4\n" + "ldr s22, [x23], #0x4\n" "ldr s21, [x22], #0x4\n" - "ldr s16, [x21], #0x4\n" + "ldr s20, [x21], #0x4\n" "tbz %x[width], #1, 10f\n" "ld1 { v27.h }[2], [x28], #0x2\n" - "ld1 { v19.h }[2], [x27], #0x2\n" + "ld1 { v26.h }[2], [x27], #0x2\n" "mov x20, #0x1\n" "ld1 { v25.h }[2], [x26], #0x2\n" - "ld1 { v18.h }[2], [x25], #0x2\n" + "ld1 { v24.h }[2], [x25], #0x2\n" "ld1 { v23.h }[2], [x24], #0x2\n" - "ld1 { v17.h }[2], [x23], #0x2\n" + "ld1 { v22.h }[2], [x23], #0x2\n" "ld1 { v21.h }[2], [x22], #0x2\n" - "ld1 { v16.h }[2], [x21], #0x2\n" + "ld1 { v20.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[6], [x28]\n" - "ld1 { v19.b }[6], [x27]\n" + "ld1 { v26.b }[6], [x27]\n" "ld1 { v25.b }[6], [x26]\n" - "ld1 { v18.b }[6], [x25]\n" + "ld1 { v24.b }[6], [x25]\n" "ld1 { v23.b }[6], [x24]\n" - "ld1 { v17.b }[6], [x23]\n" + "ld1 { v22.b }[6], [x23]\n" "ld1 { v21.b }[6], [x22]\n" - "ld1 { v16.b }[6], [x21]\n" + "ld1 { v20.b }[6], [x21]\n" "b 13f\n" "10:" // odd_loads_1_4 "mov x20, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[4], [x28]\n" - "ld1 { v19.b }[4], [x27]\n" + "ld1 { v26.b }[4], [x27]\n" "ld1 { v25.b }[4], [x26]\n" - "ld1 { v18.b }[4], [x25]\n" + "ld1 { v24.b }[4], [x25]\n" "ld1 { v23.b }[4], [x24]\n" - "ld1 { v17.b }[4], [x23]\n" + "ld1 { v22.b }[4], [x23]\n" "ld1 { v21.b }[4], [x22]\n" - "ld1 { v16.b }[4], [x21]\n" + "ld1 { v20.b }[4], [x21]\n" "b 13f\n" "11:" // odd_loads_2_0 "tbz %x[width], #1, 12f\n" "ldr h27, [x28], #0x2\n" - "ldr h19, [x27], #0x2\n" + "ldr h26, [x27], #0x2\n" "mov x20, #0x1\n" "ldr h25, [x26], #0x2\n" - "ldr h18, [x25], #0x2\n" + "ldr h24, [x25], #0x2\n" "ldr h23, [x24], #0x2\n" - "ldr h17, [x23], #0x2\n" + "ldr h22, [x23], #0x2\n" "ldr h21, [x22], #0x2\n" - "ldr h16, [x21], #0x2\n" + "ldr h20, [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[2], [x28]\n" - "ld1 { v19.b }[2], [x27]\n" + "ld1 { v26.b }[2], [x27]\n" "ld1 { v25.b }[2], [x26]\n" - "ld1 { v18.b }[2], [x25]\n" + "ld1 { v24.b }[2], [x25]\n" "ld1 { v23.b }[2], [x24]\n" - "ld1 { v17.b }[2], [x23]\n" + "ld1 { v22.b }[2], [x23]\n" "ld1 { v21.b }[2], [x22]\n" - "ld1 { v16.b }[2], [x21]\n" + "ld1 { v20.b }[2], [x21]\n" "b 13f\n" "12:" // odd_loads_1_0 "ldr b27, [x28, #0x0]\n" - "ldr b19, [x27, #0x0]\n" + "ldr b26, [x27, #0x0]\n" "mov x20, #0x1\n" "ldr b25, [x26, #0x0]\n" - "ldr b18, [x25, #0x0]\n" + "ldr b24, [x25, #0x0]\n" "ldr b23, [x24, #0x0]\n" - "ldr b17, [x23, #0x0]\n" + "ldr b22, [x23, #0x0]\n" "ldr b21, [x22, #0x0]\n" - "ldr b16, [x21, #0x0]\n" + "ldr b20, [x21, #0x0]\n" "13:" // Odd load end - "zip1 v26.2d, v27.2d, v19.2d\n" - "zip1 v24.2d, v25.2d, v18.2d\n" + "zip1 v19.2d, v27.2d, v26.2d\n" + "zip1 v18.2d, v25.2d, v24.2d\n" "subs x20, x20, #0x1\n" - "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v22.2d, v23.2d, v17.2d\n" - "zip1 v20.2d, v21.2d, v16.2d\n" - "str q24, [%x[out_ptr], #0x10]\n" - "sadalp v5.8h, v26.16b\n" - "sadalp v4.8h, v24.16b\n" - "str q22, [%x[out_ptr], #0x20]\n" - "sadalp v3.8h, v22.16b\n" - "str q20, [%x[out_ptr], #0x30]\n" - "sadalp v2.8h, v20.16b\n" + "str q19, [%x[out_ptr], #0x0]\n" + "zip1 v17.2d, v23.2d, v22.2d\n" + "zip1 v16.2d, v21.2d, v20.2d\n" + "str q18, [%x[out_ptr], #0x10]\n" + "sadalp v5.8h, v19.16b\n" + "sadalp v4.8h, v18.16b\n" + "str q17, [%x[out_ptr], #0x20]\n" + "sadalp v3.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x30]\n" + "sadalp v2.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 14f\n" - "zip2 v19.2d, v27.2d, v19.2d\n" - "zip2 v18.2d, v25.2d, v18.2d\n" + "zip2 v19.2d, v27.2d, v26.2d\n" + "zip2 v18.2d, v25.2d, v24.2d\n" "str q19, [%x[out_ptr], #0x0]\n" - "zip2 v17.2d, v23.2d, v17.2d\n" - "zip2 v16.2d, v21.2d, v16.2d\n" + "zip2 v17.2d, v23.2d, v22.2d\n" + "zip2 v16.2d, v21.2d, v20.2d\n" "str q18, [%x[out_ptr], #0x10]\n" "sadalp v5.8h, v19.16b\n" "sadalp v4.8h, v18.16b\n" @@ -346,11 +346,11 @@ void interleave_block<8, 8, VLType::None, true>( "sadalp v31.4s, v3.8h\n" "sadalp v30.4s, v2.8h\n" "addp v1.4s, v1.4s, v0.4s\n" - "addp v0.4s, v31.4s, v30.4s\n" + "addp v16.4s, v31.4s, v30.4s\n" "add v1.4s, v1.4s, v29.4s\n" - "add v0.4s, v0.4s, v28.4s\n" + "add v16.4s, v16.4s, v28.4s\n" "str q1, [%x[out_ptr], #0x0]\n" - "str q0, [%x[out_ptr], #0x10]\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp index 6c4a5fa62b..56d34a8a64 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/a64_interleave8_block8_u8_u8_summing.hpp @@ -156,182 +156,182 @@ void interleave_block<8, 8, VLType::None, true>( "cbz %x[width], 14f\n" "tbz %x[width], #3, 9f\n" "ldr d27, [x28], #0x8\n" - "ldr d19, [x27], #0x8\n" + "ldr d26, [x27], #0x8\n" "ldr d25, [x26], #0x8\n" - "ldr d18, [x25], #0x8\n" + "ldr d24, [x25], #0x8\n" "ldr d23, [x24], #0x8\n" - "ldr d17, [x23], #0x8\n" + "ldr d22, [x23], #0x8\n" "ldr d21, [x22], #0x8\n" - "ldr d16, [x21], #0x8\n" + "ldr d20, [x21], #0x8\n" "tbz %x[width], #2, 7f\n" "ld1 { v27.s }[2], [x28], #0x4\n" - "ld1 { v19.s }[2], [x27], #0x4\n" + "ld1 { v26.s }[2], [x27], #0x4\n" "ld1 { v25.s }[2], [x26], #0x4\n" - "ld1 { v18.s }[2], [x25], #0x4\n" + "ld1 { v24.s }[2], [x25], #0x4\n" "ld1 { v23.s }[2], [x24], #0x4\n" - "ld1 { v17.s }[2], [x23], #0x4\n" + "ld1 { v22.s }[2], [x23], #0x4\n" "ld1 { v21.s }[2], [x22], #0x4\n" - "ld1 { v16.s }[2], [x21], #0x4\n" + "ld1 { v20.s }[2], [x21], #0x4\n" "tbz %x[width], #1, 6f\n" "ld1 { v27.h }[6], [x28], #0x2\n" - "ld1 { v19.h }[6], [x27], #0x2\n" + "ld1 { v26.h }[6], [x27], #0x2\n" "mov x20, #0x2\n" "ld1 { v25.h }[6], [x26], #0x2\n" - "ld1 { v18.h }[6], [x25], #0x2\n" + "ld1 { v24.h }[6], [x25], #0x2\n" "ld1 { v23.h }[6], [x24], #0x2\n" - "ld1 { v17.h }[6], [x23], #0x2\n" + "ld1 { v22.h }[6], [x23], #0x2\n" "ld1 { v21.h }[6], [x22], #0x2\n" - "ld1 { v16.h }[6], [x21], #0x2\n" + "ld1 { v20.h }[6], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[14], [x28]\n" - "ld1 { v19.b }[14], [x27]\n" + "ld1 { v26.b }[14], [x27]\n" "ld1 { v25.b }[14], [x26]\n" - "ld1 { v18.b }[14], [x25]\n" + "ld1 { v24.b }[14], [x25]\n" "ld1 { v23.b }[14], [x24]\n" - "ld1 { v17.b }[14], [x23]\n" + "ld1 { v22.b }[14], [x23]\n" "ld1 { v21.b }[14], [x22]\n" - "ld1 { v16.b }[14], [x21]\n" + "ld1 { v20.b }[14], [x21]\n" "b 13f\n" "6:" // odd_loads_1_12 "mov x20, #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[12], [x28]\n" - "ld1 { v19.b }[12], [x27]\n" + "ld1 { v26.b }[12], [x27]\n" "ld1 { v25.b }[12], [x26]\n" - "ld1 { v18.b }[12], [x25]\n" + "ld1 { v24.b }[12], [x25]\n" "ld1 { v23.b }[12], [x24]\n" - "ld1 { v17.b }[12], [x23]\n" + "ld1 { v22.b }[12], [x23]\n" "ld1 { v21.b }[12], [x22]\n" - "ld1 { v16.b }[12], [x21]\n" + "ld1 { v20.b }[12], [x21]\n" "b 13f\n" "7:" // odd_loads_2_8 "tbz %x[width], #1, 8f\n" "ld1 { v27.h }[4], [x28], #0x2\n" - "ld1 { v19.h }[4], [x27], #0x2\n" + "ld1 { v26.h }[4], [x27], #0x2\n" "mov x20, #0x2\n" "ld1 { v25.h }[4], [x26], #0x2\n" - "ld1 { v18.h }[4], [x25], #0x2\n" + "ld1 { v24.h }[4], [x25], #0x2\n" "ld1 { v23.h }[4], [x24], #0x2\n" - "ld1 { v17.h }[4], [x23], #0x2\n" + "ld1 { v22.h }[4], [x23], #0x2\n" "ld1 { v21.h }[4], [x22], #0x2\n" - "ld1 { v16.h }[4], [x21], #0x2\n" + "ld1 { v20.h }[4], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[10], [x28]\n" - "ld1 { v19.b }[10], [x27]\n" + "ld1 { v26.b }[10], [x27]\n" "ld1 { v25.b }[10], [x26]\n" - "ld1 { v18.b }[10], [x25]\n" + "ld1 { v24.b }[10], [x25]\n" "ld1 { v23.b }[10], [x24]\n" - "ld1 { v17.b }[10], [x23]\n" + "ld1 { v22.b }[10], [x23]\n" "ld1 { v21.b }[10], [x22]\n" - "ld1 { v16.b }[10], [x21]\n" + "ld1 { v20.b }[10], [x21]\n" "b 13f\n" "8:" // odd_loads_1_8 "mov x20, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[8], [x28]\n" - "ld1 { v19.b }[8], [x27]\n" + "ld1 { v26.b }[8], [x27]\n" "mov x20, #0x2\n" "ld1 { v25.b }[8], [x26]\n" - "ld1 { v18.b }[8], [x25]\n" + "ld1 { v24.b }[8], [x25]\n" "ld1 { v23.b }[8], [x24]\n" - "ld1 { v17.b }[8], [x23]\n" + "ld1 { v22.b }[8], [x23]\n" "ld1 { v21.b }[8], [x22]\n" - "ld1 { v16.b }[8], [x21]\n" + "ld1 { v20.b }[8], [x21]\n" "b 13f\n" "9:" // odd_loads_4_0 "tbz %x[width], #2, 11f\n" "ldr s27, [x28], #0x4\n" - "ldr s19, [x27], #0x4\n" + "ldr s26, [x27], #0x4\n" "ldr s25, [x26], #0x4\n" - "ldr s18, [x25], #0x4\n" + "ldr s24, [x25], #0x4\n" "ldr s23, [x24], #0x4\n" - "ldr s17, [x23], #0x4\n" + "ldr s22, [x23], #0x4\n" "ldr s21, [x22], #0x4\n" - "ldr s16, [x21], #0x4\n" + "ldr s20, [x21], #0x4\n" "tbz %x[width], #1, 10f\n" "ld1 { v27.h }[2], [x28], #0x2\n" - "ld1 { v19.h }[2], [x27], #0x2\n" + "ld1 { v26.h }[2], [x27], #0x2\n" "mov x20, #0x1\n" "ld1 { v25.h }[2], [x26], #0x2\n" - "ld1 { v18.h }[2], [x25], #0x2\n" + "ld1 { v24.h }[2], [x25], #0x2\n" "ld1 { v23.h }[2], [x24], #0x2\n" - "ld1 { v17.h }[2], [x23], #0x2\n" + "ld1 { v22.h }[2], [x23], #0x2\n" "ld1 { v21.h }[2], [x22], #0x2\n" - "ld1 { v16.h }[2], [x21], #0x2\n" + "ld1 { v20.h }[2], [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[6], [x28]\n" - "ld1 { v19.b }[6], [x27]\n" + "ld1 { v26.b }[6], [x27]\n" "ld1 { v25.b }[6], [x26]\n" - "ld1 { v18.b }[6], [x25]\n" + "ld1 { v24.b }[6], [x25]\n" "ld1 { v23.b }[6], [x24]\n" - "ld1 { v17.b }[6], [x23]\n" + "ld1 { v22.b }[6], [x23]\n" "ld1 { v21.b }[6], [x22]\n" - "ld1 { v16.b }[6], [x21]\n" + "ld1 { v20.b }[6], [x21]\n" "b 13f\n" "10:" // odd_loads_1_4 "mov x20, #0x1\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[4], [x28]\n" - "ld1 { v19.b }[4], [x27]\n" + "ld1 { v26.b }[4], [x27]\n" "ld1 { v25.b }[4], [x26]\n" - "ld1 { v18.b }[4], [x25]\n" + "ld1 { v24.b }[4], [x25]\n" "ld1 { v23.b }[4], [x24]\n" - "ld1 { v17.b }[4], [x23]\n" + "ld1 { v22.b }[4], [x23]\n" "ld1 { v21.b }[4], [x22]\n" - "ld1 { v16.b }[4], [x21]\n" + "ld1 { v20.b }[4], [x21]\n" "b 13f\n" "11:" // odd_loads_2_0 "tbz %x[width], #1, 12f\n" "ldr h27, [x28], #0x2\n" - "ldr h19, [x27], #0x2\n" + "ldr h26, [x27], #0x2\n" "mov x20, #0x1\n" "ldr h25, [x26], #0x2\n" - "ldr h18, [x25], #0x2\n" + "ldr h24, [x25], #0x2\n" "ldr h23, [x24], #0x2\n" - "ldr h17, [x23], #0x2\n" + "ldr h22, [x23], #0x2\n" "ldr h21, [x22], #0x2\n" - "ldr h16, [x21], #0x2\n" + "ldr h20, [x21], #0x2\n" "tbz %x[width], #0, 13f\n" "ld1 { v27.b }[2], [x28]\n" - "ld1 { v19.b }[2], [x27]\n" + "ld1 { v26.b }[2], [x27]\n" "ld1 { v25.b }[2], [x26]\n" - "ld1 { v18.b }[2], [x25]\n" + "ld1 { v24.b }[2], [x25]\n" "ld1 { v23.b }[2], [x24]\n" - "ld1 { v17.b }[2], [x23]\n" + "ld1 { v22.b }[2], [x23]\n" "ld1 { v21.b }[2], [x22]\n" - "ld1 { v16.b }[2], [x21]\n" + "ld1 { v20.b }[2], [x21]\n" "b 13f\n" "12:" // odd_loads_1_0 "ldr b27, [x28, #0x0]\n" - "ldr b19, [x27, #0x0]\n" + "ldr b26, [x27, #0x0]\n" "mov x20, #0x1\n" "ldr b25, [x26, #0x0]\n" - "ldr b18, [x25, #0x0]\n" + "ldr b24, [x25, #0x0]\n" "ldr b23, [x24, #0x0]\n" - "ldr b17, [x23, #0x0]\n" + "ldr b22, [x23, #0x0]\n" "ldr b21, [x22, #0x0]\n" - "ldr b16, [x21, #0x0]\n" + "ldr b20, [x21, #0x0]\n" "13:" // Odd load end - "zip1 v26.2d, v27.2d, v19.2d\n" - "zip1 v24.2d, v25.2d, v18.2d\n" + "zip1 v19.2d, v27.2d, v26.2d\n" + "zip1 v18.2d, v25.2d, v24.2d\n" "subs x20, x20, #0x1\n" - "str q26, [%x[out_ptr], #0x0]\n" - "zip1 v22.2d, v23.2d, v17.2d\n" - "zip1 v20.2d, v21.2d, v16.2d\n" - "str q24, [%x[out_ptr], #0x10]\n" - "uadalp v5.8h, v26.16b\n" - "uadalp v4.8h, v24.16b\n" - "str q22, [%x[out_ptr], #0x20]\n" - "uadalp v3.8h, v22.16b\n" - "str q20, [%x[out_ptr], #0x30]\n" - "uadalp v2.8h, v20.16b\n" + "str q19, [%x[out_ptr], #0x0]\n" + "zip1 v17.2d, v23.2d, v22.2d\n" + "zip1 v16.2d, v21.2d, v20.2d\n" + "str q18, [%x[out_ptr], #0x10]\n" + "uadalp v5.8h, v19.16b\n" + "uadalp v4.8h, v18.16b\n" + "str q17, [%x[out_ptr], #0x20]\n" + "uadalp v3.8h, v17.16b\n" + "str q16, [%x[out_ptr], #0x30]\n" + "uadalp v2.8h, v16.16b\n" "add %x[out_ptr], %x[out_ptr], #0x40\n" "beq 14f\n" - "zip2 v19.2d, v27.2d, v19.2d\n" - "zip2 v18.2d, v25.2d, v18.2d\n" + "zip2 v19.2d, v27.2d, v26.2d\n" + "zip2 v18.2d, v25.2d, v24.2d\n" "str q19, [%x[out_ptr], #0x0]\n" - "zip2 v17.2d, v23.2d, v17.2d\n" - "zip2 v16.2d, v21.2d, v16.2d\n" + "zip2 v17.2d, v23.2d, v22.2d\n" + "zip2 v16.2d, v21.2d, v20.2d\n" "str q18, [%x[out_ptr], #0x10]\n" "uadalp v5.8h, v19.16b\n" "uadalp v4.8h, v18.16b\n" @@ -346,11 +346,11 @@ void interleave_block<8, 8, VLType::None, true>( "uadalp v31.4s, v3.8h\n" "uadalp v30.4s, v2.8h\n" "addp v1.4s, v1.4s, v0.4s\n" - "addp v0.4s, v31.4s, v30.4s\n" + "addp v16.4s, v31.4s, v30.4s\n" "add v1.4s, v1.4s, v29.4s\n" - "add v0.4s, v0.4s, v28.4s\n" + "add v16.4s, v16.4s, v28.4s\n" "str q1, [%x[out_ptr], #0x0]\n" - "str q0, [%x[out_ptr], #0x10]\n" + "str q16, [%x[out_ptr], #0x10]\n" "add %x[out_ptr], %x[out_ptr], #0x20\n" : [out_ptr] "+&r" (out_ptr), [width] "+&r" (width) : [first] "r" (first), [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave1VL_block2_fp32_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave1VL_block2_fp32_bf16.hpp index 51b91d16e1..a5f4754d3d 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave1VL_block2_fp32_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave1VL_block2_fp32_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME2) template <> void interleave_block<1, 2, VLType::SME, false>( bfloat16 * &out, const float * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x22, ALL, MUL #2\n" @@ -153,4 +151,4 @@ void interleave_block<1, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave2VL_block2_fp32_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave2VL_block2_fp32_bf16.hpp index 25bfad18b1..c1d0ac5bc7 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave2VL_block2_fp32_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave2VL_block2_fp32_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME2) template <> void interleave_block<2, 2, VLType::SME, false>( bfloat16 * &out, const float * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x22, ALL, MUL #2\n" @@ -184,4 +182,4 @@ void interleave_block<2, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave4VL_block2_fp32_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave4VL_block2_fp32_bf16.hpp index 9255831e86..03575d7ff2 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave4VL_block2_fp32_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme2_interleave4VL_block2_fp32_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME2) template <> void interleave_block<4, 2, VLType::SME, false>( bfloat16 * &out, const float * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x23, ALL, MUL #2\n" @@ -159,4 +157,4 @@ void interleave_block<4, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_bf16_bf16.hpp index 9b66a6fb10..453778ae3f 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_bf16_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 1, VLType::SME, false>( bfloat16 * &out, const bfloat16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "mov x21, %x[width]\n" @@ -168,9 +166,9 @@ void interleave_block<1, 1, VLType::SME, false>( "9:" // K loop: Tails: Even: First ".inst 0x25286d20 // psel p0.h, p11.h/Z, p9.h[w12]\n" ".inst 0xe07f82a0 // st1h { za0v.h[x12] }, p0/Z, [x21, XZR, LSL #1]\n" - "ldr x25, [x26, #0x0]\n" + "ldr x20, [x26, #0x0]\n" ".inst 0x25286140 // psel p0.h, p8.h/Z, p10.h[w12]\n" - ".inst 0xe0560328 // ld1h { za1h.h[x12] }, p0/Z, [x25, x22, LSL #1]\n" + ".inst 0xe0560288 // ld1h { za1h.h[x12] }, p0/Z, [x20, x22, LSL #1]\n" "add x12, x12, #0x1\n" "cmp x12, x11\n" "add x26, x26, #0x8\n" @@ -186,7 +184,7 @@ void interleave_block<1, 1, VLType::SME, false>( "cmp x12, x10\n" "addvl x21, x21, #1\n" "blt 10b\n" - "whilelt p9.h, x27, %x[width]\n" + "whilelt p8.h, x27, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -206,4 +204,4 @@ void interleave_block<1, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block2_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block2_bf16_bf16.hpp index d0375de76f..98bdcd2fa2 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block2_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block2_bf16_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 2, VLType::SME, false>( bfloat16 * &out, const bfloat16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cnth x22\n" @@ -176,11 +174,11 @@ void interleave_block<1, 2, VLType::SME, false>( "9:" // K loop: Tails: Even: First ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" - "ldr x25, [x26, #0x0]\n" + "ldr x20, [x26, #0x0]\n" "add x12, x12, #0x1\n" ".inst 0x25396140 // psel p0.h, p8.h/Z, p10.h[w13, #1]\n" "cmp x12, x10\n" - ".inst 0xe0562321 // ld1h { za0h.h[x13, #1] }, p0/Z, [x25, x22, LSL #1]\n" + ".inst 0xe0562281 // ld1h { za0h.h[x13, #1] }, p0/Z, [x20, x22, LSL #1]\n" "add x26, x26, #0x8\n" "addvl x21, x21, #1\n" "add x13, x13, #0x2\n" @@ -197,7 +195,7 @@ void interleave_block<1, 2, VLType::SME, false>( "addvl x21, x21, #1\n" "add x20, x20, #0x2\n" "blt 10b\n" - "whilelt p9.h, x27, %x[width]\n" + "whilelt p8.h, x27, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -217,4 +215,4 @@ void interleave_block<1, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8.hpp index 622d9aa4fc..4390bb7c7f 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 4, VLType::SME, false>( int8_t * &out, const int8_t * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntb x21\n" @@ -179,11 +177,11 @@ void interleave_block<1, 4, VLType::SME, false>( "9:" // K loop: Tails: Even: First ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" - "ldr x25, [x26, #0x0]\n" + "ldr x20, [x26, #0x0]\n" "add x12, x12, #0x1\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" "cmp x12, x9\n" - ".inst 0xe0162322 // ld1b { za0h.b[x13, #2] }, p0/Z, [x25, x22]\n" + ".inst 0xe0162282 // ld1b { za0h.b[x13, #2] }, p0/Z, [x20, x22]\n" "add x26, x26, #0x8\n" "addvl x21, x21, #1\n" "add x13, x13, #0x4\n" @@ -200,7 +198,7 @@ void interleave_block<1, 4, VLType::SME, false>( "addvl x21, x21, #1\n" "add x20, x20, #0x4\n" "blt 10b\n" - "whilelt p9.b, x27, %x[width]\n" + "whilelt p8.b, x27, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -220,4 +218,4 @@ void interleave_block<1, 4, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8_summing.hpp index 07f03702d9..f5ee261964 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_s8_s8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 4, VLType::SME, true>( @@ -200,12 +200,12 @@ void interleave_block<1, 4, VLType::SME, true>( "10:" // K loop: Tails: Even: First ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8300 // st1w { za0v.s[x12] }, p0/Z, [x24, XZR, LSL #2]\n" - "ldr x22, [x23, #0x0]\n" + "ldr x20, [x23, #0x0]\n" ".inst 0xc0828810 // mova z16.s, p2/M, za0v.s[x12]\n" "add x12, x12, #0x1\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" "sdot z17.s, z16.b, z18.b\n" - ".inst 0xe01922c2 // ld1b { za0h.b[x13, #2] }, p0/Z, [x22, x25]\n" + ".inst 0xe0192282 // ld1b { za0h.b[x13, #2] }, p0/Z, [x20, x25]\n" "cmp x12, x9\n" "add x23, x23, #0x8\n" "addvl x24, x24, #1\n" @@ -225,7 +225,7 @@ void interleave_block<1, 4, VLType::SME, true>( "addvl x24, x24, #1\n" "add x20, x20, #0x4\n" "blt 11b\n" - "whilelt p9.b, x28, %x[width]\n" + "whilelt p8.b, x28, %x[width]\n" "b 14f\n" "12:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -249,4 +249,4 @@ void interleave_block<1, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8.hpp index 618570de08..76c1d053cd 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 4, VLType::SME, false>( uint8_t * &out, const uint8_t * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntb x21\n" @@ -179,11 +177,11 @@ void interleave_block<1, 4, VLType::SME, false>( "9:" // K loop: Tails: Even: First ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" - "ldr x25, [x26, #0x0]\n" + "ldr x20, [x26, #0x0]\n" "add x12, x12, #0x1\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" "cmp x12, x9\n" - ".inst 0xe0162322 // ld1b { za0h.b[x13, #2] }, p0/Z, [x25, x22]\n" + ".inst 0xe0162282 // ld1b { za0h.b[x13, #2] }, p0/Z, [x20, x22]\n" "add x26, x26, #0x8\n" "addvl x21, x21, #1\n" "add x13, x13, #0x4\n" @@ -200,7 +198,7 @@ void interleave_block<1, 4, VLType::SME, false>( "addvl x21, x21, #1\n" "add x20, x20, #0x4\n" "blt 10b\n" - "whilelt p9.b, x27, %x[width]\n" + "whilelt p8.b, x27, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -220,4 +218,4 @@ void interleave_block<1, 4, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8_summing.hpp index 646db0caa8..daf2d3a100 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_block4_u8_u8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 4, VLType::SME, true>( @@ -200,12 +200,12 @@ void interleave_block<1, 4, VLType::SME, true>( "10:" // K loop: Tails: Even: First ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8300 // st1w { za0v.s[x12] }, p0/Z, [x24, XZR, LSL #2]\n" - "ldr x22, [x23, #0x0]\n" + "ldr x20, [x23, #0x0]\n" ".inst 0xc0828810 // mova z16.s, p2/M, za0v.s[x12]\n" "add x12, x12, #0x1\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" "udot z17.s, z16.b, z18.b\n" - ".inst 0xe01922c2 // ld1b { za0h.b[x13, #2] }, p0/Z, [x22, x25]\n" + ".inst 0xe0192282 // ld1b { za0h.b[x13, #2] }, p0/Z, [x20, x25]\n" "cmp x12, x9\n" "add x23, x23, #0x8\n" "addvl x24, x24, #1\n" @@ -225,7 +225,7 @@ void interleave_block<1, 4, VLType::SME, true>( "addvl x24, x24, #1\n" "add x20, x20, #0x4\n" "blt 11b\n" - "whilelt p9.b, x28, %x[width]\n" + "whilelt p8.b, x28, %x[width]\n" "b 14f\n" "12:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -249,4 +249,4 @@ void interleave_block<1, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp16_fp16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp16_fp16.hpp index 788c1a2eca..274f69f370 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp16_fp16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp16_fp16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 1, VLType::SME, false>( __fp16 * &out, const __fp16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "mov x21, %x[width]\n" @@ -168,9 +166,9 @@ void interleave_block<1, 1, VLType::SME, false>( "9:" // K loop: Tails: Even: First ".inst 0x25286d20 // psel p0.h, p11.h/Z, p9.h[w12]\n" ".inst 0xe07f82a0 // st1h { za0v.h[x12] }, p0/Z, [x21, XZR, LSL #1]\n" - "ldr x25, [x26, #0x0]\n" + "ldr x20, [x26, #0x0]\n" ".inst 0x25286140 // psel p0.h, p8.h/Z, p10.h[w12]\n" - ".inst 0xe0560328 // ld1h { za1h.h[x12] }, p0/Z, [x25, x22, LSL #1]\n" + ".inst 0xe0560288 // ld1h { za1h.h[x12] }, p0/Z, [x20, x22, LSL #1]\n" "add x12, x12, #0x1\n" "cmp x12, x11\n" "add x26, x26, #0x8\n" @@ -186,7 +184,7 @@ void interleave_block<1, 1, VLType::SME, false>( "cmp x12, x10\n" "addvl x21, x21, #1\n" "blt 10b\n" - "whilelt p9.h, x27, %x[width]\n" + "whilelt p8.h, x27, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -206,4 +204,4 @@ void interleave_block<1, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp32_fp32.hpp index 7de88543d7..ab290649fd 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave1VL_fp32_fp32.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<1, 1, VLType::SME, false>( float * &out, const float * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "mov x22, %x[width]\n" @@ -167,9 +165,9 @@ void interleave_block<1, 1, VLType::SME, false>( "9:" // K loop: Tails: Even: First ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" - "ldr x25, [x26, #0x0]\n" + "ldr x20, [x26, #0x0]\n" ".inst 0x25306140 // psel p0.s, p8.s/Z, p10.s[w12]\n" - ".inst 0xe0960328 // ld1w { za2h.s[x12] }, p0/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0960288 // ld1w { za2h.s[x12] }, p0/Z, [x20, x22, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x10\n" "add x26, x26, #0x8\n" @@ -185,7 +183,7 @@ void interleave_block<1, 1, VLType::SME, false>( "cmp x12, x9\n" "addvl x21, x21, #1\n" "blt 10b\n" - "whilelt p9.s, x27, %x[width]\n" + "whilelt p8.s, x27, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -205,4 +203,4 @@ void interleave_block<1, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_bf16_bf16.hpp index 14ee5d6304..dc6d12b61e 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_bf16_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 1, VLType::SME, false>( bfloat16 * &out, const bfloat16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cnth x28\n" @@ -97,4 +95,4 @@ void interleave_block<2, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_bf16_bf16.hpp index f648ccf771..d9189258c1 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_bf16_bf16.hpp @@ -22,32 +22,30 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 2, VLType::SME, false>( bfloat16 * &out, const bfloat16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" - "cnth x21\n" - "mov x22, %x[width]\n" - "inch x22\n" + "cnth x22\n" + "mov x21, %x[width]\n" + "inch x21\n" "mov x20, %x[width]\n" - "sub x17, x21, #0x1\n" - "sub x22, x22, #0x1\n" + "sub x17, x22, #0x1\n" + "sub x21, x21, #0x1\n" "ands x17, x20, x17\n" "cntw x16\n" - "udiv x22, x22, x21\n" // n_passes = ceildiv(width, VL<T>) - "csel x17, x17, x21, NE\n" - "sub x13, x22, #0x1\n" + "udiv x21, x21, x22\n" // n_passes = ceildiv(width, VL<T>) + "csel x17, x17, x22, NE\n" + "sub x13, x21, #0x1\n" "add x17, x17, #0x1\n" "sub x15, x16, #0x2\n" - "lsl x21, %x[height], #0x1\n" // height * 2 + "lsl x22, %x[height], #0x1\n" // height * 2 "lsl x20, x16, #0x1\n" "mov x14, #0x0\n" "mov x11, %x[in]\n" @@ -57,15 +55,15 @@ void interleave_block<2, 2, VLType::SME, false>( "cntw x27, ALL, MUL #3\n" "ldr x26, [x10, #0x0]\n" "lsr x13, x13, #0x1\n" // n_loops = (n_passes - 1) / 2 - "and x25, x22, #0x1\n" // odd_tail = bool(n_passes & 0x1) + "and x25, x21, #0x1\n" // odd_tail = bool(n_passes & 0x1) "ldr x24, [x11, #0x8]\n" "lsr x17, x17, #0x1\n" "ptrue p13.s\n" - "ldr x23, [x10, #0x8]\n" - "whilelt p12.h, XZR, x21\n" - "whilelt p11.h, x20, x21\n" - "mov x22, %x[row_offset]\n" - "mov x21, %x[out]\n" + "ldr x21, [x10, #0x8]\n" + "whilelt p12.h, XZR, x22\n" + "whilelt p11.h, x20, x22\n" + "mov x23, %x[row_offset]\n" + "mov x22, %x[out]\n" "whilelt p10.h, x14, %x[width]\n" "whilelt p9.h, x14, %x[width]\n" "whilelt p8.h, x14, %x[width]\n" @@ -76,39 +74,39 @@ void interleave_block<2, 2, VLType::SME, false>( "1:" // K loop: Charge: Loop ".inst 0x25286581 // psel p1.h, p9.h/Z, p12.h[w12]\n" ".inst 0x25286160 // psel p0.h, p8.h/Z, p11.h[w12]\n" - ".inst 0xe0560520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x22, LSL #1]\n" + ".inst 0xe0570520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe0560348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0570348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25686581 // psel p1.h, p9.h/Z, p12.h[w12, #2]\n" ".inst 0x25686160 // psel p0.h, p8.h/Z, p11.h[w12, #2]\n" "ldr x26, [x10, #0x0]\n" - ".inst 0xe0560702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0570702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" "add x11, x11, #0x10\n" - ".inst 0xe05602ea // ld1h { za1h.h[x12, #2] }, p0/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05702aa // ld1h { za1h.h[x12, #2] }, p0/Z, [x21, x23, LSL #1]\n" "add x12, x12, #0x4\n" "cmp x12, x15, LSL #1\n" - "ldr x23, [x10, #0x8]\n" + "ldr x21, [x10, #0x8]\n" "add x10, x10, #0x10\n" "blt 1b\n" "2:" // K loop: Charge: End ".inst 0x25286581 // psel p1.h, p9.h/Z, p12.h[w12]\n" ".inst 0x25286160 // psel p0.h, p8.h/Z, p11.h[w12]\n" - ".inst 0xe0560520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0560348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0570520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x23, LSL #1]\n" + ".inst 0xe0570348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25686581 // psel p1.h, p9.h/Z, p12.h[w12, #2]\n" ".inst 0x25686160 // psel p0.h, p8.h/Z, p11.h[w12, #2]\n" "mov x11, %x[in]\n" "add x10, %x[in], x16, LSL #3\n" - ".inst 0xe0560702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0570702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe05602ea // ld1h { za1h.h[x12, #2] }, p0/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05702aa // ld1h { za1h.h[x12, #2] }, p0/Z, [x21, x23, LSL #1]\n" "ldr x26, [x10, #0x0]\n" - "inch x22\n" + "inch x23\n" "inch x14\n" "ldr x24, [x11, #0x8]\n" "add x11, x11, #0x10\n" - "ldr x23, [x10, #0x8]\n" + "ldr x21, [x10, #0x8]\n" "add x10, x10, #0x10\n" "cbz x13, 8f\n" "mov x20, x13\n" @@ -121,60 +119,60 @@ void interleave_block<2, 2, VLType::SME, false>( "4:" // K loop: Main loop: First: Loop ".inst 0x25396581 // psel p1.h, p9.h/Z, p12.h[w13, #1]\n" ".inst 0x25396160 // psel p0.h, p8.h/Z, p11.h[w13, #1]\n" - ".inst 0xe0562521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x22, LSL #1]\n" + ".inst 0xe0572521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe0562349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25796580 // psel p0.h, p9.h/Z, p12.h[w13, #3]\n" ".inst 0x25796162 // psel p2.h, p8.h/Z, p11.h[w13, #3]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307541 // psel p1.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562aeb // ld1h { za1h.h[x13, #3] }, p2/Z, [x23, x22, LSL #1]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf86a0 // st1w { za0v.s[x12] }, p1/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0572aab // ld1h { za1h.h[x13, #3] }, p2/Z, [x21, x23, LSL #1]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf86c0 // st1w { za0v.s[x12] }, p1/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" "add x11, x11, #0x10\n" - ".inst 0xe0bc86a1 // st1w { za0v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c1 // st1w { za0v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x10, x10, #0x10\n" "add x13, x13, #0x4\n" - ".inst 0xe0bb82a5 // st1w { za1v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" + ".inst 0xe0bb82c5 // st1w { za1v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x15\n" - "addvl x21, x21, #4\n" + "addvl x22, x22, #4\n" "blt 4b\n" "5:" // K loop: Main loop: First: Tail ".inst 0x25396581 // psel p1.h, p9.h/Z, p12.h[w13, #1]\n" ".inst 0x25396160 // psel p0.h, p8.h/Z, p11.h[w13, #1]\n" - ".inst 0xe0562521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0562349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x23, LSL #1]\n" + ".inst 0xe0572349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x23, LSL #1]\n" "mov x11, %x[in]\n" "add x10, %x[in], x16, LSL #3\n" "ldr x9, [x11, #0x0]\n" ".inst 0x25796580 // psel p0.h, p9.h/Z, p12.h[w13, #3]\n" ".inst 0x25796161 // psel p1.h, p8.h/Z, p11.h[w13, #3]\n" - ".inst 0xe0562303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe05626eb // ld1h { za1h.h[x13, #3] }, p1/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05726ab // ld1h { za1h.h[x13, #3] }, p1/Z, [x21, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307542 // psel p2.s, p13.s/Z, p10.s[w12]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b08aa4 // st1w { za1v.s[x12] }, p2/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b08ac4 // st1w { za1v.s[x12] }, p2/Z, [x22, x16, LSL #2]\n" "whilelt p10.h, x14, %x[width]\n" "inch x14\n" - ".inst 0xe0bc86a1 // st1w { za0v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c1 // st1w { za0v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x11, x11, #0x10\n" "add x10, x10, #0x10\n" - ".inst 0xe0bb82a5 // st1w { za1v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" - "addvl x21, x21, #4\n" - "inch x22\n" + ".inst 0xe0bb82c5 // st1w { za1v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" + "addvl x22, x22, #4\n" + "inch x23\n" "whilelt p9.h, x14, %x[width]\n" "whilelt p8.h, x14, %x[width]\n" "mov x13, #0x0\n" @@ -183,61 +181,61 @@ void interleave_block<2, 2, VLType::SME, false>( "6:" // K loop: Main loop: Second: Loop ".inst 0x25296581 // psel p1.h, p9.h/Z, p12.h[w13]\n" ".inst 0x25296160 // psel p0.h, p8.h/Z, p11.h[w13]\n" - ".inst 0xe0562520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x22, LSL #1]\n" + ".inst 0xe0572520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe0562348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25696580 // psel p0.h, p9.h/Z, p12.h[w13, #2]\n" ".inst 0x25696162 // psel p2.h, p8.h/Z, p11.h[w13, #2]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307541 // psel p1.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562aea // ld1h { za1h.h[x13, #2] }, p2/Z, [x23, x22, LSL #1]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf86a8 // st1w { za2v.s[x12] }, p1/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0572aaa // ld1h { za1h.h[x13, #2] }, p2/Z, [x21, x23, LSL #1]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf86c8 // st1w { za2v.s[x12] }, p1/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b082ac // st1w { za3v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082cc // st1w { za3v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" "add x11, x11, #0x10\n" - ".inst 0xe0bc86a9 // st1w { za2v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c9 // st1w { za2v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x10, x10, #0x10\n" "add x13, x13, #0x4\n" - ".inst 0xe0bb82ad // st1w { za3v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" + ".inst 0xe0bb82cd // st1w { za3v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x15\n" - "addvl x21, x21, #4\n" + "addvl x22, x22, #4\n" "blt 6b\n" "7:" // K loop: Main loop: Second: Tail ".inst 0x25296581 // psel p1.h, p9.h/Z, p12.h[w13]\n" ".inst 0x25296160 // psel p0.h, p8.h/Z, p11.h[w13]\n" - ".inst 0xe0562520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0562348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x23, LSL #1]\n" + ".inst 0xe0572348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x23, LSL #1]\n" "mov x11, %x[in]\n" "add x10, %x[in], x16, LSL #3\n" "ldr x9, [x11, #0x0]\n" ".inst 0x25696580 // psel p0.h, p9.h/Z, p12.h[w13, #2]\n" ".inst 0x25696161 // psel p1.h, p8.h/Z, p11.h[w13, #2]\n" - ".inst 0xe0562302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe05626ea // ld1h { za1h.h[x13, #2] }, p1/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05726aa // ld1h { za1h.h[x13, #2] }, p1/Z, [x21, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307542 // psel p2.s, p13.s/Z, p10.s[w12]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf82a8 // st1w { za2v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf82c8 // st1w { za2v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b08aac // st1w { za3v.s[x12] }, p2/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b08acc // st1w { za3v.s[x12] }, p2/Z, [x22, x16, LSL #2]\n" "whilelt p10.h, x14, %x[width]\n" "subs x20, x20, #0x1\n" - ".inst 0xe0bc86a9 // st1w { za2v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c9 // st1w { za2v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x11, x11, #0x10\n" "add x10, x10, #0x10\n" - ".inst 0xe0bb82ad // st1w { za3v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" - "addvl x21, x21, #4\n" + ".inst 0xe0bb82cd // st1w { za3v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" + "addvl x22, x22, #4\n" "inch x14\n" - "inch x22\n" + "inch x23\n" "bgt 3b\n" "8:" // K loop: Tails "cbnz x25, 11f\n" @@ -248,51 +246,51 @@ void interleave_block<2, 2, VLType::SME, false>( "mov x12, #0x0\n" "9:" // K loop: Tails: Even: First ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" - "ldr x9, [x11, #0x0]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" + "ldr x21, [x11, #0x0]\n" "add x12, x12, #0x1\n" ".inst 0x25396581 // psel p1.h, p9.h/Z, p12.h[w13, #1]\n" - "ldr x26, [x11, x16, LSL #0x3]\n" + "ldr x20, [x11, x16, LSL #0x3]\n" ".inst 0x25396160 // psel p0.h, p8.h/Z, p11.h[w13, #1]\n" "cmp x12, x16\n" - ".inst 0xe0562521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0562349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe05726a1 // ld1h { za0h.h[x13, #1] }, p1/Z, [x21, x23, LSL #1]\n" + ".inst 0xe0572289 // ld1h { za1h.h[x13, #1] }, p0/Z, [x20, x23, LSL #1]\n" "add x11, x11, #0x8\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "add x13, x13, #0x2\n" "blt 9b\n" "whilelt p10.h, x14, %x[width]\n" - "whilelt p9.h, x14, %x[width]\n" + "whilelt p8.h, x14, %x[width]\n" "whilelt p8.h, x14, %x[width]\n" "mov x20, #0x0\n" "mov x12, #0x0\n" "10:" // K loop: Tails: Even: Second ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a8 // st1w { za2v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c8 // st1w { za2v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082ac // st1w { za3v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082cc // st1w { za3v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "add x20, x20, #0x2\n" "blt 10b\n" - "whilelt p10.h, x14, %x[width]\n" + "whilelt p8.h, x14, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" "12:" // K loop: Tails: Odd: Loop ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "blt 12b\n" "13:" // K loop: End - "mov %x[out], x21\n" + "mov %x[out], x22\n" ".inst 0xd503467f // SMSTOP\n" : [out] "+&r" (out) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset), [width] "r" (width) @@ -300,4 +298,4 @@ void interleave_block<2, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_fp16_fp16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_fp16_fp16.hpp index 61536d38a5..ef787c89b9 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_fp16_fp16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block2_fp16_fp16.hpp @@ -22,32 +22,30 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 2, VLType::SME, false>( __fp16 * &out, const __fp16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" - "cnth x21\n" - "mov x22, %x[width]\n" - "inch x22\n" + "cnth x22\n" + "mov x21, %x[width]\n" + "inch x21\n" "mov x20, %x[width]\n" - "sub x17, x21, #0x1\n" - "sub x22, x22, #0x1\n" + "sub x17, x22, #0x1\n" + "sub x21, x21, #0x1\n" "ands x17, x20, x17\n" "cntw x16\n" - "udiv x22, x22, x21\n" // n_passes = ceildiv(width, VL<T>) - "csel x17, x17, x21, NE\n" - "sub x13, x22, #0x1\n" + "udiv x21, x21, x22\n" // n_passes = ceildiv(width, VL<T>) + "csel x17, x17, x22, NE\n" + "sub x13, x21, #0x1\n" "add x17, x17, #0x1\n" "sub x15, x16, #0x2\n" - "lsl x21, %x[height], #0x1\n" // height * 2 + "lsl x22, %x[height], #0x1\n" // height * 2 "lsl x20, x16, #0x1\n" "mov x14, #0x0\n" "mov x11, %x[in]\n" @@ -57,15 +55,15 @@ void interleave_block<2, 2, VLType::SME, false>( "cntw x27, ALL, MUL #3\n" "ldr x26, [x10, #0x0]\n" "lsr x13, x13, #0x1\n" // n_loops = (n_passes - 1) / 2 - "and x25, x22, #0x1\n" // odd_tail = bool(n_passes & 0x1) + "and x25, x21, #0x1\n" // odd_tail = bool(n_passes & 0x1) "ldr x24, [x11, #0x8]\n" "lsr x17, x17, #0x1\n" "ptrue p13.s\n" - "ldr x23, [x10, #0x8]\n" - "whilelt p12.h, XZR, x21\n" - "whilelt p11.h, x20, x21\n" - "mov x22, %x[row_offset]\n" - "mov x21, %x[out]\n" + "ldr x21, [x10, #0x8]\n" + "whilelt p12.h, XZR, x22\n" + "whilelt p11.h, x20, x22\n" + "mov x23, %x[row_offset]\n" + "mov x22, %x[out]\n" "whilelt p10.h, x14, %x[width]\n" "whilelt p9.h, x14, %x[width]\n" "whilelt p8.h, x14, %x[width]\n" @@ -76,39 +74,39 @@ void interleave_block<2, 2, VLType::SME, false>( "1:" // K loop: Charge: Loop ".inst 0x25286581 // psel p1.h, p9.h/Z, p12.h[w12]\n" ".inst 0x25286160 // psel p0.h, p8.h/Z, p11.h[w12]\n" - ".inst 0xe0560520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x22, LSL #1]\n" + ".inst 0xe0570520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe0560348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0570348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25686581 // psel p1.h, p9.h/Z, p12.h[w12, #2]\n" ".inst 0x25686160 // psel p0.h, p8.h/Z, p11.h[w12, #2]\n" "ldr x26, [x10, #0x0]\n" - ".inst 0xe0560702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0570702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" "add x11, x11, #0x10\n" - ".inst 0xe05602ea // ld1h { za1h.h[x12, #2] }, p0/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05702aa // ld1h { za1h.h[x12, #2] }, p0/Z, [x21, x23, LSL #1]\n" "add x12, x12, #0x4\n" "cmp x12, x15, LSL #1\n" - "ldr x23, [x10, #0x8]\n" + "ldr x21, [x10, #0x8]\n" "add x10, x10, #0x10\n" "blt 1b\n" "2:" // K loop: Charge: End ".inst 0x25286581 // psel p1.h, p9.h/Z, p12.h[w12]\n" ".inst 0x25286160 // psel p0.h, p8.h/Z, p11.h[w12]\n" - ".inst 0xe0560520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0560348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0570520 // ld1h { za0h.h[x12] }, p1/Z, [x9, x23, LSL #1]\n" + ".inst 0xe0570348 // ld1h { za1h.h[x12] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25686581 // psel p1.h, p9.h/Z, p12.h[w12, #2]\n" ".inst 0x25686160 // psel p0.h, p8.h/Z, p11.h[w12, #2]\n" "mov x11, %x[in]\n" "add x10, %x[in], x16, LSL #3\n" - ".inst 0xe0560702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0570702 // ld1h { za0h.h[x12, #2] }, p1/Z, [x24, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe05602ea // ld1h { za1h.h[x12, #2] }, p0/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05702aa // ld1h { za1h.h[x12, #2] }, p0/Z, [x21, x23, LSL #1]\n" "ldr x26, [x10, #0x0]\n" - "inch x22\n" + "inch x23\n" "inch x14\n" "ldr x24, [x11, #0x8]\n" "add x11, x11, #0x10\n" - "ldr x23, [x10, #0x8]\n" + "ldr x21, [x10, #0x8]\n" "add x10, x10, #0x10\n" "cbz x13, 8f\n" "mov x20, x13\n" @@ -121,60 +119,60 @@ void interleave_block<2, 2, VLType::SME, false>( "4:" // K loop: Main loop: First: Loop ".inst 0x25396581 // psel p1.h, p9.h/Z, p12.h[w13, #1]\n" ".inst 0x25396160 // psel p0.h, p8.h/Z, p11.h[w13, #1]\n" - ".inst 0xe0562521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x22, LSL #1]\n" + ".inst 0xe0572521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe0562349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25796580 // psel p0.h, p9.h/Z, p12.h[w13, #3]\n" ".inst 0x25796162 // psel p2.h, p8.h/Z, p11.h[w13, #3]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307541 // psel p1.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562aeb // ld1h { za1h.h[x13, #3] }, p2/Z, [x23, x22, LSL #1]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf86a0 // st1w { za0v.s[x12] }, p1/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0572aab // ld1h { za1h.h[x13, #3] }, p2/Z, [x21, x23, LSL #1]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf86c0 // st1w { za0v.s[x12] }, p1/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" "add x11, x11, #0x10\n" - ".inst 0xe0bc86a1 // st1w { za0v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c1 // st1w { za0v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x10, x10, #0x10\n" "add x13, x13, #0x4\n" - ".inst 0xe0bb82a5 // st1w { za1v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" + ".inst 0xe0bb82c5 // st1w { za1v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x15\n" - "addvl x21, x21, #4\n" + "addvl x22, x22, #4\n" "blt 4b\n" "5:" // K loop: Main loop: First: Tail ".inst 0x25396581 // psel p1.h, p9.h/Z, p12.h[w13, #1]\n" ".inst 0x25396160 // psel p0.h, p8.h/Z, p11.h[w13, #1]\n" - ".inst 0xe0562521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0562349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x23, LSL #1]\n" + ".inst 0xe0572349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x23, LSL #1]\n" "mov x11, %x[in]\n" "add x10, %x[in], x16, LSL #3\n" "ldr x9, [x11, #0x0]\n" ".inst 0x25796580 // psel p0.h, p9.h/Z, p12.h[w13, #3]\n" ".inst 0x25796161 // psel p1.h, p8.h/Z, p11.h[w13, #3]\n" - ".inst 0xe0562303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572303 // ld1h { za0h.h[x13, #3] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe05626eb // ld1h { za1h.h[x13, #3] }, p1/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05726ab // ld1h { za1h.h[x13, #3] }, p1/Z, [x21, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307542 // psel p2.s, p13.s/Z, p10.s[w12]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b08aa4 // st1w { za1v.s[x12] }, p2/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b08ac4 // st1w { za1v.s[x12] }, p2/Z, [x22, x16, LSL #2]\n" "whilelt p10.h, x14, %x[width]\n" "inch x14\n" - ".inst 0xe0bc86a1 // st1w { za0v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c1 // st1w { za0v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x11, x11, #0x10\n" "add x10, x10, #0x10\n" - ".inst 0xe0bb82a5 // st1w { za1v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" - "addvl x21, x21, #4\n" - "inch x22\n" + ".inst 0xe0bb82c5 // st1w { za1v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" + "addvl x22, x22, #4\n" + "inch x23\n" "whilelt p9.h, x14, %x[width]\n" "whilelt p8.h, x14, %x[width]\n" "mov x13, #0x0\n" @@ -183,61 +181,61 @@ void interleave_block<2, 2, VLType::SME, false>( "6:" // K loop: Main loop: Second: Loop ".inst 0x25296581 // psel p1.h, p9.h/Z, p12.h[w13]\n" ".inst 0x25296160 // psel p0.h, p8.h/Z, p11.h[w13]\n" - ".inst 0xe0562520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x22, LSL #1]\n" + ".inst 0xe0572520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x23, LSL #1]\n" "ldr x9, [x11, #0x0]\n" - ".inst 0xe0562348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x23, LSL #1]\n" ".inst 0x25696580 // psel p0.h, p9.h/Z, p12.h[w13, #2]\n" ".inst 0x25696162 // psel p2.h, p8.h/Z, p11.h[w13, #2]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307541 // psel p1.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0562aea // ld1h { za1h.h[x13, #2] }, p2/Z, [x23, x22, LSL #1]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf86a8 // st1w { za2v.s[x12] }, p1/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0572aaa // ld1h { za1h.h[x13, #2] }, p2/Z, [x21, x23, LSL #1]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf86c8 // st1w { za2v.s[x12] }, p1/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b082ac // st1w { za3v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082cc // st1w { za3v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" "add x11, x11, #0x10\n" - ".inst 0xe0bc86a9 // st1w { za2v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c9 // st1w { za2v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x10, x10, #0x10\n" "add x13, x13, #0x4\n" - ".inst 0xe0bb82ad // st1w { za3v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" + ".inst 0xe0bb82cd // st1w { za3v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x15\n" - "addvl x21, x21, #4\n" + "addvl x22, x22, #4\n" "blt 6b\n" "7:" // K loop: Main loop: Second: Tail ".inst 0x25296581 // psel p1.h, p9.h/Z, p12.h[w13]\n" ".inst 0x25296160 // psel p0.h, p8.h/Z, p11.h[w13]\n" - ".inst 0xe0562520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0562348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe0572520 // ld1h { za0h.h[x13] }, p1/Z, [x9, x23, LSL #1]\n" + ".inst 0xe0572348 // ld1h { za1h.h[x13] }, p0/Z, [x26, x23, LSL #1]\n" "mov x11, %x[in]\n" "add x10, %x[in], x16, LSL #3\n" "ldr x9, [x11, #0x0]\n" ".inst 0x25696580 // psel p0.h, p9.h/Z, p12.h[w13, #2]\n" ".inst 0x25696161 // psel p1.h, p8.h/Z, p11.h[w13, #2]\n" - ".inst 0xe0562302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x22, LSL #1]\n" + ".inst 0xe0572302 // ld1h { za0h.h[x13, #2] }, p0/Z, [x24, x23, LSL #1]\n" "ldr x26, [x10, #0x0]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe05626ea // ld1h { za1h.h[x13, #2] }, p1/Z, [x23, x22, LSL #1]\n" + ".inst 0xe05726aa // ld1h { za1h.h[x13, #2] }, p1/Z, [x21, x23, LSL #1]\n" "ldr x24, [x11, #0x8]\n" ".inst 0x25307542 // psel p2.s, p13.s/Z, p10.s[w12]\n" - "ldr x23, [x10, #0x8]\n" - ".inst 0xe0bf82a8 // st1w { za2v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + "ldr x21, [x10, #0x8]\n" + ".inst 0xe0bf82c8 // st1w { za2v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b08aac // st1w { za3v.s[x12] }, p2/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b08acc // st1w { za3v.s[x12] }, p2/Z, [x22, x16, LSL #2]\n" "whilelt p10.h, x14, %x[width]\n" "subs x20, x20, #0x1\n" - ".inst 0xe0bc86a9 // st1w { za2v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c9 // st1w { za2v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x11, x11, #0x10\n" "add x10, x10, #0x10\n" - ".inst 0xe0bb82ad // st1w { za3v.s[x12, #1] }, p0/Z, [x21, x27, LSL #2]\n" - "addvl x21, x21, #4\n" + ".inst 0xe0bb82cd // st1w { za3v.s[x12, #1] }, p0/Z, [x22, x27, LSL #2]\n" + "addvl x22, x22, #4\n" "inch x14\n" - "inch x22\n" + "inch x23\n" "bgt 3b\n" "8:" // K loop: Tails "cbnz x25, 11f\n" @@ -248,51 +246,51 @@ void interleave_block<2, 2, VLType::SME, false>( "mov x12, #0x0\n" "9:" // K loop: Tails: Even: First ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" - "ldr x9, [x11, #0x0]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" + "ldr x21, [x11, #0x0]\n" "add x12, x12, #0x1\n" ".inst 0x25396581 // psel p1.h, p9.h/Z, p12.h[w13, #1]\n" - "ldr x26, [x11, x16, LSL #0x3]\n" + "ldr x20, [x11, x16, LSL #0x3]\n" ".inst 0x25396160 // psel p0.h, p8.h/Z, p11.h[w13, #1]\n" "cmp x12, x16\n" - ".inst 0xe0562521 // ld1h { za0h.h[x13, #1] }, p1/Z, [x9, x22, LSL #1]\n" - ".inst 0xe0562349 // ld1h { za1h.h[x13, #1] }, p0/Z, [x26, x22, LSL #1]\n" + ".inst 0xe05726a1 // ld1h { za0h.h[x13, #1] }, p1/Z, [x21, x23, LSL #1]\n" + ".inst 0xe0572289 // ld1h { za1h.h[x13, #1] }, p0/Z, [x20, x23, LSL #1]\n" "add x11, x11, #0x8\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "add x13, x13, #0x2\n" "blt 9b\n" "whilelt p10.h, x14, %x[width]\n" - "whilelt p9.h, x14, %x[width]\n" + "whilelt p8.h, x14, %x[width]\n" "whilelt p8.h, x14, %x[width]\n" "mov x20, #0x0\n" "mov x12, #0x0\n" "10:" // K loop: Tails: Even: Second ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a8 // st1w { za2v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c8 // st1w { za2v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082ac // st1w { za3v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082cc // st1w { za3v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "add x20, x20, #0x2\n" "blt 10b\n" - "whilelt p10.h, x14, %x[width]\n" + "whilelt p8.h, x14, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" "12:" // K loop: Tails: Odd: Loop ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "blt 12b\n" "13:" // K loop: End - "mov %x[out], x21\n" + "mov %x[out], x22\n" ".inst 0xd503467f // SMSTOP\n" : [out] "+&r" (out) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset), [width] "r" (width) @@ -300,4 +298,4 @@ void interleave_block<2, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8.hpp index 4c701cff19..905c6b41eb 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 4, VLType::SME, false>( int8_t * &out, const int8_t * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntb x21\n" @@ -248,13 +246,13 @@ void interleave_block<2, 4, VLType::SME, false>( ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" - "ldr x9, [x11, #0x0]\n" + "ldr x20, [x11, #0x0]\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" - ".inst 0xe0162122 // ld1b { za0h.b[x13, #2] }, p0/Z, [x9, x22]\n" - "ldr x26, [x11, x16, LSL #0x3]\n" + ".inst 0xe0162282 // ld1b { za0h.b[x13, #2] }, p0/Z, [x20, x22]\n" + "ldr x20, [x11, x16, LSL #0x3]\n" "add x12, x12, #0x1\n" ".inst 0x253d6140 // psel p0.b, p8.b/Z, p10.b[w13, #3]\n" - ".inst 0xe0162343 // ld1b { za0h.b[x13, #3] }, p0/Z, [x26, x22]\n" + ".inst 0xe0162283 // ld1b { za0h.b[x13, #3] }, p0/Z, [x20, x22]\n" "cmp x12, x16\n" "add x11, x11, #0x8\n" "addvl x21, x21, #2\n" @@ -274,7 +272,7 @@ void interleave_block<2, 4, VLType::SME, false>( "addvl x21, x21, #2\n" "add x20, x20, #0x4\n" "blt 10b\n" - "whilelt p9.b, x14, %x[width]\n" + "whilelt p8.b, x14, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -296,4 +294,4 @@ void interleave_block<2, 4, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8_summing.hpp index 25262d3db9..c5c5af20e2 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_s8_s8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 4, VLType::SME, true>( @@ -140,23 +140,23 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0xe01c2aa7 // ld1b { za0h.b[x13, #7] }, p2/Z, [x21, x28]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8760 // st1w { za0v.s[x12] }, p1/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" - ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" - "sdot z19.s, z16.b, z20.b\n" + ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" + "sdot z19.s, z17.b, z20.b\n" ".inst 0xe0b08364 // st1w { za1v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" ".inst 0xe0ae8361 // st1w { za0v.s[x12, #1] }, p0/Z, [x27, x14, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829030 // mova z16.s, p4/M, za0v.s[x12, #1]\n" + ".inst 0xc0829031 // mova z17.s, p4/M, za0v.s[x12, #1]\n" ".inst 0xe0ab8365 // st1w { za1v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" - ".inst 0xc08290b1 // mova z17.s, p4/M, za1v.s[x12, #1]\n" + ".inst 0xc08290b0 // mova z16.s, p4/M, za1v.s[x12, #1]\n" "add x12, x12, #0x2\n" "cmp x12, x9\n" "add x26, x26, #0x10\n" "add x25, x25, #0x10\n" - "sdot z19.s, z16.b, z20.b\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" "addvl x27, x27, #4\n" "add x13, x13, #0x8\n" "blt 5b\n" @@ -172,28 +172,28 @@ void interleave_block<2, 4, VLType::SME, true>( "add x25, %x[in], x16, LSL #3\n" "ldr x24, [x26, #0x0]\n" ".inst 0xe01c22a7 // ld1b { za0h.b[x13, #7] }, p0/Z, [x21, x28]\n" - ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" ".inst 0x25306d23 // psel p3.s, p11.s/Z, p9.s[w12]\n" - "sdot z19.s, z16.b, z20.b\n" - ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" + ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" + "sdot z18.s, z16.b, z20.b\n" "ldr x23, [x25, #0x0]\n" ".inst 0x25306d22 // psel p2.s, p11.s/Z, p9.s[w12]\n" "ldr x22, [x26, #0x8]\n" ".inst 0x25706d21 // psel p1.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829030 // mova z16.s, p4/M, za0v.s[x12, #1]\n" + ".inst 0xc0829031 // mova z17.s, p4/M, za0v.s[x12, #1]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8f60 // st1w { za0v.s[x12] }, p3/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc08290b1 // mova z17.s, p4/M, za1v.s[x12, #1]\n" + ".inst 0xc08290b0 // mova z16.s, p4/M, za1v.s[x12, #1]\n" "whilelt p9.b, x15, %x[width]\n" ".inst 0xe0b08b64 // st1w { za1v.s[x12] }, p2/Z, [x27, x16, LSL #2]\n" "incb x15\n" "add x26, x26, #0x10\n" - "sdot z19.s, z16.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" ".inst 0xe0ae8761 // st1w { za0v.s[x12, #1] }, p1/Z, [x27, x14, LSL #2]\n" "add x25, x25, #0x10\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" "incb x28\n" ".inst 0xe0ab8365 // st1w { za1v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" "addvl x27, x27, #4\n" @@ -217,23 +217,23 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0xe01c2aa5 // ld1b { za0h.b[x13, #5] }, p2/Z, [x21, x28]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8768 // st1w { za2v.s[x12] }, p1/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc0829110 // mova z16.s, p4/M, za2v.s[x12]\n" - ".inst 0xc0829191 // mova z17.s, p4/M, za3v.s[x12]\n" - "sdot z19.s, z16.b, z20.b\n" + ".inst 0xc0829111 // mova z17.s, p4/M, za2v.s[x12]\n" + ".inst 0xc0829190 // mova z16.s, p4/M, za3v.s[x12]\n" + "sdot z19.s, z17.b, z20.b\n" ".inst 0xe0b0836c // st1w { za3v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" ".inst 0xe0ae8369 // st1w { za2v.s[x12, #1] }, p0/Z, [x27, x14, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829130 // mova z16.s, p4/M, za2v.s[x12, #1]\n" + ".inst 0xc0829131 // mova z17.s, p4/M, za2v.s[x12, #1]\n" ".inst 0xe0ab836d // st1w { za3v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" - ".inst 0xc08291b1 // mova z17.s, p4/M, za3v.s[x12, #1]\n" + ".inst 0xc08291b0 // mova z16.s, p4/M, za3v.s[x12, #1]\n" "add x12, x12, #0x2\n" "cmp x12, x9\n" "add x26, x26, #0x10\n" "add x25, x25, #0x10\n" - "sdot z19.s, z16.b, z20.b\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" "addvl x27, x27, #4\n" "add x13, x13, #0x8\n" "blt 7b\n" @@ -249,28 +249,28 @@ void interleave_block<2, 4, VLType::SME, true>( "add x25, %x[in], x16, LSL #3\n" "ldr x24, [x26, #0x0]\n" ".inst 0xe01c22a5 // ld1b { za0h.b[x13, #5] }, p0/Z, [x21, x28]\n" - ".inst 0xc0829110 // mova z16.s, p4/M, za2v.s[x12]\n" + ".inst 0xc0829111 // mova z17.s, p4/M, za2v.s[x12]\n" ".inst 0x25306d23 // psel p3.s, p11.s/Z, p9.s[w12]\n" - "sdot z19.s, z16.b, z20.b\n" - ".inst 0xc0829191 // mova z17.s, p4/M, za3v.s[x12]\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" + ".inst 0xc0829190 // mova z16.s, p4/M, za3v.s[x12]\n" + "sdot z18.s, z16.b, z20.b\n" "ldr x23, [x25, #0x0]\n" ".inst 0x25306d22 // psel p2.s, p11.s/Z, p9.s[w12]\n" "ldr x22, [x26, #0x8]\n" ".inst 0x25706d21 // psel p1.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829130 // mova z16.s, p4/M, za2v.s[x12, #1]\n" + ".inst 0xc0829131 // mova z17.s, p4/M, za2v.s[x12, #1]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8f68 // st1w { za2v.s[x12] }, p3/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc08291b1 // mova z17.s, p4/M, za3v.s[x12, #1]\n" + ".inst 0xc08291b0 // mova z16.s, p4/M, za3v.s[x12, #1]\n" "whilelt p9.b, x15, %x[width]\n" ".inst 0xe0b08b6c // st1w { za3v.s[x12] }, p2/Z, [x27, x16, LSL #2]\n" "subs x20, x20, #0x1\n" "add x26, x26, #0x10\n" - "sdot z19.s, z16.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" ".inst 0xe0ae8769 // st1w { za2v.s[x12, #1] }, p1/Z, [x27, x14, LSL #2]\n" "add x25, x25, #0x10\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" "incb x15\n" ".inst 0xe0ab836d // st1w { za3v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" "addvl x27, x27, #4\n" @@ -286,19 +286,19 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8360 // st1w { za0v.s[x12] }, p0/Z, [x27, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" ".inst 0xe0b08364 // st1w { za1v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" - "ldr x24, [x26, #0x0]\n" + "ldr x21, [x26, #0x0]\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" - ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" - "ldr x23, [x26, x16, LSL #0x3]\n" - ".inst 0xe01c2302 // ld1b { za0h.b[x13, #2] }, p0/Z, [x24, x28]\n" + ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" + "ldr x20, [x26, x16, LSL #0x3]\n" + ".inst 0xe01c22a2 // ld1b { za0h.b[x13, #2] }, p0/Z, [x21, x28]\n" "add x12, x12, #0x1\n" ".inst 0x253d6140 // psel p0.b, p8.b/Z, p10.b[w13, #3]\n" "cmp x12, x16\n" - "sdot z19.s, z16.b, z20.b\n" - "sdot z18.s, z17.b, z20.b\n" - ".inst 0xe01c22e3 // ld1b { za0h.b[x13, #3] }, p0/Z, [x23, x28]\n" + "sdot z19.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" + ".inst 0xe01c2283 // ld1b { za0h.b[x13, #3] }, p0/Z, [x20, x28]\n" "add x26, x26, #0x8\n" "addvl x27, x27, #2\n" "add x13, x13, #0x4\n" @@ -311,17 +311,17 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8368 // st1w { za2v.s[x12] }, p0/Z, [x27, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0829110 // mova z16.s, p4/M, za2v.s[x12]\n" + ".inst 0xc0829111 // mova z17.s, p4/M, za2v.s[x12]\n" ".inst 0xe0b0836c // st1w { za3v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" - ".inst 0xc0829191 // mova z17.s, p4/M, za3v.s[x12]\n" + ".inst 0xc0829190 // mova z16.s, p4/M, za3v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "sdot z19.s, z16.b, z20.b\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" "addvl x27, x27, #2\n" "add x20, x20, #0x4\n" "blt 11b\n" - "whilelt p9.b, x15, %x[width]\n" + "whilelt p8.b, x15, %x[width]\n" "b 14f\n" "12:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -329,13 +329,13 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8360 // st1w { za0v.s[x12] }, p0/Z, [x27, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" ".inst 0xe0b08364 // st1w { za1v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" - ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" + ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "sdot z19.s, z16.b, z20.b\n" - "sdot z18.s, z17.b, z20.b\n" + "sdot z19.s, z17.b, z20.b\n" + "sdot z18.s, z16.b, z20.b\n" "addvl x27, x27, #2\n" "blt 13b\n" "14:" // K loop: End @@ -350,4 +350,4 @@ void interleave_block<2, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8.hpp index 683a315a96..ce9a0065c7 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 4, VLType::SME, false>( uint8_t * &out, const uint8_t * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntb x21\n" @@ -248,13 +246,13 @@ void interleave_block<2, 4, VLType::SME, false>( ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" - "ldr x9, [x11, #0x0]\n" + "ldr x20, [x11, #0x0]\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" - ".inst 0xe0162122 // ld1b { za0h.b[x13, #2] }, p0/Z, [x9, x22]\n" - "ldr x26, [x11, x16, LSL #0x3]\n" + ".inst 0xe0162282 // ld1b { za0h.b[x13, #2] }, p0/Z, [x20, x22]\n" + "ldr x20, [x11, x16, LSL #0x3]\n" "add x12, x12, #0x1\n" ".inst 0x253d6140 // psel p0.b, p8.b/Z, p10.b[w13, #3]\n" - ".inst 0xe0162343 // ld1b { za0h.b[x13, #3] }, p0/Z, [x26, x22]\n" + ".inst 0xe0162283 // ld1b { za0h.b[x13, #3] }, p0/Z, [x20, x22]\n" "cmp x12, x16\n" "add x11, x11, #0x8\n" "addvl x21, x21, #2\n" @@ -274,7 +272,7 @@ void interleave_block<2, 4, VLType::SME, false>( "addvl x21, x21, #2\n" "add x20, x20, #0x4\n" "blt 10b\n" - "whilelt p9.b, x14, %x[width]\n" + "whilelt p8.b, x14, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -296,4 +294,4 @@ void interleave_block<2, 4, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8_summing.hpp index e7571f7da7..7805152656 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_block4_u8_u8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 4, VLType::SME, true>( @@ -140,23 +140,23 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0xe01c2aa7 // ld1b { za0h.b[x13, #7] }, p2/Z, [x21, x28]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8760 // st1w { za0v.s[x12] }, p1/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" - ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" - "udot z19.s, z17.b, z20.b\n" + ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" + "udot z19.s, z16.b, z20.b\n" ".inst 0xe0b08364 // st1w { za1v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - "udot z18.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" ".inst 0xe0ae8361 // st1w { za0v.s[x12, #1] }, p0/Z, [x27, x14, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829031 // mova z17.s, p4/M, za0v.s[x12, #1]\n" + ".inst 0xc0829030 // mova z16.s, p4/M, za0v.s[x12, #1]\n" ".inst 0xe0ab8365 // st1w { za1v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" - ".inst 0xc08290b0 // mova z16.s, p4/M, za1v.s[x12, #1]\n" + ".inst 0xc08290b1 // mova z17.s, p4/M, za1v.s[x12, #1]\n" "add x12, x12, #0x2\n" "cmp x12, x9\n" "add x26, x26, #0x10\n" "add x25, x25, #0x10\n" - "udot z19.s, z17.b, z20.b\n" - "udot z18.s, z16.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" "addvl x27, x27, #4\n" "add x13, x13, #0x8\n" "blt 5b\n" @@ -172,28 +172,28 @@ void interleave_block<2, 4, VLType::SME, true>( "add x25, %x[in], x16, LSL #3\n" "ldr x24, [x26, #0x0]\n" ".inst 0xe01c22a7 // ld1b { za0h.b[x13, #7] }, p0/Z, [x21, x28]\n" - ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" ".inst 0x25306d23 // psel p3.s, p11.s/Z, p9.s[w12]\n" - "udot z19.s, z17.b, z20.b\n" - ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" - "udot z18.s, z16.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" + ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" + "udot z18.s, z17.b, z20.b\n" "ldr x23, [x25, #0x0]\n" ".inst 0x25306d22 // psel p2.s, p11.s/Z, p9.s[w12]\n" "ldr x22, [x26, #0x8]\n" ".inst 0x25706d21 // psel p1.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829031 // mova z17.s, p4/M, za0v.s[x12, #1]\n" + ".inst 0xc0829030 // mova z16.s, p4/M, za0v.s[x12, #1]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8f60 // st1w { za0v.s[x12] }, p3/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc08290b0 // mova z16.s, p4/M, za1v.s[x12, #1]\n" + ".inst 0xc08290b1 // mova z17.s, p4/M, za1v.s[x12, #1]\n" "whilelt p9.b, x15, %x[width]\n" ".inst 0xe0b08b64 // st1w { za1v.s[x12] }, p2/Z, [x27, x16, LSL #2]\n" "incb x15\n" "add x26, x26, #0x10\n" - "udot z19.s, z17.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" ".inst 0xe0ae8761 // st1w { za0v.s[x12, #1] }, p1/Z, [x27, x14, LSL #2]\n" "add x25, x25, #0x10\n" - "udot z18.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" "incb x28\n" ".inst 0xe0ab8365 // st1w { za1v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" "addvl x27, x27, #4\n" @@ -217,23 +217,23 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0xe01c2aa5 // ld1b { za0h.b[x13, #5] }, p2/Z, [x21, x28]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8768 // st1w { za2v.s[x12] }, p1/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc0829111 // mova z17.s, p4/M, za2v.s[x12]\n" - ".inst 0xc0829190 // mova z16.s, p4/M, za3v.s[x12]\n" - "udot z19.s, z17.b, z20.b\n" + ".inst 0xc0829110 // mova z16.s, p4/M, za2v.s[x12]\n" + ".inst 0xc0829191 // mova z17.s, p4/M, za3v.s[x12]\n" + "udot z19.s, z16.b, z20.b\n" ".inst 0xe0b0836c // st1w { za3v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - "udot z18.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" ".inst 0xe0ae8369 // st1w { za2v.s[x12, #1] }, p0/Z, [x27, x14, LSL #2]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829131 // mova z17.s, p4/M, za2v.s[x12, #1]\n" + ".inst 0xc0829130 // mova z16.s, p4/M, za2v.s[x12, #1]\n" ".inst 0xe0ab836d // st1w { za3v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" - ".inst 0xc08291b0 // mova z16.s, p4/M, za3v.s[x12, #1]\n" + ".inst 0xc08291b1 // mova z17.s, p4/M, za3v.s[x12, #1]\n" "add x12, x12, #0x2\n" "cmp x12, x9\n" "add x26, x26, #0x10\n" "add x25, x25, #0x10\n" - "udot z19.s, z17.b, z20.b\n" - "udot z18.s, z16.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" "addvl x27, x27, #4\n" "add x13, x13, #0x8\n" "blt 7b\n" @@ -249,28 +249,28 @@ void interleave_block<2, 4, VLType::SME, true>( "add x25, %x[in], x16, LSL #3\n" "ldr x24, [x26, #0x0]\n" ".inst 0xe01c22a5 // ld1b { za0h.b[x13, #5] }, p0/Z, [x21, x28]\n" - ".inst 0xc0829111 // mova z17.s, p4/M, za2v.s[x12]\n" + ".inst 0xc0829110 // mova z16.s, p4/M, za2v.s[x12]\n" ".inst 0x25306d23 // psel p3.s, p11.s/Z, p9.s[w12]\n" - "udot z19.s, z17.b, z20.b\n" - ".inst 0xc0829190 // mova z16.s, p4/M, za3v.s[x12]\n" - "udot z18.s, z16.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" + ".inst 0xc0829191 // mova z17.s, p4/M, za3v.s[x12]\n" + "udot z18.s, z17.b, z20.b\n" "ldr x23, [x25, #0x0]\n" ".inst 0x25306d22 // psel p2.s, p11.s/Z, p9.s[w12]\n" "ldr x22, [x26, #0x8]\n" ".inst 0x25706d21 // psel p1.s, p11.s/Z, p9.s[w12, #1]\n" - ".inst 0xc0829131 // mova z17.s, p4/M, za2v.s[x12, #1]\n" + ".inst 0xc0829130 // mova z16.s, p4/M, za2v.s[x12, #1]\n" ".inst 0x25706d20 // psel p0.s, p11.s/Z, p9.s[w12, #1]\n" "ldr x21, [x25, #0x8]\n" ".inst 0xe0bf8f68 // st1w { za2v.s[x12] }, p3/Z, [x27, XZR, LSL #2]\n" - ".inst 0xc08291b0 // mova z16.s, p4/M, za3v.s[x12, #1]\n" + ".inst 0xc08291b1 // mova z17.s, p4/M, za3v.s[x12, #1]\n" "whilelt p9.b, x15, %x[width]\n" ".inst 0xe0b08b6c // st1w { za3v.s[x12] }, p2/Z, [x27, x16, LSL #2]\n" "subs x20, x20, #0x1\n" "add x26, x26, #0x10\n" - "udot z19.s, z17.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" ".inst 0xe0ae8769 // st1w { za2v.s[x12, #1] }, p1/Z, [x27, x14, LSL #2]\n" "add x25, x25, #0x10\n" - "udot z18.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" "incb x15\n" ".inst 0xe0ab836d // st1w { za3v.s[x12, #1] }, p0/Z, [x27, x11, LSL #2]\n" "addvl x27, x27, #4\n" @@ -286,19 +286,19 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8360 // st1w { za0v.s[x12] }, p0/Z, [x27, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" ".inst 0xe0b08364 // st1w { za1v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" - "ldr x24, [x26, #0x0]\n" + "ldr x21, [x26, #0x0]\n" ".inst 0x25356140 // psel p0.b, p8.b/Z, p10.b[w13, #2]\n" - ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" - "ldr x23, [x26, x16, LSL #0x3]\n" - ".inst 0xe01c2302 // ld1b { za0h.b[x13, #2] }, p0/Z, [x24, x28]\n" + ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" + "ldr x20, [x26, x16, LSL #0x3]\n" + ".inst 0xe01c22a2 // ld1b { za0h.b[x13, #2] }, p0/Z, [x21, x28]\n" "add x12, x12, #0x1\n" ".inst 0x253d6140 // psel p0.b, p8.b/Z, p10.b[w13, #3]\n" "cmp x12, x16\n" - "udot z19.s, z17.b, z20.b\n" - "udot z18.s, z16.b, z20.b\n" - ".inst 0xe01c22e3 // ld1b { za0h.b[x13, #3] }, p0/Z, [x23, x28]\n" + "udot z19.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" + ".inst 0xe01c2283 // ld1b { za0h.b[x13, #3] }, p0/Z, [x20, x28]\n" "add x26, x26, #0x8\n" "addvl x27, x27, #2\n" "add x13, x13, #0x4\n" @@ -311,17 +311,17 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8368 // st1w { za2v.s[x12] }, p0/Z, [x27, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0829111 // mova z17.s, p4/M, za2v.s[x12]\n" + ".inst 0xc0829110 // mova z16.s, p4/M, za2v.s[x12]\n" ".inst 0xe0b0836c // st1w { za3v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" - ".inst 0xc0829190 // mova z16.s, p4/M, za3v.s[x12]\n" + ".inst 0xc0829191 // mova z17.s, p4/M, za3v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "udot z19.s, z17.b, z20.b\n" - "udot z18.s, z16.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" "addvl x27, x27, #2\n" "add x20, x20, #0x4\n" "blt 11b\n" - "whilelt p9.b, x15, %x[width]\n" + "whilelt p8.b, x15, %x[width]\n" "b 14f\n" "12:" // K loop: Tails: Odd "mov x12, #0x0\n" @@ -329,13 +329,13 @@ void interleave_block<2, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8360 // st1w { za0v.s[x12] }, p0/Z, [x27, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0829011 // mova z17.s, p4/M, za0v.s[x12]\n" + ".inst 0xc0829010 // mova z16.s, p4/M, za0v.s[x12]\n" ".inst 0xe0b08364 // st1w { za1v.s[x12] }, p0/Z, [x27, x16, LSL #2]\n" - ".inst 0xc0829090 // mova z16.s, p4/M, za1v.s[x12]\n" + ".inst 0xc0829091 // mova z17.s, p4/M, za1v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x17\n" - "udot z19.s, z17.b, z20.b\n" - "udot z18.s, z16.b, z20.b\n" + "udot z19.s, z16.b, z20.b\n" + "udot z18.s, z17.b, z20.b\n" "addvl x27, x27, #2\n" "blt 13b\n" "14:" // K loop: End @@ -350,4 +350,4 @@ void interleave_block<2, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp16_fp16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp16_fp16.hpp index 522f310cc0..96ab55ee06 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp16_fp16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp16_fp16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 1, VLType::SME, false>( __fp16 * &out, const __fp16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cnth x28\n" @@ -97,4 +95,4 @@ void interleave_block<2, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp32_fp32.hpp index 949e003598..ac4b1b5086 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave2VL_fp32_fp32.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<2, 1, VLType::SME, false>( float * &out, const float * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "mov x22, %x[width]\n" @@ -55,12 +53,12 @@ void interleave_block<2, 1, VLType::SME, false>( "ldr x25, [x11, #0x8]\n" "and x24, x22, #0x1\n" // odd_tail = bool(n_passes & 0x1) "csel x15, x15, x16, NE\n" - "ldr x23, [x9, #0x8]\n" + "ldr x21, [x9, #0x8]\n" "ptrue p13.s\n" "whilelt p12.s, XZR, %x[height]\n" "whilelt p11.s, x16, %x[height]\n" - "mov x22, %x[row_offset]\n" - "mov x21, %x[out]\n" + "mov x23, %x[row_offset]\n" + "mov x22, %x[out]\n" "whilelt p10.s, x13, %x[width]\n" "whilelt p9.s, x13, %x[width]\n" "whilelt p8.s, x13, %x[width]\n" @@ -71,39 +69,39 @@ void interleave_block<2, 1, VLType::SME, false>( "1:" // K loop: Charge: Loop ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - ".inst 0xe0960540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" + ".inst 0xe0970540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x23, LSL #2]\n" "ldr x10, [x11, #0x0]\n" - ".inst 0xe0960364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + ".inst 0xe0970364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x23, LSL #2]\n" ".inst 0x25706581 // psel p1.s, p9.s/Z, p12.s[w12, #1]\n" ".inst 0x25706160 // psel p0.s, p8.s/Z, p11.s[w12, #1]\n" "ldr x27, [x9, #0x0]\n" - ".inst 0xe0960721 // ld1w { za0h.s[x12, #1] }, p1/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0970721 // ld1w { za0h.s[x12, #1] }, p1/Z, [x25, x23, LSL #2]\n" "ldr x25, [x11, #0x8]\n" "add x11, x11, #0x10\n" - ".inst 0xe09602e5 // ld1w { za1h.s[x12, #1] }, p0/Z, [x23, x22, LSL #2]\n" + ".inst 0xe09702a5 // ld1w { za1h.s[x12, #1] }, p0/Z, [x21, x23, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x14\n" - "ldr x23, [x9, #0x8]\n" + "ldr x21, [x9, #0x8]\n" "add x9, x9, #0x10\n" "blt 1b\n" "2:" // K loop: Charge: End ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - ".inst 0xe0960540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" - ".inst 0xe0960364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + ".inst 0xe0970540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x23, LSL #2]\n" + ".inst 0xe0970364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x23, LSL #2]\n" ".inst 0x25706581 // psel p1.s, p9.s/Z, p12.s[w12, #1]\n" ".inst 0x25706160 // psel p0.s, p8.s/Z, p11.s[w12, #1]\n" "mov x11, %x[in]\n" "add x9, %x[in], x16, LSL #3\n" - ".inst 0xe0960721 // ld1w { za0h.s[x12, #1] }, p1/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0970721 // ld1w { za0h.s[x12, #1] }, p1/Z, [x25, x23, LSL #2]\n" "ldr x10, [x11, #0x0]\n" - ".inst 0xe09602e5 // ld1w { za1h.s[x12, #1] }, p0/Z, [x23, x22, LSL #2]\n" + ".inst 0xe09702a5 // ld1w { za1h.s[x12, #1] }, p0/Z, [x21, x23, LSL #2]\n" "ldr x27, [x9, #0x0]\n" - "incw x22\n" + "incw x23\n" "incw x13\n" "ldr x25, [x11, #0x8]\n" "add x11, x11, #0x10\n" - "ldr x23, [x9, #0x8]\n" + "ldr x21, [x9, #0x8]\n" "add x9, x9, #0x10\n" "cbz x20, 8f\n" "mov x20, x20\n" @@ -115,59 +113,59 @@ void interleave_block<2, 1, VLType::SME, false>( "4:" // K loop: Main loop: First: Loop ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - ".inst 0xe0960548 // ld1w { za2h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" + ".inst 0xe0970548 // ld1w { za2h.s[x12] }, p1/Z, [x10, x23, LSL #2]\n" "ldr x10, [x11, #0x0]\n" - ".inst 0xe096036c // ld1w { za3h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + ".inst 0xe097036c // ld1w { za3h.s[x12] }, p0/Z, [x27, x23, LSL #2]\n" ".inst 0x25706580 // psel p0.s, p9.s/Z, p12.s[w12, #1]\n" ".inst 0x25706162 // psel p2.s, p8.s/Z, p11.s[w12, #1]\n" "ldr x27, [x9, #0x0]\n" ".inst 0x25307541 // psel p1.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0960329 // ld1w { za2h.s[x12, #1] }, p0/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0970329 // ld1w { za2h.s[x12, #1] }, p0/Z, [x25, x23, LSL #2]\n" "ldr x25, [x11, #0x8]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0960aed // ld1w { za3h.s[x12, #1] }, p2/Z, [x23, x22, LSL #2]\n" - "ldr x23, [x9, #0x8]\n" - ".inst 0xe0bf86a0 // st1w { za0v.s[x12] }, p1/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0970aad // ld1w { za3h.s[x12, #1] }, p2/Z, [x21, x23, LSL #2]\n" + "ldr x21, [x9, #0x8]\n" + ".inst 0xe0bf86c0 // st1w { za0v.s[x12] }, p1/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" "add x11, x11, #0x10\n" - ".inst 0xe0bc86a1 // st1w { za0v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c1 // st1w { za0v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x9, x9, #0x10\n" - ".inst 0xe0ba82a5 // st1w { za1v.s[x12, #1] }, p0/Z, [x21, x26, LSL #2]\n" + ".inst 0xe0ba82c5 // st1w { za1v.s[x12, #1] }, p0/Z, [x22, x26, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x14\n" - "addvl x21, x21, #4\n" + "addvl x22, x22, #4\n" "blt 4b\n" "5:" // K loop: Main loop: First: Tail ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - ".inst 0xe0960548 // ld1w { za2h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" - ".inst 0xe096036c // ld1w { za3h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + ".inst 0xe0970548 // ld1w { za2h.s[x12] }, p1/Z, [x10, x23, LSL #2]\n" + ".inst 0xe097036c // ld1w { za3h.s[x12] }, p0/Z, [x27, x23, LSL #2]\n" "mov x11, %x[in]\n" "add x9, %x[in], x16, LSL #3\n" "ldr x10, [x11, #0x0]\n" ".inst 0x25706580 // psel p0.s, p9.s/Z, p12.s[w12, #1]\n" ".inst 0x25706161 // psel p1.s, p8.s/Z, p11.s[w12, #1]\n" - ".inst 0xe0960329 // ld1w { za2h.s[x12, #1] }, p0/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0970329 // ld1w { za2h.s[x12, #1] }, p0/Z, [x25, x23, LSL #2]\n" "ldr x27, [x9, #0x0]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe09606ed // ld1w { za3h.s[x12, #1] }, p1/Z, [x23, x22, LSL #2]\n" + ".inst 0xe09706ad // ld1w { za3h.s[x12, #1] }, p1/Z, [x21, x23, LSL #2]\n" "ldr x25, [x11, #0x8]\n" ".inst 0x25307542 // psel p2.s, p13.s/Z, p10.s[w12]\n" - "ldr x23, [x9, #0x8]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + "ldr x21, [x9, #0x8]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b08aa4 // st1w { za1v.s[x12] }, p2/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b08ac4 // st1w { za1v.s[x12] }, p2/Z, [x22, x16, LSL #2]\n" "whilelt p10.s, x13, %x[width]\n" "incw x13\n" - ".inst 0xe0bc86a1 // st1w { za0v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c1 // st1w { za0v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x11, x11, #0x10\n" "add x9, x9, #0x10\n" - ".inst 0xe0ba82a5 // st1w { za1v.s[x12, #1] }, p0/Z, [x21, x26, LSL #2]\n" - "addvl x21, x21, #4\n" - "incw x22\n" + ".inst 0xe0ba82c5 // st1w { za1v.s[x12, #1] }, p0/Z, [x22, x26, LSL #2]\n" + "addvl x22, x22, #4\n" + "incw x23\n" "whilelt p9.s, x13, %x[width]\n" "whilelt p8.s, x13, %x[width]\n" "mov x12, #0x0\n" @@ -175,60 +173,60 @@ void interleave_block<2, 1, VLType::SME, false>( "6:" // K loop: Main loop: Second: Loop ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - ".inst 0xe0960540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" + ".inst 0xe0970540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x23, LSL #2]\n" "ldr x10, [x11, #0x0]\n" - ".inst 0xe0960364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + ".inst 0xe0970364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x23, LSL #2]\n" ".inst 0x25706580 // psel p0.s, p9.s/Z, p12.s[w12, #1]\n" ".inst 0x25706162 // psel p2.s, p8.s/Z, p11.s[w12, #1]\n" "ldr x27, [x9, #0x0]\n" ".inst 0x25307541 // psel p1.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0960321 // ld1w { za0h.s[x12, #1] }, p0/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0970321 // ld1w { za0h.s[x12, #1] }, p0/Z, [x25, x23, LSL #2]\n" "ldr x25, [x11, #0x8]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0960ae5 // ld1w { za1h.s[x12, #1] }, p2/Z, [x23, x22, LSL #2]\n" - "ldr x23, [x9, #0x8]\n" - ".inst 0xe0bf86a8 // st1w { za2v.s[x12] }, p1/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0970aa5 // ld1w { za1h.s[x12, #1] }, p2/Z, [x21, x23, LSL #2]\n" + "ldr x21, [x9, #0x8]\n" + ".inst 0xe0bf86c8 // st1w { za2v.s[x12] }, p1/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b082ac // st1w { za3v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082cc // st1w { za3v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" "add x11, x11, #0x10\n" - ".inst 0xe0bc86a9 // st1w { za2v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c9 // st1w { za2v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x9, x9, #0x10\n" - ".inst 0xe0ba82ad // st1w { za3v.s[x12, #1] }, p0/Z, [x21, x26, LSL #2]\n" + ".inst 0xe0ba82cd // st1w { za3v.s[x12, #1] }, p0/Z, [x22, x26, LSL #2]\n" "add x12, x12, #0x2\n" "cmp x12, x14\n" - "addvl x21, x21, #4\n" + "addvl x22, x22, #4\n" "blt 6b\n" "7:" // K loop: Main loop: Second: Tail ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - ".inst 0xe0960540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" - ".inst 0xe0960364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + ".inst 0xe0970540 // ld1w { za0h.s[x12] }, p1/Z, [x10, x23, LSL #2]\n" + ".inst 0xe0970364 // ld1w { za1h.s[x12] }, p0/Z, [x27, x23, LSL #2]\n" "mov x11, %x[in]\n" "add x9, %x[in], x16, LSL #3\n" "ldr x10, [x11, #0x0]\n" ".inst 0x25706580 // psel p0.s, p9.s/Z, p12.s[w12, #1]\n" ".inst 0x25706161 // psel p1.s, p8.s/Z, p11.s[w12, #1]\n" - ".inst 0xe0960321 // ld1w { za0h.s[x12, #1] }, p0/Z, [x25, x22, LSL #2]\n" + ".inst 0xe0970321 // ld1w { za0h.s[x12, #1] }, p0/Z, [x25, x23, LSL #2]\n" "ldr x27, [x9, #0x0]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe09606e5 // ld1w { za1h.s[x12, #1] }, p1/Z, [x23, x22, LSL #2]\n" + ".inst 0xe09706a5 // ld1w { za1h.s[x12, #1] }, p1/Z, [x21, x23, LSL #2]\n" "ldr x25, [x11, #0x8]\n" ".inst 0x25307542 // psel p2.s, p13.s/Z, p10.s[w12]\n" - "ldr x23, [x9, #0x8]\n" - ".inst 0xe0bf82a8 // st1w { za2v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + "ldr x21, [x9, #0x8]\n" + ".inst 0xe0bf82c8 // st1w { za2v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25707541 // psel p1.s, p13.s/Z, p10.s[w12, #1]\n" ".inst 0x25707540 // psel p0.s, p13.s/Z, p10.s[w12, #1]\n" - ".inst 0xe0b08aac // st1w { za3v.s[x12] }, p2/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b08acc // st1w { za3v.s[x12] }, p2/Z, [x22, x16, LSL #2]\n" "whilelt p10.s, x13, %x[width]\n" "subs x20, x20, #0x1\n" - ".inst 0xe0bc86a9 // st1w { za2v.s[x12, #1] }, p1/Z, [x21, x28, LSL #2]\n" + ".inst 0xe0bc86c9 // st1w { za2v.s[x12, #1] }, p1/Z, [x22, x28, LSL #2]\n" "add x11, x11, #0x10\n" "add x9, x9, #0x10\n" - ".inst 0xe0ba82ad // st1w { za3v.s[x12, #1] }, p0/Z, [x21, x26, LSL #2]\n" - "addvl x21, x21, #4\n" + ".inst 0xe0ba82cd // st1w { za3v.s[x12, #1] }, p0/Z, [x22, x26, LSL #2]\n" + "addvl x22, x22, #4\n" "incw x13\n" - "incw x22\n" + "incw x23\n" "bgt 3b\n" "8:" // K loop: Tails "cbnz x24, 11f\n" @@ -238,48 +236,48 @@ void interleave_block<2, 1, VLType::SME, false>( "mov x12, #0x0\n" "9:" // K loop: Tails: Even: First ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" - "ldr x10, [x11, #0x0]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" + "ldr x21, [x11, #0x0]\n" ".inst 0x25306581 // psel p1.s, p9.s/Z, p12.s[w12]\n" ".inst 0x25306160 // psel p0.s, p8.s/Z, p11.s[w12]\n" - "ldr x27, [x11, x16, LSL #0x3]\n" - ".inst 0xe0960548 // ld1w { za2h.s[x12] }, p1/Z, [x10, x22, LSL #2]\n" + "ldr x20, [x11, x16, LSL #0x3]\n" + ".inst 0xe09706a8 // ld1w { za2h.s[x12] }, p1/Z, [x21, x23, LSL #2]\n" "add x11, x11, #0x8\n" - "addvl x21, x21, #2\n" - ".inst 0xe096036c // ld1w { za3h.s[x12] }, p0/Z, [x27, x22, LSL #2]\n" + "addvl x22, x22, #2\n" + ".inst 0xe097028c // ld1w { za3h.s[x12] }, p0/Z, [x20, x23, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x16\n" "blt 9b\n" "whilelt p10.s, x13, %x[width]\n" - "whilelt p9.s, x13, %x[width]\n" + "whilelt p8.s, x13, %x[width]\n" "whilelt p8.s, x13, %x[width]\n" "mov x12, #0x0\n" "10:" // K loop: Tails: Even: Second ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a8 // st1w { za2v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c8 // st1w { za2v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082ac // st1w { za3v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082cc // st1w { za3v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x15\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "blt 10b\n" - "whilelt p10.s, x13, %x[width]\n" + "whilelt p8.s, x13, %x[width]\n" "b 13f\n" "11:" // K loop: Tails: Odd "mov x12, #0x0\n" "12:" // K loop: Tails: Odd: Loop ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0bf82a0 // st1w { za0v.s[x12] }, p0/Z, [x21, XZR, LSL #2]\n" + ".inst 0xe0bf82c0 // st1w { za0v.s[x12] }, p0/Z, [x22, XZR, LSL #2]\n" ".inst 0x25307540 // psel p0.s, p13.s/Z, p10.s[w12]\n" - ".inst 0xe0b082a4 // st1w { za1v.s[x12] }, p0/Z, [x21, x16, LSL #2]\n" + ".inst 0xe0b082c4 // st1w { za1v.s[x12] }, p0/Z, [x22, x16, LSL #2]\n" "add x12, x12, #0x1\n" "cmp x12, x15\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "blt 12b\n" "13:" // K loop: End - "mov %x[out], x21\n" + "mov %x[out], x22\n" ".inst 0xd503467f // SMSTOP\n" : [out] "+&r" (out) : [height] "r" (height), [in] "r" (in), [row_offset] "r" (row_offset), [width] "r" (width) @@ -287,4 +285,4 @@ void interleave_block<2, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block2_bf16_bf16.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block2_bf16_bf16.hpp index 4cc84d344a..2e53475b5c 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block2_bf16_bf16.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block2_bf16_bf16.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 2, VLType::SME, false>( bfloat16 * &out, const bfloat16 * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x16\n" @@ -124,4 +122,4 @@ void interleave_block<4, 2, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8.hpp index 465939c30d..67dd5a9bb7 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 4, VLType::SME, false>( int8_t * &out, const int8_t * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x16\n" @@ -123,4 +121,4 @@ void interleave_block<4, 4, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8_summing.hpp index ffd9384a13..21d9378368 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_s8_s8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 4, VLType::SME, true>( @@ -112,22 +112,22 @@ void interleave_block<4, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8120 // st1w { za0v.s[x12] }, p0/Z, [x9, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0828812 // mova z18.s, p2/M, za0v.s[x12]\n" + ".inst 0xc0828811 // mova z17.s, p2/M, za0v.s[x12]\n" ".inst 0xe0af8124 // st1w { za1v.s[x12] }, p0/Z, [x9, x15, LSL #2]\n" ".inst 0x25306d21 // psel p1.s, p11.s/Z, p9.s[w12]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0828891 // mova z17.s, p2/M, za1v.s[x12]\n" + ".inst 0xc0828893 // mova z19.s, p2/M, za1v.s[x12]\n" ".inst 0xe0ae8528 // st1w { za2v.s[x12] }, p1/Z, [x9, x14, LSL #2]\n" ".inst 0xc0828910 // mova z16.s, p2/M, za2v.s[x12]\n" - "sdot z23.s, z18.b, z24.b\n" + "sdot z23.s, z17.b, z24.b\n" ".inst 0xe0ad812c // st1w { za3v.s[x12] }, p0/Z, [x9, x13, LSL #2]\n" - ".inst 0xc0828993 // mova z19.s, p2/M, za3v.s[x12]\n" + ".inst 0xc0828992 // mova z18.s, p2/M, za3v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x20\n" - "sdot z22.s, z17.b, z24.b\n" + "sdot z22.s, z19.b, z24.b\n" "sdot z21.s, z16.b, z24.b\n" "addvl x9, x9, #4\n" - "sdot z20.s, z19.b, z24.b\n" + "sdot z20.s, z18.b, z24.b\n" "blt 5b\n" "incb x28\n" "whilelt p9.b, x28, %x[width]\n" @@ -147,4 +147,4 @@ void interleave_block<4, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8.hpp index 9f5db6ba3d..f149c93293 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 4, VLType::SME, false>( uint8_t * &out, const uint8_t * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x16\n" @@ -123,4 +121,4 @@ void interleave_block<4, 4, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp index 49d2acf1cd..252152e3da 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 4, VLType::SME, true>( @@ -112,22 +112,22 @@ void interleave_block<4, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8120 // st1w { za0v.s[x12] }, p0/Z, [x9, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0828813 // mova z19.s, p2/M, za0v.s[x12]\n" + ".inst 0xc0828810 // mova z16.s, p2/M, za0v.s[x12]\n" ".inst 0xe0af8124 // st1w { za1v.s[x12] }, p0/Z, [x9, x15, LSL #2]\n" ".inst 0x25306d21 // psel p1.s, p11.s/Z, p9.s[w12]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xc0828891 // mova z17.s, p2/M, za1v.s[x12]\n" ".inst 0xe0ae8528 // st1w { za2v.s[x12] }, p1/Z, [x9, x14, LSL #2]\n" - ".inst 0xc0828912 // mova z18.s, p2/M, za2v.s[x12]\n" - "udot z23.s, z19.b, z24.b\n" + ".inst 0xc0828913 // mova z19.s, p2/M, za2v.s[x12]\n" + "udot z23.s, z16.b, z24.b\n" ".inst 0xe0ad812c // st1w { za3v.s[x12] }, p0/Z, [x9, x13, LSL #2]\n" - ".inst 0xc0828990 // mova z16.s, p2/M, za3v.s[x12]\n" + ".inst 0xc0828992 // mova z18.s, p2/M, za3v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x20\n" "udot z22.s, z17.b, z24.b\n" - "udot z21.s, z18.b, z24.b\n" + "udot z21.s, z19.b, z24.b\n" "addvl x9, x9, #4\n" - "udot z20.s, z16.b, z24.b\n" + "udot z20.s, z18.b, z24.b\n" "blt 5b\n" "incb x28\n" "whilelt p9.b, x28, %x[width]\n" @@ -147,4 +147,4 @@ void interleave_block<4, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_fp32_fp32.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_fp32_fp32.hpp index 9579263204..b11bb93c42 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_fp32_fp32.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_fp32_fp32.hpp @@ -22,16 +22,14 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 1, VLType::SME, false>( float * &out, const float * const *in, - size_t width, size_t height, size_t row_offset, bool first + size_t width, size_t height, size_t row_offset, bool ) { - ARM_COMPUTE_UNUSED(first); - __asm__ __volatile__( ".inst 0xd503477f // SMSTART ZA\n" "cntw x15\n" @@ -123,4 +121,4 @@ void interleave_block<4, 1, VLType::SME, false>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) |