diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp | 208 |
1 files changed, 104 insertions, 104 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 3c1858633b..1ba78f3fba 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -82,126 +82,126 @@ void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x3, [%x[args], %[offsetof_n_channels]]\n" - "mov x4, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x5, #0x0\n" - "ldr x6, [%x[args], %[offsetof_inptrs]]\n" - "mov x19, #0x4\n" - "add x7, %x[args], %[offsetof_rescale]\n" - "ldp x8, x17, [x20, #0x0]\n" - "ldp x16, x15, [x20, #0x10]\n" - "whilelt p0.h, XZR, x19\n" - "ldp x14, x13, [x6, #0x0]\n" - "whilelt p1.h, x4, x3\n" - "ldp x12, x11, [x6, #0x10]\n" - "ldp x10, x9, [x6, #0x20]\n" - "ldp x28, x27, [x6, #0x30]\n" - "ldp x26, x25, [x6, #0x40]\n" - "ldp x24, x23, [x6, #0x50]\n" - "ldp x22, x21, [x6, #0x60]\n" - "ldp x20, x19, [x6, #0x70]\n" - "ld1rqh { z7.h }, p0/Z, [x7]\n" - "ld1h { z8.h }, p1/Z, [x9, x4, LSL #1]\n" - "ld1h { z6.h }, p1/Z, [x28, x4, LSL #1]\n" - "ld1h { z5.h }, p1/Z, [x25, x4, LSL #1]\n" - "ld1h { z4.h }, p1/Z, [x24, x4, LSL #1]\n" - "ld1h { z3.h }, p1/Z, [x13, x4, LSL #1]\n" - "ld1h { z2.h }, p1/Z, [x12, x4, LSL #1]\n" - "ld1h { z1.h }, p1/Z, [x10, x4, LSL #1]\n" - "ld1h { z0.h }, p1/Z, [x26, x4, LSL #1]\n" - "ld1h { z31.h }, p1/Z, [x27, x4, LSL #1]\n" - "ld1h { z30.h }, p1/Z, [x23, x4, LSL #1]\n" - "ld1h { z29.h }, p1/Z, [x21, x4, LSL #1]\n" - "ld1h { z28.h }, p1/Z, [x20, x4, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x14, x4, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x11, x4, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x22, x4, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x19, x4, LSL #1]\n" - "incw x4\n" - "whilelt p1.h, x4, x3\n" + "ldr x2, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x3, #0x0\n" + "mov x20, #0x4\n" + "ldr x4, [%x[args], %[offsetof_inptrs]]\n" + "ldp x5, x6, [x21, #0x0]\n" + "whilelt p2.h, XZR, x20\n" + "whilelt p0.h, x3, x2\n" + "ldp x7, x8, [x21, #0x10]\n" + "ldp x17, x16, [x4, #0x0]\n" + "add x15, %x[args], %[offsetof_rescale]\n" + "mov x14, #0x0\n" + "ldp x13, x12, [x4, #0x10]\n" + "ldp x11, x10, [x4, #0x20]\n" + "ldp x9, x28, [x4, #0x30]\n" + "ldp x27, x26, [x4, #0x40]\n" + "ldp x25, x24, [x4, #0x50]\n" + "ldp x23, x22, [x4, #0x60]\n" + "ldp x21, x20, [x4, #0x70]\n" + "ld1h { z7.h }, p0/Z, [x10, x3, LSL #1]\n" + "ld1h { z6.h }, p0/Z, [x9, x3, LSL #1]\n" + "ld1h { z5.h }, p0/Z, [x26, x3, LSL #1]\n" + "ld1h { z4.h }, p0/Z, [x25, x3, LSL #1]\n" + "ld1h { z3.h }, p0/Z, [x16, x3, LSL #1]\n" + "ld1h { z2.h }, p0/Z, [x13, x3, LSL #1]\n" + "ld1h { z1.h }, p0/Z, [x11, x3, LSL #1]\n" + "ld1h { z31.h }, p0/Z, [x27, x3, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x28, x3, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x24, x3, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x22, x3, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x21, x3, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x17, x3, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x12, x3, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x3, LSL #1]\n" + "incw x3\n" + "whilelt p1.h, x3, x2\n" + "ld1rqh { z0.h }, p2/Z, [x15]\n" "b.none 2f\n" "1:" // Vector: Loop - "fadd z17.h, z8.h, z6.h\n" - "ld1h { z8.h }, p1/Z, [x9, x4, LSL #1]\n" - "whilelt p0.h, x5, x3\n" + "fadd z17.h, z7.h, z6.h\n" "fadd z16.h, z5.h, z4.h\n" - "ld1h { z6.h }, p1/Z, [x28, x4, LSL #1]\n" + "ld1h { z7.h }, p1/Z, [x10, x3, LSL #1]\n" + "ld1h { z6.h }, p1/Z, [x9, x3, LSL #1]\n" + "fadd z19.h, z17.h, z16.h\n" "fadd z18.h, z3.h, z2.h\n" - "ld1h { z5.h }, p1/Z, [x25, x4, LSL #1]\n" - "fadd z23.h, z1.h, z0.h\n" - "ld1h { z4.h }, p1/Z, [x24, x4, LSL #1]\n" - "fadd z22.h, z31.h, z30.h\n" - "ld1h { z3.h }, p1/Z, [x13, x4, LSL #1]\n" - "fadd z17.h, z17.h, z16.h\n" - "ld1h { z2.h }, p1/Z, [x12, x4, LSL #1]\n" - "fadd z16.h, z29.h, z28.h\n" - "ld1h { z1.h }, p1/Z, [x10, x4, LSL #1]\n" - "fadd z19.h, z27.h, z23.h\n" - "ld1h { z0.h }, p1/Z, [x26, x4, LSL #1]\n" - "fadd z21.h, z18.h, z17.h\n" - "ld1h { z31.h }, p1/Z, [x27, x4, LSL #1]\n" - "fadd z20.h, z16.h, z17.h\n" - "ld1h { z30.h }, p1/Z, [x23, x4, LSL #1]\n" - "fadd z18.h, z26.h, z22.h\n" - "ld1h { z29.h }, p1/Z, [x21, x4, LSL #1]\n" - "fadd z17.h, z25.h, z23.h\n" - "ld1h { z28.h }, p1/Z, [x20, x4, LSL #1]\n" - "fadd z16.h, z24.h, z22.h\n" - "ld1h { z27.h }, p1/Z, [x14, x4, LSL #1]\n" + "ld1h { z5.h }, p1/Z, [x26, x3, LSL #1]\n" + "ld1h { z4.h }, p1/Z, [x25, x3, LSL #1]\n" + "fadd z17.h, z1.h, z31.h\n" + "fadd z22.h, z30.h, z29.h\n" + "ld1h { z3.h }, p1/Z, [x16, x3, LSL #1]\n" + "ld1h { z2.h }, p1/Z, [x13, x3, LSL #1]\n" + "fadd z16.h, z28.h, z27.h\n" + "fadd z21.h, z18.h, z19.h\n" + "ld1h { z1.h }, p1/Z, [x11, x3, LSL #1]\n" + "ld1h { z31.h }, p1/Z, [x27, x3, LSL #1]\n" + "fadd z20.h, z16.h, z19.h\n" + "fadd z19.h, z26.h, z17.h\n" + "ld1h { z30.h }, p1/Z, [x28, x3, LSL #1]\n" + "ld1h { z29.h }, p1/Z, [x24, x3, LSL #1]\n" + "fadd z18.h, z25.h, z22.h\n" + "fadd z17.h, z24.h, z17.h\n" + "ld1h { z28.h }, p1/Z, [x22, x3, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x21, x3, LSL #1]\n" + "fadd z16.h, z23.h, z22.h\n" + "ld1h { z26.h }, p1/Z, [x17, x3, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x12, x3, LSL #1]\n" "fadd z19.h, z21.h, z19.h\n" - "ld1h { z26.h }, p1/Z, [x11, x4, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x20, x3, LSL #1]\n" + "incw x3\n" "fadd z18.h, z21.h, z18.h\n" - "ld1h { z25.h }, p1/Z, [x22, x4, LSL #1]\n" "fadd z17.h, z17.h, z20.h\n" - "ld1h { z24.h }, p1/Z, [x19, x4, LSL #1]\n" - "incw x4\n" - "fadd z16.h, z20.h, z16.h\n" - "whilelt p1.h, x4, x3\n" - "fmul z19.h, z19.h, z7.h[0]\n" - "st1h { z19.h }, p0, [x8, x5, LSL #1]\n" - "fmul z18.h, z18.h, z7.h[1]\n" - "fmul z17.h, z17.h, z7.h[2]\n" - "st1h { z18.h }, p0, [x17, x5, LSL #1]\n" - "fmul z16.h, z16.h, z7.h[3]\n" - "st1h { z17.h }, p0, [x16, x5, LSL #1]\n" - "st1h { z16.h }, p0, [x15, x5, LSL #1]\n" - "incw x5\n" + "fadd z16.h, z16.h, z20.h\n" + "whilelt p0.h, x14, x2\n" + "whilelt p1.h, x3, x2\n" + "fmul z19.h, z19.h, z0.h[0]\n" + "fmul z18.h, z18.h, z0.h[1]\n" + "st1h { z19.h }, p0, [x5, x14, LSL #1]\n" + "fmul z17.h, z17.h, z0.h[2]\n" + "fmul z16.h, z16.h, z0.h[3]\n" + "st1h { z18.h }, p0, [x6, x14, LSL #1]\n" + "st1h { z17.h }, p0, [x7, x14, LSL #1]\n" + "st1h { z16.h }, p0, [x8, x14, LSL #1]\n" + "incw x14\n" "b.any 1b\n" "2:" // Vector: Tail - "fadd z17.h, z8.h, z6.h\n" - "whilelt p0.h, x5, x3\n" + "fadd z17.h, z7.h, z6.h\n" "fadd z16.h, z5.h, z4.h\n" + "whilelt p0.h, x14, x2\n" + "fadd z20.h, z17.h, z16.h\n" "fadd z18.h, z3.h, z2.h\n" - "fadd z23.h, z1.h, z0.h\n" - "fadd z17.h, z17.h, z16.h\n" - "fadd z22.h, z31.h, z30.h\n" - "fadd z16.h, z29.h, z28.h\n" - "fadd z21.h, z18.h, z17.h\n" - "fadd z19.h, z27.h, z23.h\n" - "fadd z20.h, z16.h, z17.h\n" - "fadd z18.h, z26.h, z22.h\n" - "fadd z17.h, z25.h, z23.h\n" - "fadd z16.h, z24.h, z22.h\n" - "fadd z19.h, z21.h, z19.h\n" + "fadd z17.h, z1.h, z31.h\n" + "fadd z19.h, z30.h, z29.h\n" + "fadd z16.h, z28.h, z27.h\n" + "fadd z21.h, z18.h, z20.h\n" + "fadd z20.h, z16.h, z20.h\n" + "fadd z16.h, z26.h, z17.h\n" + "fadd z18.h, z25.h, z19.h\n" + "fadd z17.h, z24.h, z17.h\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z16.h, z21.h, z16.h\n" + "fmul z16.h, z16.h, z0.h[0]\n" + "st1h { z16.h }, p0, [x5, x14, LSL #1]\n" "fadd z18.h, z21.h, z18.h\n" "fadd z17.h, z17.h, z20.h\n" - "fadd z16.h, z20.h, z16.h\n" - "fmul z19.h, z19.h, z7.h[0]\n" - "st1h { z19.h }, p0, [x8, x5, LSL #1]\n" - "fmul z18.h, z18.h, z7.h[1]\n" - "fmul z17.h, z17.h, z7.h[2]\n" - "st1h { z18.h }, p0, [x17, x5, LSL #1]\n" - "fmul z16.h, z16.h, z7.h[3]\n" - "st1h { z17.h }, p0, [x16, x5, LSL #1]\n" - "st1h { z16.h }, p0, [x15, x5, LSL #1]\n" + "fmul z18.h, z18.h, z0.h[1]\n" + "fmul z17.h, z17.h, z0.h[2]\n" + "fadd z16.h, z19.h, z20.h\n" + "fmul z16.h, z16.h, z0.h[3]\n" + "st1h { z18.h }, p0, [x6, x14, LSL #1]\n" + "st1h { z17.h }, p0, [x7, x14, LSL #1]\n" + "st1h { z16.h }, p0, [x8, x14, LSL #1]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "p0", "p1", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) |