diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels')
110 files changed, 12441 insertions, 6892 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index 178db4a0b0..6b3ebe6664 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) namespace arm_conv { namespace pooling { void a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst +struct a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; + using Parent = DepthfirstStrategy<__fp16, __fp16>; - typedef void (*kern_type)(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } + a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 3; } - constexpr static unsigned int pool_cols(void) { return 3; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; - - a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 89dbf5ce02..5df848d1dd 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) namespace arm_conv { namespace pooling { @@ -82,174 +82,173 @@ void a64_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x4, [%x[args], %[offsetof_n_channels]]\n" + "ldr d7, [%x[args], %[offsetof_rescale]]\n" + "ldr x3, [%x[args], %[offsetof_n_channels]]\n" + "cmp x3, #0x8\n" + "mov x4, #0x0\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "mov x5, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x6, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "cmp x4, #0x8\n" - "ldp x7, x8, [x20, #0x0]\n" - "ldp x17, x16, [x20, #0x10]\n" - "ldp x15, x14, [x19, #0x0]\n" - "ldp x13, x12, [x19, #0x10]\n" - "ldp x11, x10, [x19, #0x20]\n" - "ldp x9, x28, [x19, #0x30]\n" - "ldp x27, x26, [x19, #0x40]\n" - "ldp x25, x24, [x19, #0x50]\n" - "ldp x23, x22, [x19, #0x60]\n" - "ldp x21, x20, [x19, #0x70]\n" - "ldr d8, [%x[args], %[offsetof_rescale]]\n" + "ldp x6, x7, [x21, #0x0]\n" + "ldp x8, x17, [x21, #0x10]\n" + "ldp x16, x15, [x20, #0x0]\n" + "ldp x14, x13, [x20, #0x10]\n" + "ldp x12, x11, [x20, #0x20]\n" + "ldp x10, x9, [x20, #0x30]\n" + "ldp x28, x27, [x20, #0x40]\n" + "ldp x26, x25, [x20, #0x50]\n" + "ldp x24, x23, [x20, #0x60]\n" + "ldp x22, x21, [x20, #0x70]\n" "blt 3f\n" - "ldr q7, [x10, x5]\n" - "lsr x19, x4, #0x3\n" - "ldr q6, [x9, x5]\n" - "sub x4, x4, x19, LSL #3\n" - "ldr q5, [x26, x5]\n" - "subs x19, x19, #0x1\n" - "ldr q4, [x25, x5]\n" - "ldr q3, [x14, x5]\n" - "ldr q2, [x13, x5]\n" - "ldr q1, [x11, x5]\n" - "ldr q0, [x27, x5]\n" - "ldr q31, [x28, x5]\n" - "ldr q30, [x24, x5]\n" - "ldr q29, [x22, x5]\n" - "ldr q28, [x21, x5]\n" - "ldr q27, [x15, x5]\n" - "ldr q26, [x12, x5]\n" - "ldr q25, [x23, x5]\n" - "ldr q24, [x20, x5]\n" - "add x5, x5, #0x10\n" + "ldr q6, [x11, x4]\n" + "ldr q5, [x10, x4]\n" + "lsr x20, x3, #0x3\n" + "sub x3, x3, x20, LSL #3\n" + "ldr q4, [x27, x4]\n" + "ldr q3, [x26, x4]\n" + "subs x20, x20, #0x1\n" + "ldr q2, [x15, x4]\n" + "ldr q1, [x14, x4]\n" + "ldr q0, [x12, x4]\n" + "ldr q31, [x28, x4]\n" + "ldr q30, [x9, x4]\n" + "ldr q29, [x25, x4]\n" + "ldr q28, [x23, x4]\n" + "ldr q27, [x22, x4]\n" + "ldr q26, [x16, x4]\n" + "ldr q25, [x13, x4]\n" + "ldr q24, [x24, x4]\n" + "ldr q23, [x21, x4]\n" + "add x4, x4, #0x10\n" "beq 2f\n" "1:" // Vector: Loop - "fadd v17.8h, v7.8h, v6.8h\n" - "ldr q7, [x10, x5]\n" - "subs x19, x19, #0x1\n" - "fadd v16.8h, v5.8h, v4.8h\n" - "ldr q6, [x9, x5]\n" - "fadd v18.8h, v3.8h, v2.8h\n" - "ldr q5, [x26, x5]\n" - "fadd v23.8h, v1.8h, v0.8h\n" - "ldr q4, [x25, x5]\n" - "fadd v22.8h, v31.8h, v30.8h\n" - "ldr q3, [x14, x5]\n" - "fadd v17.8h, v17.8h, v16.8h\n" - "ldr q2, [x13, x5]\n" - "fadd v16.8h, v29.8h, v28.8h\n" - "ldr q1, [x11, x5]\n" - "fadd v19.8h, v27.8h, v23.8h\n" - "ldr q0, [x27, x5]\n" - "fadd v21.8h, v18.8h, v17.8h\n" - "ldr q31, [x28, x5]\n" - "fadd v20.8h, v16.8h, v17.8h\n" - "ldr q30, [x24, x5]\n" - "fadd v18.8h, v26.8h, v22.8h\n" - "ldr q29, [x22, x5]\n" - "fadd v17.8h, v25.8h, v23.8h\n" - "ldr q28, [x21, x5]\n" - "fadd v16.8h, v24.8h, v22.8h\n" - "ldr q27, [x15, x5]\n" + "fadd v17.8h, v6.8h, v5.8h\n" + "ldr q6, [x11, x4]\n" + "ldr q5, [x10, x4]\n" + "fadd v16.8h, v4.8h, v3.8h\n" + "ldr q4, [x27, x4]\n" + "ldr q3, [x26, x4]\n" + "fadd v19.8h, v17.8h, v16.8h\n" + "fadd v18.8h, v2.8h, v1.8h\n" + "ldr q2, [x15, x4]\n" + "ldr q1, [x14, x4]\n" + "fadd v17.8h, v0.8h, v31.8h\n" + "fadd v22.8h, v30.8h, v29.8h\n" + "ldr q0, [x12, x4]\n" + "ldr q31, [x28, x4]\n" + "fadd v16.8h, v28.8h, v27.8h\n" + "fadd v21.8h, v18.8h, v19.8h\n" + "ldr q30, [x9, x4]\n" + "ldr q29, [x25, x4]\n" + "fadd v20.8h, v16.8h, v19.8h\n" + "fadd v19.8h, v26.8h, v17.8h\n" + "ldr q28, [x23, x4]\n" + "ldr q27, [x22, x4]\n" + "fadd v18.8h, v25.8h, v22.8h\n" + "fadd v17.8h, v24.8h, v17.8h\n" + "ldr q26, [x16, x4]\n" + "ldr q25, [x13, x4]\n" + "fadd v16.8h, v23.8h, v22.8h\n" "fadd v19.8h, v21.8h, v19.8h\n" - "ldr q26, [x12, x5]\n" + "ldr q24, [x24, x4]\n" + "ldr q23, [x21, x4]\n" "fadd v18.8h, v21.8h, v18.8h\n" - "ldr q25, [x23, x5]\n" "fadd v17.8h, v17.8h, v20.8h\n" - "ldr q24, [x20, x5]\n" + "fadd v16.8h, v16.8h, v20.8h\n" + "subs x20, x20, #0x1\n" + "fmul v19.8h, v19.8h, v7.h[0]\n" + "add x4, x4, #0x10\n" + "fmul v18.8h, v18.8h, v7.h[1]\n" + "fmul v17.8h, v17.8h, v7.h[2]\n" + "str q19, [x6, x5]\n" + "fmul v16.8h, v16.8h, v7.h[3]\n" + "str q18, [x7, x5]\n" + "str q17, [x8, x5]\n" + "str q16, [x17, x5]\n" "add x5, x5, #0x10\n" - "fadd v16.8h, v20.8h, v16.8h\n" - "fmul v19.8h, v19.8h, v8.h[0]\n" - "str q19, [x7, x6]\n" - "fmul v18.8h, v18.8h, v8.h[1]\n" - "fmul v17.8h, v17.8h, v8.h[2]\n" - "str q18, [x8, x6]\n" - "fmul v16.8h, v16.8h, v8.h[3]\n" - "str q17, [x17, x6]\n" - "str q16, [x16, x6]\n" - "add x6, x6, #0x10\n" "bgt 1b\n" "2:" // Vector: Tail - "fadd v17.8h, v7.8h, v6.8h\n" - "fadd v16.8h, v5.8h, v4.8h\n" - "fadd v18.8h, v3.8h, v2.8h\n" - "fadd v23.8h, v1.8h, v0.8h\n" - "fadd v17.8h, v17.8h, v16.8h\n" - "fadd v22.8h, v31.8h, v30.8h\n" - "fadd v16.8h, v29.8h, v28.8h\n" - "fadd v21.8h, v18.8h, v17.8h\n" - "fadd v19.8h, v27.8h, v23.8h\n" - "fadd v20.8h, v16.8h, v17.8h\n" - "fadd v18.8h, v26.8h, v22.8h\n" - "fadd v17.8h, v25.8h, v23.8h\n" - "fadd v16.8h, v24.8h, v22.8h\n" + "fadd v17.8h, v6.8h, v5.8h\n" + "fadd v16.8h, v4.8h, v3.8h\n" + "fadd v19.8h, v17.8h, v16.8h\n" + "fadd v18.8h, v2.8h, v1.8h\n" + "fadd v17.8h, v0.8h, v31.8h\n" + "fadd v22.8h, v30.8h, v29.8h\n" + "fadd v16.8h, v28.8h, v27.8h\n" + "fadd v21.8h, v18.8h, v19.8h\n" + "fadd v20.8h, v16.8h, v19.8h\n" + "fadd v19.8h, v26.8h, v17.8h\n" + "fadd v18.8h, v25.8h, v22.8h\n" + "fadd v17.8h, v24.8h, v17.8h\n" + "fadd v16.8h, v23.8h, v22.8h\n" "fadd v19.8h, v21.8h, v19.8h\n" "fadd v18.8h, v21.8h, v18.8h\n" "fadd v17.8h, v17.8h, v20.8h\n" - "fadd v16.8h, v20.8h, v16.8h\n" - "fmul v19.8h, v19.8h, v8.h[0]\n" - "str q19, [x7, x6]\n" - "fmul v18.8h, v18.8h, v8.h[1]\n" - "fmul v17.8h, v17.8h, v8.h[2]\n" - "str q18, [x8, x6]\n" - "fmul v16.8h, v16.8h, v8.h[3]\n" - "str q17, [x17, x6]\n" - "str q16, [x16, x6]\n" - "add x6, x6, #0x10\n" - "cbz x4, 4f\n" + "fadd v16.8h, v16.8h, v20.8h\n" + "fmul v19.8h, v19.8h, v7.h[0]\n" + "str q19, [x6, x5]\n" + "fmul v18.8h, v18.8h, v7.h[1]\n" + "fmul v17.8h, v17.8h, v7.h[2]\n" + "str q18, [x7, x5]\n" + "fmul v16.8h, v16.8h, v7.h[3]\n" + "str q17, [x8, x5]\n" + "str q16, [x17, x5]\n" + "add x5, x5, #0x10\n" + "cbz x3, 4f\n" "3:" // Oddments - "ldr h7, [x10, x5]\n" - "subs x4, x4, #0x1\n" - "ldr h6, [x9, x5]\n" - "fadd v17.8h, v7.8h, v6.8h\n" - "ldr h5, [x26, x5]\n" - "ldr h4, [x25, x5]\n" - "fadd v16.8h, v5.8h, v4.8h\n" - "ldr h3, [x14, x5]\n" - "ldr h2, [x13, x5]\n" - "fadd v17.8h, v17.8h, v16.8h\n" - "ldr h1, [x11, x5]\n" - "ldr h0, [x27, x5]\n" - "fadd v18.8h, v3.8h, v2.8h\n" - "ldr h31, [x28, x5]\n" - "fadd v23.8h, v1.8h, v0.8h\n" - "ldr h30, [x24, x5]\n" - "fadd v21.8h, v18.8h, v17.8h\n" - "ldr h29, [x22, x5]\n" - "ldr h28, [x21, x5]\n" - "fadd v22.8h, v31.8h, v30.8h\n" - "ldr h27, [x15, x5]\n" - "ldr h26, [x12, x5]\n" - "fadd v16.8h, v29.8h, v28.8h\n" - "ldr h25, [x23, x5]\n" - "fadd v20.8h, v16.8h, v17.8h\n" - "ldr h24, [x20, x5]\n" - "add x5, x5, #0x2\n" - "fadd v19.8h, v27.8h, v23.8h\n" - "fadd v18.8h, v26.8h, v22.8h\n" - "fadd v17.8h, v25.8h, v23.8h\n" - "fadd v16.8h, v24.8h, v22.8h\n" - "fadd v19.8h, v21.8h, v19.8h\n" - "fadd v18.8h, v21.8h, v18.8h\n" + "ldr h17, [x11, x4]\n" + "ldr h16, [x10, x4]\n" + "fadd v18.8h, v17.8h, v16.8h\n" + "subs x3, x3, #0x1\n" + "ldr h17, [x27, x4]\n" + "ldr h16, [x26, x4]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v18.8h, v18.8h, v16.8h\n" + "ldr h17, [x15, x4]\n" + "ldr h16, [x14, x4]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v23.8h, v16.8h, v18.8h\n" + "ldr h17, [x12, x4]\n" + "ldr h16, [x28, x4]\n" + "fadd v22.8h, v17.8h, v16.8h\n" + "ldr h17, [x9, x4]\n" + "ldr h16, [x25, x4]\n" + "fadd v21.8h, v17.8h, v16.8h\n" + "ldr h17, [x23, x4]\n" + "ldr h16, [x22, x4]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v20.8h, v16.8h, v18.8h\n" + "ldr h17, [x16, x4]\n" + "ldr h16, [x13, x4]\n" + "fadd v19.8h, v17.8h, v22.8h\n" + "fadd v18.8h, v16.8h, v21.8h\n" + "ldr h17, [x24, x4]\n" + "ldr h16, [x21, x4]\n" + "fadd v17.8h, v17.8h, v22.8h\n" + "fadd v16.8h, v16.8h, v21.8h\n" + "fadd v19.8h, v23.8h, v19.8h\n" + "fadd v18.8h, v23.8h, v18.8h\n" + "add x4, x4, #0x2\n" "fadd v17.8h, v17.8h, v20.8h\n" - "fadd v16.8h, v20.8h, v16.8h\n" - "fmul v19.8h, v19.8h, v8.h[0]\n" - "str h19, [x7, x6]\n" - "fmul v18.8h, v18.8h, v8.h[1]\n" - "fmul v17.8h, v17.8h, v8.h[2]\n" - "str h18, [x8, x6]\n" - "fmul v16.8h, v16.8h, v8.h[3]\n" - "str h17, [x17, x6]\n" - "str h16, [x16, x6]\n" - "add x6, x6, #0x2\n" + "fadd v16.8h, v16.8h, v20.8h\n" + "fmul v19.8h, v19.8h, v7.h[0]\n" + "fmul v18.8h, v18.8h, v7.h[1]\n" + "str h19, [x6, x5]\n" + "fmul v17.8h, v17.8h, v7.h[2]\n" + "fmul v16.8h, v16.8h, v7.h[3]\n" + "str h18, [x7, x5]\n" + "str h17, [x8, x5]\n" + "str h16, [x17, x5]\n" + "add x5, x5, #0x2\n" "bgt 3b\n" "4:" // End - : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst.hpp index 9dc153a764..25e7af1cee 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_fp16_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); -struct a64_fp16_nhwc_avg_generic_depthfirst +struct a64_fp16_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = a64_fp16_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; a64_fp16_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_fp16_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp index 5bef7f2bf4..f7be92e53f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) @@ -41,308 +42,306 @@ void a64_fp16_nhwc_avg_generic_depthfirst_impl( const auto rescale_value = static_cast<__fp16>(1.0f / static_cast<float>(window_cells)); __asm__ __volatile__( - "ld1r { v8.8h }, [%x[rescale_ptr]]\n" - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 + "ld1r { v9.8h }, [%x[rescale_ptr]]\n" "cmp %x[n_channels], #0x20\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x19, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "movi v5.16b, #0x0\n" - "movi v4.16b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "fadd v23.8h, v3.8h, v2.8h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd v19.8h, v1.8h, v0.8h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd v22.8h, v31.8h, v30.8h\n" - "ldr q3, [x23, x28]\n" - "fadd v18.8h, v29.8h, v28.8h\n" - "fadd v21.8h, v27.8h, v21.8h\n" - "ldr q2, [x22, x28]\n" - "fadd v17.8h, v26.8h, v17.8h\n" - "ldr q1, [x21, x28]\n" - "fadd v20.8h, v25.8h, v20.8h\n" - "ldr q0, [x20, x28]\n" - "fadd v16.8h, v24.8h, v16.8h\n" - "ldr q31, [x23, x27]\n" + "fadd v23.8h, v4.8h, v3.8h\n" + "fadd v19.8h, v28.8h, v22.8h\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fadd v22.8h, v2.8h, v1.8h\n" + "ldr q2, [x21, x26]\n" + "fadd v18.8h, v27.8h, v21.8h\n" + "ldr q1, [x20, x26]\n" + "fadd v21.8h, v0.8h, v31.8h\n" + "ldr q0, [x21, x24]\n" + "fadd v17.8h, v26.8h, v20.8h\n" + "ldr q31, [x20, x24]\n" + "fadd v20.8h, v30.8h, v29.8h\n" + "ldr q30, [x21, x23]\n" + "fadd v16.8h, v25.8h, v24.8h\n" + "ldr q29, [x20, x23]\n" "fadd v19.8h, v23.8h, v19.8h\n" - "ldr q30, [x22, x27]\n" "fadd v18.8h, v22.8h, v18.8h\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fadd v17.8h, v21.8h, v17.8h\n" - "ldr q28, [x20, x27]\n" "fadd v16.8h, v20.8h, v16.8h\n" - "ldr q27, [x23, x26]\n" - "fadd v7.8h, v7.8h, v19.8h\n" - "ldr q21, [x22, x26]\n" - "fadd v6.8h, v6.8h, v18.8h\n" - "ldr q26, [x21, x26]\n" - "fadd v5.8h, v5.8h, v17.8h\n" - "ldr q17, [x20, x26]\n" - "fadd v4.8h, v4.8h, v16.8h\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "fadd v8.8h, v8.8h, v19.8h\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "fadd v7.8h, v7.8h, v18.8h\n" + "fadd v6.8h, v6.8h, v17.8h\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "fadd v5.8h, v5.8h, v16.8h\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "fadd v23.8h, v3.8h, v2.8h\n" - "fadd v19.8h, v1.8h, v0.8h\n" - "fadd v22.8h, v31.8h, v30.8h\n" - "fadd v18.8h, v29.8h, v28.8h\n" - "fadd v21.8h, v27.8h, v21.8h\n" - "fadd v17.8h, v26.8h, v17.8h\n" - "fadd v20.8h, v25.8h, v20.8h\n" - "fadd v16.8h, v24.8h, v16.8h\n" + "fadd v23.8h, v4.8h, v3.8h\n" + "fadd v19.8h, v28.8h, v22.8h\n" + "fadd v22.8h, v2.8h, v1.8h\n" + "fadd v18.8h, v27.8h, v21.8h\n" + "fadd v21.8h, v0.8h, v31.8h\n" + "fadd v17.8h, v26.8h, v20.8h\n" + "fadd v20.8h, v30.8h, v29.8h\n" + "fadd v16.8h, v25.8h, v24.8h\n" "fadd v19.8h, v23.8h, v19.8h\n" "fadd v18.8h, v22.8h, v18.8h\n" "fadd v17.8h, v21.8h, v17.8h\n" "fadd v16.8h, v20.8h, v16.8h\n" - "fadd v7.8h, v7.8h, v19.8h\n" - "fadd v6.8h, v6.8h, v18.8h\n" - "fadd v5.8h, v5.8h, v17.8h\n" - "fadd v4.8h, v4.8h, v16.8h\n" + "fadd v8.8h, v8.8h, v19.8h\n" + "fadd v7.8h, v7.8h, v18.8h\n" + "fadd v6.8h, v6.8h, v17.8h\n" + "fadd v5.8h, v5.8h, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fadd v7.8h, v7.8h, v3.8h\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "fadd v6.8h, v6.8h, v31.8h\n" - "ldr q25, [x23, x25]\n" - "fadd v5.8h, v5.8h, v27.8h\n" - "fadd v4.8h, v4.8h, v25.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fadd v8.8h, v8.8h, v16.8h\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fadd v7.8h, v7.8h, v17.8h\n" + "fadd v6.8h, v6.8h, v16.8h\n" + "ldr q16, [x20, x23]\n" + "fadd v5.8h, v5.8h, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "fmul v7.8h, v7.8h, v8.8h\n" - "str q7, [%x[outptr], x28]\n" - "fmul v6.8h, v6.8h, v8.8h\n" - "add x28, x28, #0x40\n" - "fmul v5.8h, v5.8h, v8.8h\n" - "str q6, [%x[outptr], x27]\n" - "fmul v4.8h, v4.8h, v8.8h\n" - "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" "sub %x[n_channels], %x[n_channels], #0x20\n" - "str q4, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" "cmp %x[n_channels], #0x20\n" + "fmul v8.8h, v8.8h, v9.8h\n" + "fmul v7.8h, v7.8h, v9.8h\n" + "fmul v6.8h, v6.8h, v9.8h\n" + "fmul v5.8h, v5.8h, v9.8h\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" + "str q7, [%x[outptr], x26]\n" + "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 31f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x8\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "movi v7.16b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd v23.8h, v3.8h, v2.8h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd v19.8h, v1.8h, v0.8h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd v19.8h, v23.8h, v19.8h\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "fadd v7.8h, v7.8h, v19.8h\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "fadd v17.8h, v4.8h, v3.8h\n" + "fadd v16.8h, v28.8h, v22.8h\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fadd v8.8h, v8.8h, v16.8h\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd v23.8h, v3.8h, v2.8h\n" - "fadd v19.8h, v1.8h, v0.8h\n" - "fadd v19.8h, v23.8h, v19.8h\n" - "fadd v7.8h, v7.8h, v19.8h\n" + "fadd v17.8h, v4.8h, v3.8h\n" + "fadd v16.8h, v28.8h, v22.8h\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v8.8h, v8.8h, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fadd v7.8h, v7.8h, v3.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fadd v8.8h, v8.8h, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "fmul v7.8h, v7.8h, v8.8h\n" - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" "sub %x[n_channels], %x[n_channels], #0x8\n" "cmp %x[n_channels], #0x8\n" + "fmul v8.8h, v8.8h, v9.8h\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 31f\n" "14:" // Oddments - "movi v7.16b, #0x0\n" - "add %x[outptr], %x[outptr], x28\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 20f\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "add %x[outptr], %x[outptr], x27\n" + "movi v8.16b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 20f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #2, 17f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v2.h }[6], [x22], #0x2\n" - "ld1 { v1.h }[6], [x21], #0x2\n" - "ld1 { v0.h }[6], [x20], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "b 19f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v2.h }[4], [x22], #0x2\n" - "ld1 { v1.h }[4], [x21], #0x2\n" - "ld1 { v0.h }[4], [x20], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "b 19f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v2.h }[2], [x22], #0x2\n" - "ld1 { v1.h }[2], [x21], #0x2\n" - "ld1 { v0.h }[2], [x20], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "b 19f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ldr h3, [x23], #0x2\n" - "ldr h2, [x22], #0x2\n" - "ldr h1, [x21], #0x2\n" - "ldr h0, [x20], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "19:" // Oddments: 4 inputs loop: Load: Bit 2: End - "fadd v23.8h, v3.8h, v2.8h\n" - "subs x24, x24, #0x1\n" - "fadd v19.8h, v1.8h, v0.8h\n" - "fadd v19.8h, v23.8h, v19.8h\n" - "fadd v7.8h, v7.8h, v19.8h\n" + "fadd v17.8h, v4.8h, v3.8h\n" + "fadd v16.8h, v28.8h, v22.8h\n" + "subs x25, x25, #0x1\n" + "fadd v16.8h, v17.8h, v16.8h\n" + "fadd v8.8h, v8.8h, v16.8h\n" "bgt 15b\n" "20:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 26f\n" "21:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #2, 23f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #1, 22f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "b 25f\n" "22:" // Oddments: Single input loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "b 25f\n" "23:" // Oddments: Single input loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 24f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "b 25f\n" "24:" // Oddments: Single input loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ldr h3, [x23], #0x2\n" + "ldr h4, [x23], #0x2\n" "25:" // Oddments: Single input loop: Load: Bit 2: End - "fadd v7.8h, v7.8h, v3.8h\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "fadd v8.8h, v8.8h, v4.8h\n" "bgt 21b\n" "26:" // Oddments: Single input loop: End - "fmul v7.8h, v7.8h, v8.8h\n" + "fmul v8.8h, v8.8h, v9.8h\n" "tbz %x[n_channels], #2, 28f\n" - "st1 { v7.d }[0], [%x[outptr]], #0x8\n" + "st1 { v8.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #1, 27f\n" - "st1 { v7.s }[2], [%x[outptr]], #0x4\n" + "st1 { v8.s }[2], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[6], [%x[outptr]], #0x2\n" + "st1 { v8.h }[6], [%x[outptr]], #0x2\n" "b 30f\n" "27:" // Oddments: Store: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[4], [%x[outptr]], #0x2\n" + "st1 { v8.h }[4], [%x[outptr]], #0x2\n" "b 30f\n" "28:" // Oddments: Store: Bit 2: Unset "tbz %x[n_channels], #1, 29f\n" - "st1 { v7.s }[0], [%x[outptr]], #0x4\n" + "st1 { v8.s }[0], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[2], [%x[outptr]], #0x2\n" + "st1 { v8.h }[2], [%x[outptr]], #0x2\n" "b 30f\n" "29:" // Oddments: Store: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[0], [%x[outptr]], #0x2\n" + "st1 { v8.h }[0], [%x[outptr]], #0x2\n" "30:" // Oddments: Store: Bit 2: End - "31:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [rescale_ptr] "r" (&rescale_value) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 9950bb8cdb..b65ac7e9fa 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) namespace arm_conv { namespace pooling { void a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst +struct a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; + using Parent = DepthfirstStrategy<__fp16, __fp16>; - typedef void (*kern_type)(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 1c461ee163..4b073b9076 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) namespace arm_conv { namespace pooling { @@ -63,116 +63,115 @@ void a64_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x15, [%x[args], %[offsetof_n_channels]]\n" - "mov x14, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "cmp x15, #0x8\n" - "ldp x12, x11, [x20, #0x0]\n" - "ldp x10, x9, [x20, #0x10]\n" - "ldp x28, x27, [x19, #0x0]\n" - "ldp x26, x25, [x19, #0x10]\n" - "ldp x24, x23, [x19, #0x20]\n" - "ldp x22, x21, [x19, #0x30]\n" - "ldr x20, [x19, #0x40]\n" + "ldr x16, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "cmp x16, #0x8\n" + "mov x15, #0x0\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x14, x13, [x21, #0x0]\n" + "mov x12, #0x0\n" + "ldp x11, x10, [x21, #0x10]\n" + "ldp x9, x28, [x20, #0x0]\n" + "ldp x27, x26, [x20, #0x10]\n" + "ldp x25, x24, [x20, #0x20]\n" + "ldp x23, x22, [x20, #0x30]\n" + "ldr x21, [x20, #0x40]\n" "blt 3f\n" - "ldr q30, [x27, x14]\n" - "lsr x19, x15, #0x3\n" - "ldr q29, [x24, x14]\n" - "sub x15, x15, x19, LSL #3\n" - "ldr q28, [x21, x14]\n" - "subs x19, x19, #0x1\n" - "ldr q27, [x25, x14]\n" - "ldr q26, [x28, x14]\n" - "ldr q25, [x23, x14]\n" - "ldr q24, [x26, x14]\n" - "ldr q23, [x22, x14]\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q30, [x28, x15]\n" + "ldr q29, [x25, x15]\n" + "lsr x20, x16, #0x3\n" + "sub x16, x16, x20, LSL #3\n" + "ldr q28, [x22, x15]\n" + "ldr q27, [x26, x15]\n" + "subs x20, x20, #0x1\n" + "ldr q26, [x9, x15]\n" + "ldr q25, [x27, x15]\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "ldr q22, [x21, x15]\n" + "add x15, x15, #0x10\n" "beq 2f\n" "1:" // Vector: Loop "fmax v21.8h, v30.8h, v29.8h\n" - "ldr q30, [x27, x14]\n" - "subs x19, x19, #0x1\n" + "ldr q30, [x28, x15]\n" "fmax v20.8h, v29.8h, v28.8h\n" - "ldr q29, [x24, x14]\n" + "ldr q29, [x25, x15]\n" + "ldr q28, [x22, x15]\n" "fmax v19.8h, v27.8h, v26.8h\n" - "ldr q28, [x21, x14]\n" + "ldr q26, [x9, x15]\n" "fmax v18.8h, v25.8h, v24.8h\n" - "ldr q26, [x28, x14]\n" - "fmax v17.8h, v23.8h, v27.8h\n" - "ldr q27, [x25, x14]\n" - "fmax v16.8h, v25.8h, v22.8h\n" - "ldr q25, [x23, x14]\n" + "ldr q25, [x27, x15]\n" + "fmax v17.8h, v27.8h, v23.8h\n" + "ldr q27, [x26, x15]\n" + "fmax v16.8h, v24.8h, v22.8h\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "subs x20, x20, #0x1\n" "fmax v19.8h, v21.8h, v19.8h\n" - "ldr q24, [x26, x14]\n" - "fmax v18.8h, v21.8h, v18.8h\n" - "ldr q23, [x22, x14]\n" - "fmax v17.8h, v20.8h, v17.8h\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q22, [x21, x15]\n" + "fmax v18.8h, v18.8h, v21.8h\n" + "fmax v17.8h, v17.8h, v20.8h\n" + "add x15, x15, #0x10\n" "fmax v16.8h, v20.8h, v16.8h\n" - "str q19, [x12, x13]\n" - "str q18, [x11, x13]\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" + "str q19, [x14, x12]\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" "bgt 1b\n" "2:" // Vector: Tail "fmax v21.8h, v30.8h, v29.8h\n" "fmax v20.8h, v29.8h, v28.8h\n" - "fmax v19.8h, v27.8h, v26.8h\n" + "fmax v16.8h, v27.8h, v26.8h\n" "fmax v18.8h, v25.8h, v24.8h\n" - "fmax v17.8h, v23.8h, v27.8h\n" - "fmax v16.8h, v25.8h, v22.8h\n" - "fmax v19.8h, v21.8h, v19.8h\n" - "str q19, [x12, x13]\n" - "fmax v18.8h, v21.8h, v18.8h\n" - "fmax v17.8h, v20.8h, v17.8h\n" - "str q18, [x11, x13]\n" - "fmax v16.8h, v20.8h, v16.8h\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" - "cbz x15, 4f\n" + "fmax v17.8h, v27.8h, v23.8h\n" + "fmax v19.8h, v24.8h, v22.8h\n" + "fmax v16.8h, v21.8h, v16.8h\n" + "fmax v18.8h, v18.8h, v21.8h\n" + "str q16, [x14, x12]\n" + "fmax v17.8h, v17.8h, v20.8h\n" + "fmax v16.8h, v20.8h, v19.8h\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" + "cbz x16, 4f\n" "3:" // Oddments - "ldr h30, [x27, x14]\n" - "subs x15, x15, #0x1\n" - "ldr h29, [x24, x14]\n" - "fmax v21.8h, v30.8h, v29.8h\n" - "ldr h28, [x21, x14]\n" - "ldr h27, [x25, x14]\n" - "fmax v20.8h, v29.8h, v28.8h\n" - "ldr h26, [x28, x14]\n" - "ldr h25, [x23, x14]\n" - "fmax v19.8h, v27.8h, v26.8h\n" - "ldr h24, [x26, x14]\n" - "ldr h23, [x22, x14]\n" - "fmax v19.8h, v21.8h, v19.8h\n" - "ldr h22, [x20, x14]\n" - "add x14, x14, #0x2\n" - "fmax v18.8h, v25.8h, v24.8h\n" - "str h19, [x12, x13]\n" - "fmax v17.8h, v23.8h, v27.8h\n" - "fmax v16.8h, v25.8h, v22.8h\n" - "fmax v18.8h, v21.8h, v18.8h\n" - "str h18, [x11, x13]\n" - "fmax v17.8h, v20.8h, v17.8h\n" - "fmax v16.8h, v20.8h, v16.8h\n" - "str h17, [x10, x13]\n" - "str h16, [x9, x13]\n" - "add x13, x13, #0x2\n" + "ldr h16, [x28, x15]\n" + "ldr h17, [x25, x15]\n" + "fmax v23.8h, v16.8h, v17.8h\n" + "subs x16, x16, #0x1\n" + "ldr h16, [x22, x15]\n" + "ldr h22, [x26, x15]\n" + "fmax v21.8h, v17.8h, v16.8h\n" + "ldr h16, [x9, x15]\n" + "ldr h17, [x27, x15]\n" + "fmax v16.8h, v22.8h, v16.8h\n" + "fmax v20.8h, v23.8h, v16.8h\n" + "ldr h19, [x24, x15]\n" + "ldr h16, [x23, x15]\n" + "fmax v18.8h, v17.8h, v19.8h\n" + "fmax v17.8h, v22.8h, v16.8h\n" + "ldr h16, [x21, x15]\n" + "fmax v16.8h, v19.8h, v16.8h\n" + "add x15, x15, #0x2\n" + "fmax v18.8h, v18.8h, v23.8h\n" + "fmax v17.8h, v17.8h, v21.8h\n" + "fmax v16.8h, v21.8h, v16.8h\n" + "str h20, [x14, x12]\n" + "str h18, [x13, x12]\n" + "str h17, [x11, x12]\n" + "str h16, [x10, x12]\n" + "add x12, x12, #0x2\n" "bgt 3b\n" "4:" // End - : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) +#endif // defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst.hpp index 8bea0bf5df..4998b37b4b 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_fp16_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); -struct a64_fp16_nhwc_max_generic_depthfirst +struct a64_fp16_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = a64_fp16_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; a64_fp16_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_fp16_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp index e5f7ee3c72..c92e2cdebd 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #if defined(__aarch64__) && defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) @@ -39,304 +40,302 @@ void a64_fp16_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x20\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "mov w20, #0xfc00\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "dup v8.8h, w20\n" "dup v7.8h, w20\n" - "mov x19, %x[inptrs]\n" "dup v6.8h, w20\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "dup v5.8h, w20\n" - "dup v4.8h, w20\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "fmax v23.8h, v3.8h, v2.8h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fmax v19.8h, v1.8h, v0.8h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fmax v22.8h, v31.8h, v30.8h\n" - "ldr q3, [x23, x28]\n" - "fmax v18.8h, v29.8h, v28.8h\n" - "fmax v21.8h, v27.8h, v21.8h\n" - "ldr q2, [x22, x28]\n" - "fmax v17.8h, v26.8h, v17.8h\n" - "ldr q1, [x21, x28]\n" - "fmax v20.8h, v25.8h, v20.8h\n" - "ldr q0, [x20, x28]\n" - "fmax v16.8h, v24.8h, v16.8h\n" - "ldr q31, [x23, x27]\n" + "fmax v23.8h, v4.8h, v3.8h\n" + "fmax v19.8h, v28.8h, v22.8h\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fmax v22.8h, v2.8h, v1.8h\n" + "ldr q2, [x21, x26]\n" + "fmax v18.8h, v27.8h, v21.8h\n" + "ldr q1, [x20, x26]\n" + "fmax v21.8h, v0.8h, v31.8h\n" + "ldr q0, [x21, x24]\n" + "fmax v17.8h, v26.8h, v20.8h\n" + "ldr q31, [x20, x24]\n" + "fmax v20.8h, v30.8h, v29.8h\n" + "ldr q30, [x21, x23]\n" + "fmax v16.8h, v25.8h, v24.8h\n" + "ldr q29, [x20, x23]\n" "fmax v19.8h, v23.8h, v19.8h\n" - "ldr q30, [x22, x27]\n" "fmax v18.8h, v22.8h, v18.8h\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fmax v17.8h, v21.8h, v17.8h\n" - "ldr q28, [x20, x27]\n" "fmax v16.8h, v20.8h, v16.8h\n" - "ldr q27, [x23, x26]\n" - "fmax v7.8h, v7.8h, v19.8h\n" - "ldr q21, [x22, x26]\n" - "fmax v6.8h, v6.8h, v18.8h\n" - "ldr q26, [x21, x26]\n" - "fmax v5.8h, v5.8h, v17.8h\n" - "ldr q17, [x20, x26]\n" - "fmax v4.8h, v4.8h, v16.8h\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "fmax v8.8h, v8.8h, v19.8h\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "fmax v7.8h, v7.8h, v18.8h\n" + "fmax v6.8h, v6.8h, v17.8h\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "fmax v5.8h, v5.8h, v16.8h\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "fmax v23.8h, v3.8h, v2.8h\n" - "fmax v19.8h, v1.8h, v0.8h\n" - "fmax v22.8h, v31.8h, v30.8h\n" - "fmax v18.8h, v29.8h, v28.8h\n" - "fmax v21.8h, v27.8h, v21.8h\n" - "fmax v17.8h, v26.8h, v17.8h\n" - "fmax v20.8h, v25.8h, v20.8h\n" - "fmax v16.8h, v24.8h, v16.8h\n" + "fmax v23.8h, v4.8h, v3.8h\n" + "fmax v19.8h, v28.8h, v22.8h\n" + "fmax v22.8h, v2.8h, v1.8h\n" + "fmax v18.8h, v27.8h, v21.8h\n" + "fmax v21.8h, v0.8h, v31.8h\n" + "fmax v17.8h, v26.8h, v20.8h\n" + "fmax v20.8h, v30.8h, v29.8h\n" + "fmax v16.8h, v25.8h, v24.8h\n" "fmax v19.8h, v23.8h, v19.8h\n" "fmax v18.8h, v22.8h, v18.8h\n" "fmax v17.8h, v21.8h, v17.8h\n" "fmax v16.8h, v20.8h, v16.8h\n" - "fmax v7.8h, v7.8h, v19.8h\n" - "fmax v6.8h, v6.8h, v18.8h\n" - "fmax v5.8h, v5.8h, v17.8h\n" - "fmax v4.8h, v4.8h, v16.8h\n" + "fmax v8.8h, v8.8h, v19.8h\n" + "fmax v7.8h, v7.8h, v18.8h\n" + "fmax v6.8h, v6.8h, v17.8h\n" + "fmax v5.8h, v5.8h, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fmax v7.8h, v7.8h, v3.8h\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "fmax v6.8h, v6.8h, v31.8h\n" - "ldr q25, [x23, x25]\n" - "fmax v5.8h, v5.8h, v27.8h\n" - "fmax v4.8h, v4.8h, v25.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fmax v8.8h, v8.8h, v16.8h\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fmax v7.8h, v7.8h, v17.8h\n" + "fmax v6.8h, v6.8h, v16.8h\n" + "ldr q16, [x20, x23]\n" + "fmax v5.8h, v5.8h, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" - "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" - "str q4, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" "sub %x[n_channels], %x[n_channels], #0x20\n" "cmp %x[n_channels], #0x20\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" + "add x27, x27, #0x40\n" + "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 31f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x8\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "mov w19, #0xfc00\n" - "dup v7.8h, w19\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "mov w20, #0xfc00\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "dup v8.8h, w20\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fmax v23.8h, v3.8h, v2.8h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fmax v19.8h, v1.8h, v0.8h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fmax v19.8h, v23.8h, v19.8h\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "fmax v7.8h, v7.8h, v19.8h\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "fmax v17.8h, v4.8h, v3.8h\n" + "fmax v16.8h, v28.8h, v22.8h\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fmax v16.8h, v17.8h, v16.8h\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fmax v8.8h, v8.8h, v16.8h\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fmax v23.8h, v3.8h, v2.8h\n" - "fmax v19.8h, v1.8h, v0.8h\n" - "fmax v19.8h, v23.8h, v19.8h\n" - "fmax v7.8h, v7.8h, v19.8h\n" + "fmax v17.8h, v4.8h, v3.8h\n" + "fmax v16.8h, v28.8h, v22.8h\n" + "fmax v16.8h, v17.8h, v16.8h\n" + "fmax v8.8h, v8.8h, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fmax v7.8h, v7.8h, v3.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fmax v8.8h, v8.8h, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" "sub %x[n_channels], %x[n_channels], #0x8\n" "cmp %x[n_channels], #0x8\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 31f\n" "14:" // Oddments - "add %x[outptr], %x[outptr], x28\n" - "mov w19, #0xfc00\n" - "dup v7.8h, w19\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 20f\n" + "mov w20, #0xfc00\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "dup v8.8h, w20\n" + "add %x[outptr], %x[outptr], x27\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 20f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #2, 17f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v2.h }[6], [x22], #0x2\n" - "ld1 { v1.h }[6], [x21], #0x2\n" - "ld1 { v0.h }[6], [x20], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "b 19f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v2.h }[4], [x22], #0x2\n" - "ld1 { v1.h }[4], [x21], #0x2\n" - "ld1 { v0.h }[4], [x20], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "b 19f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v2.h }[2], [x22], #0x2\n" - "ld1 { v1.h }[2], [x21], #0x2\n" - "ld1 { v0.h }[2], [x20], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "b 19f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ldr h3, [x23], #0x2\n" - "ldr h2, [x22], #0x2\n" - "ldr h1, [x21], #0x2\n" - "ldr h0, [x20], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "19:" // Oddments: 4 inputs loop: Load: Bit 2: End - "fmax v23.8h, v3.8h, v2.8h\n" - "subs x24, x24, #0x1\n" - "fmax v19.8h, v1.8h, v0.8h\n" - "fmax v19.8h, v23.8h, v19.8h\n" - "fmax v7.8h, v7.8h, v19.8h\n" + "fmax v17.8h, v4.8h, v3.8h\n" + "fmax v16.8h, v28.8h, v22.8h\n" + "subs x25, x25, #0x1\n" + "fmax v16.8h, v17.8h, v16.8h\n" + "fmax v8.8h, v8.8h, v16.8h\n" "bgt 15b\n" "20:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 26f\n" "21:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #2, 23f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #1, 22f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "b 25f\n" "22:" // Oddments: Single input loop: Load: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "b 25f\n" "23:" // Oddments: Single input loop: Load: Bit 2: Unset "tbz %x[n_channels], #1, 24f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #0, 25f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "b 25f\n" "24:" // Oddments: Single input loop: Load: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 25f\n" - "ldr h3, [x23], #0x2\n" + "ldr h4, [x23], #0x2\n" "25:" // Oddments: Single input loop: Load: Bit 2: End - "fmax v7.8h, v7.8h, v3.8h\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "fmax v8.8h, v8.8h, v4.8h\n" "bgt 21b\n" "26:" // Oddments: Single input loop: End "tbz %x[n_channels], #2, 28f\n" - "st1 { v7.d }[0], [%x[outptr]], #0x8\n" + "st1 { v8.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #1, 27f\n" - "st1 { v7.s }[2], [%x[outptr]], #0x4\n" + "st1 { v8.s }[2], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[6], [%x[outptr]], #0x2\n" + "st1 { v8.h }[6], [%x[outptr]], #0x2\n" "b 30f\n" "27:" // Oddments: Store: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[4], [%x[outptr]], #0x2\n" + "st1 { v8.h }[4], [%x[outptr]], #0x2\n" "b 30f\n" "28:" // Oddments: Store: Bit 2: Unset "tbz %x[n_channels], #1, 29f\n" - "st1 { v7.s }[0], [%x[outptr]], #0x4\n" + "st1 { v8.s }[0], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[2], [%x[outptr]], #0x2\n" + "st1 { v8.h }[2], [%x[outptr]], #0x2\n" "b 30f\n" "29:" // Oddments: Store: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 30f\n" - "st1 { v7.h }[0], [%x[outptr]], #0x2\n" + "st1 { v8.h }[0], [%x[outptr]], #0x2\n" "30:" // Oddments: Store: Bit 2: End - "31:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index 9a16b99a71..7add5feb1d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,33 +24,28 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst +struct a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; - - typedef void (*kern_type)(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } + using Parent = DepthfirstStrategy<float, float>; - constexpr static unsigned int pool_rows(void) { return 3; } - constexpr static unsigned int pool_cols(void) { return 3; } + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } + a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; - - a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index ff8d7d8ba1..cf0047638e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -80,172 +82,173 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x4, [%x[args], %[offsetof_n_channels]]\n" + "ldr q7, [%x[args], %[offsetof_rescale]]\n" + "ldr x3, [%x[args], %[offsetof_n_channels]]\n" + "cmp x3, #0x4\n" + "mov x4, #0x0\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" "mov x5, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x6, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "cmp x4, #0x4\n" - "ldp x7, x8, [x20, #0x0]\n" - "ldp x17, x16, [x20, #0x10]\n" - "ldp x15, x14, [x19, #0x0]\n" - "ldp x13, x12, [x19, #0x10]\n" - "ldp x11, x10, [x19, #0x20]\n" - "ldp x9, x28, [x19, #0x30]\n" - "ldp x27, x26, [x19, #0x40]\n" - "ldp x25, x24, [x19, #0x50]\n" - "ldp x23, x22, [x19, #0x60]\n" - "ldp x21, x20, [x19, #0x70]\n" - "ldr q8, [%x[args], %[offsetof_rescale]]\n" + "ldp x6, x7, [x21, #0x0]\n" + "ldp x8, x17, [x21, #0x10]\n" + "ldp x16, x15, [x20, #0x0]\n" + "ldp x14, x13, [x20, #0x10]\n" + "ldp x12, x11, [x20, #0x20]\n" + "ldp x10, x9, [x20, #0x30]\n" + "ldp x28, x27, [x20, #0x40]\n" + "ldp x26, x25, [x20, #0x50]\n" + "ldp x24, x23, [x20, #0x60]\n" + "ldp x22, x21, [x20, #0x70]\n" "blt 3f\n" - "ldr q7, [x10, x5]\n" - "lsr x19, x4, #0x2\n" - "ldr q6, [x9, x5]\n" - "sub x4, x4, x19, LSL #2\n" - "ldr q5, [x26, x5]\n" - "subs x19, x19, #0x1\n" - "ldr q4, [x25, x5]\n" - "ldr q3, [x14, x5]\n" - "ldr q2, [x13, x5]\n" - "ldr q1, [x11, x5]\n" - "ldr q0, [x27, x5]\n" - "ldr q31, [x28, x5]\n" - "ldr q30, [x24, x5]\n" - "ldr q29, [x22, x5]\n" - "ldr q28, [x21, x5]\n" - "ldr q27, [x15, x5]\n" - "ldr q26, [x12, x5]\n" - "ldr q25, [x23, x5]\n" - "ldr q24, [x20, x5]\n" - "add x5, x5, #0x10\n" + "ldr q6, [x11, x4]\n" + "ldr q5, [x10, x4]\n" + "lsr x20, x3, #0x2\n" + "sub x3, x3, x20, LSL #2\n" + "ldr q4, [x27, x4]\n" + "ldr q3, [x26, x4]\n" + "subs x20, x20, #0x1\n" + "ldr q2, [x15, x4]\n" + "ldr q1, [x14, x4]\n" + "ldr q0, [x12, x4]\n" + "ldr q31, [x28, x4]\n" + "ldr q30, [x9, x4]\n" + "ldr q29, [x25, x4]\n" + "ldr q28, [x23, x4]\n" + "ldr q27, [x22, x4]\n" + "ldr q26, [x16, x4]\n" + "ldr q25, [x13, x4]\n" + "ldr q24, [x24, x4]\n" + "ldr q23, [x21, x4]\n" + "add x4, x4, #0x10\n" "beq 2f\n" "1:" // Vector: Loop - "fadd v17.4s, v7.4s, v6.4s\n" - "ldr q7, [x10, x5]\n" - "subs x19, x19, #0x1\n" - "fadd v16.4s, v5.4s, v4.4s\n" - "ldr q6, [x9, x5]\n" - "fadd v18.4s, v3.4s, v2.4s\n" - "ldr q5, [x26, x5]\n" - "fadd v23.4s, v1.4s, v0.4s\n" - "ldr q4, [x25, x5]\n" - "fadd v22.4s, v31.4s, v30.4s\n" - "ldr q3, [x14, x5]\n" - "fadd v17.4s, v17.4s, v16.4s\n" - "ldr q2, [x13, x5]\n" - "fadd v16.4s, v29.4s, v28.4s\n" - "ldr q1, [x11, x5]\n" - "fadd v19.4s, v27.4s, v23.4s\n" - "ldr q0, [x27, x5]\n" - "fadd v21.4s, v18.4s, v17.4s\n" - "ldr q31, [x28, x5]\n" - "fadd v20.4s, v16.4s, v17.4s\n" - "ldr q30, [x24, x5]\n" - "fadd v18.4s, v26.4s, v22.4s\n" - "ldr q29, [x22, x5]\n" - "fadd v17.4s, v25.4s, v23.4s\n" - "ldr q28, [x21, x5]\n" - "fadd v16.4s, v24.4s, v22.4s\n" - "ldr q27, [x15, x5]\n" + "fadd v17.4s, v6.4s, v5.4s\n" + "ldr q6, [x11, x4]\n" + "ldr q5, [x10, x4]\n" + "fadd v16.4s, v4.4s, v3.4s\n" + "ldr q4, [x27, x4]\n" + "ldr q3, [x26, x4]\n" + "fadd v19.4s, v17.4s, v16.4s\n" + "fadd v18.4s, v2.4s, v1.4s\n" + "ldr q2, [x15, x4]\n" + "ldr q1, [x14, x4]\n" + "fadd v17.4s, v0.4s, v31.4s\n" + "fadd v22.4s, v30.4s, v29.4s\n" + "ldr q0, [x12, x4]\n" + "ldr q31, [x28, x4]\n" + "fadd v16.4s, v28.4s, v27.4s\n" + "fadd v21.4s, v18.4s, v19.4s\n" + "ldr q30, [x9, x4]\n" + "ldr q29, [x25, x4]\n" + "fadd v20.4s, v16.4s, v19.4s\n" + "fadd v19.4s, v26.4s, v17.4s\n" + "ldr q28, [x23, x4]\n" + "ldr q27, [x22, x4]\n" + "fadd v18.4s, v25.4s, v22.4s\n" + "fadd v17.4s, v24.4s, v17.4s\n" + "ldr q26, [x16, x4]\n" + "ldr q25, [x13, x4]\n" + "fadd v16.4s, v23.4s, v22.4s\n" "fadd v19.4s, v21.4s, v19.4s\n" - "ldr q26, [x12, x5]\n" + "ldr q24, [x24, x4]\n" + "ldr q23, [x21, x4]\n" "fadd v18.4s, v21.4s, v18.4s\n" - "ldr q25, [x23, x5]\n" "fadd v17.4s, v17.4s, v20.4s\n" - "ldr q24, [x20, x5]\n" + "fadd v16.4s, v16.4s, v20.4s\n" + "subs x20, x20, #0x1\n" + "fmul v19.4s, v19.4s, v7.s[0]\n" + "add x4, x4, #0x10\n" + "fmul v18.4s, v18.4s, v7.s[1]\n" + "fmul v17.4s, v17.4s, v7.s[2]\n" + "str q19, [x6, x5]\n" + "fmul v16.4s, v16.4s, v7.s[3]\n" + "str q18, [x7, x5]\n" + "str q17, [x8, x5]\n" + "str q16, [x17, x5]\n" "add x5, x5, #0x10\n" - "fadd v16.4s, v20.4s, v16.4s\n" - "fmul v19.4s, v19.4s, v8.s[0]\n" - "str q19, [x7, x6]\n" - "fmul v18.4s, v18.4s, v8.s[1]\n" - "fmul v17.4s, v17.4s, v8.s[2]\n" - "str q18, [x8, x6]\n" - "fmul v16.4s, v16.4s, v8.s[3]\n" - "str q17, [x17, x6]\n" - "str q16, [x16, x6]\n" - "add x6, x6, #0x10\n" "bgt 1b\n" "2:" // Vector: Tail - "fadd v17.4s, v7.4s, v6.4s\n" - "fadd v16.4s, v5.4s, v4.4s\n" - "fadd v18.4s, v3.4s, v2.4s\n" - "fadd v23.4s, v1.4s, v0.4s\n" - "fadd v17.4s, v17.4s, v16.4s\n" - "fadd v22.4s, v31.4s, v30.4s\n" - "fadd v16.4s, v29.4s, v28.4s\n" - "fadd v21.4s, v18.4s, v17.4s\n" - "fadd v19.4s, v27.4s, v23.4s\n" - "fadd v20.4s, v16.4s, v17.4s\n" - "fadd v18.4s, v26.4s, v22.4s\n" - "fadd v17.4s, v25.4s, v23.4s\n" - "fadd v16.4s, v24.4s, v22.4s\n" + "fadd v17.4s, v6.4s, v5.4s\n" + "fadd v16.4s, v4.4s, v3.4s\n" + "fadd v19.4s, v17.4s, v16.4s\n" + "fadd v18.4s, v2.4s, v1.4s\n" + "fadd v17.4s, v0.4s, v31.4s\n" + "fadd v22.4s, v30.4s, v29.4s\n" + "fadd v16.4s, v28.4s, v27.4s\n" + "fadd v21.4s, v18.4s, v19.4s\n" + "fadd v20.4s, v16.4s, v19.4s\n" + "fadd v19.4s, v26.4s, v17.4s\n" + "fadd v18.4s, v25.4s, v22.4s\n" + "fadd v17.4s, v24.4s, v17.4s\n" + "fadd v16.4s, v23.4s, v22.4s\n" "fadd v19.4s, v21.4s, v19.4s\n" "fadd v18.4s, v21.4s, v18.4s\n" "fadd v17.4s, v17.4s, v20.4s\n" - "fadd v16.4s, v20.4s, v16.4s\n" - "fmul v19.4s, v19.4s, v8.s[0]\n" - "str q19, [x7, x6]\n" - "fmul v18.4s, v18.4s, v8.s[1]\n" - "fmul v17.4s, v17.4s, v8.s[2]\n" - "str q18, [x8, x6]\n" - "fmul v16.4s, v16.4s, v8.s[3]\n" - "str q17, [x17, x6]\n" - "str q16, [x16, x6]\n" - "add x6, x6, #0x10\n" - "cbz x4, 4f\n" + "fadd v16.4s, v16.4s, v20.4s\n" + "fmul v19.4s, v19.4s, v7.s[0]\n" + "str q19, [x6, x5]\n" + "fmul v18.4s, v18.4s, v7.s[1]\n" + "fmul v17.4s, v17.4s, v7.s[2]\n" + "str q18, [x7, x5]\n" + "fmul v16.4s, v16.4s, v7.s[3]\n" + "str q17, [x8, x5]\n" + "str q16, [x17, x5]\n" + "add x5, x5, #0x10\n" + "cbz x3, 4f\n" "3:" // Oddments - "ldr s7, [x10, x5]\n" - "subs x4, x4, #0x1\n" - "ldr s6, [x9, x5]\n" - "fadd v17.4s, v7.4s, v6.4s\n" - "ldr s5, [x26, x5]\n" - "ldr s4, [x25, x5]\n" - "fadd v16.4s, v5.4s, v4.4s\n" - "ldr s3, [x14, x5]\n" - "ldr s2, [x13, x5]\n" - "fadd v17.4s, v17.4s, v16.4s\n" - "ldr s1, [x11, x5]\n" - "ldr s0, [x27, x5]\n" - "fadd v18.4s, v3.4s, v2.4s\n" - "ldr s31, [x28, x5]\n" - "fadd v23.4s, v1.4s, v0.4s\n" - "ldr s30, [x24, x5]\n" - "fadd v21.4s, v18.4s, v17.4s\n" - "ldr s29, [x22, x5]\n" - "ldr s28, [x21, x5]\n" - "fadd v22.4s, v31.4s, v30.4s\n" - "ldr s27, [x15, x5]\n" - "ldr s26, [x12, x5]\n" - "fadd v16.4s, v29.4s, v28.4s\n" - "ldr s25, [x23, x5]\n" - "fadd v20.4s, v16.4s, v17.4s\n" - "ldr s24, [x20, x5]\n" - "add x5, x5, #0x4\n" - "fadd v19.4s, v27.4s, v23.4s\n" - "fadd v18.4s, v26.4s, v22.4s\n" - "fadd v17.4s, v25.4s, v23.4s\n" - "fadd v16.4s, v24.4s, v22.4s\n" - "fadd v19.4s, v21.4s, v19.4s\n" - "fadd v18.4s, v21.4s, v18.4s\n" + "ldr s17, [x11, x4]\n" + "ldr s16, [x10, x4]\n" + "fadd v18.4s, v17.4s, v16.4s\n" + "subs x3, x3, #0x1\n" + "ldr s17, [x27, x4]\n" + "ldr s16, [x26, x4]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v18.4s, v18.4s, v16.4s\n" + "ldr s17, [x15, x4]\n" + "ldr s16, [x14, x4]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v23.4s, v16.4s, v18.4s\n" + "ldr s17, [x12, x4]\n" + "ldr s16, [x28, x4]\n" + "fadd v22.4s, v17.4s, v16.4s\n" + "ldr s17, [x9, x4]\n" + "ldr s16, [x25, x4]\n" + "fadd v21.4s, v17.4s, v16.4s\n" + "ldr s17, [x23, x4]\n" + "ldr s16, [x22, x4]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v20.4s, v16.4s, v18.4s\n" + "ldr s17, [x16, x4]\n" + "ldr s16, [x13, x4]\n" + "fadd v19.4s, v17.4s, v22.4s\n" + "fadd v18.4s, v16.4s, v21.4s\n" + "ldr s17, [x24, x4]\n" + "ldr s16, [x21, x4]\n" + "fadd v17.4s, v17.4s, v22.4s\n" + "fadd v16.4s, v16.4s, v21.4s\n" + "fadd v19.4s, v23.4s, v19.4s\n" + "fadd v18.4s, v23.4s, v18.4s\n" + "add x4, x4, #0x4\n" "fadd v17.4s, v17.4s, v20.4s\n" - "fadd v16.4s, v20.4s, v16.4s\n" - "fmul v19.4s, v19.4s, v8.s[0]\n" - "str s19, [x7, x6]\n" - "fmul v18.4s, v18.4s, v8.s[1]\n" - "fmul v17.4s, v17.4s, v8.s[2]\n" - "str s18, [x8, x6]\n" - "fmul v16.4s, v16.4s, v8.s[3]\n" - "str s17, [x17, x6]\n" - "str s16, [x16, x6]\n" - "add x6, x6, #0x4\n" + "fadd v16.4s, v16.4s, v20.4s\n" + "fmul v19.4s, v19.4s, v7.s[0]\n" + "fmul v18.4s, v18.4s, v7.s[1]\n" + "str s19, [x6, x5]\n" + "fmul v17.4s, v17.4s, v7.s[2]\n" + "fmul v16.4s, v16.4s, v7.s[3]\n" + "str s18, [x7, x5]\n" + "str s17, [x8, x5]\n" + "str s16, [x17, x5]\n" + "add x5, x5, #0x4\n" "bgt 3b\n" "4:" // End - : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst.hpp index 4ef26318d4..26895e610d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_fp32_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); -struct a64_fp32_nhwc_avg_generic_depthfirst +struct a64_fp32_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = a64_fp32_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<float, float>; a64_fp32_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_fp32_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp index 21f705451a..d236f07b1c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #if defined(__aarch64__) @@ -41,260 +42,258 @@ void a64_fp32_nhwc_avg_generic_depthfirst_impl( const auto rescale_value = static_cast<float>(1.0f / static_cast<float>(window_cells)); __asm__ __volatile__( - "ld1r { v8.4s }, [%x[rescale_ptr]]\n" - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 + "ld1r { v9.4s }, [%x[rescale_ptr]]\n" "cmp %x[n_channels], #0x10\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x19, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "movi v5.16b, #0x0\n" - "movi v4.16b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "fadd v23.4s, v3.4s, v2.4s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd v19.4s, v1.4s, v0.4s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd v22.4s, v31.4s, v30.4s\n" - "ldr q3, [x23, x28]\n" - "fadd v18.4s, v29.4s, v28.4s\n" - "fadd v21.4s, v27.4s, v21.4s\n" - "ldr q2, [x22, x28]\n" - "fadd v17.4s, v26.4s, v17.4s\n" - "ldr q1, [x21, x28]\n" - "fadd v20.4s, v25.4s, v20.4s\n" - "ldr q0, [x20, x28]\n" - "fadd v16.4s, v24.4s, v16.4s\n" - "ldr q31, [x23, x27]\n" + "fadd v23.4s, v4.4s, v3.4s\n" + "fadd v19.4s, v28.4s, v22.4s\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fadd v22.4s, v2.4s, v1.4s\n" + "ldr q2, [x21, x26]\n" + "fadd v18.4s, v27.4s, v21.4s\n" + "ldr q1, [x20, x26]\n" + "fadd v21.4s, v0.4s, v31.4s\n" + "ldr q0, [x21, x24]\n" + "fadd v17.4s, v26.4s, v20.4s\n" + "ldr q31, [x20, x24]\n" + "fadd v20.4s, v30.4s, v29.4s\n" + "ldr q30, [x21, x23]\n" + "fadd v16.4s, v25.4s, v24.4s\n" + "ldr q29, [x20, x23]\n" "fadd v19.4s, v23.4s, v19.4s\n" - "ldr q30, [x22, x27]\n" "fadd v18.4s, v22.4s, v18.4s\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fadd v17.4s, v21.4s, v17.4s\n" - "ldr q28, [x20, x27]\n" "fadd v16.4s, v20.4s, v16.4s\n" - "ldr q27, [x23, x26]\n" - "fadd v7.4s, v7.4s, v19.4s\n" - "ldr q21, [x22, x26]\n" - "fadd v6.4s, v6.4s, v18.4s\n" - "ldr q26, [x21, x26]\n" - "fadd v5.4s, v5.4s, v17.4s\n" - "ldr q17, [x20, x26]\n" - "fadd v4.4s, v4.4s, v16.4s\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "fadd v8.4s, v8.4s, v19.4s\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "fadd v7.4s, v7.4s, v18.4s\n" + "fadd v6.4s, v6.4s, v17.4s\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "fadd v5.4s, v5.4s, v16.4s\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "fadd v23.4s, v3.4s, v2.4s\n" - "fadd v19.4s, v1.4s, v0.4s\n" - "fadd v22.4s, v31.4s, v30.4s\n" - "fadd v18.4s, v29.4s, v28.4s\n" - "fadd v21.4s, v27.4s, v21.4s\n" - "fadd v17.4s, v26.4s, v17.4s\n" - "fadd v20.4s, v25.4s, v20.4s\n" - "fadd v16.4s, v24.4s, v16.4s\n" + "fadd v23.4s, v4.4s, v3.4s\n" + "fadd v19.4s, v28.4s, v22.4s\n" + "fadd v22.4s, v2.4s, v1.4s\n" + "fadd v18.4s, v27.4s, v21.4s\n" + "fadd v21.4s, v0.4s, v31.4s\n" + "fadd v17.4s, v26.4s, v20.4s\n" + "fadd v20.4s, v30.4s, v29.4s\n" + "fadd v16.4s, v25.4s, v24.4s\n" "fadd v19.4s, v23.4s, v19.4s\n" "fadd v18.4s, v22.4s, v18.4s\n" "fadd v17.4s, v21.4s, v17.4s\n" "fadd v16.4s, v20.4s, v16.4s\n" - "fadd v7.4s, v7.4s, v19.4s\n" - "fadd v6.4s, v6.4s, v18.4s\n" - "fadd v5.4s, v5.4s, v17.4s\n" - "fadd v4.4s, v4.4s, v16.4s\n" + "fadd v8.4s, v8.4s, v19.4s\n" + "fadd v7.4s, v7.4s, v18.4s\n" + "fadd v6.4s, v6.4s, v17.4s\n" + "fadd v5.4s, v5.4s, v16.4s\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fadd v7.4s, v7.4s, v3.4s\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "fadd v6.4s, v6.4s, v31.4s\n" - "ldr q25, [x23, x25]\n" - "fadd v5.4s, v5.4s, v27.4s\n" - "fadd v4.4s, v4.4s, v25.4s\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fadd v8.4s, v8.4s, v16.4s\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fadd v7.4s, v7.4s, v17.4s\n" + "fadd v6.4s, v6.4s, v16.4s\n" + "ldr q16, [x20, x23]\n" + "fadd v5.4s, v5.4s, v16.4s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "fmul v7.4s, v7.4s, v8.4s\n" - "str q7, [%x[outptr], x28]\n" - "fmul v6.4s, v6.4s, v8.4s\n" - "add x28, x28, #0x40\n" - "fmul v5.4s, v5.4s, v8.4s\n" - "str q6, [%x[outptr], x27]\n" - "fmul v4.4s, v4.4s, v8.4s\n" - "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" "sub %x[n_channels], %x[n_channels], #0x10\n" - "str q4, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" "cmp %x[n_channels], #0x10\n" + "fmul v8.4s, v8.4s, v9.4s\n" + "fmul v7.4s, v7.4s, v9.4s\n" + "fmul v6.4s, v6.4s, v9.4s\n" + "fmul v5.4s, v5.4s, v9.4s\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" + "str q7, [%x[outptr], x26]\n" + "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 25f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x4\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "movi v7.16b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd v23.4s, v3.4s, v2.4s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd v19.4s, v1.4s, v0.4s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd v19.4s, v23.4s, v19.4s\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "fadd v7.4s, v7.4s, v19.4s\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "fadd v17.4s, v4.4s, v3.4s\n" + "fadd v16.4s, v28.4s, v22.4s\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fadd v8.4s, v8.4s, v16.4s\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd v23.4s, v3.4s, v2.4s\n" - "fadd v19.4s, v1.4s, v0.4s\n" - "fadd v19.4s, v23.4s, v19.4s\n" - "fadd v7.4s, v7.4s, v19.4s\n" + "fadd v17.4s, v4.4s, v3.4s\n" + "fadd v16.4s, v28.4s, v22.4s\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v8.4s, v8.4s, v16.4s\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fadd v7.4s, v7.4s, v3.4s\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fadd v8.4s, v8.4s, v16.4s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "fmul v7.4s, v7.4s, v8.4s\n" - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" "sub %x[n_channels], %x[n_channels], #0x4\n" "cmp %x[n_channels], #0x4\n" + "fmul v8.4s, v8.4s, v9.4s\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 25f\n" "14:" // Oddments - "movi v7.16b, #0x0\n" - "add %x[outptr], %x[outptr], x28\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 18f\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "add %x[outptr], %x[outptr], x27\n" + "movi v8.16b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 18f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #1, 16f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #0, 17f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "b 17f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 17f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "17:" // Oddments: 4 inputs loop: Load: Bit 1: End - "fadd v23.4s, v3.4s, v2.4s\n" - "subs x24, x24, #0x1\n" - "fadd v19.4s, v1.4s, v0.4s\n" - "fadd v19.4s, v23.4s, v19.4s\n" - "fadd v7.4s, v7.4s, v19.4s\n" + "fadd v17.4s, v4.4s, v3.4s\n" + "fadd v16.4s, v28.4s, v22.4s\n" + "subs x25, x25, #0x1\n" + "fadd v16.4s, v17.4s, v16.4s\n" + "fadd v8.4s, v8.4s, v16.4s\n" "bgt 15b\n" "18:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 22f\n" "19:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #1, 20f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #0, 21f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "b 21f\n" "20:" // Oddments: Single input loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 21f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "21:" // Oddments: Single input loop: Load: Bit 1: End - "fadd v7.4s, v7.4s, v3.4s\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "fadd v8.4s, v8.4s, v4.4s\n" "bgt 19b\n" "22:" // Oddments: Single input loop: End - "fmul v7.4s, v7.4s, v8.4s\n" + "fmul v8.4s, v8.4s, v9.4s\n" "tbz %x[n_channels], #1, 23f\n" - "st1 { v7.d }[0], [%x[outptr]], #0x8\n" + "st1 { v8.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #0, 24f\n" - "st1 { v7.s }[2], [%x[outptr]], #0x4\n" + "st1 { v8.s }[2], [%x[outptr]], #0x4\n" "b 24f\n" "23:" // Oddments: Store: Bit 1: Unset "tbz %x[n_channels], #0, 24f\n" - "st1 { v7.s }[0], [%x[outptr]], #0x4\n" + "st1 { v8.s }[0], [%x[outptr]], #0x4\n" "24:" // Oddments: Store: Bit 1: End - "25:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [rescale_ptr] "r" (&rescale_value) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 9a22adf6f4..2f72b59d70 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,33 +24,28 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst +struct a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; - - typedef void (*kern_type)(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + using Parent = DepthfirstStrategy<float, float>; - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } + a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index ea7e2195d1..f4202de1ed 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -61,114 +63,115 @@ void a64_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x15, [%x[args], %[offsetof_n_channels]]\n" - "mov x14, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "cmp x15, #0x4\n" - "ldp x12, x11, [x20, #0x0]\n" - "ldp x10, x9, [x20, #0x10]\n" - "ldp x28, x27, [x19, #0x0]\n" - "ldp x26, x25, [x19, #0x10]\n" - "ldp x24, x23, [x19, #0x20]\n" - "ldp x22, x21, [x19, #0x30]\n" - "ldr x20, [x19, #0x40]\n" + "ldr x16, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "cmp x16, #0x4\n" + "mov x15, #0x0\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x14, x13, [x21, #0x0]\n" + "mov x12, #0x0\n" + "ldp x11, x10, [x21, #0x10]\n" + "ldp x9, x28, [x20, #0x0]\n" + "ldp x27, x26, [x20, #0x10]\n" + "ldp x25, x24, [x20, #0x20]\n" + "ldp x23, x22, [x20, #0x30]\n" + "ldr x21, [x20, #0x40]\n" "blt 3f\n" - "ldr q30, [x27, x14]\n" - "lsr x19, x15, #0x2\n" - "ldr q29, [x24, x14]\n" - "sub x15, x15, x19, LSL #2\n" - "ldr q28, [x21, x14]\n" - "subs x19, x19, #0x1\n" - "ldr q27, [x25, x14]\n" - "ldr q26, [x28, x14]\n" - "ldr q25, [x23, x14]\n" - "ldr q24, [x26, x14]\n" - "ldr q23, [x22, x14]\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q30, [x28, x15]\n" + "ldr q29, [x25, x15]\n" + "lsr x20, x16, #0x2\n" + "sub x16, x16, x20, LSL #2\n" + "ldr q28, [x22, x15]\n" + "ldr q27, [x26, x15]\n" + "subs x20, x20, #0x1\n" + "ldr q26, [x9, x15]\n" + "ldr q25, [x27, x15]\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "ldr q22, [x21, x15]\n" + "add x15, x15, #0x10\n" "beq 2f\n" "1:" // Vector: Loop "fmax v21.4s, v30.4s, v29.4s\n" - "ldr q30, [x27, x14]\n" - "subs x19, x19, #0x1\n" + "ldr q30, [x28, x15]\n" "fmax v20.4s, v29.4s, v28.4s\n" - "ldr q29, [x24, x14]\n" + "ldr q29, [x25, x15]\n" + "ldr q28, [x22, x15]\n" "fmax v19.4s, v27.4s, v26.4s\n" - "ldr q28, [x21, x14]\n" + "ldr q26, [x9, x15]\n" "fmax v18.4s, v25.4s, v24.4s\n" - "ldr q26, [x28, x14]\n" - "fmax v17.4s, v23.4s, v27.4s\n" - "ldr q27, [x25, x14]\n" - "fmax v16.4s, v25.4s, v22.4s\n" - "ldr q25, [x23, x14]\n" + "ldr q25, [x27, x15]\n" + "fmax v17.4s, v27.4s, v23.4s\n" + "ldr q27, [x26, x15]\n" + "fmax v16.4s, v24.4s, v22.4s\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "subs x20, x20, #0x1\n" "fmax v19.4s, v21.4s, v19.4s\n" - "ldr q24, [x26, x14]\n" - "fmax v18.4s, v21.4s, v18.4s\n" - "ldr q23, [x22, x14]\n" - "fmax v17.4s, v20.4s, v17.4s\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q22, [x21, x15]\n" + "fmax v18.4s, v18.4s, v21.4s\n" + "fmax v17.4s, v17.4s, v20.4s\n" + "add x15, x15, #0x10\n" "fmax v16.4s, v20.4s, v16.4s\n" - "str q19, [x12, x13]\n" - "str q18, [x11, x13]\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" + "str q19, [x14, x12]\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" "bgt 1b\n" "2:" // Vector: Tail "fmax v21.4s, v30.4s, v29.4s\n" "fmax v20.4s, v29.4s, v28.4s\n" - "fmax v19.4s, v27.4s, v26.4s\n" + "fmax v16.4s, v27.4s, v26.4s\n" "fmax v18.4s, v25.4s, v24.4s\n" - "fmax v17.4s, v23.4s, v27.4s\n" - "fmax v16.4s, v25.4s, v22.4s\n" - "fmax v19.4s, v21.4s, v19.4s\n" - "str q19, [x12, x13]\n" - "fmax v18.4s, v21.4s, v18.4s\n" - "fmax v17.4s, v20.4s, v17.4s\n" - "str q18, [x11, x13]\n" - "fmax v16.4s, v20.4s, v16.4s\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" - "cbz x15, 4f\n" + "fmax v17.4s, v27.4s, v23.4s\n" + "fmax v19.4s, v24.4s, v22.4s\n" + "fmax v16.4s, v21.4s, v16.4s\n" + "fmax v18.4s, v18.4s, v21.4s\n" + "str q16, [x14, x12]\n" + "fmax v17.4s, v17.4s, v20.4s\n" + "fmax v16.4s, v20.4s, v19.4s\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" + "cbz x16, 4f\n" "3:" // Oddments - "ldr s30, [x27, x14]\n" - "subs x15, x15, #0x1\n" - "ldr s29, [x24, x14]\n" - "fmax v21.4s, v30.4s, v29.4s\n" - "ldr s28, [x21, x14]\n" - "ldr s27, [x25, x14]\n" - "fmax v20.4s, v29.4s, v28.4s\n" - "ldr s26, [x28, x14]\n" - "ldr s25, [x23, x14]\n" - "fmax v19.4s, v27.4s, v26.4s\n" - "ldr s24, [x26, x14]\n" - "ldr s23, [x22, x14]\n" - "fmax v19.4s, v21.4s, v19.4s\n" - "ldr s22, [x20, x14]\n" - "add x14, x14, #0x4\n" - "fmax v18.4s, v25.4s, v24.4s\n" - "str s19, [x12, x13]\n" - "fmax v17.4s, v23.4s, v27.4s\n" - "fmax v16.4s, v25.4s, v22.4s\n" - "fmax v18.4s, v21.4s, v18.4s\n" - "str s18, [x11, x13]\n" - "fmax v17.4s, v20.4s, v17.4s\n" - "fmax v16.4s, v20.4s, v16.4s\n" - "str s17, [x10, x13]\n" - "str s16, [x9, x13]\n" - "add x13, x13, #0x4\n" + "ldr s16, [x28, x15]\n" + "ldr s17, [x25, x15]\n" + "fmax v23.4s, v16.4s, v17.4s\n" + "subs x16, x16, #0x1\n" + "ldr s16, [x22, x15]\n" + "ldr s22, [x26, x15]\n" + "fmax v21.4s, v17.4s, v16.4s\n" + "ldr s16, [x9, x15]\n" + "ldr s17, [x27, x15]\n" + "fmax v16.4s, v22.4s, v16.4s\n" + "fmax v20.4s, v23.4s, v16.4s\n" + "ldr s19, [x24, x15]\n" + "ldr s16, [x23, x15]\n" + "fmax v18.4s, v17.4s, v19.4s\n" + "fmax v17.4s, v22.4s, v16.4s\n" + "ldr s16, [x21, x15]\n" + "fmax v16.4s, v19.4s, v16.4s\n" + "add x15, x15, #0x4\n" + "fmax v18.4s, v18.4s, v23.4s\n" + "fmax v17.4s, v17.4s, v21.4s\n" + "fmax v16.4s, v21.4s, v16.4s\n" + "str s20, [x14, x12]\n" + "str s18, [x13, x12]\n" + "str s17, [x11, x12]\n" + "str s16, [x10, x12]\n" + "add x12, x12, #0x4\n" "bgt 3b\n" "4:" // End - : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst.hpp index b20ffc20cf..7577b31d7d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_fp32_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); -struct a64_fp32_nhwc_max_generic_depthfirst +struct a64_fp32_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = a64_fp32_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<float, float>; a64_fp32_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_fp32_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp index e0acb7ac02..f4706635dc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #if defined(__aarch64__) @@ -39,256 +40,254 @@ void a64_fp32_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x10\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "mov w20, #0xff800000\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "dup v8.4s, w20\n" "dup v7.4s, w20\n" - "mov x19, %x[inptrs]\n" "dup v6.4s, w20\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "dup v5.4s, w20\n" - "dup v4.4s, w20\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "fmax v23.4s, v3.4s, v2.4s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fmax v19.4s, v1.4s, v0.4s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fmax v22.4s, v31.4s, v30.4s\n" - "ldr q3, [x23, x28]\n" - "fmax v18.4s, v29.4s, v28.4s\n" - "fmax v21.4s, v27.4s, v21.4s\n" - "ldr q2, [x22, x28]\n" - "fmax v17.4s, v26.4s, v17.4s\n" - "ldr q1, [x21, x28]\n" - "fmax v20.4s, v25.4s, v20.4s\n" - "ldr q0, [x20, x28]\n" - "fmax v16.4s, v24.4s, v16.4s\n" - "ldr q31, [x23, x27]\n" + "fmax v23.4s, v4.4s, v3.4s\n" + "fmax v19.4s, v28.4s, v22.4s\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fmax v22.4s, v2.4s, v1.4s\n" + "ldr q2, [x21, x26]\n" + "fmax v18.4s, v27.4s, v21.4s\n" + "ldr q1, [x20, x26]\n" + "fmax v21.4s, v0.4s, v31.4s\n" + "ldr q0, [x21, x24]\n" + "fmax v17.4s, v26.4s, v20.4s\n" + "ldr q31, [x20, x24]\n" + "fmax v20.4s, v30.4s, v29.4s\n" + "ldr q30, [x21, x23]\n" + "fmax v16.4s, v25.4s, v24.4s\n" + "ldr q29, [x20, x23]\n" "fmax v19.4s, v23.4s, v19.4s\n" - "ldr q30, [x22, x27]\n" "fmax v18.4s, v22.4s, v18.4s\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "fmax v17.4s, v21.4s, v17.4s\n" - "ldr q28, [x20, x27]\n" "fmax v16.4s, v20.4s, v16.4s\n" - "ldr q27, [x23, x26]\n" - "fmax v7.4s, v7.4s, v19.4s\n" - "ldr q21, [x22, x26]\n" - "fmax v6.4s, v6.4s, v18.4s\n" - "ldr q26, [x21, x26]\n" - "fmax v5.4s, v5.4s, v17.4s\n" - "ldr q17, [x20, x26]\n" - "fmax v4.4s, v4.4s, v16.4s\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "fmax v8.4s, v8.4s, v19.4s\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "fmax v7.4s, v7.4s, v18.4s\n" + "fmax v6.4s, v6.4s, v17.4s\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "fmax v5.4s, v5.4s, v16.4s\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "fmax v23.4s, v3.4s, v2.4s\n" - "fmax v19.4s, v1.4s, v0.4s\n" - "fmax v22.4s, v31.4s, v30.4s\n" - "fmax v18.4s, v29.4s, v28.4s\n" - "fmax v21.4s, v27.4s, v21.4s\n" - "fmax v17.4s, v26.4s, v17.4s\n" - "fmax v20.4s, v25.4s, v20.4s\n" - "fmax v16.4s, v24.4s, v16.4s\n" + "fmax v23.4s, v4.4s, v3.4s\n" + "fmax v19.4s, v28.4s, v22.4s\n" + "fmax v22.4s, v2.4s, v1.4s\n" + "fmax v18.4s, v27.4s, v21.4s\n" + "fmax v21.4s, v0.4s, v31.4s\n" + "fmax v17.4s, v26.4s, v20.4s\n" + "fmax v20.4s, v30.4s, v29.4s\n" + "fmax v16.4s, v25.4s, v24.4s\n" "fmax v19.4s, v23.4s, v19.4s\n" "fmax v18.4s, v22.4s, v18.4s\n" "fmax v17.4s, v21.4s, v17.4s\n" "fmax v16.4s, v20.4s, v16.4s\n" - "fmax v7.4s, v7.4s, v19.4s\n" - "fmax v6.4s, v6.4s, v18.4s\n" - "fmax v5.4s, v5.4s, v17.4s\n" - "fmax v4.4s, v4.4s, v16.4s\n" + "fmax v8.4s, v8.4s, v19.4s\n" + "fmax v7.4s, v7.4s, v18.4s\n" + "fmax v6.4s, v6.4s, v17.4s\n" + "fmax v5.4s, v5.4s, v16.4s\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fmax v7.4s, v7.4s, v3.4s\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "fmax v6.4s, v6.4s, v31.4s\n" - "ldr q25, [x23, x25]\n" - "fmax v5.4s, v5.4s, v27.4s\n" - "fmax v4.4s, v4.4s, v25.4s\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fmax v8.4s, v8.4s, v16.4s\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "fmax v7.4s, v7.4s, v17.4s\n" + "fmax v6.4s, v6.4s, v16.4s\n" + "ldr q16, [x20, x23]\n" + "fmax v5.4s, v5.4s, v16.4s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" - "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" - "str q4, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" + "add x27, x27, #0x40\n" + "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 25f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x4\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "mov w19, #0xff800000\n" - "dup v7.4s, w19\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "mov w20, #0xff800000\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "dup v8.4s, w20\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fmax v23.4s, v3.4s, v2.4s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fmax v19.4s, v1.4s, v0.4s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fmax v19.4s, v23.4s, v19.4s\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "fmax v7.4s, v7.4s, v19.4s\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "fmax v17.4s, v4.4s, v3.4s\n" + "fmax v16.4s, v28.4s, v22.4s\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "fmax v16.4s, v17.4s, v16.4s\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "fmax v8.4s, v8.4s, v16.4s\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fmax v23.4s, v3.4s, v2.4s\n" - "fmax v19.4s, v1.4s, v0.4s\n" - "fmax v19.4s, v23.4s, v19.4s\n" - "fmax v7.4s, v7.4s, v19.4s\n" + "fmax v17.4s, v4.4s, v3.4s\n" + "fmax v16.4s, v28.4s, v22.4s\n" + "fmax v16.4s, v17.4s, v16.4s\n" + "fmax v8.4s, v8.4s, v16.4s\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "fmax v7.4s, v7.4s, v3.4s\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "fmax v8.4s, v8.4s, v16.4s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" "sub %x[n_channels], %x[n_channels], #0x4\n" "cmp %x[n_channels], #0x4\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 25f\n" "14:" // Oddments - "add %x[outptr], %x[outptr], x28\n" - "mov w19, #0xff800000\n" - "dup v7.4s, w19\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 18f\n" + "mov w20, #0xff800000\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "dup v8.4s, w20\n" + "add %x[outptr], %x[outptr], x27\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 18f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #1, 16f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #0, 17f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "b 17f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 17f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "17:" // Oddments: 4 inputs loop: Load: Bit 1: End - "fmax v23.4s, v3.4s, v2.4s\n" - "subs x24, x24, #0x1\n" - "fmax v19.4s, v1.4s, v0.4s\n" - "fmax v19.4s, v23.4s, v19.4s\n" - "fmax v7.4s, v7.4s, v19.4s\n" + "fmax v17.4s, v4.4s, v3.4s\n" + "fmax v16.4s, v28.4s, v22.4s\n" + "subs x25, x25, #0x1\n" + "fmax v16.4s, v17.4s, v16.4s\n" + "fmax v8.4s, v8.4s, v16.4s\n" "bgt 15b\n" "18:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 22f\n" "19:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #1, 20f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #0, 21f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "b 21f\n" "20:" // Oddments: Single input loop: Load: Bit 1: Unset "tbz %x[n_channels], #0, 21f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "21:" // Oddments: Single input loop: Load: Bit 1: End - "fmax v7.4s, v7.4s, v3.4s\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "fmax v8.4s, v8.4s, v4.4s\n" "bgt 19b\n" "22:" // Oddments: Single input loop: End "tbz %x[n_channels], #1, 23f\n" - "st1 { v7.d }[0], [%x[outptr]], #0x8\n" + "st1 { v8.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #0, 24f\n" - "st1 { v7.s }[2], [%x[outptr]], #0x4\n" + "st1 { v8.s }[2], [%x[outptr]], #0x4\n" "b 24f\n" "23:" // Oddments: Store: Bit 1: Unset "tbz %x[n_channels], #0, 24f\n" - "st1 { v7.s }[0], [%x[outptr]], #0x4\n" + "st1 { v8.s }[0], [%x[outptr]], #0x4\n" "24:" // Oddments: Store: Bit 1: End - "25:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst.hpp index df66ab7a2c..de94ec0ec3 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_s8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); -struct a64_s8_nhwc_avg_generic_depthfirst +struct a64_s8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = a64_s8_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; a64_s8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_s8_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp index 405ae66755..5d082102b3 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> @@ -83,27 +84,28 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( shift_value--; f_rescale_value *= 2.0f; } - int64_t large_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); - if (large_rescale_value == (1ll << 31)) + + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - large_rescale_value >>= 1; + long_rescale_value >>= 1; } - rescale_value = static_cast<int32_t>(large_rescale_value); + rescale_value = static_cast<int32_t>(long_rescale_value); } __asm__ __volatile__( - "mov x26, #0x0\n" - "mov x25, #0x10\n" // cntb _, ALL, #1 - "mov x24, #0x20\n" // cntb _, ALL, #2 - "mov x23, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x25, #0x20\n" // cntb _, ALL, #2 + "mov x24, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v14.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -118,43 +120,43 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "movi v2.4s, #0x0\n" "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ldr q29, [x21, x25]\n" - "ldr q28, [x20, x25]\n" - "ldr q27, [x21, x24]\n" - "ldr q26, [x20, x24]\n" - "ldr q25, [x21, x23]\n" - "ldr q24, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "saddl v21.8h, v29.8b, v28.8b\n" - "subs x22, x22, #0x1\n" "saddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q30, [x20, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "saddl v19.8h, v27.8b, v26.8b\n" - "ldr q29, [x21, x25]\n" "saddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q28, [x20, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" "saddl v17.8h, v25.8b, v24.8b\n" - "ldr q27, [x21, x24]\n" "saddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q26, [x20, x24]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" - "ldr q25, [x21, x23]\n" "saddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q24, [x20, x23]\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" + "add x22, x22, #0x10\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" "saddw v9.4s, v9.4s, v20.4h\n" @@ -194,23 +196,23 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "saddw v1.4s, v1.4s, v16.4h\n" "saddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "sxtl v23.8h, v31.8b\n" - "ldr q29, [x21, x25]\n" - "sxtl2 v22.8h, v31.16b\n" - "ldr q27, [x21, x24]\n" - "ldr q25, [x21, x23]\n" - "sxtl v21.8h, v29.8b\n" - "sxtl2 v20.8h, v29.16b\n" - "sxtl v19.8h, v27.8b\n" - "sxtl2 v18.8h, v27.16b\n" - "sxtl v17.8h, v25.8b\n" - "sxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v23.8h, v16.8b\n" + "sxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "sxtl v21.8h, v16.8b\n" + "sxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "sxtl v19.8h, v17.8b\n" + "sxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -229,195 +231,195 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "saddw2 v0.4s, v0.4s, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "movi v19.4s, #0x7f\n" - "ld1r { v18.4s }, [%x[rescale_ptr]]\n" + "ld1r { v17.4s }, [%x[rescale_ptr]]\n" + "ld1r { v16.4s }, [%x[shift_ptr]]\n" + "sqdmulh v15.4s, v15.4s, v17.4s\n" + "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqdmulh v13.4s, v13.4s, v17.4s\n" + "sqdmulh v12.4s, v12.4s, v17.4s\n" "sub %x[n_channels], %x[n_channels], #0x40\n" - "sqdmulh v15.4s, v15.4s, v18.4s\n" - "ld1r { v17.4s }, [%x[shift_ptr]]\n" - "not v16.16b, v19.16b\n" - "sqdmulh v14.4s, v14.4s, v18.4s\n" "cmp %x[n_channels], #0x40\n" - "sqdmulh v13.4s, v13.4s, v18.4s\n" - "sqdmulh v12.4s, v12.4s, v18.4s\n" - "sqdmulh v11.4s, v11.4s, v18.4s\n" - "sqdmulh v10.4s, v10.4s, v18.4s\n" - "sqdmulh v9.4s, v9.4s, v18.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" - "srshl v11.4s, v11.4s, v17.4s\n" - "srshl v10.4s, v10.4s, v17.4s\n" - "srshl v9.4s, v9.4s, v17.4s\n" - "sqdmulh v8.4s, v8.4s, v18.4s\n" - "sqdmulh v7.4s, v7.4s, v18.4s\n" - "sqdmulh v6.4s, v6.4s, v18.4s\n" - "sqdmulh v5.4s, v5.4s, v18.4s\n" - "srshl v8.4s, v8.4s, v17.4s\n" - "srshl v7.4s, v7.4s, v17.4s\n" - "srshl v6.4s, v6.4s, v17.4s\n" - "srshl v5.4s, v5.4s, v17.4s\n" - "sqdmulh v4.4s, v4.4s, v18.4s\n" - "sqdmulh v3.4s, v3.4s, v18.4s\n" - "sqdmulh v2.4s, v2.4s, v18.4s\n" - "sqdmulh v1.4s, v1.4s, v18.4s\n" - "srshl v4.4s, v4.4s, v17.4s\n" - "srshl v3.4s, v3.4s, v17.4s\n" - "srshl v2.4s, v2.4s, v17.4s\n" - "srshl v1.4s, v1.4s, v17.4s\n" - "sqdmulh v0.4s, v0.4s, v18.4s\n" + "sqdmulh v11.4s, v11.4s, v17.4s\n" + "sqdmulh v10.4s, v10.4s, v17.4s\n" + "sqdmulh v9.4s, v9.4s, v17.4s\n" + "sqdmulh v8.4s, v8.4s, v17.4s\n" + "sqdmulh v7.4s, v7.4s, v17.4s\n" + "sqdmulh v6.4s, v6.4s, v17.4s\n" + "sqdmulh v5.4s, v5.4s, v17.4s\n" + "sqdmulh v4.4s, v4.4s, v17.4s\n" + "sqdmulh v3.4s, v3.4s, v17.4s\n" + "sqdmulh v2.4s, v2.4s, v17.4s\n" + "sqdmulh v1.4s, v1.4s, v17.4s\n" + "sqdmulh v0.4s, v0.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "srshl v11.4s, v11.4s, v16.4s\n" + "srshl v10.4s, v10.4s, v16.4s\n" + "srshl v9.4s, v9.4s, v16.4s\n" + "srshl v8.4s, v8.4s, v16.4s\n" + "srshl v7.4s, v7.4s, v16.4s\n" + "srshl v6.4s, v6.4s, v16.4s\n" + "srshl v5.4s, v5.4s, v16.4s\n" + "srshl v4.4s, v4.4s, v16.4s\n" + "srshl v3.4s, v3.4s, v16.4s\n" + "srshl v2.4s, v2.4s, v16.4s\n" + "srshl v1.4s, v1.4s, v16.4s\n" + "srshl v0.4s, v0.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" - "srshl v0.4s, v0.4s, v17.4s\n" - "smin v15.4s, v15.4s, v19.4s\n" - "smin v14.4s, v14.4s, v19.4s\n" - "smin v13.4s, v13.4s, v19.4s\n" "smax v12.4s, v12.4s, v16.4s\n" "smax v11.4s, v11.4s, v16.4s\n" "smax v10.4s, v10.4s, v16.4s\n" - "smin v12.4s, v12.4s, v19.4s\n" - "smin v11.4s, v11.4s, v19.4s\n" - "smin v10.4s, v10.4s, v19.4s\n" "smax v9.4s, v9.4s, v16.4s\n" "smax v8.4s, v8.4s, v16.4s\n" "smax v7.4s, v7.4s, v16.4s\n" - "smin v9.4s, v9.4s, v19.4s\n" - "smin v8.4s, v8.4s, v19.4s\n" - "smin v7.4s, v7.4s, v19.4s\n" "smax v6.4s, v6.4s, v16.4s\n" "smax v5.4s, v5.4s, v16.4s\n" "smax v4.4s, v4.4s, v16.4s\n" - "smin v6.4s, v6.4s, v19.4s\n" - "smin v5.4s, v5.4s, v19.4s\n" - "smin v4.4s, v4.4s, v19.4s\n" "smax v3.4s, v3.4s, v16.4s\n" "smax v2.4s, v2.4s, v16.4s\n" "smax v1.4s, v1.4s, v16.4s\n" - "smin v3.4s, v3.4s, v19.4s\n" - "smin v2.4s, v2.4s, v19.4s\n" - "smin v1.4s, v1.4s, v19.4s\n" "smax v0.4s, v0.4s, v16.4s\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "smin v11.4s, v11.4s, v17.4s\n" + "smin v10.4s, v10.4s, v17.4s\n" + "smin v9.4s, v9.4s, v17.4s\n" + "smin v8.4s, v8.4s, v17.4s\n" + "smin v7.4s, v7.4s, v17.4s\n" + "smin v6.4s, v6.4s, v17.4s\n" + "smin v5.4s, v5.4s, v17.4s\n" + "smin v4.4s, v4.4s, v17.4s\n" + "smin v3.4s, v3.4s, v17.4s\n" + "smin v2.4s, v2.4s, v17.4s\n" + "smin v1.4s, v1.4s, v17.4s\n" + "smin v0.4s, v0.4s, v17.4s\n" "uzp1 v23.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "smin v0.4s, v0.4s, v19.4s\n" "uzp1 v22.16b, v11.16b, v10.16b\n" - "uzp1 v21.16b, v9.16b, v8.16b\n" - "uzp1 v20.16b, v7.16b, v6.16b\n" + "uzp1 v18.16b, v9.16b, v8.16b\n" + "uzp1 v21.16b, v7.16b, v6.16b\n" "uzp1 v17.16b, v5.16b, v4.16b\n" - "uzp1 v19.16b, v3.16b, v2.16b\n" - "uzp1 v18.16b, v1.16b, v0.16b\n" + "uzp1 v20.16b, v3.16b, v2.16b\n" + "uzp1 v19.16b, v1.16b, v0.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "uzp1 v16.16b, v22.16b, v21.16b\n" + "uzp1 v18.16b, v22.16b, v18.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" + "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v20.16b, v19.16b\n" + "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" - "uzp1 v17.16b, v20.16b, v17.16b\n" - "str q16, [%x[outptr], x25]\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" + "str q17, [%x[outptr], x25]\n" "add x25, x25, #0x40\n" - "str q17, [%x[outptr], x24]\n" + "str q16, [%x[outptr], x24]\n" "add x24, x24, #0x40\n" - "str q16, [%x[outptr], x23]\n" - "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v14.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "saddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "subs x22, x22, #0x1\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q30, [x20, x26]\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "movi v19.4s, #0x7f\n" - "ld1r { v18.4s }, [%x[rescale_ptr]]\n" + "ld1r { v17.4s }, [%x[rescale_ptr]]\n" + "ld1r { v16.4s }, [%x[shift_ptr]]\n" + "sqdmulh v15.4s, v15.4s, v17.4s\n" + "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqdmulh v13.4s, v13.4s, v17.4s\n" + "sqdmulh v12.4s, v12.4s, v17.4s\n" "sub %x[n_channels], %x[n_channels], #0x10\n" - "sqdmulh v15.4s, v15.4s, v18.4s\n" - "ld1r { v17.4s }, [%x[shift_ptr]]\n" - "not v16.16b, v19.16b\n" - "sqdmulh v14.4s, v14.4s, v18.4s\n" "cmp %x[n_channels], #0x10\n" - "sqdmulh v13.4s, v13.4s, v18.4s\n" - "sqdmulh v12.4s, v12.4s, v18.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v15.4s, v15.4s, v19.4s\n" - "smin v14.4s, v14.4s, v19.4s\n" - "smin v13.4s, v13.4s, v19.4s\n" - "smin v12.4s, v12.4s, v19.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "add x26, x26, #0x10\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments + "lsr x23, %x[n_valid_cells], #0x1\n" + "add %x[outptr], %x[outptr], x27\n" "movi v15.4s, #0x0\n" - "add %x[outptr], %x[outptr], x26\n" "movi v14.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v13.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "movi v12.4s, #0x0\n" - "cbz x22, 24f\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" - "add x21, x21, x26\n" - "add x20, x20, x26\n" "tbz %x[n_channels], #3, 19f\n" "ldr d31, [x21], #0x8\n" "ldr d30, [x20], #0x8\n" @@ -478,21 +480,21 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "ldr b31, [x21], #0x1\n" "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "saddl v23.8h, v31.8b, v30.8b\n" - "subs x22, x22, #0x1\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldr x21, [x19], #0x8\n" - "add x21, x21, x26\n" "tbz %x[n_channels], #3, 29f\n" "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" @@ -538,38 +540,38 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 33f\n" "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "sxtl v23.8h, v31.8b\n" - "subs x20, x20, #0x1\n" - "sxtl2 v22.8h, v31.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "sxtl v17.8h, v31.8b\n" + "sxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "movi v19.4s, #0x7f\n" - "ld1r { v18.4s }, [%x[rescale_ptr]]\n" - "not v16.16b, v19.16b\n" - "sqdmulh v15.4s, v15.4s, v18.4s\n" - "ld1r { v17.4s }, [%x[shift_ptr]]\n" - "sqdmulh v14.4s, v14.4s, v18.4s\n" - "sqdmulh v13.4s, v13.4s, v18.4s\n" - "sqdmulh v12.4s, v12.4s, v18.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" + "ld1r { v17.4s }, [%x[rescale_ptr]]\n" + "ld1r { v16.4s }, [%x[shift_ptr]]\n" + "sqdmulh v15.4s, v15.4s, v17.4s\n" + "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqdmulh v13.4s, v13.4s, v17.4s\n" + "sqdmulh v12.4s, v12.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v15.4s, v15.4s, v19.4s\n" - "smin v14.4s, v14.4s, v19.4s\n" - "smin v13.4s, v13.4s, v19.4s\n" - "smin v12.4s, v12.4s, v19.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -615,12 +617,10 @@ void a64_s8_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 42f\n" "st1 { v16.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 7829ecc0e9..f8f1134866 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,33 +24,28 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { void a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const int8_t *const *const, int8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst +struct a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<int8_t, int8_t> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(unsigned int, const int8_t *const *const, int8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + using Parent = DepthfirstStrategy<int8_t, int8_t>; - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } + a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 298db96861..7e62ac1afc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -61,114 +63,115 @@ void a64_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x15, [%x[args], %[offsetof_n_channels]]\n" - "mov x14, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "cmp x15, #0x10\n" - "ldp x12, x11, [x20, #0x0]\n" - "ldp x10, x9, [x20, #0x10]\n" - "ldp x28, x27, [x19, #0x0]\n" - "ldp x26, x25, [x19, #0x10]\n" - "ldp x24, x23, [x19, #0x20]\n" - "ldp x22, x21, [x19, #0x30]\n" - "ldr x20, [x19, #0x40]\n" + "ldr x16, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "cmp x16, #0x10\n" + "mov x15, #0x0\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x14, x13, [x21, #0x0]\n" + "mov x12, #0x0\n" + "ldp x11, x10, [x21, #0x10]\n" + "ldp x9, x28, [x20, #0x0]\n" + "ldp x27, x26, [x20, #0x10]\n" + "ldp x25, x24, [x20, #0x20]\n" + "ldp x23, x22, [x20, #0x30]\n" + "ldr x21, [x20, #0x40]\n" "blt 3f\n" - "ldr q30, [x27, x14]\n" - "lsr x19, x15, #0x4\n" - "ldr q29, [x24, x14]\n" - "sub x15, x15, x19, LSL #4\n" - "ldr q28, [x21, x14]\n" - "subs x19, x19, #0x1\n" - "ldr q27, [x25, x14]\n" - "ldr q26, [x28, x14]\n" - "ldr q25, [x23, x14]\n" - "ldr q24, [x26, x14]\n" - "ldr q23, [x22, x14]\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q30, [x28, x15]\n" + "ldr q29, [x25, x15]\n" + "lsr x20, x16, #0x4\n" + "sub x16, x16, x20, LSL #4\n" + "ldr q28, [x22, x15]\n" + "ldr q27, [x26, x15]\n" + "subs x20, x20, #0x1\n" + "ldr q26, [x9, x15]\n" + "ldr q25, [x27, x15]\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "ldr q22, [x21, x15]\n" + "add x15, x15, #0x10\n" "beq 2f\n" "1:" // Vector: Loop "smax v21.16b, v30.16b, v29.16b\n" - "ldr q30, [x27, x14]\n" - "subs x19, x19, #0x1\n" + "ldr q30, [x28, x15]\n" "smax v20.16b, v29.16b, v28.16b\n" - "ldr q29, [x24, x14]\n" + "ldr q29, [x25, x15]\n" + "ldr q28, [x22, x15]\n" "smax v19.16b, v27.16b, v26.16b\n" - "ldr q28, [x21, x14]\n" + "ldr q26, [x9, x15]\n" "smax v18.16b, v25.16b, v24.16b\n" - "ldr q26, [x28, x14]\n" - "smax v17.16b, v23.16b, v27.16b\n" - "ldr q27, [x25, x14]\n" - "smax v16.16b, v25.16b, v22.16b\n" - "ldr q25, [x23, x14]\n" + "ldr q25, [x27, x15]\n" + "smax v17.16b, v27.16b, v23.16b\n" + "ldr q27, [x26, x15]\n" + "smax v16.16b, v24.16b, v22.16b\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "subs x20, x20, #0x1\n" "smax v19.16b, v21.16b, v19.16b\n" - "ldr q24, [x26, x14]\n" - "smax v18.16b, v21.16b, v18.16b\n" - "ldr q23, [x22, x14]\n" - "smax v17.16b, v20.16b, v17.16b\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q22, [x21, x15]\n" + "smax v18.16b, v18.16b, v21.16b\n" + "smax v17.16b, v17.16b, v20.16b\n" + "add x15, x15, #0x10\n" "smax v16.16b, v20.16b, v16.16b\n" - "str q19, [x12, x13]\n" - "str q18, [x11, x13]\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" + "str q19, [x14, x12]\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" "bgt 1b\n" "2:" // Vector: Tail "smax v21.16b, v30.16b, v29.16b\n" "smax v20.16b, v29.16b, v28.16b\n" - "smax v19.16b, v27.16b, v26.16b\n" + "smax v16.16b, v27.16b, v26.16b\n" "smax v18.16b, v25.16b, v24.16b\n" - "smax v17.16b, v23.16b, v27.16b\n" - "smax v16.16b, v25.16b, v22.16b\n" - "smax v19.16b, v21.16b, v19.16b\n" - "str q19, [x12, x13]\n" - "smax v18.16b, v21.16b, v18.16b\n" - "smax v17.16b, v20.16b, v17.16b\n" - "str q18, [x11, x13]\n" - "smax v16.16b, v20.16b, v16.16b\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" - "cbz x15, 4f\n" + "smax v17.16b, v27.16b, v23.16b\n" + "smax v19.16b, v24.16b, v22.16b\n" + "smax v16.16b, v21.16b, v16.16b\n" + "smax v18.16b, v18.16b, v21.16b\n" + "str q16, [x14, x12]\n" + "smax v17.16b, v17.16b, v20.16b\n" + "smax v16.16b, v20.16b, v19.16b\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" + "cbz x16, 4f\n" "3:" // Oddments - "ldr b30, [x27, x14]\n" - "subs x15, x15, #0x1\n" - "ldr b29, [x24, x14]\n" - "smax v21.16b, v30.16b, v29.16b\n" - "ldr b28, [x21, x14]\n" - "ldr b27, [x25, x14]\n" - "smax v20.16b, v29.16b, v28.16b\n" - "ldr b26, [x28, x14]\n" - "ldr b25, [x23, x14]\n" - "smax v19.16b, v27.16b, v26.16b\n" - "ldr b24, [x26, x14]\n" - "ldr b23, [x22, x14]\n" - "smax v19.16b, v21.16b, v19.16b\n" - "ldr b22, [x20, x14]\n" - "add x14, x14, #0x1\n" - "smax v18.16b, v25.16b, v24.16b\n" - "str b19, [x12, x13]\n" - "smax v17.16b, v23.16b, v27.16b\n" - "smax v16.16b, v25.16b, v22.16b\n" - "smax v18.16b, v21.16b, v18.16b\n" - "str b18, [x11, x13]\n" - "smax v17.16b, v20.16b, v17.16b\n" - "smax v16.16b, v20.16b, v16.16b\n" - "str b17, [x10, x13]\n" - "str b16, [x9, x13]\n" - "add x13, x13, #0x1\n" + "ldr b16, [x28, x15]\n" + "ldr b17, [x25, x15]\n" + "smax v23.16b, v16.16b, v17.16b\n" + "subs x16, x16, #0x1\n" + "ldr b16, [x22, x15]\n" + "ldr b22, [x26, x15]\n" + "smax v21.16b, v17.16b, v16.16b\n" + "ldr b16, [x9, x15]\n" + "ldr b17, [x27, x15]\n" + "smax v16.16b, v22.16b, v16.16b\n" + "smax v20.16b, v23.16b, v16.16b\n" + "ldr b19, [x24, x15]\n" + "ldr b16, [x23, x15]\n" + "smax v18.16b, v17.16b, v19.16b\n" + "smax v17.16b, v22.16b, v16.16b\n" + "ldr b16, [x21, x15]\n" + "smax v16.16b, v19.16b, v16.16b\n" + "add x15, x15, #0x1\n" + "smax v18.16b, v18.16b, v23.16b\n" + "smax v17.16b, v17.16b, v21.16b\n" + "smax v16.16b, v21.16b, v16.16b\n" + "str b20, [x14, x12]\n" + "str b18, [x13, x12]\n" + "str b17, [x11, x12]\n" + "str b16, [x10, x12]\n" + "add x12, x12, #0x1\n" "bgt 3b\n" "4:" // End - : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst.hpp index 6c4cd1467f..ba6d52f570 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_s8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); -struct a64_s8_nhwc_max_generic_depthfirst +struct a64_s8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = a64_s8_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; a64_s8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_s8_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp index 5e4c84d23e..411fd11460 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #if defined(__aarch64__) @@ -39,397 +40,395 @@ void a64_s8_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x80\n" "movi v7.16b, #0x80\n" - "mov x19, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x80\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "movi v5.16b, #0x80\n" - "movi v4.16b, #0x80\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "smax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "smax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "smax v22.16b, v31.16b, v30.16b\n" - "ldr q3, [x23, x28]\n" - "smax v18.16b, v29.16b, v28.16b\n" - "smax v21.16b, v27.16b, v21.16b\n" - "ldr q2, [x22, x28]\n" - "smax v17.16b, v26.16b, v17.16b\n" - "ldr q1, [x21, x28]\n" - "smax v20.16b, v25.16b, v20.16b\n" - "ldr q0, [x20, x28]\n" - "smax v16.16b, v24.16b, v16.16b\n" - "ldr q31, [x23, x27]\n" + "smax v23.16b, v4.16b, v3.16b\n" + "smax v19.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "smax v22.16b, v2.16b, v1.16b\n" + "ldr q2, [x21, x26]\n" + "smax v18.16b, v27.16b, v21.16b\n" + "ldr q1, [x20, x26]\n" + "smax v21.16b, v0.16b, v31.16b\n" + "ldr q0, [x21, x24]\n" + "smax v17.16b, v26.16b, v20.16b\n" + "ldr q31, [x20, x24]\n" + "smax v20.16b, v30.16b, v29.16b\n" + "ldr q30, [x21, x23]\n" + "smax v16.16b, v25.16b, v24.16b\n" + "ldr q29, [x20, x23]\n" "smax v19.16b, v23.16b, v19.16b\n" - "ldr q30, [x22, x27]\n" "smax v18.16b, v22.16b, v18.16b\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "smax v17.16b, v21.16b, v17.16b\n" - "ldr q28, [x20, x27]\n" "smax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x23, x26]\n" - "smax v7.16b, v7.16b, v19.16b\n" - "ldr q21, [x22, x26]\n" - "smax v6.16b, v6.16b, v18.16b\n" - "ldr q26, [x21, x26]\n" - "smax v5.16b, v5.16b, v17.16b\n" - "ldr q17, [x20, x26]\n" - "smax v4.16b, v4.16b, v16.16b\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "smax v8.16b, v8.16b, v19.16b\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "smax v7.16b, v7.16b, v18.16b\n" + "smax v6.16b, v6.16b, v17.16b\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "smax v5.16b, v5.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "smax v23.16b, v3.16b, v2.16b\n" - "smax v19.16b, v1.16b, v0.16b\n" - "smax v22.16b, v31.16b, v30.16b\n" - "smax v18.16b, v29.16b, v28.16b\n" - "smax v21.16b, v27.16b, v21.16b\n" - "smax v17.16b, v26.16b, v17.16b\n" - "smax v20.16b, v25.16b, v20.16b\n" - "smax v16.16b, v24.16b, v16.16b\n" + "smax v23.16b, v4.16b, v3.16b\n" + "smax v19.16b, v28.16b, v22.16b\n" + "smax v22.16b, v2.16b, v1.16b\n" + "smax v18.16b, v27.16b, v21.16b\n" + "smax v21.16b, v0.16b, v31.16b\n" + "smax v17.16b, v26.16b, v20.16b\n" + "smax v20.16b, v30.16b, v29.16b\n" + "smax v16.16b, v25.16b, v24.16b\n" "smax v19.16b, v23.16b, v19.16b\n" "smax v18.16b, v22.16b, v18.16b\n" "smax v17.16b, v21.16b, v17.16b\n" "smax v16.16b, v20.16b, v16.16b\n" - "smax v7.16b, v7.16b, v19.16b\n" - "smax v6.16b, v6.16b, v18.16b\n" - "smax v5.16b, v5.16b, v17.16b\n" - "smax v4.16b, v4.16b, v16.16b\n" + "smax v8.16b, v8.16b, v19.16b\n" + "smax v7.16b, v7.16b, v18.16b\n" + "smax v6.16b, v6.16b, v17.16b\n" + "smax v5.16b, v5.16b, v16.16b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "smax v7.16b, v7.16b, v3.16b\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "smax v6.16b, v6.16b, v31.16b\n" - "ldr q25, [x23, x25]\n" - "smax v5.16b, v5.16b, v27.16b\n" - "smax v4.16b, v4.16b, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "smax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "smax v7.16b, v7.16b, v17.16b\n" + "smax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "smax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" - "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" - "str q4, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" "sub %x[n_channels], %x[n_channels], #0x40\n" "cmp %x[n_channels], #0x40\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" + "add x27, x27, #0x40\n" + "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "movi v7.16b, #0x80\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x80\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "smax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "smax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "smax v19.16b, v23.16b, v19.16b\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "smax v7.16b, v7.16b, v19.16b\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "smax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "smax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "smax v23.16b, v3.16b, v2.16b\n" - "smax v19.16b, v1.16b, v0.16b\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v7.16b, v7.16b, v19.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "smax v7.16b, v7.16b, v3.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments - "movi v7.16b, #0x80\n" - "add %x[outptr], %x[outptr], x28\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 24f\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "add %x[outptr], %x[outptr], x27\n" + "movi v8.16b, #0x80\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v2.h }[6], [x22], #0x2\n" - "ld1 { v1.h }[6], [x21], #0x2\n" - "ld1 { v0.h }[6], [x20], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v2.b }[14], [x22], #0x1\n" - "ld1 { v1.b }[14], [x21], #0x1\n" - "ld1 { v0.b }[14], [x20], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v2.b }[12], [x22], #0x1\n" - "ld1 { v1.b }[12], [x21], #0x1\n" - "ld1 { v0.b }[12], [x20], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v2.h }[4], [x22], #0x2\n" - "ld1 { v1.h }[4], [x21], #0x2\n" - "ld1 { v0.h }[4], [x20], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v2.b }[10], [x22], #0x1\n" - "ld1 { v1.b }[10], [x21], #0x1\n" - "ld1 { v0.b }[10], [x20], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v2.b }[8], [x22], #0x1\n" - "ld1 { v1.b }[8], [x21], #0x1\n" - "ld1 { v0.b }[8], [x20], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v2.h }[2], [x22], #0x2\n" - "ld1 { v1.h }[2], [x21], #0x2\n" - "ld1 { v0.h }[2], [x20], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v2.b }[6], [x22], #0x1\n" - "ld1 { v1.b }[6], [x21], #0x1\n" - "ld1 { v0.b }[6], [x20], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v2.b }[4], [x22], #0x1\n" - "ld1 { v1.b }[4], [x21], #0x1\n" - "ld1 { v0.b }[4], [x20], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h3, [x23], #0x2\n" - "ldr h2, [x22], #0x2\n" - "ldr h1, [x21], #0x2\n" - "ldr h0, [x20], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v2.b }[2], [x22], #0x1\n" - "ld1 { v1.b }[2], [x21], #0x1\n" - "ld1 { v0.b }[2], [x20], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b3, [x23], #0x1\n" - "ldr b2, [x22], #0x1\n" - "ldr b1, [x21], #0x1\n" - "ldr b0, [x20], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "smax v23.16b, v3.16b, v2.16b\n" - "subs x24, x24, #0x1\n" - "smax v19.16b, v1.16b, v0.16b\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v7.16b, v7.16b, v19.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "subs x25, x25, #0x1\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h3, [x23], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b3, [x23], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "smax v7.16b, v7.16b, v3.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "smax v8.16b, v8.16b, v4.16b\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End "tbz %x[n_channels], #3, 38f\n" - "st1 { v7.d }[0], [%x[outptr]], #0x8\n" + "st1 { v8.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" - "st1 { v7.s }[2], [%x[outptr]], #0x4\n" + "st1 { v8.s }[2], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #1, 35f\n" - "st1 { v7.h }[6], [%x[outptr]], #0x2\n" + "st1 { v8.h }[6], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[14], [%x[outptr]], #0x1\n" + "st1 { v8.b }[14], [%x[outptr]], #0x1\n" "b 42f\n" "35:" // Oddments: Store: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[12], [%x[outptr]], #0x1\n" + "st1 { v8.b }[12], [%x[outptr]], #0x1\n" "b 42f\n" "36:" // Oddments: Store: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 37f\n" - "st1 { v7.h }[4], [%x[outptr]], #0x2\n" + "st1 { v8.h }[4], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[10], [%x[outptr]], #0x1\n" + "st1 { v8.b }[10], [%x[outptr]], #0x1\n" "b 42f\n" "37:" // Oddments: Store: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[8], [%x[outptr]], #0x1\n" + "st1 { v8.b }[8], [%x[outptr]], #0x1\n" "b 42f\n" "38:" // Oddments: Store: Bit 3: Unset "tbz %x[n_channels], #2, 40f\n" - "st1 { v7.s }[0], [%x[outptr]], #0x4\n" + "st1 { v8.s }[0], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #1, 39f\n" - "st1 { v7.h }[2], [%x[outptr]], #0x2\n" + "st1 { v8.h }[2], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[6], [%x[outptr]], #0x1\n" + "st1 { v8.b }[6], [%x[outptr]], #0x1\n" "b 42f\n" "39:" // Oddments: Store: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[4], [%x[outptr]], #0x1\n" + "st1 { v8.b }[4], [%x[outptr]], #0x1\n" "b 42f\n" "40:" // Oddments: Store: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 41f\n" - "st1 { v7.h }[0], [%x[outptr]], #0x2\n" + "st1 { v8.h }[0], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[2], [%x[outptr]], #0x1\n" + "st1 { v8.b }[2], [%x[outptr]], #0x1\n" "b 42f\n" "41:" // Oddments: Store: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[0], [%x[outptr]], #0x1\n" + "st1 { v8.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst.hpp index a50e99a009..d5d7313a90 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_s8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); -struct a64_s8q_nhwc_avg_generic_depthfirst +struct a64_s8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = a64_s8q_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; a64_s8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_s8q_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp index f288a4119c..019f402911 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,7 @@ #include "pooling.hpp" #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> @@ -86,12 +87,13 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } // Combine together the rescale value for the requantization and the scaling @@ -112,17 +114,17 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( ); __asm__ __volatile__( - "mov x26, #0x0\n" - "mov x25, #0x10\n" // cntb _, ALL, #1 - "mov x24, #0x20\n" // cntb _, ALL, #2 - "mov x23, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x25, #0x20\n" // cntb _, ALL, #2 + "mov x24, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v14.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -137,43 +139,43 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v2.4s, #0x0\n" "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ldr q29, [x21, x25]\n" - "ldr q28, [x20, x25]\n" - "ldr q27, [x21, x24]\n" - "ldr q26, [x20, x24]\n" - "ldr q25, [x21, x23]\n" - "ldr q24, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "saddl v21.8h, v29.8b, v28.8b\n" - "subs x22, x22, #0x1\n" "saddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q30, [x20, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "saddl v19.8h, v27.8b, v26.8b\n" - "ldr q29, [x21, x25]\n" "saddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q28, [x20, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" "saddl v17.8h, v25.8b, v24.8b\n" - "ldr q27, [x21, x24]\n" "saddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q26, [x20, x24]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v23.4h\n" - "ldr q25, [x21, x23]\n" "saddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q24, [x20, x23]\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" + "add x22, x22, #0x10\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" "saddw v9.4s, v9.4s, v20.4h\n" @@ -213,23 +215,23 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw v1.4s, v1.4s, v16.4h\n" "saddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "sxtl v23.8h, v31.8b\n" - "ldr q29, [x21, x25]\n" - "sxtl2 v22.8h, v31.16b\n" - "ldr q27, [x21, x24]\n" - "ldr q25, [x21, x23]\n" - "sxtl v21.8h, v29.8b\n" - "sxtl2 v20.8h, v29.16b\n" - "sxtl v19.8h, v27.8b\n" - "sxtl2 v18.8h, v27.16b\n" - "sxtl v17.8h, v25.8b\n" - "sxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v23.8h, v16.8b\n" + "sxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "sxtl v21.8h, v16.8b\n" + "sxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "sxtl v19.8h, v17.8b\n" + "sxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" "saddw v15.4s, v15.4s, v23.4h\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -248,217 +250,217 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw2 v0.4s, v0.4s, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "movi v20.4s, #0x7f\n" - "ld1r { v19.4s }, [%x[combined_rescale_value]]\n" - "sub %x[n_channels], %x[n_channels], #0x40\n" "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" "srshl v15.4s, v15.4s, v18.4s\n" - "ld1r { v17.4s }, [%x[right_shift]]\n" - "not v16.16b, v20.16b\n" "srshl v14.4s, v14.4s, v18.4s\n" - "cmp %x[n_channels], #0x40\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" "srshl v13.4s, v13.4s, v18.4s\n" "srshl v12.4s, v12.4s, v18.4s\n" + "sub %x[n_channels], %x[n_channels], #0x40\n" "srshl v11.4s, v11.4s, v18.4s\n" - "sqrdmulh v15.4s, v15.4s, v19.4s\n" - "sqrdmulh v14.4s, v14.4s, v19.4s\n" - "sqrdmulh v13.4s, v13.4s, v19.4s\n" - "sqrdmulh v12.4s, v12.4s, v19.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" - "sqrdmulh v11.4s, v11.4s, v19.4s\n" "srshl v10.4s, v10.4s, v18.4s\n" + "cmp %x[n_channels], #0x40\n" "srshl v9.4s, v9.4s, v18.4s\n" "srshl v8.4s, v8.4s, v18.4s\n" - "srshl v11.4s, v11.4s, v17.4s\n" - "sqrdmulh v10.4s, v10.4s, v19.4s\n" - "sqrdmulh v9.4s, v9.4s, v19.4s\n" - "sqrdmulh v8.4s, v8.4s, v19.4s\n" "srshl v7.4s, v7.4s, v18.4s\n" - "srshl v10.4s, v10.4s, v17.4s\n" - "srshl v9.4s, v9.4s, v17.4s\n" - "srshl v8.4s, v8.4s, v17.4s\n" - "sqrdmulh v7.4s, v7.4s, v19.4s\n" "srshl v6.4s, v6.4s, v18.4s\n" "srshl v5.4s, v5.4s, v18.4s\n" "srshl v4.4s, v4.4s, v18.4s\n" - "srshl v7.4s, v7.4s, v17.4s\n" - "sqrdmulh v6.4s, v6.4s, v19.4s\n" - "sqrdmulh v5.4s, v5.4s, v19.4s\n" - "sqrdmulh v4.4s, v4.4s, v19.4s\n" "srshl v3.4s, v3.4s, v18.4s\n" - "srshl v6.4s, v6.4s, v17.4s\n" - "srshl v5.4s, v5.4s, v17.4s\n" - "srshl v4.4s, v4.4s, v17.4s\n" - "sqrdmulh v3.4s, v3.4s, v19.4s\n" "srshl v2.4s, v2.4s, v18.4s\n" "srshl v1.4s, v1.4s, v18.4s\n" "srshl v0.4s, v0.4s, v18.4s\n" - "srshl v3.4s, v3.4s, v17.4s\n" - "sqrdmulh v2.4s, v2.4s, v19.4s\n" - "sqrdmulh v1.4s, v1.4s, v19.4s\n" - "sqrdmulh v0.4s, v0.4s, v19.4s\n" + "sqrdmulh v15.4s, v15.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v13.4s, v13.4s, v17.4s\n" + "sqrdmulh v12.4s, v12.4s, v17.4s\n" + "sqrdmulh v11.4s, v11.4s, v17.4s\n" + "sqrdmulh v10.4s, v10.4s, v17.4s\n" + "sqrdmulh v9.4s, v9.4s, v17.4s\n" + "sqrdmulh v8.4s, v8.4s, v17.4s\n" + "sqrdmulh v7.4s, v7.4s, v17.4s\n" + "sqrdmulh v6.4s, v6.4s, v17.4s\n" + "sqrdmulh v5.4s, v5.4s, v17.4s\n" + "sqrdmulh v4.4s, v4.4s, v17.4s\n" + "sqrdmulh v3.4s, v3.4s, v17.4s\n" + "sqrdmulh v2.4s, v2.4s, v17.4s\n" + "sqrdmulh v1.4s, v1.4s, v17.4s\n" + "sqrdmulh v0.4s, v0.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "srshl v11.4s, v11.4s, v16.4s\n" + "srshl v10.4s, v10.4s, v16.4s\n" + "srshl v9.4s, v9.4s, v16.4s\n" + "srshl v8.4s, v8.4s, v16.4s\n" + "srshl v7.4s, v7.4s, v16.4s\n" + "srshl v6.4s, v6.4s, v16.4s\n" + "srshl v5.4s, v5.4s, v16.4s\n" + "srshl v4.4s, v4.4s, v16.4s\n" + "srshl v3.4s, v3.4s, v16.4s\n" + "srshl v2.4s, v2.4s, v16.4s\n" + "srshl v1.4s, v1.4s, v16.4s\n" + "srshl v0.4s, v0.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" - "srshl v2.4s, v2.4s, v17.4s\n" - "srshl v1.4s, v1.4s, v17.4s\n" - "srshl v0.4s, v0.4s, v17.4s\n" - "smin v15.4s, v15.4s, v20.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v14.4s, v14.4s, v20.4s\n" - "smin v13.4s, v13.4s, v20.4s\n" - "smin v12.4s, v12.4s, v20.4s\n" "smax v11.4s, v11.4s, v16.4s\n" "smax v10.4s, v10.4s, v16.4s\n" "smax v9.4s, v9.4s, v16.4s\n" - "smin v11.4s, v11.4s, v20.4s\n" - "smin v10.4s, v10.4s, v20.4s\n" - "smin v9.4s, v9.4s, v20.4s\n" "smax v8.4s, v8.4s, v16.4s\n" "smax v7.4s, v7.4s, v16.4s\n" "smax v6.4s, v6.4s, v16.4s\n" - "smin v8.4s, v8.4s, v20.4s\n" - "smin v7.4s, v7.4s, v20.4s\n" - "smin v6.4s, v6.4s, v20.4s\n" "smax v5.4s, v5.4s, v16.4s\n" "smax v4.4s, v4.4s, v16.4s\n" "smax v3.4s, v3.4s, v16.4s\n" - "smin v5.4s, v5.4s, v20.4s\n" - "smin v4.4s, v4.4s, v20.4s\n" - "smin v3.4s, v3.4s, v20.4s\n" "smax v2.4s, v2.4s, v16.4s\n" "smax v1.4s, v1.4s, v16.4s\n" "smax v0.4s, v0.4s, v16.4s\n" - "smin v2.4s, v2.4s, v20.4s\n" - "smin v1.4s, v1.4s, v20.4s\n" - "smin v0.4s, v0.4s, v20.4s\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "smin v11.4s, v11.4s, v17.4s\n" + "smin v10.4s, v10.4s, v17.4s\n" + "smin v9.4s, v9.4s, v17.4s\n" + "smin v8.4s, v8.4s, v17.4s\n" + "smin v7.4s, v7.4s, v17.4s\n" + "smin v6.4s, v6.4s, v17.4s\n" + "smin v5.4s, v5.4s, v17.4s\n" + "smin v4.4s, v4.4s, v17.4s\n" + "smin v3.4s, v3.4s, v17.4s\n" + "smin v2.4s, v2.4s, v17.4s\n" + "smin v1.4s, v1.4s, v17.4s\n" + "smin v0.4s, v0.4s, v17.4s\n" "uzp1 v23.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v22.16b, v11.16b, v10.16b\n" - "uzp1 v21.16b, v9.16b, v8.16b\n" - "uzp1 v20.16b, v7.16b, v6.16b\n" + "uzp1 v18.16b, v9.16b, v8.16b\n" + "uzp1 v21.16b, v7.16b, v6.16b\n" "uzp1 v17.16b, v5.16b, v4.16b\n" - "uzp1 v19.16b, v3.16b, v2.16b\n" - "uzp1 v18.16b, v1.16b, v0.16b\n" + "uzp1 v20.16b, v3.16b, v2.16b\n" + "uzp1 v19.16b, v1.16b, v0.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "uzp1 v16.16b, v22.16b, v21.16b\n" + "uzp1 v18.16b, v22.16b, v18.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" + "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v20.16b, v19.16b\n" + "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" - "uzp1 v17.16b, v20.16b, v17.16b\n" - "str q16, [%x[outptr], x25]\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" + "str q17, [%x[outptr], x25]\n" "add x25, x25, #0x40\n" - "str q17, [%x[outptr], x24]\n" + "str q16, [%x[outptr], x24]\n" "add x24, x24, #0x40\n" - "str q16, [%x[outptr], x23]\n" - "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v14.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "saddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "subs x22, x22, #0x1\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q30, [x20, x26]\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "saddl v23.8h, v31.8b, v30.8b\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "sxtl v23.8h, v31.8b\n" - "sxtl2 v22.8h, v31.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "sxtl v17.8h, v16.8b\n" + "sxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "movi v20.4s, #0x7f\n" - "ld1r { v19.4s }, [%x[combined_rescale_value]]\n" - "sub %x[n_channels], %x[n_channels], #0x10\n" "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" "srshl v15.4s, v15.4s, v18.4s\n" - "ld1r { v17.4s }, [%x[right_shift]]\n" - "not v16.16b, v20.16b\n" "srshl v14.4s, v14.4s, v18.4s\n" - "cmp %x[n_channels], #0x10\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" "srshl v13.4s, v13.4s, v18.4s\n" "srshl v12.4s, v12.4s, v18.4s\n" - "sqrdmulh v15.4s, v15.4s, v19.4s\n" - "sqrdmulh v14.4s, v14.4s, v19.4s\n" - "sqrdmulh v13.4s, v13.4s, v19.4s\n" - "sqrdmulh v12.4s, v12.4s, v19.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" + "sub %x[n_channels], %x[n_channels], #0x10\n" + "sqrdmulh v15.4s, v15.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" + "cmp %x[n_channels], #0x10\n" + "sqrdmulh v13.4s, v13.4s, v17.4s\n" + "sqrdmulh v12.4s, v12.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v15.4s, v15.4s, v20.4s\n" - "smin v14.4s, v14.4s, v20.4s\n" - "smin v13.4s, v13.4s, v20.4s\n" - "smin v12.4s, v12.4s, v20.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "add x26, x26, #0x10\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments + "lsr x23, %x[n_valid_cells], #0x1\n" + "add %x[outptr], %x[outptr], x27\n" "movi v15.4s, #0x0\n" - "add %x[outptr], %x[outptr], x26\n" "movi v14.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v13.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "movi v12.4s, #0x0\n" - "cbz x22, 24f\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" - "add x21, x21, x26\n" - "add x20, x20, x26\n" "tbz %x[n_channels], #3, 19f\n" "ldr d31, [x21], #0x8\n" "ldr d30, [x20], #0x8\n" @@ -519,21 +521,21 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ldr b31, [x21], #0x1\n" "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "saddl v23.8h, v31.8b, v30.8b\n" - "subs x22, x22, #0x1\n" - "saddl2 v22.8h, v31.16b, v30.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "saddl v17.8h, v31.8b, v30.8b\n" + "saddl2 v16.8h, v31.16b, v30.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldr x21, [x19], #0x8\n" - "add x21, x21, x26\n" "tbz %x[n_channels], #3, 29f\n" "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" @@ -579,43 +581,43 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 33f\n" "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "sxtl v23.8h, v31.8b\n" - "subs x20, x20, #0x1\n" - "sxtl2 v22.8h, v31.16b\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" - "saddw v13.4s, v13.4s, v22.4h\n" - "saddw2 v12.4s, v12.4s, v22.8h\n" + "sxtl v17.8h, v31.8b\n" + "sxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v17.4h\n" + "saddw2 v14.4s, v14.4s, v17.8h\n" + "saddw v13.4s, v13.4s, v16.4h\n" + "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "movi v20.4s, #0x7f\n" - "ld1r { v19.4s }, [%x[combined_rescale_value]]\n" - "not v16.16b, v20.16b\n" "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" "srshl v15.4s, v15.4s, v18.4s\n" - "ld1r { v17.4s }, [%x[right_shift]]\n" "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" "srshl v13.4s, v13.4s, v18.4s\n" "srshl v12.4s, v12.4s, v18.4s\n" - "sqrdmulh v15.4s, v15.4s, v19.4s\n" - "sqrdmulh v14.4s, v14.4s, v19.4s\n" - "sqrdmulh v13.4s, v13.4s, v19.4s\n" - "sqrdmulh v12.4s, v12.4s, v19.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" + "sqrdmulh v15.4s, v15.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v13.4s, v13.4s, v17.4s\n" + "sqrdmulh v12.4s, v12.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v15.4s, v15.4s, v20.4s\n" - "smin v14.4s, v14.4s, v20.4s\n" - "smin v13.4s, v13.4s, v20.4s\n" - "smin v12.4s, v12.4s, v20.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -661,12 +663,10 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 42f\n" "st1 { v16.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_valid_cells] "r" (n_valid_cells), [right_shift] "r" (&right_shift) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst.hpp index ea7f7f89fe..68e7a98d0a 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_s8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); -struct a64_s8q_nhwc_max_generic_depthfirst +struct a64_s8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = a64_s8q_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; a64_s8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_s8q_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp index a077121991..f7b8dc761c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,8 @@ */ #include "pooling.hpp" -#include <cstddef> #include <cstdint> +#include <cstddef> #if defined(__aarch64__) @@ -42,88 +42,88 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x80\n" - "mov x19, %x[inptrs]\n" "movi v7.16b, #0x80\n" - "lsr x24, %x[n_valid_cells], #0x2\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x80\n" "movi v5.16b, #0x80\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "smax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "smax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "smax v22.16b, v31.16b, v30.16b\n" - "ldr q3, [x23, x28]\n" - "smax v18.16b, v29.16b, v28.16b\n" - "smax v21.16b, v27.16b, v21.16b\n" - "ldr q2, [x22, x28]\n" - "smax v17.16b, v26.16b, v17.16b\n" - "ldr q1, [x21, x28]\n" - "smax v20.16b, v25.16b, v20.16b\n" - "ldr q0, [x20, x28]\n" - "smax v16.16b, v24.16b, v16.16b\n" - "ldr q31, [x23, x27]\n" + "smax v23.16b, v4.16b, v3.16b\n" + "smax v19.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "smax v22.16b, v2.16b, v1.16b\n" + "ldr q2, [x21, x26]\n" + "smax v18.16b, v27.16b, v21.16b\n" + "ldr q1, [x20, x26]\n" + "smax v21.16b, v0.16b, v31.16b\n" + "ldr q0, [x21, x24]\n" + "smax v17.16b, v26.16b, v20.16b\n" + "ldr q31, [x20, x24]\n" + "smax v20.16b, v30.16b, v29.16b\n" + "ldr q30, [x21, x23]\n" + "smax v16.16b, v25.16b, v24.16b\n" + "ldr q29, [x20, x23]\n" "smax v19.16b, v23.16b, v19.16b\n" - "ldr q30, [x22, x27]\n" "smax v18.16b, v22.16b, v18.16b\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "smax v17.16b, v21.16b, v17.16b\n" - "ldr q28, [x20, x27]\n" "smax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x23, x26]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" "smax v8.16b, v8.16b, v19.16b\n" - "ldr q21, [x22, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" "smax v7.16b, v7.16b, v18.16b\n" - "ldr q26, [x21, x26]\n" "smax v6.16b, v6.16b, v17.16b\n" - "ldr q17, [x20, x26]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "smax v5.16b, v5.16b, v16.16b\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "smax v23.16b, v3.16b, v2.16b\n" - "smax v19.16b, v1.16b, v0.16b\n" - "smax v22.16b, v31.16b, v30.16b\n" - "smax v18.16b, v29.16b, v28.16b\n" - "smax v21.16b, v27.16b, v21.16b\n" - "smax v17.16b, v26.16b, v17.16b\n" - "smax v20.16b, v25.16b, v20.16b\n" - "smax v16.16b, v24.16b, v16.16b\n" + "smax v23.16b, v4.16b, v3.16b\n" + "smax v19.16b, v28.16b, v22.16b\n" + "smax v22.16b, v2.16b, v1.16b\n" + "smax v18.16b, v27.16b, v21.16b\n" + "smax v21.16b, v0.16b, v31.16b\n" + "smax v17.16b, v26.16b, v20.16b\n" + "smax v20.16b, v30.16b, v29.16b\n" + "smax v16.16b, v25.16b, v24.16b\n" "smax v19.16b, v23.16b, v19.16b\n" "smax v18.16b, v22.16b, v18.16b\n" "smax v17.16b, v21.16b, v17.16b\n" @@ -133,453 +133,453 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( "smax v6.16b, v6.16b, v17.16b\n" "smax v5.16b, v5.16b, v16.16b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "smax v8.16b, v8.16b, v3.16b\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "smax v7.16b, v7.16b, v31.16b\n" - "ldr q25, [x23, x25]\n" - "smax v6.16b, v6.16b, v27.16b\n" - "smax v5.16b, v5.16b, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "smax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "smax v7.16b, v7.16b, v17.16b\n" + "smax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "smax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End "sxtl v23.8h, v8.8b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v4.4s }, [x19]\n" "sxtl2 v22.8h, v8.16b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1r { v4.4s }, [x20]\n" "sxtl v21.8h, v7.8b\n" - "ld1r { v3.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "sxtl2 v20.8h, v7.16b\n" - "ld1r { v2.4s }, [x19]\n" - "sub %x[n_channels], %x[n_channels], #0x40\n" - "sxtl v19.8h, v6.8b\n" - "cmp %x[n_channels], #0x40\n" - "sxtl2 v18.8h, v6.16b\n" + "sxtl2 v18.8h, v7.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1r { v3.4s }, [x20]\n" + "sxtl v20.8h, v6.8b\n" + "sxtl2 v19.8h, v6.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1r { v2.4s }, [x20]\n" "sxtl v17.8h, v5.8b\n" "sxtl2 v16.8h, v5.16b\n" + "sub %x[n_channels], %x[n_channels], #0x40\n" + "cmp %x[n_channels], #0x40\n" "sxtl v1.4s, v23.4h\n" "sxtl2 v23.4s, v23.8h\n" "sxtl v0.4s, v22.4h\n" "sxtl2 v31.4s, v22.8h\n" "sxtl v30.4s, v21.4h\n" "sxtl2 v22.4s, v21.8h\n" - "sxtl v29.4s, v20.4h\n" + "sxtl v29.4s, v18.4h\n" + "sxtl2 v18.4s, v18.8h\n" + "sxtl v28.4s, v20.4h\n" "sxtl2 v21.4s, v20.8h\n" - "sxtl v28.4s, v19.4h\n" - "sxtl2 v20.4s, v19.8h\n" - "sxtl v27.4s, v18.4h\n" - "sxtl2 v26.4s, v18.8h\n" + "sxtl v27.4s, v19.4h\n" + "sxtl2 v26.4s, v19.8h\n" "sxtl v25.4s, v17.4h\n" - "sxtl2 v19.4s, v17.8h\n" + "sxtl2 v20.4s, v17.8h\n" "sxtl v24.4s, v16.4h\n" - "sxtl2 v18.4s, v16.8h\n" - "srshl v1.4s, v1.4s, v3.4s\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v0.4s, v0.4s, v3.4s\n" - "srshl v31.4s, v31.4s, v3.4s\n" - "sqrdmulh v1.4s, v1.4s, v4.4s\n" - "sqrdmulh v23.4s, v23.4s, v4.4s\n" - "sqrdmulh v0.4s, v0.4s, v4.4s\n" - "sqrdmulh v31.4s, v31.4s, v4.4s\n" + "sxtl2 v19.4s, v16.8h\n" + "srshl v1.4s, v1.4s, v4.4s\n" + "srshl v23.4s, v23.4s, v4.4s\n" + "srshl v0.4s, v0.4s, v4.4s\n" + "srshl v31.4s, v31.4s, v4.4s\n" + "srshl v30.4s, v30.4s, v4.4s\n" + "srshl v22.4s, v22.4s, v4.4s\n" + "srshl v29.4s, v29.4s, v4.4s\n" + "srshl v18.4s, v18.4s, v4.4s\n" + "srshl v28.4s, v28.4s, v4.4s\n" + "srshl v21.4s, v21.4s, v4.4s\n" + "srshl v27.4s, v27.4s, v4.4s\n" + "srshl v26.4s, v26.4s, v4.4s\n" + "srshl v25.4s, v25.4s, v4.4s\n" + "srshl v20.4s, v20.4s, v4.4s\n" + "srshl v24.4s, v24.4s, v4.4s\n" + "srshl v19.4s, v19.4s, v4.4s\n" + "sqrdmulh v1.4s, v1.4s, v3.4s\n" + "sqrdmulh v23.4s, v23.4s, v3.4s\n" + "sqrdmulh v0.4s, v0.4s, v3.4s\n" + "sqrdmulh v31.4s, v31.4s, v3.4s\n" + "sqrdmulh v30.4s, v30.4s, v3.4s\n" + "sqrdmulh v22.4s, v22.4s, v3.4s\n" + "sqrdmulh v29.4s, v29.4s, v3.4s\n" + "sqrdmulh v18.4s, v18.4s, v3.4s\n" + "sqrdmulh v28.4s, v28.4s, v3.4s\n" + "sqrdmulh v21.4s, v21.4s, v3.4s\n" + "sqrdmulh v27.4s, v27.4s, v3.4s\n" + "sqrdmulh v26.4s, v26.4s, v3.4s\n" + "sqrdmulh v25.4s, v25.4s, v3.4s\n" + "sqrdmulh v20.4s, v20.4s, v3.4s\n" + "sqrdmulh v24.4s, v24.4s, v3.4s\n" + "sqrdmulh v19.4s, v19.4s, v3.4s\n" + "movi v17.4s, #0x7f\n" "srshl v1.4s, v1.4s, v2.4s\n" "srshl v23.4s, v23.4s, v2.4s\n" "srshl v0.4s, v0.4s, v2.4s\n" "srshl v31.4s, v31.4s, v2.4s\n" - "srshl v30.4s, v30.4s, v3.4s\n" - "srshl v22.4s, v22.4s, v3.4s\n" - "srshl v29.4s, v29.4s, v3.4s\n" - "srshl v21.4s, v21.4s, v3.4s\n" - "sqrdmulh v30.4s, v30.4s, v4.4s\n" - "sqrdmulh v22.4s, v22.4s, v4.4s\n" - "sqrdmulh v29.4s, v29.4s, v4.4s\n" - "sqrdmulh v21.4s, v21.4s, v4.4s\n" "srshl v30.4s, v30.4s, v2.4s\n" "srshl v22.4s, v22.4s, v2.4s\n" "srshl v29.4s, v29.4s, v2.4s\n" - "srshl v21.4s, v21.4s, v2.4s\n" - "srshl v28.4s, v28.4s, v3.4s\n" - "srshl v20.4s, v20.4s, v3.4s\n" - "srshl v27.4s, v27.4s, v3.4s\n" - "srshl v26.4s, v26.4s, v3.4s\n" - "sqrdmulh v28.4s, v28.4s, v4.4s\n" - "sqrdmulh v20.4s, v20.4s, v4.4s\n" - "sqrdmulh v27.4s, v27.4s, v4.4s\n" - "sqrdmulh v26.4s, v26.4s, v4.4s\n" + "srshl v18.4s, v18.4s, v2.4s\n" "srshl v28.4s, v28.4s, v2.4s\n" - "srshl v20.4s, v20.4s, v2.4s\n" + "srshl v21.4s, v21.4s, v2.4s\n" "srshl v27.4s, v27.4s, v2.4s\n" "srshl v26.4s, v26.4s, v2.4s\n" - "srshl v25.4s, v25.4s, v3.4s\n" - "srshl v19.4s, v19.4s, v3.4s\n" - "srshl v24.4s, v24.4s, v3.4s\n" - "srshl v18.4s, v18.4s, v3.4s\n" - "sqrdmulh v25.4s, v25.4s, v4.4s\n" - "sqrdmulh v19.4s, v19.4s, v4.4s\n" - "sqrdmulh v24.4s, v24.4s, v4.4s\n" - "sqrdmulh v18.4s, v18.4s, v4.4s\n" "srshl v25.4s, v25.4s, v2.4s\n" - "srshl v19.4s, v19.4s, v2.4s\n" + "srshl v20.4s, v20.4s, v2.4s\n" "srshl v24.4s, v24.4s, v2.4s\n" - "srshl v18.4s, v18.4s, v2.4s\n" - "movi v17.4s, #0x7f\n" + "srshl v19.4s, v19.4s, v2.4s\n" "not v16.16b, v17.16b\n" "smax v1.4s, v1.4s, v16.4s\n" "smax v23.4s, v23.4s, v16.4s\n" "smax v0.4s, v0.4s, v16.4s\n" "smax v31.4s, v31.4s, v16.4s\n" + "smax v30.4s, v30.4s, v16.4s\n" + "smax v22.4s, v22.4s, v16.4s\n" + "smax v29.4s, v29.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "smax v28.4s, v28.4s, v16.4s\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v27.4s, v27.4s, v16.4s\n" + "smax v26.4s, v26.4s, v16.4s\n" + "smax v25.4s, v25.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v24.4s, v24.4s, v16.4s\n" + "smax v19.4s, v19.4s, v16.4s\n" "smin v1.4s, v1.4s, v17.4s\n" "smin v23.4s, v23.4s, v17.4s\n" "smin v0.4s, v0.4s, v17.4s\n" "smin v31.4s, v31.4s, v17.4s\n" - "smax v30.4s, v30.4s, v16.4s\n" - "smax v22.4s, v22.4s, v16.4s\n" - "smax v29.4s, v29.4s, v16.4s\n" "smin v30.4s, v30.4s, v17.4s\n" "smin v22.4s, v22.4s, v17.4s\n" "smin v29.4s, v29.4s, v17.4s\n" - "smax v21.4s, v21.4s, v16.4s\n" - "smax v28.4s, v28.4s, v16.4s\n" - "smax v20.4s, v20.4s, v16.4s\n" - "smin v21.4s, v21.4s, v17.4s\n" + "smin v18.4s, v18.4s, v17.4s\n" "smin v28.4s, v28.4s, v17.4s\n" - "smin v20.4s, v20.4s, v17.4s\n" - "smax v27.4s, v27.4s, v16.4s\n" - "smax v26.4s, v26.4s, v16.4s\n" - "smax v25.4s, v25.4s, v16.4s\n" + "smin v21.4s, v21.4s, v17.4s\n" "smin v27.4s, v27.4s, v17.4s\n" "smin v26.4s, v26.4s, v17.4s\n" "smin v25.4s, v25.4s, v17.4s\n" - "smax v19.4s, v19.4s, v16.4s\n" - "smax v24.4s, v24.4s, v16.4s\n" - "smax v18.4s, v18.4s, v16.4s\n" - "smin v19.4s, v19.4s, v17.4s\n" + "smin v20.4s, v20.4s, v17.4s\n" "smin v24.4s, v24.4s, v17.4s\n" - "smin v18.4s, v18.4s, v17.4s\n" + "smin v19.4s, v19.4s, v17.4s\n" "uzp1 v23.16b, v1.16b, v23.16b\n" "uzp1 v16.16b, v0.16b, v31.16b\n" "uzp1 v22.16b, v30.16b, v22.16b\n" - "uzp1 v21.16b, v29.16b, v21.16b\n" - "uzp1 v20.16b, v28.16b, v20.16b\n" + "uzp1 v18.16b, v29.16b, v18.16b\n" + "uzp1 v21.16b, v28.16b, v21.16b\n" "uzp1 v17.16b, v27.16b, v26.16b\n" - "uzp1 v19.16b, v25.16b, v19.16b\n" - "uzp1 v18.16b, v24.16b, v18.16b\n" + "uzp1 v20.16b, v25.16b, v20.16b\n" + "uzp1 v19.16b, v24.16b, v19.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x28]\n" - "uzp1 v16.16b, v22.16b, v21.16b\n" - "add x28, x28, #0x40\n" - "uzp1 v17.16b, v20.16b, v17.16b\n" + "uzp1 v18.16b, v22.16b, v18.16b\n" "str q16, [%x[outptr], x27]\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" "add x27, x27, #0x40\n" - "str q17, [%x[outptr], x26]\n" + "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v20.16b, v19.16b\n" + "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" - "str q16, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" + "str q17, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q16, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x80\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "smax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "smax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "smax v19.16b, v23.16b, v19.16b\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "smax v8.16b, v8.16b, v19.16b\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "smax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "smax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "smax v23.16b, v3.16b, v2.16b\n" - "smax v19.16b, v1.16b, v0.16b\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v8.16b, v8.16b, v19.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "smax v8.16b, v8.16b, v3.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "sxtl v23.8h, v8.8b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v4.4s }, [x19]\n" - "sxtl2 v22.8h, v8.16b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "movi v17.4s, #0x7f\n" - "ld1r { v3.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "sxtl v1.4s, v23.4h\n" - "ld1r { v2.4s }, [x19]\n" - "not v16.16b, v17.16b\n" - "sxtl2 v23.4s, v23.8h\n" + "sxtl v17.8h, v8.8b\n" + "sxtl2 v16.8h, v8.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1r { v22.4s }, [x20]\n" + "sxtl v21.4s, v17.4h\n" + "sxtl2 v20.4s, v17.8h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1r { v17.4s }, [x20]\n" + "sxtl v19.4s, v16.4h\n" + "sxtl2 v18.4s, v16.8h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v22.4s\n" + "srshl v20.4s, v20.4s, v22.4s\n" "sub %x[n_channels], %x[n_channels], #0x10\n" - "sxtl v0.4s, v22.4h\n" "cmp %x[n_channels], #0x10\n" - "sxtl2 v31.4s, v22.8h\n" - "srshl v1.4s, v1.4s, v3.4s\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v0.4s, v0.4s, v3.4s\n" - "srshl v31.4s, v31.4s, v3.4s\n" - "sqrdmulh v1.4s, v1.4s, v4.4s\n" - "sqrdmulh v23.4s, v23.4s, v4.4s\n" - "sqrdmulh v0.4s, v0.4s, v4.4s\n" - "sqrdmulh v31.4s, v31.4s, v4.4s\n" - "srshl v1.4s, v1.4s, v2.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v0.4s, v0.4s, v2.4s\n" - "srshl v31.4s, v31.4s, v2.4s\n" - "smax v1.4s, v1.4s, v16.4s\n" - "smax v23.4s, v23.4s, v16.4s\n" - "smax v0.4s, v0.4s, v16.4s\n" - "smax v31.4s, v31.4s, v16.4s\n" - "smin v1.4s, v1.4s, v17.4s\n" - "smin v23.4s, v23.4s, v17.4s\n" - "smin v0.4s, v0.4s, v17.4s\n" - "smin v31.4s, v31.4s, v17.4s\n" - "uzp1 v23.16b, v1.16b, v23.16b\n" - "uzp1 v16.16b, v0.16b, v31.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" + "srshl v19.4s, v19.4s, v22.4s\n" + "srshl v18.4s, v18.4s, v22.4s\n" + "sqrdmulh v21.4s, v21.4s, v17.4s\n" + "sqrdmulh v20.4s, v20.4s, v17.4s\n" + "sqrdmulh v19.4s, v19.4s, v17.4s\n" + "sqrdmulh v18.4s, v18.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v21.4s, v21.4s, v16.4s\n" + "srshl v20.4s, v20.4s, v16.4s\n" + "srshl v19.4s, v19.4s, v16.4s\n" + "srshl v18.4s, v18.4s, v16.4s\n" + "not v16.16b, v17.16b\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v19.4s, v19.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "smin v21.4s, v21.4s, v17.4s\n" + "smin v20.4s, v20.4s, v17.4s\n" + "smin v19.4s, v19.4s, v17.4s\n" + "smin v18.4s, v18.4s, v17.4s\n" + "uzp1 v17.16b, v21.16b, v20.16b\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments + "lsr x25, %x[n_valid_cells], #0x2\n" + "add %x[outptr], %x[outptr], x27\n" "movi v8.16b, #0x80\n" - "add %x[outptr], %x[outptr], x28\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 24f\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v2.h }[6], [x22], #0x2\n" - "ld1 { v1.h }[6], [x21], #0x2\n" - "ld1 { v0.h }[6], [x20], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v2.b }[14], [x22], #0x1\n" - "ld1 { v1.b }[14], [x21], #0x1\n" - "ld1 { v0.b }[14], [x20], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v2.b }[12], [x22], #0x1\n" - "ld1 { v1.b }[12], [x21], #0x1\n" - "ld1 { v0.b }[12], [x20], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v2.h }[4], [x22], #0x2\n" - "ld1 { v1.h }[4], [x21], #0x2\n" - "ld1 { v0.h }[4], [x20], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v2.b }[10], [x22], #0x1\n" - "ld1 { v1.b }[10], [x21], #0x1\n" - "ld1 { v0.b }[10], [x20], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v2.b }[8], [x22], #0x1\n" - "ld1 { v1.b }[8], [x21], #0x1\n" - "ld1 { v0.b }[8], [x20], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v2.h }[2], [x22], #0x2\n" - "ld1 { v1.h }[2], [x21], #0x2\n" - "ld1 { v0.h }[2], [x20], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v2.b }[6], [x22], #0x1\n" - "ld1 { v1.b }[6], [x21], #0x1\n" - "ld1 { v0.b }[6], [x20], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v2.b }[4], [x22], #0x1\n" - "ld1 { v1.b }[4], [x21], #0x1\n" - "ld1 { v0.b }[4], [x20], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h3, [x23], #0x2\n" - "ldr h2, [x22], #0x2\n" - "ldr h1, [x21], #0x2\n" - "ldr h0, [x20], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v2.b }[2], [x22], #0x1\n" - "ld1 { v1.b }[2], [x21], #0x1\n" - "ld1 { v0.b }[2], [x20], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b3, [x23], #0x1\n" - "ldr b2, [x22], #0x1\n" - "ldr b1, [x21], #0x1\n" - "ldr b0, [x20], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "smax v23.16b, v3.16b, v2.16b\n" - "subs x24, x24, #0x1\n" - "smax v19.16b, v1.16b, v0.16b\n" - "smax v19.16b, v23.16b, v19.16b\n" - "smax v8.16b, v8.16b, v19.16b\n" + "smax v17.16b, v4.16b, v3.16b\n" + "smax v16.16b, v28.16b, v22.16b\n" + "subs x25, x25, #0x1\n" + "smax v16.16b, v17.16b, v16.16b\n" + "smax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h3, [x23], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b3, [x23], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "smax v8.16b, v8.16b, v3.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "smax v8.16b, v8.16b, v4.16b\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "sxtl v23.8h, v8.8b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1r { v4.4s }, [x19]\n" - "sxtl2 v22.8h, v8.16b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "sxtl v17.8h, v8.8b\n" + "sxtl2 v16.8h, v8.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1r { v22.4s }, [x20]\n" + "sxtl v21.4s, v17.4h\n" + "sxtl2 v20.4s, v17.8h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1r { v17.4s }, [x20]\n" + "sxtl v19.4s, v16.4h\n" + "sxtl2 v18.4s, v16.8h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v22.4s\n" + "srshl v20.4s, v20.4s, v22.4s\n" + "srshl v19.4s, v19.4s, v22.4s\n" + "srshl v18.4s, v18.4s, v22.4s\n" + "sqrdmulh v21.4s, v21.4s, v17.4s\n" + "sqrdmulh v20.4s, v20.4s, v17.4s\n" + "sqrdmulh v19.4s, v19.4s, v17.4s\n" + "sqrdmulh v18.4s, v18.4s, v17.4s\n" "movi v17.4s, #0x7f\n" - "ld1r { v3.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "sxtl v1.4s, v23.4h\n" - "ld1r { v2.4s }, [x19]\n" + "srshl v21.4s, v21.4s, v16.4s\n" + "srshl v20.4s, v20.4s, v16.4s\n" + "srshl v19.4s, v19.4s, v16.4s\n" + "srshl v18.4s, v18.4s, v16.4s\n" "not v16.16b, v17.16b\n" - "sxtl2 v23.4s, v23.8h\n" - "sxtl v0.4s, v22.4h\n" - "sxtl2 v31.4s, v22.8h\n" - "srshl v1.4s, v1.4s, v3.4s\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v0.4s, v0.4s, v3.4s\n" - "srshl v31.4s, v31.4s, v3.4s\n" - "sqrdmulh v1.4s, v1.4s, v4.4s\n" - "sqrdmulh v23.4s, v23.4s, v4.4s\n" - "sqrdmulh v0.4s, v0.4s, v4.4s\n" - "sqrdmulh v31.4s, v31.4s, v4.4s\n" - "srshl v1.4s, v1.4s, v2.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v0.4s, v0.4s, v2.4s\n" - "srshl v31.4s, v31.4s, v2.4s\n" - "smax v1.4s, v1.4s, v16.4s\n" - "smax v23.4s, v23.4s, v16.4s\n" - "smax v0.4s, v0.4s, v16.4s\n" - "smax v31.4s, v31.4s, v16.4s\n" - "smin v1.4s, v1.4s, v17.4s\n" - "smin v23.4s, v23.4s, v17.4s\n" - "smin v0.4s, v0.4s, v17.4s\n" - "smin v31.4s, v31.4s, v17.4s\n" - "uzp1 v23.16b, v1.16b, v23.16b\n" - "uzp1 v16.16b, v0.16b, v31.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v19.4s, v19.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "smin v21.4s, v21.4s, v17.4s\n" + "smin v20.4s, v20.4s, v17.4s\n" + "smin v19.4s, v19.4s, v17.4s\n" + "smin v18.4s, v18.4s, v17.4s\n" + "uzp1 v17.16b, v21.16b, v20.16b\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -625,12 +625,10 @@ void a64_s8q_nhwc_max_generic_depthfirst_impl( "tbz %x[n_channels], #0, 42f\n" "st1 { v16.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [quant_params] "r" (&qp) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst.hpp index 230952452b..97818595e8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_u8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); -struct a64_u8_nhwc_avg_generic_depthfirst +struct a64_u8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = a64_u8_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; a64_u8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_u8_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp index 2c8a29248d..f8984c451c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> @@ -84,26 +85,27 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } __asm__ __volatile__( - "mov x26, #0x0\n" - "mov x25, #0x10\n" // cntb _, ALL, #1 - "mov x24, #0x20\n" // cntb _, ALL, #2 - "mov x23, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x25, #0x20\n" // cntb _, ALL, #2 + "mov x24, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v14.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" "movi v11.4s, #0x0\n" @@ -118,43 +120,43 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "movi v2.4s, #0x0\n" "movi v1.4s, #0x0\n" "movi v0.4s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ldr q29, [x21, x25]\n" - "ldr q28, [x20, x25]\n" - "ldr q27, [x21, x24]\n" - "ldr q26, [x20, x24]\n" - "ldr q25, [x21, x23]\n" - "ldr q24, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "uaddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "uaddl v21.8h, v29.8b, v28.8b\n" - "subs x22, x22, #0x1\n" "uaddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q30, [x20, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "uaddl v19.8h, v27.8b, v26.8b\n" - "ldr q29, [x21, x25]\n" "uaddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q28, [x20, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" "uaddl v17.8h, v25.8b, v24.8b\n" - "ldr q27, [x21, x24]\n" "uaddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q26, [x20, x24]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" + "subs x23, x23, #0x1\n" "uaddw v15.4s, v15.4s, v23.4h\n" - "ldr q25, [x21, x23]\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q24, [x20, x23]\n" "uaddw v13.4s, v13.4s, v22.4h\n" "uaddw2 v12.4s, v12.4s, v22.8h\n" + "add x22, x22, #0x10\n" "uaddw v11.4s, v11.4s, v21.4h\n" "uaddw2 v10.4s, v10.4s, v21.8h\n" "uaddw v9.4s, v9.4s, v20.4h\n" @@ -194,23 +196,23 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "uaddw v1.4s, v1.4s, v16.4h\n" "uaddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "uxtl v23.8h, v31.8b\n" - "ldr q29, [x21, x25]\n" - "uxtl2 v22.8h, v31.16b\n" - "ldr q27, [x21, x24]\n" - "ldr q25, [x21, x23]\n" - "uxtl v21.8h, v29.8b\n" - "uxtl2 v20.8h, v29.16b\n" - "uxtl v19.8h, v27.8b\n" - "uxtl2 v18.8h, v27.16b\n" - "uxtl v17.8h, v25.8b\n" - "uxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v23.8h, v16.8b\n" + "uxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "uxtl v21.8h, v16.8b\n" + "uxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "uxtl v19.8h, v17.8b\n" + "uxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" "uaddw v15.4s, v15.4s, v23.4h\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" "uaddw v13.4s, v13.4s, v22.4h\n" @@ -229,195 +231,195 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "uaddw2 v0.4s, v0.4s, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "movi v19.4s, #0x0\n" - "ld1r { v18.4s }, [%x[rescale_ptr]]\n" - "sub %x[n_channels], %x[n_channels], #0x40\n" - "movi v17.4s, #0xff\n" + "ld1r { v17.4s }, [%x[rescale_ptr]]\n" "ld1r { v16.4s }, [%x[shift_ptr]]\n" + "sqdmulh v15.4s, v15.4s, v17.4s\n" + "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqdmulh v13.4s, v13.4s, v17.4s\n" + "sqdmulh v12.4s, v12.4s, v17.4s\n" + "sub %x[n_channels], %x[n_channels], #0x40\n" "cmp %x[n_channels], #0x40\n" - "sqdmulh v15.4s, v15.4s, v18.4s\n" - "sqdmulh v14.4s, v14.4s, v18.4s\n" - "sqdmulh v13.4s, v13.4s, v18.4s\n" - "sqdmulh v12.4s, v12.4s, v18.4s\n" - "sqdmulh v11.4s, v11.4s, v18.4s\n" + "sqdmulh v11.4s, v11.4s, v17.4s\n" + "sqdmulh v10.4s, v10.4s, v17.4s\n" + "sqdmulh v9.4s, v9.4s, v17.4s\n" + "sqdmulh v8.4s, v8.4s, v17.4s\n" + "sqdmulh v7.4s, v7.4s, v17.4s\n" + "sqdmulh v6.4s, v6.4s, v17.4s\n" + "sqdmulh v5.4s, v5.4s, v17.4s\n" + "sqdmulh v4.4s, v4.4s, v17.4s\n" + "sqdmulh v3.4s, v3.4s, v17.4s\n" + "sqdmulh v2.4s, v2.4s, v17.4s\n" + "sqdmulh v1.4s, v1.4s, v17.4s\n" + "sqdmulh v0.4s, v0.4s, v17.4s\n" "srshl v15.4s, v15.4s, v16.4s\n" "srshl v14.4s, v14.4s, v16.4s\n" "srshl v13.4s, v13.4s, v16.4s\n" "srshl v12.4s, v12.4s, v16.4s\n" "srshl v11.4s, v11.4s, v16.4s\n" - "sqdmulh v10.4s, v10.4s, v18.4s\n" - "sqdmulh v9.4s, v9.4s, v18.4s\n" - "sqdmulh v8.4s, v8.4s, v18.4s\n" - "sqdmulh v7.4s, v7.4s, v18.4s\n" "srshl v10.4s, v10.4s, v16.4s\n" "srshl v9.4s, v9.4s, v16.4s\n" "srshl v8.4s, v8.4s, v16.4s\n" "srshl v7.4s, v7.4s, v16.4s\n" - "sqdmulh v6.4s, v6.4s, v18.4s\n" - "sqdmulh v5.4s, v5.4s, v18.4s\n" - "sqdmulh v4.4s, v4.4s, v18.4s\n" - "sqdmulh v3.4s, v3.4s, v18.4s\n" "srshl v6.4s, v6.4s, v16.4s\n" "srshl v5.4s, v5.4s, v16.4s\n" "srshl v4.4s, v4.4s, v16.4s\n" "srshl v3.4s, v3.4s, v16.4s\n" - "sqdmulh v2.4s, v2.4s, v18.4s\n" - "sqdmulh v1.4s, v1.4s, v18.4s\n" - "sqdmulh v0.4s, v0.4s, v18.4s\n" - "smax v15.4s, v15.4s, v19.4s\n" "srshl v2.4s, v2.4s, v16.4s\n" "srshl v1.4s, v1.4s, v16.4s\n" "srshl v0.4s, v0.4s, v16.4s\n" - "smin v15.4s, v15.4s, v17.4s\n" - "smax v14.4s, v14.4s, v19.4s\n" - "smax v13.4s, v13.4s, v19.4s\n" - "smax v12.4s, v12.4s, v19.4s\n" - "smin v14.4s, v14.4s, v17.4s\n" - "smin v13.4s, v13.4s, v17.4s\n" - "smin v12.4s, v12.4s, v17.4s\n" - "smax v11.4s, v11.4s, v19.4s\n" - "smax v10.4s, v10.4s, v19.4s\n" - "smax v9.4s, v9.4s, v19.4s\n" - "smin v11.4s, v11.4s, v17.4s\n" - "smin v10.4s, v10.4s, v17.4s\n" - "smin v9.4s, v9.4s, v17.4s\n" - "smax v8.4s, v8.4s, v19.4s\n" - "smax v7.4s, v7.4s, v19.4s\n" - "smax v6.4s, v6.4s, v19.4s\n" - "smin v8.4s, v8.4s, v17.4s\n" - "smin v7.4s, v7.4s, v17.4s\n" - "smin v6.4s, v6.4s, v17.4s\n" - "smax v5.4s, v5.4s, v19.4s\n" - "smax v4.4s, v4.4s, v19.4s\n" - "smax v3.4s, v3.4s, v19.4s\n" - "smin v5.4s, v5.4s, v17.4s\n" - "smin v4.4s, v4.4s, v17.4s\n" - "smin v3.4s, v3.4s, v17.4s\n" - "smax v2.4s, v2.4s, v19.4s\n" - "smax v1.4s, v1.4s, v19.4s\n" - "smax v0.4s, v0.4s, v19.4s\n" - "smin v2.4s, v2.4s, v17.4s\n" - "smin v1.4s, v1.4s, v17.4s\n" - "smin v0.4s, v0.4s, v17.4s\n" + "movi v16.4s, #0x0\n" + "smax v15.4s, v15.4s, v16.4s\n" + "smax v14.4s, v14.4s, v16.4s\n" + "smax v13.4s, v13.4s, v16.4s\n" + "smax v12.4s, v12.4s, v16.4s\n" + "smax v11.4s, v11.4s, v16.4s\n" + "smax v10.4s, v10.4s, v16.4s\n" + "smax v9.4s, v9.4s, v16.4s\n" + "smax v8.4s, v8.4s, v16.4s\n" + "smax v7.4s, v7.4s, v16.4s\n" + "smax v6.4s, v6.4s, v16.4s\n" + "smax v5.4s, v5.4s, v16.4s\n" + "smax v4.4s, v4.4s, v16.4s\n" + "smax v3.4s, v3.4s, v16.4s\n" + "smax v2.4s, v2.4s, v16.4s\n" + "smax v1.4s, v1.4s, v16.4s\n" + "smax v0.4s, v0.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v15.4s, v15.4s, v16.4s\n" + "smin v14.4s, v14.4s, v16.4s\n" + "smin v13.4s, v13.4s, v16.4s\n" + "smin v12.4s, v12.4s, v16.4s\n" + "smin v11.4s, v11.4s, v16.4s\n" + "smin v10.4s, v10.4s, v16.4s\n" + "smin v9.4s, v9.4s, v16.4s\n" + "smin v8.4s, v8.4s, v16.4s\n" + "smin v7.4s, v7.4s, v16.4s\n" + "smin v6.4s, v6.4s, v16.4s\n" + "smin v5.4s, v5.4s, v16.4s\n" + "smin v4.4s, v4.4s, v16.4s\n" + "smin v3.4s, v3.4s, v16.4s\n" + "smin v2.4s, v2.4s, v16.4s\n" + "smin v1.4s, v1.4s, v16.4s\n" + "smin v0.4s, v0.4s, v16.4s\n" "uzp1 v23.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v22.16b, v11.16b, v10.16b\n" - "uzp1 v21.16b, v9.16b, v8.16b\n" - "uzp1 v20.16b, v7.16b, v6.16b\n" + "uzp1 v18.16b, v9.16b, v8.16b\n" + "uzp1 v21.16b, v7.16b, v6.16b\n" "uzp1 v17.16b, v5.16b, v4.16b\n" - "uzp1 v19.16b, v3.16b, v2.16b\n" - "uzp1 v18.16b, v1.16b, v0.16b\n" + "uzp1 v20.16b, v3.16b, v2.16b\n" + "uzp1 v19.16b, v1.16b, v0.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "uzp1 v16.16b, v22.16b, v21.16b\n" + "uzp1 v18.16b, v22.16b, v18.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" + "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v20.16b, v19.16b\n" + "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" - "uzp1 v17.16b, v20.16b, v17.16b\n" - "str q16, [%x[outptr], x25]\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" + "str q17, [%x[outptr], x25]\n" "add x25, x25, #0x40\n" - "str q17, [%x[outptr], x24]\n" + "str q16, [%x[outptr], x24]\n" "add x24, x24, #0x40\n" - "str q16, [%x[outptr], x23]\n" - "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" "movi v15.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v14.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "movi v13.4s, #0x0\n" "movi v12.4s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "uaddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "subs x22, x22, #0x1\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q30, [x20, x26]\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "movi v19.4s, #0x0\n" - "ld1r { v18.4s }, [%x[rescale_ptr]]\n" - "sub %x[n_channels], %x[n_channels], #0x10\n" - "movi v17.4s, #0xff\n" + "ld1r { v17.4s }, [%x[rescale_ptr]]\n" "ld1r { v16.4s }, [%x[shift_ptr]]\n" + "sqdmulh v15.4s, v15.4s, v17.4s\n" + "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqdmulh v13.4s, v13.4s, v17.4s\n" + "sqdmulh v12.4s, v12.4s, v17.4s\n" + "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" - "sqdmulh v15.4s, v15.4s, v18.4s\n" - "sqdmulh v14.4s, v14.4s, v18.4s\n" - "sqdmulh v13.4s, v13.4s, v18.4s\n" - "sqdmulh v12.4s, v12.4s, v18.4s\n" "srshl v15.4s, v15.4s, v16.4s\n" "srshl v14.4s, v14.4s, v16.4s\n" "srshl v13.4s, v13.4s, v16.4s\n" "srshl v12.4s, v12.4s, v16.4s\n" - "smax v15.4s, v15.4s, v19.4s\n" - "smax v14.4s, v14.4s, v19.4s\n" - "smax v13.4s, v13.4s, v19.4s\n" - "smax v12.4s, v12.4s, v19.4s\n" - "smin v15.4s, v15.4s, v17.4s\n" - "smin v14.4s, v14.4s, v17.4s\n" - "smin v13.4s, v13.4s, v17.4s\n" - "smin v12.4s, v12.4s, v17.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "movi v16.4s, #0x0\n" + "smax v15.4s, v15.4s, v16.4s\n" + "smax v14.4s, v14.4s, v16.4s\n" + "smax v13.4s, v13.4s, v16.4s\n" + "smax v12.4s, v12.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v15.4s, v15.4s, v16.4s\n" + "smin v14.4s, v14.4s, v16.4s\n" + "smin v13.4s, v13.4s, v16.4s\n" + "smin v12.4s, v12.4s, v16.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "add x26, x26, #0x10\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments + "lsr x23, %x[n_valid_cells], #0x1\n" + "add %x[outptr], %x[outptr], x27\n" "movi v15.4s, #0x0\n" - "add %x[outptr], %x[outptr], x26\n" "movi v14.4s, #0x0\n" - "mov x19, %x[inptrs]\n" "movi v13.4s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "movi v12.4s, #0x0\n" - "cbz x22, 24f\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" - "add x21, x21, x26\n" - "add x20, x20, x26\n" "tbz %x[n_channels], #3, 19f\n" "ldr d31, [x21], #0x8\n" "ldr d30, [x20], #0x8\n" @@ -478,21 +480,21 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "ldr b31, [x21], #0x1\n" "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "uaddl v23.8h, v31.8b, v30.8b\n" - "subs x22, x22, #0x1\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldr x21, [x19], #0x8\n" - "add x21, x21, x26\n" "tbz %x[n_channels], #3, 29f\n" "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" @@ -538,38 +540,38 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 33f\n" "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "uxtl v23.8h, v31.8b\n" - "subs x20, x20, #0x1\n" - "uxtl2 v22.8h, v31.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uxtl v17.8h, v31.8b\n" + "uxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "movi v19.4s, #0x0\n" - "ld1r { v18.4s }, [%x[rescale_ptr]]\n" - "movi v17.4s, #0xff\n" + "ld1r { v17.4s }, [%x[rescale_ptr]]\n" "ld1r { v16.4s }, [%x[shift_ptr]]\n" - "sqdmulh v15.4s, v15.4s, v18.4s\n" - "sqdmulh v14.4s, v14.4s, v18.4s\n" - "sqdmulh v13.4s, v13.4s, v18.4s\n" - "sqdmulh v12.4s, v12.4s, v18.4s\n" + "sqdmulh v15.4s, v15.4s, v17.4s\n" + "sqdmulh v14.4s, v14.4s, v17.4s\n" + "sqdmulh v13.4s, v13.4s, v17.4s\n" + "sqdmulh v12.4s, v12.4s, v17.4s\n" "srshl v15.4s, v15.4s, v16.4s\n" "srshl v14.4s, v14.4s, v16.4s\n" "srshl v13.4s, v13.4s, v16.4s\n" "srshl v12.4s, v12.4s, v16.4s\n" - "smax v15.4s, v15.4s, v19.4s\n" - "smax v14.4s, v14.4s, v19.4s\n" - "smax v13.4s, v13.4s, v19.4s\n" - "smax v12.4s, v12.4s, v19.4s\n" - "smin v15.4s, v15.4s, v17.4s\n" - "smin v14.4s, v14.4s, v17.4s\n" - "smin v13.4s, v13.4s, v17.4s\n" - "smin v12.4s, v12.4s, v17.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" + "movi v16.4s, #0x0\n" + "smax v15.4s, v15.4s, v16.4s\n" + "smax v14.4s, v14.4s, v16.4s\n" + "smax v13.4s, v13.4s, v16.4s\n" + "smax v12.4s, v12.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v15.4s, v15.4s, v16.4s\n" + "smin v14.4s, v14.4s, v16.4s\n" + "smin v13.4s, v13.4s, v16.4s\n" + "smin v12.4s, v12.4s, v16.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -615,12 +617,10 @@ void a64_u8_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 42f\n" "st1 { v16.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 0103de812d..9d160bf8f8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,33 +24,28 @@ #pragma once +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { void a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const uint8_t *const *const, uint8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst +struct a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<uint8_t, uint8_t> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(unsigned int, const uint8_t *const *const, uint8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + using Parent = DepthfirstStrategy<uint8_t, uint8_t>; - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } + a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 02c43ccaba..66cdb7f849 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,6 +26,8 @@ #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace pooling { @@ -61,114 +63,115 @@ void a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x15, [%x[args], %[offsetof_n_channels]]\n" - "mov x14, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "cmp x15, #0x10\n" - "ldp x12, x11, [x20, #0x0]\n" - "ldp x10, x9, [x20, #0x10]\n" - "ldp x28, x27, [x19, #0x0]\n" - "ldp x26, x25, [x19, #0x10]\n" - "ldp x24, x23, [x19, #0x20]\n" - "ldp x22, x21, [x19, #0x30]\n" - "ldr x20, [x19, #0x40]\n" + "ldr x16, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "cmp x16, #0x10\n" + "mov x15, #0x0\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x14, x13, [x21, #0x0]\n" + "mov x12, #0x0\n" + "ldp x11, x10, [x21, #0x10]\n" + "ldp x9, x28, [x20, #0x0]\n" + "ldp x27, x26, [x20, #0x10]\n" + "ldp x25, x24, [x20, #0x20]\n" + "ldp x23, x22, [x20, #0x30]\n" + "ldr x21, [x20, #0x40]\n" "blt 3f\n" - "ldr q30, [x27, x14]\n" - "lsr x19, x15, #0x4\n" - "ldr q29, [x24, x14]\n" - "sub x15, x15, x19, LSL #4\n" - "ldr q28, [x21, x14]\n" - "subs x19, x19, #0x1\n" - "ldr q27, [x25, x14]\n" - "ldr q26, [x28, x14]\n" - "ldr q25, [x23, x14]\n" - "ldr q24, [x26, x14]\n" - "ldr q23, [x22, x14]\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q30, [x28, x15]\n" + "ldr q29, [x25, x15]\n" + "lsr x20, x16, #0x4\n" + "sub x16, x16, x20, LSL #4\n" + "ldr q28, [x22, x15]\n" + "ldr q27, [x26, x15]\n" + "subs x20, x20, #0x1\n" + "ldr q26, [x9, x15]\n" + "ldr q25, [x27, x15]\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "ldr q22, [x21, x15]\n" + "add x15, x15, #0x10\n" "beq 2f\n" "1:" // Vector: Loop "umax v21.16b, v30.16b, v29.16b\n" - "ldr q30, [x27, x14]\n" - "subs x19, x19, #0x1\n" + "ldr q30, [x28, x15]\n" "umax v20.16b, v29.16b, v28.16b\n" - "ldr q29, [x24, x14]\n" + "ldr q29, [x25, x15]\n" + "ldr q28, [x22, x15]\n" "umax v19.16b, v27.16b, v26.16b\n" - "ldr q28, [x21, x14]\n" + "ldr q26, [x9, x15]\n" "umax v18.16b, v25.16b, v24.16b\n" - "ldr q26, [x28, x14]\n" - "umax v17.16b, v23.16b, v27.16b\n" - "ldr q27, [x25, x14]\n" - "umax v16.16b, v25.16b, v22.16b\n" - "ldr q25, [x23, x14]\n" + "ldr q25, [x27, x15]\n" + "umax v17.16b, v27.16b, v23.16b\n" + "ldr q27, [x26, x15]\n" + "umax v16.16b, v24.16b, v22.16b\n" + "ldr q24, [x24, x15]\n" + "ldr q23, [x23, x15]\n" + "subs x20, x20, #0x1\n" "umax v19.16b, v21.16b, v19.16b\n" - "ldr q24, [x26, x14]\n" - "umax v18.16b, v21.16b, v18.16b\n" - "ldr q23, [x22, x14]\n" - "umax v17.16b, v20.16b, v17.16b\n" - "ldr q22, [x20, x14]\n" - "add x14, x14, #0x10\n" + "ldr q22, [x21, x15]\n" + "umax v18.16b, v18.16b, v21.16b\n" + "umax v17.16b, v17.16b, v20.16b\n" + "add x15, x15, #0x10\n" "umax v16.16b, v20.16b, v16.16b\n" - "str q19, [x12, x13]\n" - "str q18, [x11, x13]\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" + "str q19, [x14, x12]\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" "bgt 1b\n" "2:" // Vector: Tail "umax v21.16b, v30.16b, v29.16b\n" "umax v20.16b, v29.16b, v28.16b\n" - "umax v19.16b, v27.16b, v26.16b\n" + "umax v16.16b, v27.16b, v26.16b\n" "umax v18.16b, v25.16b, v24.16b\n" - "umax v17.16b, v23.16b, v27.16b\n" - "umax v16.16b, v25.16b, v22.16b\n" - "umax v19.16b, v21.16b, v19.16b\n" - "str q19, [x12, x13]\n" - "umax v18.16b, v21.16b, v18.16b\n" - "umax v17.16b, v20.16b, v17.16b\n" - "str q18, [x11, x13]\n" - "umax v16.16b, v20.16b, v16.16b\n" - "str q17, [x10, x13]\n" - "str q16, [x9, x13]\n" - "add x13, x13, #0x10\n" - "cbz x15, 4f\n" + "umax v17.16b, v27.16b, v23.16b\n" + "umax v19.16b, v24.16b, v22.16b\n" + "umax v16.16b, v21.16b, v16.16b\n" + "umax v18.16b, v18.16b, v21.16b\n" + "str q16, [x14, x12]\n" + "umax v17.16b, v17.16b, v20.16b\n" + "umax v16.16b, v20.16b, v19.16b\n" + "str q18, [x13, x12]\n" + "str q17, [x11, x12]\n" + "str q16, [x10, x12]\n" + "add x12, x12, #0x10\n" + "cbz x16, 4f\n" "3:" // Oddments - "ldr b30, [x27, x14]\n" - "subs x15, x15, #0x1\n" - "ldr b29, [x24, x14]\n" - "umax v21.16b, v30.16b, v29.16b\n" - "ldr b28, [x21, x14]\n" - "ldr b27, [x25, x14]\n" - "umax v20.16b, v29.16b, v28.16b\n" - "ldr b26, [x28, x14]\n" - "ldr b25, [x23, x14]\n" - "umax v19.16b, v27.16b, v26.16b\n" - "ldr b24, [x26, x14]\n" - "ldr b23, [x22, x14]\n" - "umax v19.16b, v21.16b, v19.16b\n" - "ldr b22, [x20, x14]\n" - "add x14, x14, #0x1\n" - "umax v18.16b, v25.16b, v24.16b\n" - "str b19, [x12, x13]\n" - "umax v17.16b, v23.16b, v27.16b\n" - "umax v16.16b, v25.16b, v22.16b\n" - "umax v18.16b, v21.16b, v18.16b\n" - "str b18, [x11, x13]\n" - "umax v17.16b, v20.16b, v17.16b\n" - "umax v16.16b, v20.16b, v16.16b\n" - "str b17, [x10, x13]\n" - "str b16, [x9, x13]\n" - "add x13, x13, #0x1\n" + "ldr b16, [x28, x15]\n" + "ldr b17, [x25, x15]\n" + "umax v23.16b, v16.16b, v17.16b\n" + "subs x16, x16, #0x1\n" + "ldr b16, [x22, x15]\n" + "ldr b22, [x26, x15]\n" + "umax v21.16b, v17.16b, v16.16b\n" + "ldr b16, [x9, x15]\n" + "ldr b17, [x27, x15]\n" + "umax v16.16b, v22.16b, v16.16b\n" + "umax v20.16b, v23.16b, v16.16b\n" + "ldr b19, [x24, x15]\n" + "ldr b16, [x23, x15]\n" + "umax v18.16b, v17.16b, v19.16b\n" + "umax v17.16b, v22.16b, v16.16b\n" + "ldr b16, [x21, x15]\n" + "umax v16.16b, v19.16b, v16.16b\n" + "add x15, x15, #0x1\n" + "umax v18.16b, v18.16b, v23.16b\n" + "umax v17.16b, v17.16b, v21.16b\n" + "umax v16.16b, v21.16b, v16.16b\n" + "str b20, [x14, x12]\n" + "str b18, [x13, x12]\n" + "str b17, [x11, x12]\n" + "str b16, [x10, x12]\n" + "add x12, x12, #0x1\n" "bgt 3b\n" "4:" // End - : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace pooling } // namespace arm_conv + +#endif // defined(__aarch64__) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst.hpp index 391af31d03..7d528ccc65 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_u8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); -struct a64_u8_nhwc_max_generic_depthfirst +struct a64_u8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = a64_u8_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; a64_u8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_u8_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp index f9bbfd8b90..2ceef125ca 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,6 +23,7 @@ */ #include <cstdint> +#include <cstddef> #if defined(__aarch64__) @@ -39,397 +40,395 @@ void a64_u8_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" "movi v7.16b, #0x0\n" - "mov x19, %x[inptrs]\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "movi v5.16b, #0x0\n" - "movi v4.16b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "umax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "umax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "umax v22.16b, v31.16b, v30.16b\n" - "ldr q3, [x23, x28]\n" - "umax v18.16b, v29.16b, v28.16b\n" - "umax v21.16b, v27.16b, v21.16b\n" - "ldr q2, [x22, x28]\n" - "umax v17.16b, v26.16b, v17.16b\n" - "ldr q1, [x21, x28]\n" - "umax v20.16b, v25.16b, v20.16b\n" - "ldr q0, [x20, x28]\n" - "umax v16.16b, v24.16b, v16.16b\n" - "ldr q31, [x23, x27]\n" + "umax v23.16b, v4.16b, v3.16b\n" + "umax v19.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "umax v22.16b, v2.16b, v1.16b\n" + "ldr q2, [x21, x26]\n" + "umax v18.16b, v27.16b, v21.16b\n" + "ldr q1, [x20, x26]\n" + "umax v21.16b, v0.16b, v31.16b\n" + "ldr q0, [x21, x24]\n" + "umax v17.16b, v26.16b, v20.16b\n" + "ldr q31, [x20, x24]\n" + "umax v20.16b, v30.16b, v29.16b\n" + "ldr q30, [x21, x23]\n" + "umax v16.16b, v25.16b, v24.16b\n" + "ldr q29, [x20, x23]\n" "umax v19.16b, v23.16b, v19.16b\n" - "ldr q30, [x22, x27]\n" "umax v18.16b, v22.16b, v18.16b\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "umax v17.16b, v21.16b, v17.16b\n" - "ldr q28, [x20, x27]\n" "umax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x23, x26]\n" - "umax v7.16b, v7.16b, v19.16b\n" - "ldr q21, [x22, x26]\n" - "umax v6.16b, v6.16b, v18.16b\n" - "ldr q26, [x21, x26]\n" - "umax v5.16b, v5.16b, v17.16b\n" - "ldr q17, [x20, x26]\n" - "umax v4.16b, v4.16b, v16.16b\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "umax v8.16b, v8.16b, v19.16b\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "umax v7.16b, v7.16b, v18.16b\n" + "umax v6.16b, v6.16b, v17.16b\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "umax v5.16b, v5.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "umax v23.16b, v3.16b, v2.16b\n" - "umax v19.16b, v1.16b, v0.16b\n" - "umax v22.16b, v31.16b, v30.16b\n" - "umax v18.16b, v29.16b, v28.16b\n" - "umax v21.16b, v27.16b, v21.16b\n" - "umax v17.16b, v26.16b, v17.16b\n" - "umax v20.16b, v25.16b, v20.16b\n" - "umax v16.16b, v24.16b, v16.16b\n" + "umax v23.16b, v4.16b, v3.16b\n" + "umax v19.16b, v28.16b, v22.16b\n" + "umax v22.16b, v2.16b, v1.16b\n" + "umax v18.16b, v27.16b, v21.16b\n" + "umax v21.16b, v0.16b, v31.16b\n" + "umax v17.16b, v26.16b, v20.16b\n" + "umax v20.16b, v30.16b, v29.16b\n" + "umax v16.16b, v25.16b, v24.16b\n" "umax v19.16b, v23.16b, v19.16b\n" "umax v18.16b, v22.16b, v18.16b\n" "umax v17.16b, v21.16b, v17.16b\n" "umax v16.16b, v20.16b, v16.16b\n" - "umax v7.16b, v7.16b, v19.16b\n" - "umax v6.16b, v6.16b, v18.16b\n" - "umax v5.16b, v5.16b, v17.16b\n" - "umax v4.16b, v4.16b, v16.16b\n" + "umax v8.16b, v8.16b, v19.16b\n" + "umax v7.16b, v7.16b, v18.16b\n" + "umax v6.16b, v6.16b, v17.16b\n" + "umax v5.16b, v5.16b, v16.16b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "umax v7.16b, v7.16b, v3.16b\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "umax v6.16b, v6.16b, v31.16b\n" - "ldr q25, [x23, x25]\n" - "umax v5.16b, v5.16b, v27.16b\n" - "umax v4.16b, v4.16b, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "umax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "umax v7.16b, v7.16b, v17.16b\n" + "umax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "umax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x40\n" - "str q6, [%x[outptr], x27]\n" - "add x27, x27, #0x40\n" - "str q5, [%x[outptr], x26]\n" - "add x26, x26, #0x40\n" - "str q4, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" "sub %x[n_channels], %x[n_channels], #0x40\n" "cmp %x[n_channels], #0x40\n" + "str q8, [%x[outptr], x27]\n" + "str q7, [%x[outptr], x26]\n" + "add x27, x27, #0x40\n" + "add x26, x26, #0x40\n" + "str q6, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q5, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "movi v7.16b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "umax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "umax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "umax v19.16b, v23.16b, v19.16b\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "umax v7.16b, v7.16b, v19.16b\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "umax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "umax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "umax v23.16b, v3.16b, v2.16b\n" - "umax v19.16b, v1.16b, v0.16b\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v7.16b, v7.16b, v19.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "umax v7.16b, v7.16b, v3.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "str q7, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" "sub %x[n_channels], %x[n_channels], #0x10\n" "cmp %x[n_channels], #0x10\n" + "str q8, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments - "movi v7.16b, #0x0\n" - "add %x[outptr], %x[outptr], x28\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 24f\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "add %x[outptr], %x[outptr], x27\n" + "movi v8.16b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v2.h }[6], [x22], #0x2\n" - "ld1 { v1.h }[6], [x21], #0x2\n" - "ld1 { v0.h }[6], [x20], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v2.b }[14], [x22], #0x1\n" - "ld1 { v1.b }[14], [x21], #0x1\n" - "ld1 { v0.b }[14], [x20], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v2.b }[12], [x22], #0x1\n" - "ld1 { v1.b }[12], [x21], #0x1\n" - "ld1 { v0.b }[12], [x20], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v2.h }[4], [x22], #0x2\n" - "ld1 { v1.h }[4], [x21], #0x2\n" - "ld1 { v0.h }[4], [x20], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v2.b }[10], [x22], #0x1\n" - "ld1 { v1.b }[10], [x21], #0x1\n" - "ld1 { v0.b }[10], [x20], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v2.b }[8], [x22], #0x1\n" - "ld1 { v1.b }[8], [x21], #0x1\n" - "ld1 { v0.b }[8], [x20], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v2.h }[2], [x22], #0x2\n" - "ld1 { v1.h }[2], [x21], #0x2\n" - "ld1 { v0.h }[2], [x20], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v2.b }[6], [x22], #0x1\n" - "ld1 { v1.b }[6], [x21], #0x1\n" - "ld1 { v0.b }[6], [x20], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v2.b }[4], [x22], #0x1\n" - "ld1 { v1.b }[4], [x21], #0x1\n" - "ld1 { v0.b }[4], [x20], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h3, [x23], #0x2\n" - "ldr h2, [x22], #0x2\n" - "ldr h1, [x21], #0x2\n" - "ldr h0, [x20], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v2.b }[2], [x22], #0x1\n" - "ld1 { v1.b }[2], [x21], #0x1\n" - "ld1 { v0.b }[2], [x20], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b3, [x23], #0x1\n" - "ldr b2, [x22], #0x1\n" - "ldr b1, [x21], #0x1\n" - "ldr b0, [x20], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "umax v23.16b, v3.16b, v2.16b\n" - "subs x24, x24, #0x1\n" - "umax v19.16b, v1.16b, v0.16b\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v7.16b, v7.16b, v19.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "subs x25, x25, #0x1\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h3, [x23], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b3, [x23], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "umax v7.16b, v7.16b, v3.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "umax v8.16b, v8.16b, v4.16b\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End "tbz %x[n_channels], #3, 38f\n" - "st1 { v7.d }[0], [%x[outptr]], #0x8\n" + "st1 { v8.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" - "st1 { v7.s }[2], [%x[outptr]], #0x4\n" + "st1 { v8.s }[2], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #1, 35f\n" - "st1 { v7.h }[6], [%x[outptr]], #0x2\n" + "st1 { v8.h }[6], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[14], [%x[outptr]], #0x1\n" + "st1 { v8.b }[14], [%x[outptr]], #0x1\n" "b 42f\n" "35:" // Oddments: Store: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[12], [%x[outptr]], #0x1\n" + "st1 { v8.b }[12], [%x[outptr]], #0x1\n" "b 42f\n" "36:" // Oddments: Store: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 37f\n" - "st1 { v7.h }[4], [%x[outptr]], #0x2\n" + "st1 { v8.h }[4], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[10], [%x[outptr]], #0x1\n" + "st1 { v8.b }[10], [%x[outptr]], #0x1\n" "b 42f\n" "37:" // Oddments: Store: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[8], [%x[outptr]], #0x1\n" + "st1 { v8.b }[8], [%x[outptr]], #0x1\n" "b 42f\n" "38:" // Oddments: Store: Bit 3: Unset "tbz %x[n_channels], #2, 40f\n" - "st1 { v7.s }[0], [%x[outptr]], #0x4\n" + "st1 { v8.s }[0], [%x[outptr]], #0x4\n" "tbz %x[n_channels], #1, 39f\n" - "st1 { v7.h }[2], [%x[outptr]], #0x2\n" + "st1 { v8.h }[2], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[6], [%x[outptr]], #0x1\n" + "st1 { v8.b }[6], [%x[outptr]], #0x1\n" "b 42f\n" "39:" // Oddments: Store: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[4], [%x[outptr]], #0x1\n" + "st1 { v8.b }[4], [%x[outptr]], #0x1\n" "b 42f\n" "40:" // Oddments: Store: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 41f\n" - "st1 { v7.h }[0], [%x[outptr]], #0x2\n" + "st1 { v8.h }[0], [%x[outptr]], #0x2\n" "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[2], [%x[outptr]], #0x1\n" + "st1 { v8.b }[2], [%x[outptr]], #0x1\n" "b 42f\n" "41:" // Oddments: Store: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 42f\n" - "st1 { v7.b }[0], [%x[outptr]], #0x1\n" + "st1 { v8.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst.hpp index d46658f080..daf836f5d6 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_u8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); -struct a64_u8q_nhwc_avg_generic_depthfirst +struct a64_u8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = a64_u8q_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; a64_u8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_u8q_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp index a57fe6df68..31a3489e5c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,8 @@ */ #include "pooling.hpp" -#include <cstddef> #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> @@ -87,12 +87,13 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } @@ -118,20 +119,20 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( ); __asm__ __volatile__( - "mov x26, #0x0\n" - "mov x25, #0x10\n" // cntb _, ALL, #1 - "mov x24, #0x20\n" // cntb _, ALL, #2 - "mov x23, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x25, #0x20\n" // cntb _, ALL, #2 + "mov x24, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels "ld1r { v15.4s }, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" "mov v14.16b, v15.16b\n" - "mov x19, %x[inptrs]\n" "mov v13.16b, v15.16b\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "mov v12.16b, v15.16b\n" "mov v11.16b, v15.16b\n" + "mov x22, %x[inptrs]\n" "mov v10.16b, v15.16b\n" "mov v9.16b, v15.16b\n" "mov v8.16b, v15.16b\n" @@ -143,43 +144,43 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "mov v2.16b, v15.16b\n" "mov v1.16b, v15.16b\n" "mov v0.16b, v15.16b\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ldr q29, [x21, x25]\n" - "ldr q28, [x20, x25]\n" - "ldr q27, [x21, x24]\n" - "ldr q26, [x20, x24]\n" - "ldr q25, [x21, x23]\n" - "ldr q24, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop "uaddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" "uaddl v21.8h, v29.8b, v28.8b\n" - "subs x22, x22, #0x1\n" "uaddl2 v20.8h, v29.16b, v28.16b\n" - "ldr q30, [x20, x26]\n" + "ldr q29, [x21, x26]\n" + "ldr q28, [x20, x26]\n" "uaddl v19.8h, v27.8b, v26.8b\n" - "ldr q29, [x21, x25]\n" "uaddl2 v18.8h, v27.16b, v26.16b\n" - "ldr q28, [x20, x25]\n" + "ldr q27, [x21, x25]\n" + "ldr q26, [x20, x25]\n" "uaddl v17.8h, v25.8b, v24.8b\n" - "ldr q27, [x21, x24]\n" "uaddl2 v16.8h, v25.16b, v24.16b\n" - "ldr q26, [x20, x24]\n" + "ldr q25, [x21, x24]\n" + "ldr q24, [x20, x24]\n" + "subs x23, x23, #0x1\n" "uaddw v15.4s, v15.4s, v23.4h\n" - "ldr q25, [x21, x23]\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q24, [x20, x23]\n" "uaddw v13.4s, v13.4s, v22.4h\n" "uaddw2 v12.4s, v12.4s, v22.8h\n" + "add x22, x22, #0x10\n" "uaddw v11.4s, v11.4s, v21.4h\n" "uaddw2 v10.4s, v10.4s, v21.8h\n" "uaddw v9.4s, v9.4s, v20.4h\n" @@ -219,23 +220,23 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "uaddw v1.4s, v1.4s, v16.4h\n" "uaddw2 v0.4s, v0.4s, v16.8h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "uxtl v23.8h, v31.8b\n" - "ldr q29, [x21, x25]\n" - "uxtl2 v22.8h, v31.16b\n" - "ldr q27, [x21, x24]\n" - "ldr q25, [x21, x23]\n" - "uxtl v21.8h, v29.8b\n" - "uxtl2 v20.8h, v29.16b\n" - "uxtl v19.8h, v27.8b\n" - "uxtl2 v18.8h, v27.16b\n" - "uxtl v17.8h, v25.8b\n" - "uxtl2 v16.8h, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v23.8h, v16.8b\n" + "uxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" + "ldr q17, [x20, x25]\n" + "uxtl v21.8h, v16.8b\n" + "uxtl2 v20.8h, v16.16b\n" + "ldr q16, [x20, x24]\n" + "uxtl v19.8h, v17.8b\n" + "uxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" "uaddw v15.4s, v15.4s, v23.4h\n" "uaddw2 v14.4s, v14.4s, v23.8h\n" "uaddw v13.4s, v13.4s, v22.4h\n" @@ -254,64 +255,62 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "uaddw2 v0.4s, v0.4s, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "movi v21.4s, #0x0\n" - "ld1r { v20.4s }, [%x[combined_rescale_value]]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "movi v19.4s, #0xff\n" - "ld1r { v18.4s }, [%x[left_shift]]\n" - "sub %x[n_channels], %x[n_channels], #0x40\n" - "srshl v15.4s, v15.4s, v18.4s\n" + "ld1r { v19.4s }, [%x[left_shift]]\n" + "ld1r { v18.4s }, [%x[combined_rescale_value]]\n" + "srshl v15.4s, v15.4s, v19.4s\n" + "srshl v14.4s, v14.4s, v19.4s\n" "ld1r { v17.4s }, [%x[right_shift]]\n" + "srshl v13.4s, v13.4s, v19.4s\n" + "srshl v12.4s, v12.4s, v19.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v11.4s, v11.4s, v19.4s\n" + "srshl v10.4s, v10.4s, v19.4s\n" + "sub %x[n_channels], %x[n_channels], #0x40\n" + "srshl v9.4s, v9.4s, v19.4s\n" + "srshl v8.4s, v8.4s, v19.4s\n" "cmp %x[n_channels], #0x40\n" - "srshl v14.4s, v14.4s, v18.4s\n" - "ld1r { v16.4s }, [x19]\n" - "srshl v13.4s, v13.4s, v18.4s\n" - "srshl v12.4s, v12.4s, v18.4s\n" - "srshl v11.4s, v11.4s, v18.4s\n" - "sqrdmulh v15.4s, v15.4s, v20.4s\n" - "sqrdmulh v14.4s, v14.4s, v20.4s\n" - "sqrdmulh v13.4s, v13.4s, v20.4s\n" - "sqrdmulh v12.4s, v12.4s, v20.4s\n" + "srshl v7.4s, v7.4s, v19.4s\n" + "srshl v6.4s, v6.4s, v19.4s\n" + "srshl v5.4s, v5.4s, v19.4s\n" + "srshl v4.4s, v4.4s, v19.4s\n" + "srshl v3.4s, v3.4s, v19.4s\n" + "srshl v2.4s, v2.4s, v19.4s\n" + "srshl v1.4s, v1.4s, v19.4s\n" + "srshl v0.4s, v0.4s, v19.4s\n" + "sqrdmulh v15.4s, v15.4s, v18.4s\n" + "sqrdmulh v14.4s, v14.4s, v18.4s\n" + "sqrdmulh v13.4s, v13.4s, v18.4s\n" + "sqrdmulh v12.4s, v12.4s, v18.4s\n" + "sqrdmulh v11.4s, v11.4s, v18.4s\n" + "sqrdmulh v10.4s, v10.4s, v18.4s\n" + "sqrdmulh v9.4s, v9.4s, v18.4s\n" + "sqrdmulh v8.4s, v8.4s, v18.4s\n" + "sqrdmulh v7.4s, v7.4s, v18.4s\n" + "sqrdmulh v6.4s, v6.4s, v18.4s\n" + "sqrdmulh v5.4s, v5.4s, v18.4s\n" + "sqrdmulh v4.4s, v4.4s, v18.4s\n" + "sqrdmulh v3.4s, v3.4s, v18.4s\n" + "sqrdmulh v2.4s, v2.4s, v18.4s\n" + "sqrdmulh v1.4s, v1.4s, v18.4s\n" + "sqrdmulh v0.4s, v0.4s, v18.4s\n" "srshl v15.4s, v15.4s, v17.4s\n" "srshl v14.4s, v14.4s, v17.4s\n" "srshl v13.4s, v13.4s, v17.4s\n" "srshl v12.4s, v12.4s, v17.4s\n" - "sqrdmulh v11.4s, v11.4s, v20.4s\n" - "srshl v10.4s, v10.4s, v18.4s\n" - "srshl v9.4s, v9.4s, v18.4s\n" - "srshl v8.4s, v8.4s, v18.4s\n" "srshl v11.4s, v11.4s, v17.4s\n" - "sqrdmulh v10.4s, v10.4s, v20.4s\n" - "sqrdmulh v9.4s, v9.4s, v20.4s\n" - "sqrdmulh v8.4s, v8.4s, v20.4s\n" - "srshl v7.4s, v7.4s, v18.4s\n" "srshl v10.4s, v10.4s, v17.4s\n" "srshl v9.4s, v9.4s, v17.4s\n" "srshl v8.4s, v8.4s, v17.4s\n" - "sqrdmulh v7.4s, v7.4s, v20.4s\n" - "srshl v6.4s, v6.4s, v18.4s\n" - "srshl v5.4s, v5.4s, v18.4s\n" - "srshl v4.4s, v4.4s, v18.4s\n" "srshl v7.4s, v7.4s, v17.4s\n" - "sqrdmulh v6.4s, v6.4s, v20.4s\n" - "sqrdmulh v5.4s, v5.4s, v20.4s\n" - "sqrdmulh v4.4s, v4.4s, v20.4s\n" - "srshl v3.4s, v3.4s, v18.4s\n" "srshl v6.4s, v6.4s, v17.4s\n" "srshl v5.4s, v5.4s, v17.4s\n" "srshl v4.4s, v4.4s, v17.4s\n" - "sqrdmulh v3.4s, v3.4s, v20.4s\n" - "srshl v2.4s, v2.4s, v18.4s\n" - "srshl v1.4s, v1.4s, v18.4s\n" - "srshl v0.4s, v0.4s, v18.4s\n" "srshl v3.4s, v3.4s, v17.4s\n" - "sqrdmulh v2.4s, v2.4s, v20.4s\n" - "sqrdmulh v1.4s, v1.4s, v20.4s\n" - "sqrdmulh v0.4s, v0.4s, v20.4s\n" - "add v15.4s, v15.4s, v16.4s\n" "srshl v2.4s, v2.4s, v17.4s\n" "srshl v1.4s, v1.4s, v17.4s\n" "srshl v0.4s, v0.4s, v17.4s\n" + "add v15.4s, v15.4s, v16.4s\n" "add v14.4s, v14.4s, v16.4s\n" "add v13.4s, v13.4s, v16.4s\n" "add v12.4s, v12.4s, v16.4s\n" @@ -327,58 +326,60 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "add v2.4s, v2.4s, v16.4s\n" "add v1.4s, v1.4s, v16.4s\n" "add v0.4s, v0.4s, v16.4s\n" - "smax v15.4s, v15.4s, v21.4s\n" - "smax v14.4s, v14.4s, v21.4s\n" - "smax v13.4s, v13.4s, v21.4s\n" - "smin v15.4s, v15.4s, v19.4s\n" - "smin v14.4s, v14.4s, v19.4s\n" - "smin v13.4s, v13.4s, v19.4s\n" - "smax v12.4s, v12.4s, v21.4s\n" - "smax v11.4s, v11.4s, v21.4s\n" - "smax v10.4s, v10.4s, v21.4s\n" - "smin v12.4s, v12.4s, v19.4s\n" - "smin v11.4s, v11.4s, v19.4s\n" - "smin v10.4s, v10.4s, v19.4s\n" - "smax v9.4s, v9.4s, v21.4s\n" - "smax v8.4s, v8.4s, v21.4s\n" - "smax v7.4s, v7.4s, v21.4s\n" - "smin v9.4s, v9.4s, v19.4s\n" - "smin v8.4s, v8.4s, v19.4s\n" - "smin v7.4s, v7.4s, v19.4s\n" - "smax v6.4s, v6.4s, v21.4s\n" - "smax v5.4s, v5.4s, v21.4s\n" - "smax v4.4s, v4.4s, v21.4s\n" - "smin v6.4s, v6.4s, v19.4s\n" - "smin v5.4s, v5.4s, v19.4s\n" - "smin v4.4s, v4.4s, v19.4s\n" - "smax v3.4s, v3.4s, v21.4s\n" - "smax v2.4s, v2.4s, v21.4s\n" - "smax v1.4s, v1.4s, v21.4s\n" - "smin v3.4s, v3.4s, v19.4s\n" - "smin v2.4s, v2.4s, v19.4s\n" - "smin v1.4s, v1.4s, v19.4s\n" - "smax v0.4s, v0.4s, v21.4s\n" + "movi v16.4s, #0x0\n" + "smax v15.4s, v15.4s, v16.4s\n" + "smax v14.4s, v14.4s, v16.4s\n" + "smax v13.4s, v13.4s, v16.4s\n" + "smax v12.4s, v12.4s, v16.4s\n" + "smax v11.4s, v11.4s, v16.4s\n" + "smax v10.4s, v10.4s, v16.4s\n" + "smax v9.4s, v9.4s, v16.4s\n" + "smax v8.4s, v8.4s, v16.4s\n" + "smax v7.4s, v7.4s, v16.4s\n" + "smax v6.4s, v6.4s, v16.4s\n" + "smax v5.4s, v5.4s, v16.4s\n" + "smax v4.4s, v4.4s, v16.4s\n" + "smax v3.4s, v3.4s, v16.4s\n" + "smax v2.4s, v2.4s, v16.4s\n" + "smax v1.4s, v1.4s, v16.4s\n" + "smax v0.4s, v0.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v15.4s, v15.4s, v16.4s\n" + "smin v14.4s, v14.4s, v16.4s\n" + "smin v13.4s, v13.4s, v16.4s\n" + "smin v12.4s, v12.4s, v16.4s\n" + "smin v11.4s, v11.4s, v16.4s\n" + "smin v10.4s, v10.4s, v16.4s\n" + "smin v9.4s, v9.4s, v16.4s\n" + "smin v8.4s, v8.4s, v16.4s\n" + "smin v7.4s, v7.4s, v16.4s\n" + "smin v6.4s, v6.4s, v16.4s\n" + "smin v5.4s, v5.4s, v16.4s\n" + "smin v4.4s, v4.4s, v16.4s\n" + "smin v3.4s, v3.4s, v16.4s\n" + "smin v2.4s, v2.4s, v16.4s\n" + "smin v1.4s, v1.4s, v16.4s\n" + "smin v0.4s, v0.4s, v16.4s\n" "uzp1 v23.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "smin v0.4s, v0.4s, v19.4s\n" "uzp1 v22.16b, v11.16b, v10.16b\n" - "uzp1 v21.16b, v9.16b, v8.16b\n" - "uzp1 v20.16b, v7.16b, v6.16b\n" + "uzp1 v18.16b, v9.16b, v8.16b\n" + "uzp1 v21.16b, v7.16b, v6.16b\n" "uzp1 v17.16b, v5.16b, v4.16b\n" - "uzp1 v19.16b, v3.16b, v2.16b\n" - "uzp1 v18.16b, v1.16b, v0.16b\n" + "uzp1 v20.16b, v3.16b, v2.16b\n" + "uzp1 v19.16b, v1.16b, v0.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "uzp1 v16.16b, v22.16b, v21.16b\n" + "uzp1 v18.16b, v22.16b, v18.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x40\n" + "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v20.16b, v19.16b\n" + "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" - "uzp1 v17.16b, v20.16b, v17.16b\n" - "str q16, [%x[outptr], x25]\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" + "str q17, [%x[outptr], x25]\n" "add x25, x25, #0x40\n" - "str q17, [%x[outptr], x24]\n" + "str q16, [%x[outptr], x24]\n" "add x24, x24, #0x40\n" - "str q16, [%x[outptr], x23]\n" - "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels @@ -386,70 +387,68 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "blt 14f\n" "8:" // Single vector of channels: Loop "ld1r { v15.4s }, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" "mov v14.16b, v15.16b\n" - "mov x19, %x[inptrs]\n" "mov v13.16b, v15.16b\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "mov v12.16b, v15.16b\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ldr q31, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ldr q30, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - "uaddl v23.8h, v31.8b, v30.8b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "ldr q31, [x21, x26]\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "subs x22, x22, #0x1\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "ldr q30, [x20, x26]\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" + "ldr q30, [x20, x27]\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - "uaddl v23.8h, v31.8b, v30.8b\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q31, [x21, x26]\n" - "uxtl v23.8h, v31.8b\n" - "uxtl2 v22.8h, v31.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "uxtl v17.8h, v16.8b\n" + "uxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "movi v21.4s, #0x0\n" - "ld1r { v20.4s }, [%x[combined_rescale_value]]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "movi v19.4s, #0xff\n" - "ld1r { v18.4s }, [%x[left_shift]]\n" - "sub %x[n_channels], %x[n_channels], #0x10\n" - "srshl v15.4s, v15.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[left_shift]]\n" + "ld1r { v18.4s }, [%x[combined_rescale_value]]\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" "ld1r { v17.4s }, [%x[right_shift]]\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1r { v16.4s }, [x20]\n" + "sqrdmulh v15.4s, v15.4s, v18.4s\n" + "sqrdmulh v14.4s, v14.4s, v18.4s\n" + "sub %x[n_channels], %x[n_channels], #0x10\n" + "sqrdmulh v13.4s, v13.4s, v18.4s\n" + "sqrdmulh v12.4s, v12.4s, v18.4s\n" "cmp %x[n_channels], #0x10\n" - "srshl v14.4s, v14.4s, v18.4s\n" - "ld1r { v16.4s }, [x19]\n" - "srshl v13.4s, v13.4s, v18.4s\n" - "srshl v12.4s, v12.4s, v18.4s\n" - "sqrdmulh v15.4s, v15.4s, v20.4s\n" - "sqrdmulh v14.4s, v14.4s, v20.4s\n" - "sqrdmulh v13.4s, v13.4s, v20.4s\n" - "sqrdmulh v12.4s, v12.4s, v20.4s\n" "srshl v15.4s, v15.4s, v17.4s\n" "srshl v14.4s, v14.4s, v17.4s\n" "srshl v13.4s, v13.4s, v17.4s\n" @@ -458,37 +457,39 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "add v14.4s, v14.4s, v16.4s\n" "add v13.4s, v13.4s, v16.4s\n" "add v12.4s, v12.4s, v16.4s\n" - "smax v15.4s, v15.4s, v21.4s\n" - "smax v14.4s, v14.4s, v21.4s\n" - "smax v13.4s, v13.4s, v21.4s\n" - "smin v15.4s, v15.4s, v19.4s\n" - "smin v14.4s, v14.4s, v19.4s\n" - "smin v13.4s, v13.4s, v19.4s\n" - "smax v12.4s, v12.4s, v21.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" - "smin v12.4s, v12.4s, v19.4s\n" + "movi v16.4s, #0x0\n" + "smax v15.4s, v15.4s, v16.4s\n" + "smax v14.4s, v14.4s, v16.4s\n" + "smax v13.4s, v13.4s, v16.4s\n" + "smax v12.4s, v12.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v15.4s, v15.4s, v16.4s\n" + "smin v14.4s, v14.4s, v16.4s\n" + "smin v13.4s, v13.4s, v16.4s\n" + "smin v12.4s, v12.4s, v16.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" - "str q16, [%x[outptr], x26]\n" - "add x26, x26, #0x10\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments "ld1r { v15.4s }, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" + "add %x[outptr], %x[outptr], x27\n" "mov v14.16b, v15.16b\n" - "add %x[outptr], %x[outptr], x26\n" "mov v13.16b, v15.16b\n" - "mov x19, %x[inptrs]\n" "mov v12.16b, v15.16b\n" - "lsr x22, %x[n_valid_cells], #0x1\n" - "cbz x22, 24f\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 24f\n" "15:" // Oddments: 2 inputs loop + "ldp x21, x20, [x22, #0x0]\n" + "add x22, x22, #0x10\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" + "add x20, x20, x27\n" "movi v30.16b, #0x0\n" - "add x21, x21, x26\n" - "add x20, x20, x26\n" "tbz %x[n_channels], #3, 19f\n" "ldr d31, [x21], #0x8\n" "ldr d30, [x20], #0x8\n" @@ -549,21 +550,21 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "ldr b31, [x21], #0x1\n" "ldr b30, [x20], #0x1\n" "23:" // Oddments: 2 inputs loop: Load: Bit 3: End - "uaddl v23.8h, v31.8b, v30.8b\n" - "subs x22, x22, #0x1\n" - "uaddl2 v22.8h, v31.16b, v30.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uaddl v17.8h, v31.8b, v30.8b\n" + "uaddl2 v16.8h, v31.16b, v30.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x23, %x[n_valid_cells], #0x1\n" "beq 34f\n" "25:" // Oddments: Single input loop + "ldr x21, [x22], #0x8\n" + "add x21, x21, x27\n" "movi v31.16b, #0x0\n" - "ldr x21, [x19], #0x8\n" - "add x21, x21, x26\n" "tbz %x[n_channels], #3, 29f\n" "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" @@ -609,30 +610,28 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 33f\n" "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "uxtl v23.8h, v31.8b\n" - "subs x20, x20, #0x1\n" - "uxtl2 v22.8h, v31.16b\n" - "uaddw v15.4s, v15.4s, v23.4h\n" - "uaddw2 v14.4s, v14.4s, v23.8h\n" - "uaddw v13.4s, v13.4s, v22.4h\n" - "uaddw2 v12.4s, v12.4s, v22.8h\n" + "uxtl v17.8h, v31.8b\n" + "uxtl2 v16.8h, v31.16b\n" + "subs x23, x23, #0x1\n" + "uaddw v15.4s, v15.4s, v17.4h\n" + "uaddw2 v14.4s, v14.4s, v17.8h\n" + "uaddw v13.4s, v13.4s, v16.4h\n" + "uaddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "movi v21.4s, #0x0\n" - "ld1r { v20.4s }, [%x[combined_rescale_value]]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "movi v19.4s, #0xff\n" - "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v16.4s }, [%x[left_shift]]\n" + "ld1r { v18.4s }, [%x[combined_rescale_value]]\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" "ld1r { v17.4s }, [%x[right_shift]]\n" - "srshl v15.4s, v15.4s, v18.4s\n" - "ld1r { v16.4s }, [x19]\n" - "srshl v14.4s, v14.4s, v18.4s\n" - "srshl v13.4s, v13.4s, v18.4s\n" - "srshl v12.4s, v12.4s, v18.4s\n" - "sqrdmulh v15.4s, v15.4s, v20.4s\n" - "sqrdmulh v14.4s, v14.4s, v20.4s\n" - "sqrdmulh v13.4s, v13.4s, v20.4s\n" - "sqrdmulh v12.4s, v12.4s, v20.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1r { v16.4s }, [x20]\n" + "sqrdmulh v15.4s, v15.4s, v18.4s\n" + "sqrdmulh v14.4s, v14.4s, v18.4s\n" + "sqrdmulh v13.4s, v13.4s, v18.4s\n" + "sqrdmulh v12.4s, v12.4s, v18.4s\n" "srshl v15.4s, v15.4s, v17.4s\n" "srshl v14.4s, v14.4s, v17.4s\n" "srshl v13.4s, v13.4s, v17.4s\n" @@ -641,17 +640,19 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "add v14.4s, v14.4s, v16.4s\n" "add v13.4s, v13.4s, v16.4s\n" "add v12.4s, v12.4s, v16.4s\n" - "smax v15.4s, v15.4s, v21.4s\n" - "smax v14.4s, v14.4s, v21.4s\n" - "smax v13.4s, v13.4s, v21.4s\n" - "smin v15.4s, v15.4s, v19.4s\n" - "smin v14.4s, v14.4s, v19.4s\n" - "smin v13.4s, v13.4s, v19.4s\n" - "smax v12.4s, v12.4s, v21.4s\n" - "uzp1 v23.16b, v15.16b, v14.16b\n" - "smin v12.4s, v12.4s, v19.4s\n" + "movi v16.4s, #0x0\n" + "smax v15.4s, v15.4s, v16.4s\n" + "smax v14.4s, v14.4s, v16.4s\n" + "smax v13.4s, v13.4s, v16.4s\n" + "smax v12.4s, v12.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v15.4s, v15.4s, v16.4s\n" + "smin v14.4s, v14.4s, v16.4s\n" + "smin v13.4s, v13.4s, v16.4s\n" + "smin v12.4s, v12.4s, v16.4s\n" + "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" - "uzp1 v16.16b, v23.16b, v16.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -697,12 +698,10 @@ void a64_u8q_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 42f\n" "st1 { v16.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [accumulator_init] "r" (&accumulator_init), [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [quant_params] "r" (&qp), [right_shift] "r" (&right_shift) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst.hpp index 1b97b458c0..fa9600f83d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,19 +33,11 @@ namespace pooling { void a64_u8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); -struct a64_u8q_nhwc_max_generic_depthfirst +struct a64_u8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = a64_u8q_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; a64_u8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return a64_u8q_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp index 0d196e097e..f4927c5536 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,8 @@ */ #include "pooling.hpp" -#include <cstddef> #include <cstdint> +#include <cstddef> #if defined(__aarch64__) @@ -42,583 +42,583 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "mov x28, #0x0\n" - "mov x27, #0x10\n" // cntb _, ALL, #1 - "mov x26, #0x20\n" // cntb _, ALL, #2 - "mov x25, #0x30\n" // cntb _, ALL, #3 "cmp %x[n_channels], #0x40\n" + "mov x27, #0x0\n" + "mov x26, #0x10\n" // cntb _, ALL, #1 + "mov x24, #0x20\n" // cntb _, ALL, #2 + "mov x23, #0x30\n" // cntb _, ALL, #3 "blt 7f\n" "1:" // 4-vectors of channels - "movi v4.16b, #0x0\n" - "mov x19, %x[inptrs]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" "movi v8.16b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "movi v7.16b, #0x0\n" + "mov x22, %x[inptrs]\n" "movi v6.16b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" - "ldr q31, [x23, x27]\n" - "ldr q30, [x22, x27]\n" - "ldr q29, [x21, x27]\n" - "ldr q28, [x20, x27]\n" - "ldr q27, [x23, x26]\n" - "ldr q21, [x22, x26]\n" - "ldr q26, [x21, x26]\n" - "ldr q17, [x20, x26]\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "movi v5.16b, #0x0\n" + "cbz x25, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldr q2, [x21, x26]\n" + "ldr q1, [x20, x26]\n" + "ldr q0, [x21, x24]\n" + "ldr q31, [x20, x24]\n" + "ldr q30, [x21, x23]\n" + "ldr q29, [x20, x23]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "umax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "umax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "umax v22.16b, v31.16b, v30.16b\n" - "ldr q3, [x23, x28]\n" - "umax v18.16b, v29.16b, v28.16b\n" - "umax v21.16b, v27.16b, v21.16b\n" - "ldr q2, [x22, x28]\n" - "umax v17.16b, v26.16b, v17.16b\n" - "ldr q1, [x21, x28]\n" - "umax v20.16b, v25.16b, v20.16b\n" - "ldr q0, [x20, x28]\n" - "umax v16.16b, v24.16b, v16.16b\n" - "ldr q31, [x23, x27]\n" + "umax v23.16b, v4.16b, v3.16b\n" + "umax v19.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "umax v22.16b, v2.16b, v1.16b\n" + "ldr q2, [x21, x26]\n" + "umax v18.16b, v27.16b, v21.16b\n" + "ldr q1, [x20, x26]\n" + "umax v21.16b, v0.16b, v31.16b\n" + "ldr q0, [x21, x24]\n" + "umax v17.16b, v26.16b, v20.16b\n" + "ldr q31, [x20, x24]\n" + "umax v20.16b, v30.16b, v29.16b\n" + "ldr q30, [x21, x23]\n" + "umax v16.16b, v25.16b, v24.16b\n" + "ldr q29, [x20, x23]\n" "umax v19.16b, v23.16b, v19.16b\n" - "ldr q30, [x22, x27]\n" "umax v18.16b, v22.16b, v18.16b\n" - "ldr q29, [x21, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "umax v17.16b, v21.16b, v17.16b\n" - "ldr q28, [x20, x27]\n" "umax v16.16b, v20.16b, v16.16b\n" - "ldr q27, [x23, x26]\n" - "umax v4.16b, v4.16b, v19.16b\n" - "ldr q21, [x22, x26]\n" - "umax v8.16b, v8.16b, v18.16b\n" - "ldr q26, [x21, x26]\n" - "umax v7.16b, v7.16b, v17.16b\n" - "ldr q17, [x20, x26]\n" - "umax v6.16b, v6.16b, v16.16b\n" - "ldr q25, [x23, x25]\n" - "ldr q20, [x22, x25]\n" - "ldr q24, [x21, x25]\n" - "ldr q16, [x20, x25]\n" + "ldr q27, [x21, x26]\n" + "ldr q21, [x20, x26]\n" + "subs x25, x25, #0x1\n" + "umax v8.16b, v8.16b, v19.16b\n" + "ldr q26, [x21, x24]\n" + "ldr q20, [x20, x24]\n" + "umax v7.16b, v7.16b, v18.16b\n" + "umax v6.16b, v6.16b, v17.16b\n" + "ldr q25, [x21, x23]\n" + "ldr q24, [x20, x23]\n" + "umax v5.16b, v5.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "umax v23.16b, v3.16b, v2.16b\n" - "umax v19.16b, v1.16b, v0.16b\n" - "umax v22.16b, v31.16b, v30.16b\n" - "umax v18.16b, v29.16b, v28.16b\n" - "umax v21.16b, v27.16b, v21.16b\n" - "umax v17.16b, v26.16b, v17.16b\n" - "umax v20.16b, v25.16b, v20.16b\n" - "umax v16.16b, v24.16b, v16.16b\n" + "umax v23.16b, v4.16b, v3.16b\n" + "umax v19.16b, v28.16b, v22.16b\n" + "umax v22.16b, v2.16b, v1.16b\n" + "umax v18.16b, v27.16b, v21.16b\n" + "umax v21.16b, v0.16b, v31.16b\n" + "umax v17.16b, v26.16b, v20.16b\n" + "umax v20.16b, v30.16b, v29.16b\n" + "umax v16.16b, v25.16b, v24.16b\n" "umax v19.16b, v23.16b, v19.16b\n" "umax v18.16b, v22.16b, v18.16b\n" "umax v17.16b, v21.16b, v17.16b\n" "umax v16.16b, v20.16b, v16.16b\n" - "umax v4.16b, v4.16b, v19.16b\n" - "umax v8.16b, v8.16b, v18.16b\n" - "umax v7.16b, v7.16b, v17.16b\n" - "umax v6.16b, v6.16b, v16.16b\n" + "umax v8.16b, v8.16b, v19.16b\n" + "umax v7.16b, v7.16b, v18.16b\n" + "umax v6.16b, v6.16b, v17.16b\n" + "umax v5.16b, v5.16b, v16.16b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "umax v4.16b, v4.16b, v3.16b\n" - "ldr q31, [x23, x27]\n" - "ldr q27, [x23, x26]\n" - "umax v8.16b, v8.16b, v31.16b\n" - "ldr q25, [x23, x25]\n" - "umax v7.16b, v7.16b, v27.16b\n" - "umax v6.16b, v6.16b, v25.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "umax v8.16b, v8.16b, v16.16b\n" + "ldr q17, [x20, x26]\n" + "ldr q16, [x20, x24]\n" + "umax v7.16b, v7.16b, v17.16b\n" + "umax v6.16b, v6.16b, v16.16b\n" + "ldr q16, [x20, x23]\n" + "umax v5.16b, v5.16b, v16.16b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "uxtl v17.8h, v4.8b\n" - "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1r { v5.4s }, [x19]\n" - "uxtl2 v16.8h, v4.16b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "uxtl v21.8h, v8.8b\n" - "ld1r { v4.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "uxtl2 v20.8h, v8.16b\n" - "ld1r { v3.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "uxtl v19.8h, v7.8b\n" - "ld1r { v2.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "uxtl2 v24.8h, v7.16b\n" - "ld1r { v1.4s }, [x19]\n" + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1r { v4.4s }, [x20]\n" + "uxtl v23.8h, v8.8b\n" + "uxtl2 v24.8h, v8.16b\n" + "uxtl v22.8h, v7.8b\n" + "uxtl2 v21.8h, v7.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1r { v3.4s }, [x20]\n" + "uxtl v20.8h, v6.8b\n" + "uxtl2 v17.8h, v6.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1r { v2.4s }, [x20]\n" + "uxtl v19.8h, v5.8b\n" + "uxtl2 v18.8h, v5.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1r { v1.4s }, [x20]\n" + "neg v4.4s, v4.4s\n" + "saddw v0.4s, v4.4s, v23.4h\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1r { v16.4s }, [x20]\n" + "saddw2 v23.4s, v4.4s, v23.8h\n" + "saddw v31.4s, v4.4s, v24.4h\n" "sub %x[n_channels], %x[n_channels], #0x40\n" - "uxtl v0.8h, v6.8b\n" "cmp %x[n_channels], #0x40\n" - "uxtl2 v31.8h, v6.16b\n" - "neg v5.4s, v5.4s\n" - "movi v30.4s, #0x0\n" - "movi v29.4s, #0xff\n" - "saddw v23.4s, v5.4s, v17.4h\n" - "saddw2 v18.4s, v5.4s, v17.8h\n" - "saddw v17.4s, v5.4s, v16.4h\n" - "saddw2 v16.4s, v5.4s, v16.8h\n" - "saddw v22.4s, v5.4s, v21.4h\n" - "saddw2 v21.4s, v5.4s, v21.8h\n" - "saddw v28.4s, v5.4s, v20.4h\n" - "saddw2 v20.4s, v5.4s, v20.8h\n" - "saddw v27.4s, v5.4s, v19.4h\n" - "saddw2 v19.4s, v5.4s, v19.8h\n" + "saddw2 v30.4s, v4.4s, v24.8h\n" + "saddw v29.4s, v4.4s, v22.4h\n" + "saddw2 v22.4s, v4.4s, v22.8h\n" + "saddw v28.4s, v4.4s, v21.4h\n" + "saddw2 v21.4s, v4.4s, v21.8h\n" + "saddw v27.4s, v4.4s, v20.4h\n" + "saddw2 v20.4s, v4.4s, v20.8h\n" + "saddw v26.4s, v4.4s, v17.4h\n" + "saddw2 v17.4s, v4.4s, v17.8h\n" + "saddw v25.4s, v4.4s, v19.4h\n" + "saddw2 v19.4s, v4.4s, v19.8h\n" + "saddw v24.4s, v4.4s, v18.4h\n" + "saddw2 v18.4s, v4.4s, v18.8h\n" + "srshl v0.4s, v0.4s, v3.4s\n" "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v18.4s, v18.4s, v3.4s\n" - "srshl v17.4s, v17.4s, v3.4s\n" - "srshl v16.4s, v16.4s, v3.4s\n" - "sqrdmulh v23.4s, v23.4s, v4.4s\n" - "sqrdmulh v18.4s, v18.4s, v4.4s\n" - "sqrdmulh v17.4s, v17.4s, v4.4s\n" - "sqrdmulh v16.4s, v16.4s, v4.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v18.4s, v18.4s, v2.4s\n" - "srshl v17.4s, v17.4s, v2.4s\n" - "srshl v16.4s, v16.4s, v2.4s\n" + "srshl v31.4s, v31.4s, v3.4s\n" + "srshl v30.4s, v30.4s, v3.4s\n" + "srshl v29.4s, v29.4s, v3.4s\n" "srshl v22.4s, v22.4s, v3.4s\n" - "srshl v21.4s, v21.4s, v3.4s\n" "srshl v28.4s, v28.4s, v3.4s\n" - "srshl v20.4s, v20.4s, v3.4s\n" - "sqrdmulh v22.4s, v22.4s, v4.4s\n" - "sqrdmulh v21.4s, v21.4s, v4.4s\n" - "sqrdmulh v28.4s, v28.4s, v4.4s\n" - "sqrdmulh v20.4s, v20.4s, v4.4s\n" - "srshl v22.4s, v22.4s, v2.4s\n" - "srshl v21.4s, v21.4s, v2.4s\n" - "srshl v28.4s, v28.4s, v2.4s\n" - "srshl v20.4s, v20.4s, v2.4s\n" + "srshl v21.4s, v21.4s, v3.4s\n" "srshl v27.4s, v27.4s, v3.4s\n" - "srshl v19.4s, v19.4s, v3.4s\n" - "add v23.4s, v23.4s, v1.4s\n" - "add v18.4s, v18.4s, v1.4s\n" - "sqrdmulh v27.4s, v27.4s, v4.4s\n" - "sqrdmulh v19.4s, v19.4s, v4.4s\n" - "add v17.4s, v17.4s, v1.4s\n" - "add v16.4s, v16.4s, v1.4s\n" - "srshl v27.4s, v27.4s, v2.4s\n" - "srshl v19.4s, v19.4s, v2.4s\n" - "add v22.4s, v22.4s, v1.4s\n" - "add v21.4s, v21.4s, v1.4s\n" - "add v28.4s, v28.4s, v1.4s\n" - "add v20.4s, v20.4s, v1.4s\n" - "add v27.4s, v27.4s, v1.4s\n" - "add v19.4s, v19.4s, v1.4s\n" - "smax v23.4s, v23.4s, v30.4s\n" - "smax v18.4s, v18.4s, v30.4s\n" - "smax v17.4s, v17.4s, v30.4s\n" - "smin v23.4s, v23.4s, v29.4s\n" - "smin v18.4s, v18.4s, v29.4s\n" - "smin v17.4s, v17.4s, v29.4s\n" - "smax v16.4s, v16.4s, v30.4s\n" - "smax v22.4s, v22.4s, v30.4s\n" - "smax v21.4s, v21.4s, v30.4s\n" - "smin v16.4s, v16.4s, v29.4s\n" - "smin v22.4s, v22.4s, v29.4s\n" - "smin v21.4s, v21.4s, v29.4s\n" - "smax v28.4s, v28.4s, v30.4s\n" - "smax v20.4s, v20.4s, v30.4s\n" - "smax v27.4s, v27.4s, v30.4s\n" - "smin v28.4s, v28.4s, v29.4s\n" - "smin v20.4s, v20.4s, v29.4s\n" - "smin v27.4s, v27.4s, v29.4s\n" - "smax v19.4s, v19.4s, v30.4s\n" - "uzp1 v26.16b, v23.16b, v18.16b\n" - "saddw v25.4s, v5.4s, v24.4h\n" - "saddw2 v18.4s, v5.4s, v24.8h\n" - "smin v19.4s, v19.4s, v29.4s\n" + "srshl v20.4s, v20.4s, v3.4s\n" + "srshl v26.4s, v26.4s, v3.4s\n" + "srshl v17.4s, v17.4s, v3.4s\n" "srshl v25.4s, v25.4s, v3.4s\n" + "srshl v19.4s, v19.4s, v3.4s\n" + "srshl v24.4s, v24.4s, v3.4s\n" "srshl v18.4s, v18.4s, v3.4s\n" - "uzp1 v24.16b, v17.16b, v16.16b\n" - "saddw v17.4s, v5.4s, v0.4h\n" - "saddw2 v16.4s, v5.4s, v0.8h\n" - "sqrdmulh v25.4s, v25.4s, v4.4s\n" - "sqrdmulh v18.4s, v18.4s, v4.4s\n" - "srshl v17.4s, v17.4s, v3.4s\n" - "srshl v16.4s, v16.4s, v3.4s\n" - "srshl v25.4s, v25.4s, v2.4s\n" - "srshl v18.4s, v18.4s, v2.4s\n" - "sqrdmulh v17.4s, v17.4s, v4.4s\n" - "sqrdmulh v16.4s, v16.4s, v4.4s\n" - "add v25.4s, v25.4s, v1.4s\n" - "add v18.4s, v18.4s, v1.4s\n" - "srshl v17.4s, v17.4s, v2.4s\n" - "srshl v16.4s, v16.4s, v2.4s\n" - "smax v25.4s, v25.4s, v30.4s\n" - "smax v18.4s, v18.4s, v30.4s\n" - "add v17.4s, v17.4s, v1.4s\n" - "add v16.4s, v16.4s, v1.4s\n" - "smin v25.4s, v25.4s, v29.4s\n" - "smin v18.4s, v18.4s, v29.4s\n" - "smax v17.4s, v17.4s, v30.4s\n" - "smax v16.4s, v16.4s, v30.4s\n" - "uzp1 v23.16b, v22.16b, v21.16b\n" - "saddw v22.4s, v5.4s, v31.4h\n" - "saddw2 v21.4s, v5.4s, v31.8h\n" - "smin v17.4s, v17.4s, v29.4s\n" - "srshl v22.4s, v22.4s, v3.4s\n" - "srshl v21.4s, v21.4s, v3.4s\n" - "smin v16.4s, v16.4s, v29.4s\n" - "uzp1 v20.16b, v28.16b, v20.16b\n" - "sqrdmulh v22.4s, v22.4s, v4.4s\n" - "sqrdmulh v21.4s, v21.4s, v4.4s\n" - "uzp1 v19.16b, v27.16b, v19.16b\n" - "uzp1 v18.16b, v25.16b, v18.16b\n" - "srshl v22.4s, v22.4s, v2.4s\n" - "srshl v21.4s, v21.4s, v2.4s\n" - "uzp1 v17.16b, v17.16b, v16.16b\n" - "uzp1 v16.16b, v26.16b, v24.16b\n" - "str q16, [%x[outptr], x28]\n" - "add v22.4s, v22.4s, v1.4s\n" - "add x28, x28, #0x40\n" - "add v21.4s, v21.4s, v1.4s\n" - "uzp1 v16.16b, v23.16b, v20.16b\n" + "sqrdmulh v0.4s, v0.4s, v2.4s\n" + "sqrdmulh v23.4s, v23.4s, v2.4s\n" + "sqrdmulh v31.4s, v31.4s, v2.4s\n" + "sqrdmulh v30.4s, v30.4s, v2.4s\n" + "sqrdmulh v29.4s, v29.4s, v2.4s\n" + "sqrdmulh v22.4s, v22.4s, v2.4s\n" + "sqrdmulh v28.4s, v28.4s, v2.4s\n" + "sqrdmulh v21.4s, v21.4s, v2.4s\n" + "sqrdmulh v27.4s, v27.4s, v2.4s\n" + "sqrdmulh v20.4s, v20.4s, v2.4s\n" + "sqrdmulh v26.4s, v26.4s, v2.4s\n" + "sqrdmulh v17.4s, v17.4s, v2.4s\n" + "sqrdmulh v25.4s, v25.4s, v2.4s\n" + "sqrdmulh v19.4s, v19.4s, v2.4s\n" + "sqrdmulh v24.4s, v24.4s, v2.4s\n" + "sqrdmulh v18.4s, v18.4s, v2.4s\n" + "srshl v0.4s, v0.4s, v1.4s\n" + "srshl v23.4s, v23.4s, v1.4s\n" + "srshl v31.4s, v31.4s, v1.4s\n" + "srshl v30.4s, v30.4s, v1.4s\n" + "srshl v29.4s, v29.4s, v1.4s\n" + "srshl v22.4s, v22.4s, v1.4s\n" + "srshl v28.4s, v28.4s, v1.4s\n" + "srshl v21.4s, v21.4s, v1.4s\n" + "srshl v27.4s, v27.4s, v1.4s\n" + "srshl v20.4s, v20.4s, v1.4s\n" + "srshl v26.4s, v26.4s, v1.4s\n" + "srshl v17.4s, v17.4s, v1.4s\n" + "srshl v25.4s, v25.4s, v1.4s\n" + "srshl v19.4s, v19.4s, v1.4s\n" + "srshl v24.4s, v24.4s, v1.4s\n" + "srshl v18.4s, v18.4s, v1.4s\n" + "add v0.4s, v0.4s, v16.4s\n" + "add v23.4s, v23.4s, v16.4s\n" + "add v31.4s, v31.4s, v16.4s\n" + "add v30.4s, v30.4s, v16.4s\n" + "add v29.4s, v29.4s, v16.4s\n" + "add v22.4s, v22.4s, v16.4s\n" + "add v28.4s, v28.4s, v16.4s\n" + "add v21.4s, v21.4s, v16.4s\n" + "add v27.4s, v27.4s, v16.4s\n" + "add v20.4s, v20.4s, v16.4s\n" + "add v26.4s, v26.4s, v16.4s\n" + "add v17.4s, v17.4s, v16.4s\n" + "add v25.4s, v25.4s, v16.4s\n" + "add v19.4s, v19.4s, v16.4s\n" + "add v24.4s, v24.4s, v16.4s\n" + "add v18.4s, v18.4s, v16.4s\n" + "movi v16.4s, #0x0\n" + "smax v0.4s, v0.4s, v16.4s\n" + "smax v23.4s, v23.4s, v16.4s\n" + "smax v31.4s, v31.4s, v16.4s\n" + "smax v30.4s, v30.4s, v16.4s\n" + "smax v29.4s, v29.4s, v16.4s\n" + "smax v22.4s, v22.4s, v16.4s\n" + "smax v28.4s, v28.4s, v16.4s\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v27.4s, v27.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v26.4s, v26.4s, v16.4s\n" + "smax v17.4s, v17.4s, v16.4s\n" + "smax v25.4s, v25.4s, v16.4s\n" + "smax v19.4s, v19.4s, v16.4s\n" + "smax v24.4s, v24.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v0.4s, v0.4s, v16.4s\n" + "smin v23.4s, v23.4s, v16.4s\n" + "smin v31.4s, v31.4s, v16.4s\n" + "smin v30.4s, v30.4s, v16.4s\n" + "smin v29.4s, v29.4s, v16.4s\n" + "smin v22.4s, v22.4s, v16.4s\n" + "smin v28.4s, v28.4s, v16.4s\n" + "smin v21.4s, v21.4s, v16.4s\n" + "smin v27.4s, v27.4s, v16.4s\n" + "smin v20.4s, v20.4s, v16.4s\n" + "smin v26.4s, v26.4s, v16.4s\n" + "smin v17.4s, v17.4s, v16.4s\n" + "smin v25.4s, v25.4s, v16.4s\n" + "smin v19.4s, v19.4s, v16.4s\n" + "smin v24.4s, v24.4s, v16.4s\n" + "smin v18.4s, v18.4s, v16.4s\n" + "uzp1 v23.16b, v0.16b, v23.16b\n" + "uzp1 v16.16b, v31.16b, v30.16b\n" + "uzp1 v22.16b, v29.16b, v22.16b\n" + "uzp1 v21.16b, v28.16b, v21.16b\n" + "uzp1 v20.16b, v27.16b, v20.16b\n" + "uzp1 v17.16b, v26.16b, v17.16b\n" + "uzp1 v19.16b, v25.16b, v19.16b\n" + "uzp1 v18.16b, v24.16b, v18.16b\n" + "uzp1 v16.16b, v23.16b, v16.16b\n" "str q16, [%x[outptr], x27]\n" - "smax v22.4s, v22.4s, v30.4s\n" "add x27, x27, #0x40\n" - "smax v21.4s, v21.4s, v30.4s\n" - "uzp1 v16.16b, v19.16b, v18.16b\n" + "uzp1 v16.16b, v22.16b, v21.16b\n" + "uzp1 v17.16b, v20.16b, v17.16b\n" "str q16, [%x[outptr], x26]\n" - "smin v22.4s, v22.4s, v29.4s\n" "add x26, x26, #0x40\n" - "smin v21.4s, v21.4s, v29.4s\n" - "uzp1 v16.16b, v22.16b, v21.16b\n" - "uzp1 v16.16b, v17.16b, v16.16b\n" - "str q16, [%x[outptr], x25]\n" - "add x25, x25, #0x40\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" + "str q17, [%x[outptr], x24]\n" + "add x24, x24, #0x40\n" + "str q16, [%x[outptr], x23]\n" + "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" "7:" // Single vector of channels "cmp %x[n_channels], #0x10\n" "blt 14f\n" "8:" // Single vector of channels: Loop - "movi v4.16b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "movi v8.16b, #0x0\n" + "mov x22, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "subs x25, x25, #0x1\n" + "ldr q3, [x20, x27]\n" + "ldp x21, x20, [x22, #0x10]\n" + "add x22, x22, #0x20\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "umax v23.16b, v3.16b, v2.16b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "umax v19.16b, v1.16b, v0.16b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "umax v19.16b, v23.16b, v19.16b\n" - "ldr q3, [x23, x28]\n" - "ldr q2, [x22, x28]\n" - "umax v4.16b, v4.16b, v19.16b\n" - "ldr q1, [x21, x28]\n" - "ldr q0, [x20, x28]\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "ldp x21, x20, [x22, #0x0]\n" + "ldr q4, [x21, x27]\n" + "ldr q3, [x20, x27]\n" + "umax v16.16b, v17.16b, v16.16b\n" + "ldp x21, x20, [x22, #0x10]\n" + "subs x25, x25, #0x1\n" + "ldr q28, [x21, x27]\n" + "ldr q22, [x20, x27]\n" + "umax v8.16b, v8.16b, v16.16b\n" + "add x22, x22, #0x20\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "umax v23.16b, v3.16b, v2.16b\n" - "umax v19.16b, v1.16b, v0.16b\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v4.16b, v4.16b, v19.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ldr q3, [x23, x28]\n" - "umax v4.16b, v4.16b, v3.16b\n" + "ldr x20, [x22], #0x8\n" + "ldr q16, [x20, x27]\n" + "subs x21, x21, #0x1\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "uxtl v17.8h, v4.8b\n" - "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1r { v5.4s }, [x19]\n" - "uxtl2 v16.8h, v4.16b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "movi v30.4s, #0x0\n" - "ld1r { v4.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "movi v29.4s, #0xff\n" - "ld1r { v3.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "neg v5.4s, v5.4s\n" - "ld1r { v2.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "saddw v23.4s, v5.4s, v17.4h\n" - "ld1r { v1.4s }, [x19]\n" + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1r { v18.4s }, [x20]\n" + "uxtl v17.8h, v8.8b\n" + "uxtl2 v16.8h, v8.16b\n" + "neg v18.4s, v18.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1r { v23.4s }, [x20]\n" + "saddw v22.4s, v18.4s, v17.4h\n" + "saddw2 v21.4s, v18.4s, v17.8h\n" + "saddw v20.4s, v18.4s, v16.4h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1r { v19.4s }, [x20]\n" + "saddw2 v18.4s, v18.4s, v16.8h\n" + "srshl v22.4s, v22.4s, v23.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1r { v17.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v23.4s\n" + "srshl v20.4s, v20.4s, v23.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v18.4s, v18.4s, v23.4s\n" + "sqrdmulh v22.4s, v22.4s, v19.4s\n" "sub %x[n_channels], %x[n_channels], #0x10\n" - "saddw2 v18.4s, v5.4s, v17.8h\n" "cmp %x[n_channels], #0x10\n" - "saddw v17.4s, v5.4s, v16.4h\n" - "saddw2 v16.4s, v5.4s, v16.8h\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v18.4s, v18.4s, v3.4s\n" - "srshl v17.4s, v17.4s, v3.4s\n" - "srshl v16.4s, v16.4s, v3.4s\n" - "sqrdmulh v23.4s, v23.4s, v4.4s\n" - "sqrdmulh v18.4s, v18.4s, v4.4s\n" - "sqrdmulh v17.4s, v17.4s, v4.4s\n" - "sqrdmulh v16.4s, v16.4s, v4.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v18.4s, v18.4s, v2.4s\n" - "srshl v17.4s, v17.4s, v2.4s\n" - "srshl v16.4s, v16.4s, v2.4s\n" - "add v23.4s, v23.4s, v1.4s\n" - "add v18.4s, v18.4s, v1.4s\n" - "add v17.4s, v17.4s, v1.4s\n" - "add v16.4s, v16.4s, v1.4s\n" - "smax v23.4s, v23.4s, v30.4s\n" - "smax v18.4s, v18.4s, v30.4s\n" - "smax v17.4s, v17.4s, v30.4s\n" - "smin v23.4s, v23.4s, v29.4s\n" - "smin v18.4s, v18.4s, v29.4s\n" - "smin v17.4s, v17.4s, v29.4s\n" - "smax v16.4s, v16.4s, v30.4s\n" - "uzp1 v26.16b, v23.16b, v18.16b\n" - "smin v16.4s, v16.4s, v29.4s\n" - "uzp1 v24.16b, v17.16b, v16.16b\n" - "uzp1 v16.16b, v26.16b, v24.16b\n" - "str q16, [%x[outptr], x28]\n" - "add x28, x28, #0x10\n" + "sqrdmulh v21.4s, v21.4s, v19.4s\n" + "sqrdmulh v20.4s, v20.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" + "srshl v22.4s, v22.4s, v17.4s\n" + "srshl v21.4s, v21.4s, v17.4s\n" + "srshl v20.4s, v20.4s, v17.4s\n" + "srshl v18.4s, v18.4s, v17.4s\n" + "add v22.4s, v22.4s, v16.4s\n" + "add v21.4s, v21.4s, v16.4s\n" + "add v20.4s, v20.4s, v16.4s\n" + "add v18.4s, v18.4s, v16.4s\n" + "movi v16.4s, #0x0\n" + "smax v22.4s, v22.4s, v16.4s\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v22.4s, v22.4s, v16.4s\n" + "smin v21.4s, v21.4s, v16.4s\n" + "smin v20.4s, v20.4s, v16.4s\n" + "smin v18.4s, v18.4s, v16.4s\n" + "uzp1 v17.16b, v22.16b, v21.16b\n" + "uzp1 v16.16b, v20.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" + "str q16, [%x[outptr], x27]\n" + "add x27, x27, #0x10\n" "bge 8b\n" "cbz %x[n_channels], 43f\n" "14:" // Oddments - "movi v4.16b, #0x0\n" - "add %x[outptr], %x[outptr], x28\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 24f\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "add %x[outptr], %x[outptr], x27\n" + "movi v8.16b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 24f\n" "15:" // Oddments: 4 inputs loop + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "add x23, x23, x27\n" + "add x22, x22, x27\n" + "add x21, x21, x27\n" + "movi v4.16b, #0x0\n" "movi v3.16b, #0x0\n" - "ldp x23, x22, [x19, #0x0]\n" - "add x23, x23, x28\n" - "movi v2.16b, #0x0\n" - "ldp x21, x20, [x19, #0x10]\n" - "movi v1.16b, #0x0\n" - "add x19, x19, #0x20\n" - "movi v0.16b, #0x0\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "add x20, x20, x28\n" + "add x20, x20, x27\n" + "movi v28.16b, #0x0\n" + "movi v22.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" - "ldr d3, [x23], #0x8\n" - "ldr d2, [x22], #0x8\n" - "ldr d1, [x21], #0x8\n" - "ldr d0, [x20], #0x8\n" + "ldr d4, [x23], #0x8\n" + "ldr d3, [x22], #0x8\n" + "ldr d28, [x21], #0x8\n" + "ldr d22, [x20], #0x8\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" - "ld1 { v2.s }[2], [x22], #0x4\n" - "ld1 { v1.s }[2], [x21], #0x4\n" - "ld1 { v0.s }[2], [x20], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" + "ld1 { v3.s }[2], [x22], #0x4\n" + "ld1 { v28.s }[2], [x21], #0x4\n" + "ld1 { v22.s }[2], [x20], #0x4\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" - "ld1 { v2.h }[6], [x22], #0x2\n" - "ld1 { v1.h }[6], [x21], #0x2\n" - "ld1 { v0.h }[6], [x20], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" + "ld1 { v3.h }[6], [x22], #0x2\n" + "ld1 { v28.h }[6], [x21], #0x2\n" + "ld1 { v22.h }[6], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" - "ld1 { v2.b }[14], [x22], #0x1\n" - "ld1 { v1.b }[14], [x21], #0x1\n" - "ld1 { v0.b }[14], [x20], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" + "ld1 { v3.b }[14], [x22], #0x1\n" + "ld1 { v28.b }[14], [x21], #0x1\n" + "ld1 { v22.b }[14], [x20], #0x1\n" "b 23f\n" "16:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" - "ld1 { v2.b }[12], [x22], #0x1\n" - "ld1 { v1.b }[12], [x21], #0x1\n" - "ld1 { v0.b }[12], [x20], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" + "ld1 { v3.b }[12], [x22], #0x1\n" + "ld1 { v28.b }[12], [x21], #0x1\n" + "ld1 { v22.b }[12], [x20], #0x1\n" "b 23f\n" "17:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" - "ld1 { v2.h }[4], [x22], #0x2\n" - "ld1 { v1.h }[4], [x21], #0x2\n" - "ld1 { v0.h }[4], [x20], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" + "ld1 { v3.h }[4], [x22], #0x2\n" + "ld1 { v28.h }[4], [x21], #0x2\n" + "ld1 { v22.h }[4], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" - "ld1 { v2.b }[10], [x22], #0x1\n" - "ld1 { v1.b }[10], [x21], #0x1\n" - "ld1 { v0.b }[10], [x20], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" + "ld1 { v3.b }[10], [x22], #0x1\n" + "ld1 { v28.b }[10], [x21], #0x1\n" + "ld1 { v22.b }[10], [x20], #0x1\n" "b 23f\n" "18:" // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" - "ld1 { v2.b }[8], [x22], #0x1\n" - "ld1 { v1.b }[8], [x21], #0x1\n" - "ld1 { v0.b }[8], [x20], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" + "ld1 { v3.b }[8], [x22], #0x1\n" + "ld1 { v28.b }[8], [x21], #0x1\n" + "ld1 { v22.b }[8], [x20], #0x1\n" "b 23f\n" "19:" // Oddments: 4 inputs loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 21f\n" - "ldr s3, [x23], #0x4\n" - "ldr s2, [x22], #0x4\n" - "ldr s1, [x21], #0x4\n" - "ldr s0, [x20], #0x4\n" + "ldr s4, [x23], #0x4\n" + "ldr s3, [x22], #0x4\n" + "ldr s28, [x21], #0x4\n" + "ldr s22, [x20], #0x4\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" - "ld1 { v2.h }[2], [x22], #0x2\n" - "ld1 { v1.h }[2], [x21], #0x2\n" - "ld1 { v0.h }[2], [x20], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" + "ld1 { v3.h }[2], [x22], #0x2\n" + "ld1 { v28.h }[2], [x21], #0x2\n" + "ld1 { v22.h }[2], [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" - "ld1 { v2.b }[6], [x22], #0x1\n" - "ld1 { v1.b }[6], [x21], #0x1\n" - "ld1 { v0.b }[6], [x20], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" + "ld1 { v3.b }[6], [x22], #0x1\n" + "ld1 { v28.b }[6], [x21], #0x1\n" + "ld1 { v22.b }[6], [x20], #0x1\n" "b 23f\n" "20:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" - "ld1 { v2.b }[4], [x22], #0x1\n" - "ld1 { v1.b }[4], [x21], #0x1\n" - "ld1 { v0.b }[4], [x20], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" + "ld1 { v3.b }[4], [x22], #0x1\n" + "ld1 { v28.b }[4], [x21], #0x1\n" + "ld1 { v22.b }[4], [x20], #0x1\n" "b 23f\n" "21:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ldr h3, [x23], #0x2\n" - "ldr h2, [x22], #0x2\n" - "ldr h1, [x21], #0x2\n" - "ldr h0, [x20], #0x2\n" + "ldr h4, [x23], #0x2\n" + "ldr h3, [x22], #0x2\n" + "ldr h28, [x21], #0x2\n" + "ldr h22, [x20], #0x2\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" - "ld1 { v2.b }[2], [x22], #0x1\n" - "ld1 { v1.b }[2], [x21], #0x1\n" - "ld1 { v0.b }[2], [x20], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" + "ld1 { v3.b }[2], [x22], #0x1\n" + "ld1 { v28.b }[2], [x21], #0x1\n" + "ld1 { v22.b }[2], [x20], #0x1\n" "b 23f\n" "22:" // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ldr b3, [x23], #0x1\n" - "ldr b2, [x22], #0x1\n" - "ldr b1, [x21], #0x1\n" - "ldr b0, [x20], #0x1\n" + "ldr b4, [x23], #0x1\n" + "ldr b3, [x22], #0x1\n" + "ldr b28, [x21], #0x1\n" + "ldr b22, [x20], #0x1\n" "23:" // Oddments: 4 inputs loop: Load: Bit 3: End - "umax v23.16b, v3.16b, v2.16b\n" - "subs x24, x24, #0x1\n" - "umax v19.16b, v1.16b, v0.16b\n" - "umax v19.16b, v23.16b, v19.16b\n" - "umax v4.16b, v4.16b, v19.16b\n" + "umax v17.16b, v4.16b, v3.16b\n" + "umax v16.16b, v28.16b, v22.16b\n" + "subs x25, x25, #0x1\n" + "umax v16.16b, v17.16b, v16.16b\n" + "umax v8.16b, v8.16b, v16.16b\n" "bgt 15b\n" "24:" // Oddments: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 34f\n" "25:" // Oddments: Single input loop - "movi v3.16b, #0x0\n" - "ldr x23, [x19], #0x8\n" - "add x23, x23, x28\n" + "ldr x23, [x24], #0x8\n" + "add x23, x23, x27\n" + "movi v4.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" - "ldr d3, [x23], #0x8\n" + "ldr d4, [x23], #0x8\n" "tbz %x[n_channels], #2, 27f\n" - "ld1 { v3.s }[2], [x23], #0x4\n" + "ld1 { v4.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #1, 26f\n" - "ld1 { v3.h }[6], [x23], #0x2\n" + "ld1 { v4.h }[6], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[14], [x23], #0x1\n" + "ld1 { v4.b }[14], [x23], #0x1\n" "b 33f\n" "26:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[12], [x23], #0x1\n" + "ld1 { v4.b }[12], [x23], #0x1\n" "b 33f\n" "27:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset "tbz %x[n_channels], #1, 28f\n" - "ld1 { v3.h }[4], [x23], #0x2\n" + "ld1 { v4.h }[4], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[10], [x23], #0x1\n" + "ld1 { v4.b }[10], [x23], #0x1\n" "b 33f\n" "28:" // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[8], [x23], #0x1\n" + "ld1 { v4.b }[8], [x23], #0x1\n" "b 33f\n" "29:" // Oddments: Single input loop: Load: Bit 3: Unset "tbz %x[n_channels], #2, 31f\n" - "ldr s3, [x23], #0x4\n" + "ldr s4, [x23], #0x4\n" "tbz %x[n_channels], #1, 30f\n" - "ld1 { v3.h }[2], [x23], #0x2\n" + "ld1 { v4.h }[2], [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[6], [x23], #0x1\n" + "ld1 { v4.b }[6], [x23], #0x1\n" "b 33f\n" "30:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[4], [x23], #0x1\n" + "ld1 { v4.b }[4], [x23], #0x1\n" "b 33f\n" "31:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset "tbz %x[n_channels], #1, 32f\n" - "ldr h3, [x23], #0x2\n" + "ldr h4, [x23], #0x2\n" "tbz %x[n_channels], #0, 33f\n" - "ld1 { v3.b }[2], [x23], #0x1\n" + "ld1 { v4.b }[2], [x23], #0x1\n" "b 33f\n" "32:" // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset "tbz %x[n_channels], #0, 33f\n" - "ldr b3, [x23], #0x1\n" + "ldr b4, [x23], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "umax v4.16b, v4.16b, v3.16b\n" - "subs x20, x20, #0x1\n" + "subs x21, x21, #0x1\n" + "umax v8.16b, v8.16b, v4.16b\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "uxtl v17.8h, v4.8b\n" - "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1r { v5.4s }, [x19]\n" - "uxtl2 v16.8h, v4.16b\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "movi v30.4s, #0x0\n" - "ld1r { v4.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - "movi v29.4s, #0xff\n" - "ld1r { v3.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "neg v5.4s, v5.4s\n" - "ld1r { v2.4s }, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "saddw v23.4s, v5.4s, v17.4h\n" - "ld1r { v1.4s }, [x19]\n" - "saddw2 v18.4s, v5.4s, v17.8h\n" - "saddw v17.4s, v5.4s, v16.4h\n" - "saddw2 v16.4s, v5.4s, v16.8h\n" - "srshl v23.4s, v23.4s, v3.4s\n" - "srshl v18.4s, v18.4s, v3.4s\n" - "srshl v17.4s, v17.4s, v3.4s\n" - "srshl v16.4s, v16.4s, v3.4s\n" - "sqrdmulh v23.4s, v23.4s, v4.4s\n" - "sqrdmulh v18.4s, v18.4s, v4.4s\n" - "sqrdmulh v17.4s, v17.4s, v4.4s\n" - "sqrdmulh v16.4s, v16.4s, v4.4s\n" - "srshl v23.4s, v23.4s, v2.4s\n" - "srshl v18.4s, v18.4s, v2.4s\n" - "srshl v17.4s, v17.4s, v2.4s\n" - "srshl v16.4s, v16.4s, v2.4s\n" - "add v23.4s, v23.4s, v1.4s\n" - "add v18.4s, v18.4s, v1.4s\n" - "add v17.4s, v17.4s, v1.4s\n" - "add v16.4s, v16.4s, v1.4s\n" - "smax v23.4s, v23.4s, v30.4s\n" - "smax v18.4s, v18.4s, v30.4s\n" - "smax v17.4s, v17.4s, v30.4s\n" - "smin v23.4s, v23.4s, v29.4s\n" - "smin v18.4s, v18.4s, v29.4s\n" - "smin v17.4s, v17.4s, v29.4s\n" - "smax v16.4s, v16.4s, v30.4s\n" - "uzp1 v26.16b, v23.16b, v18.16b\n" - "smin v16.4s, v16.4s, v29.4s\n" - "uzp1 v24.16b, v17.16b, v16.16b\n" - "uzp1 v16.16b, v26.16b, v24.16b\n" + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1r { v18.4s }, [x20]\n" + "uxtl v17.8h, v8.8b\n" + "uxtl2 v16.8h, v8.16b\n" + "neg v18.4s, v18.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1r { v23.4s }, [x20]\n" + "saddw v22.4s, v18.4s, v17.4h\n" + "saddw2 v21.4s, v18.4s, v17.8h\n" + "saddw v20.4s, v18.4s, v16.4h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1r { v19.4s }, [x20]\n" + "saddw2 v18.4s, v18.4s, v16.8h\n" + "srshl v22.4s, v22.4s, v23.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1r { v17.4s }, [x20]\n" + "srshl v21.4s, v21.4s, v23.4s\n" + "srshl v20.4s, v20.4s, v23.4s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1r { v16.4s }, [x20]\n" + "srshl v18.4s, v18.4s, v23.4s\n" + "sqrdmulh v22.4s, v22.4s, v19.4s\n" + "sqrdmulh v21.4s, v21.4s, v19.4s\n" + "sqrdmulh v20.4s, v20.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" + "srshl v22.4s, v22.4s, v17.4s\n" + "srshl v21.4s, v21.4s, v17.4s\n" + "srshl v20.4s, v20.4s, v17.4s\n" + "srshl v18.4s, v18.4s, v17.4s\n" + "add v22.4s, v22.4s, v16.4s\n" + "add v21.4s, v21.4s, v16.4s\n" + "add v20.4s, v20.4s, v16.4s\n" + "add v18.4s, v18.4s, v16.4s\n" + "movi v16.4s, #0x0\n" + "smax v22.4s, v22.4s, v16.4s\n" + "smax v21.4s, v21.4s, v16.4s\n" + "smax v20.4s, v20.4s, v16.4s\n" + "smax v18.4s, v18.4s, v16.4s\n" + "movi v16.4s, #0xff\n" + "smin v22.4s, v22.4s, v16.4s\n" + "smin v21.4s, v21.4s, v16.4s\n" + "smin v20.4s, v20.4s, v16.4s\n" + "smin v18.4s, v18.4s, v16.4s\n" + "uzp1 v17.16b, v22.16b, v21.16b\n" + "uzp1 v16.16b, v20.16b, v18.16b\n" + "uzp1 v16.16b, v17.16b, v16.16b\n" "tbz %x[n_channels], #3, 38f\n" "st1 { v16.d }[0], [%x[outptr]], #0x8\n" "tbz %x[n_channels], #2, 36f\n" @@ -664,12 +664,10 @@ void a64_u8q_nhwc_max_generic_depthfirst_impl( "tbz %x[n_channels], #0, 42f\n" "st1 { v16.b }[0], [%x[outptr]], #0x1\n" "42:" // Oddments: Store: Bit 3: End - "43:" // End - : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr) : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_input_offset] "I" (offsetof(Requantize32, input_offset)), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [quant_params] "r" (&qp) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27" ); } diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst.hpp index 6dffdcf01c..225f1e42c9 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -33,18 +33,11 @@ template <typename T> void cpp_nhwc_1x1_stride_any_depthfirst_impl(const uint64_t, const uint64_t, uint64_t n_channels, const T *const *const inptrs, T *outptr); template <typename T> -struct cpp_nhwc_1x1_stride_any_depthfirst +struct cpp_nhwc_1x1_stride_any_depthfirst : IGenericDepthfirstStrategy<T, T, Nothing> { - typedef T operand_type; - typedef T return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t, uint64_t n_channels, const operand_type *const *const inptrs, return_type *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - kern_type kernel = cpp_nhwc_1x1_stride_any_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<T, T, Nothing>; cpp_nhwc_1x1_stride_any_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return cpp_nhwc_1x1_stride_any_depthfirst_impl<T>; } }; } // namespace pooling diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp index 2bb22131f7..1f8f863de2 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/cpp_nhwc_1x1_stride_any_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Arm Limited. + * Copyright (c) 2020, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,6 +24,10 @@ #include <cstdint> #include <cstring> +#ifdef ARM_COMPUTE_ENABLE_BF16 +#include "bfloat.hpp" +using arm_gemm::bfloat16; +#endif namespace arm_conv { namespace pooling { @@ -41,9 +45,15 @@ void cpp_nhwc_1x1_stride_any_depthfirst_impl( } template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const float *const *, float *); -#if defined(__ARM_FP16_ARGS) + +#ifdef __ARM_FP16_ARGS template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const __fp16 *const *, __fp16 *); -#endif // defined(__ARM_FP16_ARGS) +#endif + +#ifdef ARM_COMPUTE_ENABLE_BF16 +template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const bfloat16 *const *, bfloat16 *); +#endif + template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const int8_t *const *, int8_t *); template void cpp_nhwc_1x1_stride_any_depthfirst_impl(uint64_t, uint64_t, uint64_t, const uint8_t *const *, uint8_t *); diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..f6682e75e2 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> +{ + using Parent = DepthfirstStrategy<__fp16, __fp16>; + + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..67b07205cd --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <algorithm> +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const __fp16 *const *const inptrs, + __fp16 *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const __fp16 *const *const inptrs; + __fp16 *const *const outptrs; + __fp16 rescale_vals[4]; + + KernelArgs( + unsigned int channels, + const __fp16 *const *input_ptrs, + __fp16 *const * output_ptrs, + bool exclude_padding, unsigned int pad_left, unsigned int pad_top, unsigned int pad_right, unsigned int pad_bottom + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + for (unsigned int i = 0; i < 2; i++) + { + const int start_i = 1*i - static_cast<int>(pad_top); + const int end_i = std::min<int>(start_i + 3, 4 - pad_top - pad_bottom); + const int valid_rows = end_i - std::max<int>(0, start_i); + + for (unsigned int j = 0; j < 2; j++) + { + const int start_j = 1*j - static_cast<int>(pad_left); + const int end_j = std::min<int>(start_j + 3, 4 - pad_left - pad_right); + const int valid_cols = end_j - std::max<int>(0, start_j); + + rescale_vals[i*2 + j] = static_cast<__fp16>(1.0f / static_cast<float>( + exclude_padding ? valid_rows * valid_cols : 9 + )); + } + } + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x3, #0x0\n" + "mov x20, #0x4\n" + "ldr x4, [%x[args], %[offsetof_inptrs]]\n" + "whilelt p0.h, XZR, x20\n" + "add x20, %x[args], %[offsetof_rescale]\n" + "ld1rqh { z4.h }, p0/Z, [x20]\n" + "ldr x5, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p0.h, x3, x5\n" + "mov x6, #0x0\n" + "ldp x7, x8, [x21, #0x0]\n" + "ldp x17, x16, [x21, #0x10]\n" + "ldp x15, x14, [x4, #0x0]\n" + "ld1h { z3.h }, p0/Z, [x14, x3, LSL #1]\n" + "ldp x13, x12, [x4, #0x10]\n" + "ld1h { z2.h }, p0/Z, [x13, x3, LSL #1]\n" + "ldp x11, x10, [x4, #0x20]\n" + "ld1h { z1.h }, p0/Z, [x10, x3, LSL #1]\n" + "ldp x9, x28, [x4, #0x30]\n" + "ld1h { z0.h }, p0/Z, [x9, x3, LSL #1]\n" + "ldp x27, x26, [x4, #0x40]\n" + "ld1h { z31.h }, p0/Z, [x26, x3, LSL #1]\n" + "ldp x25, x24, [x4, #0x50]\n" + "ld1h { z30.h }, p0/Z, [x25, x3, LSL #1]\n" + "ldp x23, x22, [x4, #0x60]\n" + "ld1h { z29.h }, p0/Z, [x11, x3, LSL #1]\n" + "ldp x21, x20, [x4, #0x70]\n" + "ld1h { z28.h }, p0/Z, [x27, x3, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x28, x3, LSL #1]\n" + "ld1h { z22.h }, p0/Z, [x24, x3, LSL #1]\n" + "ld1h { z21.h }, p0/Z, [x22, x3, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x21, x3, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x15, x3, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x12, x3, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x3, LSL #1]\n" + "incw x3\n" + "whilelt p1.h, x3, x5\n" + "b.none 2f\n" + "1:" // Vector: Loop + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "ld1h { z1.h }, p1/Z, [x10, x3, LSL #1]\n" + "whilelt p0.h, x6, x5\n" + "fadd z19.h, z17.h, z16.h\n" + "fadd z18.h, z3.h, z2.h\n" + "ld1h { z0.h }, p1/Z, [x9, x3, LSL #1]\n" + "fadd z17.h, z29.h, z28.h\n" + "fadd z22.h, z27.h, z22.h\n" + "ld1h { z31.h }, p1/Z, [x26, x3, LSL #1]\n" + "fadd z16.h, z21.h, z20.h\n" + "fadd z21.h, z18.h, z19.h\n" + "ld1h { z30.h }, p1/Z, [x25, x3, LSL #1]\n" + "fadd z20.h, z16.h, z19.h\n" + "fadd z19.h, z26.h, z17.h\n" + "ld1h { z3.h }, p1/Z, [x14, x3, LSL #1]\n" + "fadd z18.h, z25.h, z22.h\n" + "fadd z17.h, z24.h, z17.h\n" + "ld1h { z2.h }, p1/Z, [x13, x3, LSL #1]\n" + "fadd z16.h, z23.h, z22.h\n" + "fadd z19.h, z21.h, z19.h\n" + "ld1h { z29.h }, p1/Z, [x11, x3, LSL #1]\n" + "fadd z18.h, z21.h, z18.h\n" + "fadd z17.h, z17.h, z20.h\n" + "ld1h { z28.h }, p1/Z, [x27, x3, LSL #1]\n" + "fadd z16.h, z16.h, z20.h\n" + "ld1h { z27.h }, p1/Z, [x28, x3, LSL #1]\n" + "fmul z19.h, z19.h, z4.h[0]\n" + "ld1h { z22.h }, p1/Z, [x24, x3, LSL #1]\n" + "fmul z18.h, z18.h, z4.h[1]\n" + "fmul z17.h, z17.h, z4.h[2]\n" + "ld1h { z21.h }, p1/Z, [x22, x3, LSL #1]\n" + "fmul z16.h, z16.h, z4.h[3]\n" + "st1h { z19.h }, p0, [x7, x6, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x3, LSL #1]\n" + "st1h { z18.h }, p0, [x8, x6, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x15, x3, LSL #1]\n" + "st1h { z17.h }, p0, [x17, x6, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x12, x3, LSL #1]\n" + "st1h { z16.h }, p0, [x16, x6, LSL #1]\n" + "incw x6\n" + "ld1h { z24.h }, p1/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x20, x3, LSL #1]\n" + "incw x3\n" + "whilelt p1.h, x3, x5\n" + "b.any 1b\n" + "2:" // Vector: Tail + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "whilelt p0.h, x6, x5\n" + "fadd z19.h, z17.h, z16.h\n" + "fadd z18.h, z3.h, z2.h\n" + "fadd z17.h, z29.h, z28.h\n" + "fadd z22.h, z27.h, z22.h\n" + "fadd z16.h, z21.h, z20.h\n" + "fadd z21.h, z18.h, z19.h\n" + "fadd z20.h, z16.h, z19.h\n" + "fadd z19.h, z26.h, z17.h\n" + "fadd z18.h, z25.h, z22.h\n" + "fadd z17.h, z24.h, z17.h\n" + "fadd z16.h, z23.h, z22.h\n" + "fadd z19.h, z21.h, z19.h\n" + "fadd z18.h, z21.h, z18.h\n" + "fadd z17.h, z17.h, z20.h\n" + "fadd z16.h, z16.h, z20.h\n" + "fmul z19.h, z19.h, z4.h[0]\n" + "st1h { z19.h }, p0, [x7, x6, LSL #1]\n" + "fmul z18.h, z18.h, z4.h[1]\n" + "fmul z17.h, z17.h, z4.h[2]\n" + "st1h { z18.h }, p0, [x8, x6, LSL #1]\n" + "fmul z16.h, z16.h, z4.h[3]\n" + "st1h { z17.h }, p0, [x17, x6, LSL #1]\n" + "st1h { z16.h }, p0, [x16, x6, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..cf09f421c4 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); + +struct sme_fp16_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> +{ + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; + sme_fp16_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp16_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..60f17b7bc2 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + + +void sme_fp16_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const __fp16 *const *const inptrs, + __fp16 *outptr +) +{ + const auto rescale_value = static_cast<__fp16>(1.0f / static_cast<float>(window_cells)); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cnth x28\n" + "cnth x27, ALL, MUL #2\n" + "cnth x26, ALL, MUL #3\n" + "ptrue p0.b\n" + "whilelt p3.h, x9, %x[n_channels]\n" + "ld1rh { z6.h }, p0/Z, [%x[rescale_ptr]]\n" + "whilelt p2.h, x28, %x[n_channels]\n" + "whilelt p1.h, x27, %x[n_channels]\n" + "whilelt p0.h, x26, %x[n_channels]\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov z4.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "mov z3.b, #0x0\n" + "mov z2.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z18.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "fadd z23.h, z1.h, z0.h\n" + "fadd z19.h, z31.h, z30.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fadd z22.h, z29.h, z22.h\n" + "fadd z18.h, z28.h, z18.h\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "fadd z21.h, z27.h, z21.h\n" + "fadd z17.h, z26.h, z17.h\n" + "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" + "fadd z20.h, z25.h, z20.h\n" + "fadd z16.h, z24.h, z16.h\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z18.h, z22.h, z18.h\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "fadd z17.h, z21.h, z17.h\n" + "fadd z16.h, z20.h, z16.h\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" + "fadd z5.h, z5.h, z19.h\n" + "fadd z4.h, z4.h, z18.h\n" + "ld1h { z29.h }, p2/Z, [x23, x28, LSL #1]\n" + "fadd z3.h, z3.h, z17.h\n" + "fadd z2.h, z2.h, z16.h\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z18.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "fadd z23.h, z1.h, z0.h\n" + "fadd z19.h, z31.h, z30.h\n" + "fadd z22.h, z29.h, z22.h\n" + "fadd z18.h, z28.h, z18.h\n" + "fadd z21.h, z27.h, z21.h\n" + "fadd z17.h, z26.h, z17.h\n" + "fadd z20.h, z25.h, z20.h\n" + "fadd z16.h, z24.h, z16.h\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z18.h, z22.h, z18.h\n" + "fadd z17.h, z21.h, z17.h\n" + "fadd z16.h, z20.h, z16.h\n" + "fadd z5.h, z5.h, z19.h\n" + "fadd z4.h, z4.h, z18.h\n" + "fadd z3.h, z3.h, z17.h\n" + "fadd z2.h, z2.h, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fadd z5.h, z5.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x20, x28, LSL #1]\n" + "fadd z4.h, z4.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x20, x27, LSL #1]\n" + "fadd z3.h, z3.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" + "fadd z2.h, z2.h, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "fmul z5.h, z5.h, z6.h\n" + "fmul z4.h, z4.h, z6.h\n" + "st1h { z5.h }, p3, [%x[outptr], x9, LSL #1]\n" + "inch x9, ALL, MUL #4\n" + "fmul z3.h, z3.h, z6.h\n" + "fmul z2.h, z2.h, z6.h\n" + "st1h { z4.h }, p2, [%x[outptr], x28, LSL #1]\n" + "inch x28, ALL, MUL #4\n" + "st1h { z3.h }, p1, [%x[outptr], x27, LSL #1]\n" + "inch x27, ALL, MUL #4\n" + "st1h { z2.h }, p0, [%x[outptr], x26, LSL #1]\n" + "inch x26, ALL, MUL #4\n" + "whilelt p0.h, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p3.h, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1h { z1.h }, p3/Z, [x20, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fadd z16.h, z17.h, z16.h\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z5.h, z5.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z1.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x9, LSL #1]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "fadd z17.h, z1.h, z0.h\n" + "fadd z16.h, z31.h, z30.h\n" + "fadd z16.h, z17.h, z16.h\n" + "fadd z5.h, z5.h, z16.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fadd z5.h, z5.h, z16.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "fmul z5.h, z5.h, z6.h\n" + "st1h { z5.h }, p3, [%x[outptr], x9, LSL #1]\n" + "inch x9\n" + "whilelt p3.h, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..cd6c7449a8 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> +{ + using Parent = DepthfirstStrategy<__fp16, __fp16>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..7fc776ed4e --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const __fp16 *const *const inptrs, + __fp16 *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const __fp16 *const *const inptrs; + __fp16 *const *const outptrs; + KernelArgs( + unsigned int channels, + const __fp16 *const *input_ptrs, + __fp16 *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x15, #0x0\n" + "ptrue p2.b\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "mov x14, #0x0\n" + "ldr x13, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p0.h, x15, x13\n" + "ldp x12, x11, [x21, #0x0]\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ld1h { z30.h }, p0/Z, [x27, x15, LSL #1]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ld1h { z29.h }, p0/Z, [x25, x15, LSL #1]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ld1h { z28.h }, p0/Z, [x24, x15, LSL #1]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ld1h { z27.h }, p0/Z, [x21, x15, LSL #1]\n" + "ldr x20, [x20, #0x40]\n" + "ld1h { z26.h }, p0/Z, [x28, x15, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x26, x15, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x15, LSL #1]\n" + "ld1h { z19.h }, p0/Z, [x22, x15, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x15, LSL #1]\n" + "incw x15\n" + "whilelt p1.h, x15, x13\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z30\n fmax z22.h, p2/M, z22.h, z28.h\n" + "movprfx z21, z28\n fmax z21.h, p2/M, z21.h, z27.h\n" + "ld1h { z30.h }, p1/Z, [x27, x15, LSL #1]\n" + "whilelt p0.h, x14, x13\n" + "movprfx z18, z29\n fmax z18.h, p2/M, z18.h, z26.h\n" + "movprfx z17, z25\n fmax z17.h, p2/M, z17.h, z24.h\n" + "ld1h { z28.h }, p1/Z, [x24, x15, LSL #1]\n" + "movprfx z16, z29\n fmax z16.h, p2/M, z16.h, z19.h\n" + "movprfx z20, z24\n fmax z20.h, p2/M, z20.h, z23.h\n" + "ld1h { z27.h }, p1/Z, [x21, x15, LSL #1]\n" + "ld1h { z29.h }, p1/Z, [x25, x15, LSL #1]\n" + "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z18.h\n" + "movprfx z18, z17\n fmax z18.h, p2/M, z18.h, z22.h\n" + "ld1h { z26.h }, p1/Z, [x28, x15, LSL #1]\n" + "movprfx z17, z16\n fmax z17.h, p2/M, z17.h, z21.h\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z20.h\n" + "ld1h { z25.h }, p1/Z, [x26, x15, LSL #1]\n" + "st1h { z19.h }, p0, [x12, x14, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x23, x15, LSL #1]\n" + "st1h { z18.h }, p0, [x11, x14, LSL #1]\n" + "ld1h { z19.h }, p1/Z, [x22, x15, LSL #1]\n" + "st1h { z17.h }, p0, [x10, x14, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x20, x15, LSL #1]\n" + "incw x15\n" + "whilelt p1.h, x15, x13\n" + "st1h { z16.h }, p0, [x9, x14, LSL #1]\n" + "incw x14\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z30\n fmax z22.h, p2/M, z22.h, z28.h\n" + "movprfx z21, z28\n fmax z21.h, p2/M, z21.h, z27.h\n" + "whilelt p0.h, x14, x13\n" + "movprfx z20, z29\n fmax z20.h, p2/M, z20.h, z26.h\n" + "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z24.h\n" + "movprfx z17, z29\n fmax z17.h, p2/M, z17.h, z19.h\n" + "movprfx z19, z24\n fmax z19.h, p2/M, z19.h, z23.h\n" + "movprfx z16, z22\n fmax z16.h, p2/M, z16.h, z20.h\n" + "fmax z18.h, p2/M, z18.h, z22.h\n" + "st1h { z16.h }, p0, [x12, x14, LSL #1]\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z19.h\n" + "st1h { z18.h }, p0, [x11, x14, LSL #1]\n" + "st1h { z17.h }, p0, [x10, x14, LSL #1]\n" + "st1h { z16.h }, p0, [x9, x14, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..bfb3bf5b1a --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + +void sme_fp16_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); + +struct sme_fp16_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> +{ + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; + sme_fp16_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp16_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..afa2ccbd71 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) + +namespace arm_conv { +namespace pooling { + + +void sme_fp16_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const __fp16 *const *const inptrs, + __fp16 *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cnth x28\n" + "cnth x27, ALL, MUL #2\n" + "cnth x26, ALL, MUL #3\n" + "whilelt p4.h, x9, %x[n_channels]\n" + "whilelt p3.h, x28, %x[n_channels]\n" + "whilelt p2.h, x27, %x[n_channels]\n" + "whilelt p1.h, x26, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.h, #0xfc00\n" + "mov z3.h, #0xfc00\n" + "mov x24, %x[inptrs]\n" + "mov z2.h, #0xfc00\n" + "mov z1.h, #0xfc00\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1h { z0.h }, p4/Z, [x23, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" + "ld1h { z18.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z29.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z17.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z26.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" + "fmax z23.h, p0/M, z23.h, z30.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fmax z18.h, p0/M, z18.h, z29.h\n" + "fmax z22.h, p0/M, z22.h, z28.h\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "fmax z17.h, p0/M, z17.h, z27.h\n" + "fmax z21.h, p0/M, z21.h, z26.h\n" + "ld1h { z0.h }, p4/Z, [x23, x9, LSL #1]\n" + "fmax z16.h, p0/M, z16.h, z25.h\n" + "fmax z20.h, p0/M, z20.h, z24.h\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z18.h, p0/M, z18.h, z22.h\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "fmax z17.h, p0/M, z17.h, z21.h\n" + "fmax z16.h, p0/M, z16.h, z20.h\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" + "fmax z4.h, p0/M, z4.h, z19.h\n" + "fmax z3.h, p0/M, z3.h, z18.h\n" + "ld1h { z18.h }, p3/Z, [x23, x28, LSL #1]\n" + "fmax z2.h, p0/M, z2.h, z17.h\n" + "fmax z1.h, p0/M, z1.h, z16.h\n" + "ld1h { z29.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z17.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z26.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n fmax z19.h, p0/M, z19.h, z31.h\n" + "fmax z23.h, p0/M, z23.h, z30.h\n" + "fmax z18.h, p0/M, z18.h, z29.h\n" + "fmax z22.h, p0/M, z22.h, z28.h\n" + "fmax z17.h, p0/M, z17.h, z27.h\n" + "fmax z21.h, p0/M, z21.h, z26.h\n" + "fmax z16.h, p0/M, z16.h, z25.h\n" + "fmax z20.h, p0/M, z20.h, z24.h\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z18.h, p0/M, z18.h, z22.h\n" + "fmax z17.h, p0/M, z17.h, z21.h\n" + "fmax z16.h, p0/M, z16.h, z20.h\n" + "fmax z4.h, p0/M, z4.h, z19.h\n" + "fmax z3.h, p0/M, z3.h, z18.h\n" + "fmax z2.h, p0/M, z2.h, z17.h\n" + "fmax z1.h, p0/M, z1.h, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" + "ld1h { z16.h }, p3/Z, [x20, x28, LSL #1]\n" + "fmax z3.h, p0/M, z3.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x20, x27, LSL #1]\n" + "fmax z2.h, p0/M, z2.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x20, x26, LSL #1]\n" + "fmax z1.h, p0/M, z1.h, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1h { z4.h }, p4, [%x[outptr], x9, LSL #1]\n" + "inch x9, ALL, MUL #4\n" + "st1h { z3.h }, p3, [%x[outptr], x28, LSL #1]\n" + "inch x28, ALL, MUL #4\n" + "st1h { z2.h }, p2, [%x[outptr], x27, LSL #1]\n" + "inch x27, ALL, MUL #4\n" + "st1h { z1.h }, p1, [%x[outptr], x26, LSL #1]\n" + "inch x26, ALL, MUL #4\n" + "whilelt p1.h, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.h, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.h, #0xfc00\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1h { z0.h }, p4/Z, [x20, x9, LSL #1]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z16, z0\n fmax z16.h, p0/M, z16.h, z31.h\n" + "movprfx z17, z23\n fmax z17.h, p0/M, z17.h, z30.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z0.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z31.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z23.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z30.h }, p4/Z, [x20, x9, LSL #1]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z16, z0\n fmax z16.h, p0/M, z16.h, z31.h\n" + "movprfx z17, z23\n fmax z17.h, p0/M, z17.h, z30.h\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fmax z4.h, p0/M, z4.h, z16.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1h { z4.h }, p4, [%x[outptr], x9, LSL #1]\n" + "inch x9\n" + "whilelt p4.h, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..23a0eee04e --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> +{ + using Parent = DepthfirstStrategy<float, float>; + + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..8c8532827a --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <algorithm> +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const float *const *const inptrs, + float *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const float *const *const inptrs; + float *const *const outptrs; + float rescale_vals[4]; + + KernelArgs( + unsigned int channels, + const float *const *input_ptrs, + float *const * output_ptrs, + bool exclude_padding, unsigned int pad_left, unsigned int pad_top, unsigned int pad_right, unsigned int pad_bottom + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + for (unsigned int i = 0; i < 2; i++) + { + const int start_i = 1*i - static_cast<int>(pad_top); + const int end_i = std::min<int>(start_i + 3, 4 - pad_top - pad_bottom); + const int valid_rows = end_i - std::max<int>(0, start_i); + + for (unsigned int j = 0; j < 2; j++) + { + const int start_j = 1*j - static_cast<int>(pad_left); + const int end_j = std::min<int>(start_j + 3, 4 - pad_left - pad_right); + const int valid_cols = end_j - std::max<int>(0, start_j); + + rescale_vals[i*2 + j] = static_cast<float>(1.0f / static_cast<float>( + exclude_padding ? valid_rows * valid_cols : 9 + )); + } + } + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x3, #0x0\n" + "mov x20, #0x4\n" + "ldr x4, [%x[args], %[offsetof_inptrs]]\n" + "whilelt p0.s, XZR, x20\n" + "add x20, %x[args], %[offsetof_rescale]\n" + "ld1rqw { z4.s }, p0/Z, [x20]\n" + "ldr x5, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p0.s, x3, x5\n" + "mov x6, #0x0\n" + "ldp x7, x8, [x21, #0x0]\n" + "ldp x17, x16, [x21, #0x10]\n" + "ldp x15, x14, [x4, #0x0]\n" + "ld1w { z3.s }, p0/Z, [x14, x3, LSL #2]\n" + "ldp x13, x12, [x4, #0x10]\n" + "ld1w { z2.s }, p0/Z, [x13, x3, LSL #2]\n" + "ldp x11, x10, [x4, #0x20]\n" + "ld1w { z1.s }, p0/Z, [x10, x3, LSL #2]\n" + "ldp x9, x28, [x4, #0x30]\n" + "ld1w { z0.s }, p0/Z, [x9, x3, LSL #2]\n" + "ldp x27, x26, [x4, #0x40]\n" + "ld1w { z31.s }, p0/Z, [x26, x3, LSL #2]\n" + "ldp x25, x24, [x4, #0x50]\n" + "ld1w { z30.s }, p0/Z, [x25, x3, LSL #2]\n" + "ldp x23, x22, [x4, #0x60]\n" + "ld1w { z29.s }, p0/Z, [x11, x3, LSL #2]\n" + "ldp x21, x20, [x4, #0x70]\n" + "ld1w { z28.s }, p0/Z, [x27, x3, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x28, x3, LSL #2]\n" + "ld1w { z22.s }, p0/Z, [x24, x3, LSL #2]\n" + "ld1w { z21.s }, p0/Z, [x22, x3, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x21, x3, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x15, x3, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x12, x3, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x23, x3, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x3, LSL #2]\n" + "incw x3\n" + "whilelt p1.s, x3, x5\n" + "b.none 2f\n" + "1:" // Vector: Loop + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "ld1w { z1.s }, p1/Z, [x10, x3, LSL #2]\n" + "whilelt p0.s, x6, x5\n" + "fadd z19.s, z17.s, z16.s\n" + "fadd z18.s, z3.s, z2.s\n" + "ld1w { z0.s }, p1/Z, [x9, x3, LSL #2]\n" + "fadd z17.s, z29.s, z28.s\n" + "fadd z22.s, z27.s, z22.s\n" + "ld1w { z31.s }, p1/Z, [x26, x3, LSL #2]\n" + "fadd z16.s, z21.s, z20.s\n" + "fadd z21.s, z18.s, z19.s\n" + "ld1w { z30.s }, p1/Z, [x25, x3, LSL #2]\n" + "fadd z20.s, z16.s, z19.s\n" + "fadd z19.s, z26.s, z17.s\n" + "ld1w { z3.s }, p1/Z, [x14, x3, LSL #2]\n" + "fadd z18.s, z25.s, z22.s\n" + "fadd z17.s, z24.s, z17.s\n" + "ld1w { z2.s }, p1/Z, [x13, x3, LSL #2]\n" + "fadd z16.s, z23.s, z22.s\n" + "fadd z19.s, z21.s, z19.s\n" + "ld1w { z29.s }, p1/Z, [x11, x3, LSL #2]\n" + "fadd z18.s, z21.s, z18.s\n" + "fadd z17.s, z17.s, z20.s\n" + "ld1w { z28.s }, p1/Z, [x27, x3, LSL #2]\n" + "fadd z16.s, z16.s, z20.s\n" + "ld1w { z27.s }, p1/Z, [x28, x3, LSL #2]\n" + "fmul z19.s, z19.s, z4.s[0]\n" + "ld1w { z22.s }, p1/Z, [x24, x3, LSL #2]\n" + "fmul z18.s, z18.s, z4.s[1]\n" + "fmul z17.s, z17.s, z4.s[2]\n" + "ld1w { z21.s }, p1/Z, [x22, x3, LSL #2]\n" + "fmul z16.s, z16.s, z4.s[3]\n" + "st1w { z19.s }, p0, [x7, x6, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x3, LSL #2]\n" + "st1w { z18.s }, p0, [x8, x6, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x15, x3, LSL #2]\n" + "st1w { z17.s }, p0, [x17, x6, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x12, x3, LSL #2]\n" + "st1w { z16.s }, p0, [x16, x6, LSL #2]\n" + "incw x6\n" + "ld1w { z24.s }, p1/Z, [x23, x3, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x20, x3, LSL #2]\n" + "incw x3\n" + "whilelt p1.s, x3, x5\n" + "b.any 1b\n" + "2:" // Vector: Tail + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "whilelt p0.s, x6, x5\n" + "fadd z19.s, z17.s, z16.s\n" + "fadd z18.s, z3.s, z2.s\n" + "fadd z17.s, z29.s, z28.s\n" + "fadd z22.s, z27.s, z22.s\n" + "fadd z16.s, z21.s, z20.s\n" + "fadd z21.s, z18.s, z19.s\n" + "fadd z20.s, z16.s, z19.s\n" + "fadd z19.s, z26.s, z17.s\n" + "fadd z18.s, z25.s, z22.s\n" + "fadd z17.s, z24.s, z17.s\n" + "fadd z16.s, z23.s, z22.s\n" + "fadd z19.s, z21.s, z19.s\n" + "fadd z18.s, z21.s, z18.s\n" + "fadd z17.s, z17.s, z20.s\n" + "fadd z16.s, z16.s, z20.s\n" + "fmul z19.s, z19.s, z4.s[0]\n" + "st1w { z19.s }, p0, [x7, x6, LSL #2]\n" + "fmul z18.s, z18.s, z4.s[1]\n" + "fmul z17.s, z17.s, z4.s[2]\n" + "st1w { z18.s }, p0, [x8, x6, LSL #2]\n" + "fmul z16.s, z16.s, z4.s[3]\n" + "st1w { z17.s }, p0, [x17, x6, LSL #2]\n" + "st1w { z16.s }, p0, [x16, x6, LSL #2]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..29bcfc5a3b --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); + +struct sme_fp32_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<float, float> +{ + using Parent = IGenericDepthfirstStrategy<float, float>; + sme_fp32_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp32_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..86e7f84542 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + + +void sme_fp32_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const float *const *const inptrs, + float *outptr +) +{ + const auto rescale_value = static_cast<float>(1.0f / static_cast<float>(window_cells)); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cntw x28\n" + "cntw x27, ALL, MUL #2\n" + "cntw x26, ALL, MUL #3\n" + "ptrue p0.b\n" + "whilelt p3.s, x9, %x[n_channels]\n" + "ld1rw { z6.s }, p0/Z, [%x[rescale_ptr]]\n" + "whilelt p2.s, x28, %x[n_channels]\n" + "whilelt p1.s, x27, %x[n_channels]\n" + "whilelt p0.s, x26, %x[n_channels]\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov z4.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "mov z3.b, #0x0\n" + "mov z2.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z18.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "fadd z23.s, z1.s, z0.s\n" + "fadd z19.s, z31.s, z30.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fadd z22.s, z29.s, z22.s\n" + "fadd z18.s, z28.s, z18.s\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "fadd z21.s, z27.s, z21.s\n" + "fadd z17.s, z26.s, z17.s\n" + "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" + "fadd z20.s, z25.s, z20.s\n" + "fadd z16.s, z24.s, z16.s\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z18.s, z22.s, z18.s\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "fadd z17.s, z21.s, z17.s\n" + "fadd z16.s, z20.s, z16.s\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" + "fadd z5.s, z5.s, z19.s\n" + "fadd z4.s, z4.s, z18.s\n" + "ld1w { z29.s }, p2/Z, [x23, x28, LSL #2]\n" + "fadd z3.s, z3.s, z17.s\n" + "fadd z2.s, z2.s, z16.s\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z18.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "fadd z23.s, z1.s, z0.s\n" + "fadd z19.s, z31.s, z30.s\n" + "fadd z22.s, z29.s, z22.s\n" + "fadd z18.s, z28.s, z18.s\n" + "fadd z21.s, z27.s, z21.s\n" + "fadd z17.s, z26.s, z17.s\n" + "fadd z20.s, z25.s, z20.s\n" + "fadd z16.s, z24.s, z16.s\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z18.s, z22.s, z18.s\n" + "fadd z17.s, z21.s, z17.s\n" + "fadd z16.s, z20.s, z16.s\n" + "fadd z5.s, z5.s, z19.s\n" + "fadd z4.s, z4.s, z18.s\n" + "fadd z3.s, z3.s, z17.s\n" + "fadd z2.s, z2.s, z16.s\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fadd z5.s, z5.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, x28, LSL #2]\n" + "fadd z4.s, z4.s, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20, x27, LSL #2]\n" + "fadd z3.s, z3.s, z16.s\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" + "fadd z2.s, z2.s, z16.s\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "fmul z5.s, z5.s, z6.s\n" + "fmul z4.s, z4.s, z6.s\n" + "st1w { z5.s }, p3, [%x[outptr], x9, LSL #2]\n" + "incw x9, ALL, MUL #4\n" + "fmul z3.s, z3.s, z6.s\n" + "fmul z2.s, z2.s, z6.s\n" + "st1w { z4.s }, p2, [%x[outptr], x28, LSL #2]\n" + "incw x28, ALL, MUL #4\n" + "st1w { z3.s }, p1, [%x[outptr], x27, LSL #2]\n" + "incw x27, ALL, MUL #4\n" + "st1w { z2.s }, p0, [%x[outptr], x26, LSL #2]\n" + "incw x26, ALL, MUL #4\n" + "whilelt p0.s, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p3.s, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1w { z1.s }, p3/Z, [x20, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fadd z16.s, z17.s, z16.s\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z5.s, z5.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z1.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x9, LSL #2]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "fadd z17.s, z1.s, z0.s\n" + "fadd z16.s, z31.s, z30.s\n" + "fadd z16.s, z17.s, z16.s\n" + "fadd z5.s, z5.s, z16.s\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fadd z5.s, z5.s, z16.s\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "fmul z5.s, z5.s, z6.s\n" + "st1w { z5.s }, p3, [%x[outptr], x9, LSL #2]\n" + "incw x9\n" + "whilelt p3.s, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..338348231f --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> +{ + using Parent = DepthfirstStrategy<float, float>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..3c7213a498 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const float *const *const inptrs, + float *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const float *const *const inptrs; + float *const *const outptrs; + KernelArgs( + unsigned int channels, + const float *const *input_ptrs, + float *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x15, #0x0\n" + "ptrue p2.b\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "mov x14, #0x0\n" + "ldr x13, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p0.s, x15, x13\n" + "ldp x12, x11, [x21, #0x0]\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ld1w { z30.s }, p0/Z, [x27, x15, LSL #2]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ld1w { z29.s }, p0/Z, [x25, x15, LSL #2]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ld1w { z28.s }, p0/Z, [x24, x15, LSL #2]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ld1w { z27.s }, p0/Z, [x21, x15, LSL #2]\n" + "ldr x20, [x20, #0x40]\n" + "ld1w { z26.s }, p0/Z, [x28, x15, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x26, x15, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x23, x15, LSL #2]\n" + "ld1w { z19.s }, p0/Z, [x22, x15, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x15, LSL #2]\n" + "incw x15\n" + "whilelt p1.s, x15, x13\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z30\n fmax z22.s, p2/M, z22.s, z28.s\n" + "movprfx z21, z28\n fmax z21.s, p2/M, z21.s, z27.s\n" + "ld1w { z30.s }, p1/Z, [x27, x15, LSL #2]\n" + "whilelt p0.s, x14, x13\n" + "movprfx z18, z29\n fmax z18.s, p2/M, z18.s, z26.s\n" + "movprfx z17, z25\n fmax z17.s, p2/M, z17.s, z24.s\n" + "ld1w { z28.s }, p1/Z, [x24, x15, LSL #2]\n" + "movprfx z16, z29\n fmax z16.s, p2/M, z16.s, z19.s\n" + "movprfx z20, z24\n fmax z20.s, p2/M, z20.s, z23.s\n" + "ld1w { z27.s }, p1/Z, [x21, x15, LSL #2]\n" + "ld1w { z29.s }, p1/Z, [x25, x15, LSL #2]\n" + "movprfx z19, z22\n fmax z19.s, p2/M, z19.s, z18.s\n" + "movprfx z18, z17\n fmax z18.s, p2/M, z18.s, z22.s\n" + "ld1w { z26.s }, p1/Z, [x28, x15, LSL #2]\n" + "movprfx z17, z16\n fmax z17.s, p2/M, z17.s, z21.s\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z20.s\n" + "ld1w { z25.s }, p1/Z, [x26, x15, LSL #2]\n" + "st1w { z19.s }, p0, [x12, x14, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x23, x15, LSL #2]\n" + "st1w { z18.s }, p0, [x11, x14, LSL #2]\n" + "ld1w { z19.s }, p1/Z, [x22, x15, LSL #2]\n" + "st1w { z17.s }, p0, [x10, x14, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x20, x15, LSL #2]\n" + "incw x15\n" + "whilelt p1.s, x15, x13\n" + "st1w { z16.s }, p0, [x9, x14, LSL #2]\n" + "incw x14\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z30\n fmax z22.s, p2/M, z22.s, z28.s\n" + "movprfx z21, z28\n fmax z21.s, p2/M, z21.s, z27.s\n" + "whilelt p0.s, x14, x13\n" + "movprfx z20, z29\n fmax z20.s, p2/M, z20.s, z26.s\n" + "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z24.s\n" + "movprfx z17, z29\n fmax z17.s, p2/M, z17.s, z19.s\n" + "movprfx z19, z24\n fmax z19.s, p2/M, z19.s, z23.s\n" + "movprfx z16, z22\n fmax z16.s, p2/M, z16.s, z20.s\n" + "fmax z18.s, p2/M, z18.s, z22.s\n" + "st1w { z16.s }, p0, [x12, x14, LSL #2]\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z19.s\n" + "st1w { z18.s }, p0, [x11, x14, LSL #2]\n" + "st1w { z17.s }, p0, [x10, x14, LSL #2]\n" + "st1w { z16.s }, p0, [x9, x14, LSL #2]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..9bc1f11601 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_fp32_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); + +struct sme_fp32_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<float, float> +{ + using Parent = IGenericDepthfirstStrategy<float, float>; + sme_fp32_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_fp32_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..0dabc2f292 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + + +void sme_fp32_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const float *const *const inptrs, + float *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cntw x28\n" + "cntw x27, ALL, MUL #2\n" + "cntw x26, ALL, MUL #3\n" + "whilelt p4.s, x9, %x[n_channels]\n" + "whilelt p3.s, x28, %x[n_channels]\n" + "whilelt p2.s, x27, %x[n_channels]\n" + "whilelt p1.s, x26, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.s, #0xff800000\n" + "mov z3.s, #0xff800000\n" + "mov x24, %x[inptrs]\n" + "mov z2.s, #0xff800000\n" + "mov z1.s, #0xff800000\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1w { z0.s }, p4/Z, [x23, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" + "ld1w { z18.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z29.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z17.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z26.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" + "fmax z23.s, p0/M, z23.s, z30.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fmax z18.s, p0/M, z18.s, z29.s\n" + "fmax z22.s, p0/M, z22.s, z28.s\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "fmax z17.s, p0/M, z17.s, z27.s\n" + "fmax z21.s, p0/M, z21.s, z26.s\n" + "ld1w { z0.s }, p4/Z, [x23, x9, LSL #2]\n" + "fmax z16.s, p0/M, z16.s, z25.s\n" + "fmax z20.s, p0/M, z20.s, z24.s\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z18.s, p0/M, z18.s, z22.s\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "fmax z17.s, p0/M, z17.s, z21.s\n" + "fmax z16.s, p0/M, z16.s, z20.s\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" + "fmax z4.s, p0/M, z4.s, z19.s\n" + "fmax z3.s, p0/M, z3.s, z18.s\n" + "ld1w { z18.s }, p3/Z, [x23, x28, LSL #2]\n" + "fmax z2.s, p0/M, z2.s, z17.s\n" + "fmax z1.s, p0/M, z1.s, z16.s\n" + "ld1w { z29.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z17.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z26.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n fmax z19.s, p0/M, z19.s, z31.s\n" + "fmax z23.s, p0/M, z23.s, z30.s\n" + "fmax z18.s, p0/M, z18.s, z29.s\n" + "fmax z22.s, p0/M, z22.s, z28.s\n" + "fmax z17.s, p0/M, z17.s, z27.s\n" + "fmax z21.s, p0/M, z21.s, z26.s\n" + "fmax z16.s, p0/M, z16.s, z25.s\n" + "fmax z20.s, p0/M, z20.s, z24.s\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z18.s, p0/M, z18.s, z22.s\n" + "fmax z17.s, p0/M, z17.s, z21.s\n" + "fmax z16.s, p0/M, z16.s, z20.s\n" + "fmax z4.s, p0/M, z4.s, z19.s\n" + "fmax z3.s, p0/M, z3.s, z18.s\n" + "fmax z2.s, p0/M, z2.s, z17.s\n" + "fmax z1.s, p0/M, z1.s, z16.s\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" + "ld1w { z16.s }, p3/Z, [x20, x28, LSL #2]\n" + "fmax z3.s, p0/M, z3.s, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, x27, LSL #2]\n" + "fmax z2.s, p0/M, z2.s, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20, x26, LSL #2]\n" + "fmax z1.s, p0/M, z1.s, z16.s\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1w { z4.s }, p4, [%x[outptr], x9, LSL #2]\n" + "incw x9, ALL, MUL #4\n" + "st1w { z3.s }, p3, [%x[outptr], x28, LSL #2]\n" + "incw x28, ALL, MUL #4\n" + "st1w { z2.s }, p2, [%x[outptr], x27, LSL #2]\n" + "incw x27, ALL, MUL #4\n" + "st1w { z1.s }, p1, [%x[outptr], x26, LSL #2]\n" + "incw x26, ALL, MUL #4\n" + "whilelt p1.s, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.s, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.s, #0xff800000\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1w { z0.s }, p4/Z, [x20, x9, LSL #2]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z16, z0\n fmax z16.s, p0/M, z16.s, z31.s\n" + "movprfx z17, z23\n fmax z17.s, p0/M, z17.s, z30.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z0.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z31.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z23.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z30.s }, p4/Z, [x20, x9, LSL #2]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z16, z0\n fmax z16.s, p0/M, z16.s, z31.s\n" + "movprfx z17, z23\n fmax z17.s, p0/M, z17.s, z30.s\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fmax z4.s, p0/M, z4.s, z16.s\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1w { z4.s }, p4, [%x[outptr], x9, LSL #2]\n" + "incw x9\n" + "whilelt p4.s, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..318510e697 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); + +struct sme_s8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; + sme_s8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..c24e977dc6 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> +#include <cstring> +#include <cmath> + + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_s8_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) + { + shift_value++; + long_rescale_value >>= 1; + } + rescale_value = static_cast<int32_t>(long_rescale_value); + } + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p2.b, x25, %x[n_channels]\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x22, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "mov z11.s, #0x0\n" + "mov z10.s, #0x0\n" + "mov z9.s, #0x0\n" + "mov z8.s, #0x0\n" + "mov z7.s, #0x0\n" + "mov z6.s, #0x0\n" + "mov z5.s, #0x0\n" + "mov z4.s, #0x0\n" + "mov z3.s, #0x0\n" + "mov z2.s, #0x0\n" + "mov z1.s, #0x0\n" + "mov z0.s, #0x0\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a213 // sshllb z19.h, z16.b, #0x0\n" + ".inst 0x4508a612 // sshllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + ".inst 0x04b1756b // sqdmulh z11.s, z11.s, z17.s\n" + ".inst 0x04b1754a // sqdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqdmulh z9.s, z9.s, z17.s\n" + ".inst 0x04b17508 // sqdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqdmulh z7.s, z7.s, z17.s\n" + ".inst 0x04b174c6 // sqdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqdmulh z5.s, z5.s, z17.s\n" + ".inst 0x04b17484 // sqdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqdmulh z1.s, z1.s, z17.s\n" + ".inst 0x04b17400 // sqdmulh z0.s, z0.s, z17.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x27, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x22, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z16.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b075ef // sqdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqdmulh z14.s, z14.s, z16.s\n" + ".inst 0x04b075ad // sqdmulh z13.s, z13.s, z16.s\n" + ".inst 0x04b0758c // sqdmulh z12.s, z12.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + "mov z18.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z18.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..c9a80e6a5b --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const int8_t *const *const, int8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<int8_t, int8_t> +{ + using Parent = DepthfirstStrategy<int8_t, int8_t>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..96617566a8 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const int8_t *const *const inptrs, + int8_t *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const int8_t *const *const inptrs; + int8_t *const *const outptrs; + KernelArgs( + unsigned int channels, + const int8_t *const *input_ptrs, + int8_t *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x15, #0x0\n" + "ptrue p2.b\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "mov x14, #0x0\n" + "ldr x13, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p0.b, x15, x13\n" + "ldp x12, x11, [x21, #0x0]\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ld1b { z30.b }, p0/Z, [x27, x15]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ld1b { z29.b }, p0/Z, [x25, x15]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ld1b { z28.b }, p0/Z, [x24, x15]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ld1b { z27.b }, p0/Z, [x21, x15]\n" + "ldr x20, [x20, #0x40]\n" + "ld1b { z26.b }, p0/Z, [x28, x15]\n" + "ld1b { z25.b }, p0/Z, [x26, x15]\n" + "ld1b { z24.b }, p0/Z, [x23, x15]\n" + "ld1b { z19.b }, p0/Z, [x22, x15]\n" + "ld1b { z23.b }, p0/Z, [x20, x15]\n" + "incw x15\n" + "whilelt p1.b, x15, x13\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z30\n smax z22.b, p2/M, z22.b, z28.b\n" + "movprfx z21, z28\n smax z21.b, p2/M, z21.b, z27.b\n" + "ld1b { z30.b }, p1/Z, [x27, x15]\n" + "whilelt p0.b, x14, x13\n" + "movprfx z18, z29\n smax z18.b, p2/M, z18.b, z26.b\n" + "movprfx z17, z25\n smax z17.b, p2/M, z17.b, z24.b\n" + "ld1b { z28.b }, p1/Z, [x24, x15]\n" + "movprfx z16, z29\n smax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z20, z24\n smax z20.b, p2/M, z20.b, z23.b\n" + "ld1b { z27.b }, p1/Z, [x21, x15]\n" + "ld1b { z29.b }, p1/Z, [x25, x15]\n" + "movprfx z19, z22\n smax z19.b, p2/M, z19.b, z18.b\n" + "movprfx z18, z17\n smax z18.b, p2/M, z18.b, z22.b\n" + "ld1b { z26.b }, p1/Z, [x28, x15]\n" + "movprfx z17, z16\n smax z17.b, p2/M, z17.b, z21.b\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z20.b\n" + "ld1b { z25.b }, p1/Z, [x26, x15]\n" + "st1b { z19.b }, p0, [x12, x14]\n" + "ld1b { z24.b }, p1/Z, [x23, x15]\n" + "st1b { z18.b }, p0, [x11, x14]\n" + "ld1b { z19.b }, p1/Z, [x22, x15]\n" + "st1b { z17.b }, p0, [x10, x14]\n" + "ld1b { z23.b }, p1/Z, [x20, x15]\n" + "incw x15\n" + "whilelt p1.b, x15, x13\n" + "st1b { z16.b }, p0, [x9, x14]\n" + "incw x14\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z30\n smax z22.b, p2/M, z22.b, z28.b\n" + "movprfx z21, z28\n smax z21.b, p2/M, z21.b, z27.b\n" + "whilelt p0.b, x14, x13\n" + "movprfx z20, z29\n smax z20.b, p2/M, z20.b, z26.b\n" + "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z24.b\n" + "movprfx z17, z29\n smax z17.b, p2/M, z17.b, z19.b\n" + "movprfx z19, z24\n smax z19.b, p2/M, z19.b, z23.b\n" + "movprfx z16, z22\n smax z16.b, p2/M, z16.b, z20.b\n" + "smax z18.b, p2/M, z18.b, z22.b\n" + "st1b { z16.b }, p0, [x12, x14]\n" + "smax z17.b, p2/M, z17.b, z21.b\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z19.b\n" + "st1b { z18.b }, p0, [x11, x14]\n" + "st1b { z17.b }, p0, [x10, x14]\n" + "st1b { z16.b }, p0, [x9, x14]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..3e0d76c277 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); + +struct sme_s8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; + sme_s8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..d2b45cd353 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + + +void sme_s8_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p2.b, x27, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov z3.b, #0x80\n" + "mov x24, %x[inptrs]\n" + "mov z2.b, #0x80\n" + "mov z1.b, #0x80\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "smax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x9]\n" + "incb x9, ALL, MUL #4\n" + "st1b { z3.b }, p3, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "st1b { z2.b }, p2, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z1.b }, p1, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..c6263f5dbc --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); + +struct sme_s8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; + sme_s8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8q_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..91f2f7ab31 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "pooling.hpp" +#include <cstdint> +#include <cstddef> +#include <cstring> +#include <cmath> + + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_s8q_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr, + const Requantize32 &qp +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) + { + shift_value++; + long_rescale_value >>= 1; + } + rescale_value = static_cast<int32_t>(long_rescale_value); + } + + // Combine together the rescale value for the requantization and the scaling + // factor for the average pool. + const int32_t shift = qp.per_layer_left_shift - qp.per_layer_right_shift + shift_value; + const int32_t left_shift = shift > 0 ? shift : 0; + const int32_t right_shift = shift <= 0 ? shift : 0; + + int32_t combined_rescale_value = 0; + __asm__ __volatile__ ( + "mov v16.s[0], %w[per_layer_mul]\n" + "mov v17.s[0], %w[rescale_value]\n" + "sqrdmulh s18, s16, s17\n" + "mov %w[combined_rescale_value], v18.s[0]\n" + : [combined_rescale_value] "=r" (combined_rescale_value) + : [per_layer_mul] "r" (qp.per_layer_mul), [rescale_value] "r" (rescale_value) + : "v16", "v17", "v18" + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p2.b, x25, %x[n_channels]\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x22, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "mov z11.s, #0x0\n" + "mov z10.s, #0x0\n" + "mov z9.s, #0x0\n" + "mov z8.s, #0x0\n" + "mov z7.s, #0x0\n" + "mov z6.s, #0x0\n" + "mov z5.s, #0x0\n" + "mov z4.s, #0x0\n" + "mov z3.s, #0x0\n" + "mov z2.s, #0x0\n" + "mov z1.s, #0x0\n" + "mov z0.s, #0x0\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a213 // sshllb z19.h, z16.b, #0x0\n" + ".inst 0x4508a612 // sshllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" + ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" + ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" + ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482824b // srshl z11.s, p0/M, z11.s, z18.s\n" + ".inst 0x4482824a // srshl z10.s, p0/M, z10.s, z18.s\n" + "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x44828249 // srshl z9.s, p0/M, z9.s, z18.s\n" + ".inst 0x44828248 // srshl z8.s, p0/M, z8.s, z18.s\n" + ".inst 0x44828247 // srshl z7.s, p0/M, z7.s, z18.s\n" + ".inst 0x44828246 // srshl z6.s, p0/M, z6.s, z18.s\n" + ".inst 0x44828245 // srshl z5.s, p0/M, z5.s, z18.s\n" + ".inst 0x44828244 // srshl z4.s, p0/M, z4.s, z18.s\n" + ".inst 0x44828243 // srshl z3.s, p0/M, z3.s, z18.s\n" + ".inst 0x44828242 // srshl z2.s, p0/M, z2.s, z18.s\n" + ".inst 0x44828241 // srshl z1.s, p0/M, z1.s, z18.s\n" + ".inst 0x44828240 // srshl z0.s, p0/M, z0.s, z18.s\n" + ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" + ".inst 0x04b1756b // sqrdmulh z11.s, z11.s, z17.s\n" + ".inst 0x04b1754a // sqrdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqrdmulh z9.s, z9.s, z17.s\n" + ".inst 0x04b17508 // sqrdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqrdmulh z7.s, z7.s, z17.s\n" + ".inst 0x04b174c6 // sqrdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqrdmulh z5.s, z5.s, z17.s\n" + ".inst 0x04b17484 // sqrdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqrdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqrdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqrdmulh z1.s, z1.s, z17.s\n" + ".inst 0x04b17400 // sqrdmulh z0.s, z0.s, z17.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x27, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x22, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z16.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z18.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [right_shift] "r" (&right_shift) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..9667d37954 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_s8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); + +struct sme_s8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; + sme_s8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_s8q_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..e9b586f4ce --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,388 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "pooling.hpp" +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + + +void sme_s8q_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const int8_t *const *const inptrs, + int8_t *outptr, + const Requantize32 &qp +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p2.b, x27, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov z3.b, #0x80\n" + "mov x24, %x[inptrs]\n" + "mov z2.b, #0x80\n" + "mov z1.b, #0x80\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n smax z19.b, p0/M, z19.b, z31.b\n" + "smax z23.b, p0/M, z23.b, z30.b\n" + "smax z18.b, p0/M, z18.b, z29.b\n" + "smax z22.b, p0/M, z22.b, z28.b\n" + "smax z17.b, p0/M, z17.b, z27.b\n" + "smax z21.b, p0/M, z21.b, z26.b\n" + "smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "smax z4.b, p0/M, z4.b, z19.b\n" + "smax z3.b, p0/M, z3.b, z18.b\n" + "smax z2.b, p0/M, z2.b, z17.b\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "smax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "smax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + ".inst 0x4508a097 // sshllb z23.h, z4.b, #0x0\n" + ".inst 0x4508a496 // sshllt z22.h, z4.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z4.s }, p0/Z, [x20]\n" + ".inst 0x4508a075 // sshllb z21.h, z3.b, #0x0\n" + ".inst 0x4508a472 // sshllt z18.h, z3.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z3.s }, p0/Z, [x20]\n" + ".inst 0x4508a054 // sshllb z20.h, z2.b, #0x0\n" + ".inst 0x4508a451 // sshllt z17.h, z2.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z2.s }, p0/Z, [x20]\n" + ".inst 0x4508a033 // sshllb z19.h, z1.b, #0x0\n" + ".inst 0x4508a430 // sshllt z16.h, z1.b, #0x0\n" + ".inst 0x4510a2e1 // sshllb z1.s, z23.h, #0x0\n" + ".inst 0x4510a6f7 // sshllt z23.s, z23.h, #0x0\n" + ".inst 0x4510a2c0 // sshllb z0.s, z22.h, #0x0\n" + ".inst 0x4510a6df // sshllt z31.s, z22.h, #0x0\n" + ".inst 0x4510a2be // sshllb z30.s, z21.h, #0x0\n" + ".inst 0x4510a6b6 // sshllt z22.s, z21.h, #0x0\n" + ".inst 0x4510a25d // sshllb z29.s, z18.h, #0x0\n" + ".inst 0x4510a652 // sshllt z18.s, z18.h, #0x0\n" + ".inst 0x4510a29c // sshllb z28.s, z20.h, #0x0\n" + ".inst 0x4510a695 // sshllt z21.s, z20.h, #0x0\n" + ".inst 0x4510a23b // sshllb z27.s, z17.h, #0x0\n" + ".inst 0x4510a631 // sshllt z17.s, z17.h, #0x0\n" + ".inst 0x4510a27a // sshllb z26.s, z19.h, #0x0\n" + ".inst 0x4510a674 // sshllt z20.s, z19.h, #0x0\n" + ".inst 0x4510a219 // sshllb z25.s, z16.h, #0x0\n" + ".inst 0x4510a618 // sshllt z24.s, z16.h, #0x0\n" + ".inst 0x44828081 // srshl z1.s, p0/M, z1.s, z4.s\n" + ".inst 0x44828097 // srshl z23.s, p0/M, z23.s, z4.s\n" + ".inst 0x44828080 // srshl z0.s, p0/M, z0.s, z4.s\n" + ".inst 0x4482809f // srshl z31.s, p0/M, z31.s, z4.s\n" + ".inst 0x4482809e // srshl z30.s, p0/M, z30.s, z4.s\n" + ".inst 0x44828096 // srshl z22.s, p0/M, z22.s, z4.s\n" + ".inst 0x4482809d // srshl z29.s, p0/M, z29.s, z4.s\n" + ".inst 0x44828092 // srshl z18.s, p0/M, z18.s, z4.s\n" + ".inst 0x4482809c // srshl z28.s, p0/M, z28.s, z4.s\n" + ".inst 0x44828095 // srshl z21.s, p0/M, z21.s, z4.s\n" + ".inst 0x4482809b // srshl z27.s, p0/M, z27.s, z4.s\n" + ".inst 0x44828091 // srshl z17.s, p0/M, z17.s, z4.s\n" + ".inst 0x4482809a // srshl z26.s, p0/M, z26.s, z4.s\n" + ".inst 0x44828094 // srshl z20.s, p0/M, z20.s, z4.s\n" + ".inst 0x44828099 // srshl z25.s, p0/M, z25.s, z4.s\n" + ".inst 0x44828098 // srshl z24.s, p0/M, z24.s, z4.s\n" + ".inst 0x04a37421 // sqrdmulh z1.s, z1.s, z3.s\n" + ".inst 0x04a376f7 // sqrdmulh z23.s, z23.s, z3.s\n" + ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" + ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" + ".inst 0x04a377de // sqrdmulh z30.s, z30.s, z3.s\n" + ".inst 0x04a376d6 // sqrdmulh z22.s, z22.s, z3.s\n" + ".inst 0x04a377bd // sqrdmulh z29.s, z29.s, z3.s\n" + ".inst 0x04a37652 // sqrdmulh z18.s, z18.s, z3.s\n" + ".inst 0x04a3779c // sqrdmulh z28.s, z28.s, z3.s\n" + ".inst 0x04a376b5 // sqrdmulh z21.s, z21.s, z3.s\n" + ".inst 0x04a3777b // sqrdmulh z27.s, z27.s, z3.s\n" + ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" + ".inst 0x04a3775a // sqrdmulh z26.s, z26.s, z3.s\n" + ".inst 0x04a37694 // sqrdmulh z20.s, z20.s, z3.s\n" + ".inst 0x04a37739 // sqrdmulh z25.s, z25.s, z3.s\n" + ".inst 0x04a37718 // sqrdmulh z24.s, z24.s, z3.s\n" + "mov z19.s, #0x7f\n" + ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" + ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" + ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" + ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" + ".inst 0x4482805e // srshl z30.s, p0/M, z30.s, z2.s\n" + ".inst 0x44828056 // srshl z22.s, p0/M, z22.s, z2.s\n" + ".inst 0x4482805d // srshl z29.s, p0/M, z29.s, z2.s\n" + ".inst 0x44828052 // srshl z18.s, p0/M, z18.s, z2.s\n" + ".inst 0x4482805c // srshl z28.s, p0/M, z28.s, z2.s\n" + ".inst 0x44828055 // srshl z21.s, p0/M, z21.s, z2.s\n" + ".inst 0x4482805b // srshl z27.s, p0/M, z27.s, z2.s\n" + ".inst 0x44828051 // srshl z17.s, p0/M, z17.s, z2.s\n" + ".inst 0x4482805a // srshl z26.s, p0/M, z26.s, z2.s\n" + ".inst 0x44828054 // srshl z20.s, p0/M, z20.s, z2.s\n" + ".inst 0x44828059 // srshl z25.s, p0/M, z25.s, z2.s\n" + ".inst 0x44828058 // srshl z24.s, p0/M, z24.s, z2.s\n" + "not z16.s, p0/M, z19.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smax z30.s, p0/M, z30.s, z16.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z29.s, p0/M, z29.s, z16.s\n" + "smax z18.s, p0/M, z18.s, z16.s\n" + "smax z28.s, p0/M, z28.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z27.s, p0/M, z27.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" + "smax z26.s, p0/M, z26.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z25.s, p0/M, z25.s, z16.s\n" + "smax z24.s, p0/M, z24.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z23.s, p0/M, z23.s, z19.s\n" + "trn1 z23.h, z1.h, z23.h\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "smin z31.s, p0/M, z31.s, z19.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "smin z30.s, p0/M, z30.s, z19.s\n" + "smin z22.s, p0/M, z22.s, z19.s\n" + "trn1 z22.h, z30.h, z22.h\n" + "smin z29.s, p0/M, z29.s, z19.s\n" + "smin z18.s, p0/M, z18.s, z19.s\n" + "trn1 z18.h, z29.h, z18.h\n" + "smin z28.s, p0/M, z28.s, z19.s\n" + "smin z21.s, p0/M, z21.s, z19.s\n" + "trn1 z21.h, z28.h, z21.h\n" + "smin z27.s, p0/M, z27.s, z19.s\n" + "smin z17.s, p0/M, z17.s, z19.s\n" + "trn1 z17.h, z27.h, z17.h\n" + "smin z26.s, p0/M, z26.s, z19.s\n" + "smin z20.s, p0/M, z20.s, z19.s\n" + "trn1 z20.h, z26.h, z20.h\n" + "smin z25.s, p0/M, z25.s, z19.s\n" + "smin z24.s, p0/M, z24.s, z19.s\n" + "trn1 z19.h, z25.h, z24.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "incb x9, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x80\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z16, z0\n smax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n smax z17.b, p0/M, z17.b, z30.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z4.b, p0/M, z4.b, z16.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + ".inst 0x4508a091 // sshllb z17.h, z4.b, #0x0\n" + ".inst 0x4508a490 // sshllt z16.h, z4.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + ".inst 0x4510a236 // sshllb z22.s, z17.h, #0x0\n" + ".inst 0x4510a635 // sshllt z21.s, z17.h, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x4510a214 // sshllb z20.s, z16.h, #0x0\n" + ".inst 0x4510a613 // sshllt z19.s, z16.h, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x44828256 // srshl z22.s, p0/M, z22.s, z18.s\n" + ".inst 0x44828255 // srshl z21.s, p0/M, z21.s, z18.s\n" + ".inst 0x44828254 // srshl z20.s, p0/M, z20.s, z18.s\n" + ".inst 0x44828253 // srshl z19.s, p0/M, z19.s, z18.s\n" + ".inst 0x04b176d6 // sqrdmulh z22.s, z22.s, z17.s\n" + ".inst 0x04b176b5 // sqrdmulh z21.s, z21.s, z17.s\n" + ".inst 0x04b17694 // sqrdmulh z20.s, z20.s, z17.s\n" + ".inst 0x04b17673 // sqrdmulh z19.s, z19.s, z17.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smin z22.s, p0/M, z22.s, z18.s\n" + "smin z21.s, p0/M, z21.s, z18.s\n" + "trn1 z17.h, z22.h, z21.h\n" + "smin z20.s, p0/M, z20.s, z18.s\n" + "smin z19.s, p0/M, z19.s, z18.s\n" + "trn1 z16.h, z20.h, z19.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [outptr] "r" (outptr), [quant_params] "r" (&qp) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..29a03ec509 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); + +struct sme_u8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; + sme_u8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..f0e7bbf5cc --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> +#include <cstring> +#include <cmath> + + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_u8_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) + { + shift_value++; + long_rescale_value >>= 1; + } + rescale_value = static_cast<int32_t>(long_rescale_value); + } + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p2.b, x25, %x[n_channels]\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x22, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "mov z11.s, #0x0\n" + "mov z10.s, #0x0\n" + "mov z9.s, #0x0\n" + "mov z8.s, #0x0\n" + "mov z7.s, #0x0\n" + "mov z6.s, #0x0\n" + "mov z5.s, #0x0\n" + "mov z4.s, #0x0\n" + "mov z3.s, #0x0\n" + "mov z2.s, #0x0\n" + "mov z1.s, #0x0\n" + "mov z0.s, #0x0\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa13 // ushllb z19.h, z16.b, #0x0\n" + ".inst 0x4508ae12 // ushllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" + ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + ".inst 0x04b1756b // sqdmulh z11.s, z11.s, z17.s\n" + ".inst 0x04b1754a // sqdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqdmulh z9.s, z9.s, z17.s\n" + ".inst 0x04b17508 // sqdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqdmulh z7.s, z7.s, z17.s\n" + ".inst 0x04b174c6 // sqdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqdmulh z5.s, z5.s, z17.s\n" + ".inst 0x04b17484 // sqdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqdmulh z1.s, z1.s, z17.s\n" + ".inst 0x04b17400 // sqdmulh z0.s, z0.s, z17.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x27, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z15.s, #0x0\n" + "mov z14.s, #0x0\n" + "mov x22, %x[inptrs]\n" + "mov z13.s, #0x0\n" + "mov z12.s, #0x0\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z16.s }, p0/Z, [%x[rescale_ptr]]\n" + ".inst 0x04b075ef // sqdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqdmulh z14.s, z14.s, z16.s\n" + ".inst 0x04b075ad // sqdmulh z13.s, z13.s, z16.s\n" + ".inst 0x04b0758c // sqdmulh z12.s, z12.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp new file mode 100644 index 0000000000..3df4e4efb8 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const uint8_t *const *const, uint8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + +struct sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<uint8_t, uint8_t> +{ + using Parent = DepthfirstStrategy<uint8_t, uint8_t>; + + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; + + sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} + + Parent::KernelType get_kernel(void) const { return sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp new file mode 100644 index 0000000000..9088cbde89 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( + const unsigned int n_channels, + const uint8_t *const *const inptrs, + uint8_t *const *const outptrs, + const bool exclude_padding, + const unsigned int pad_left, + const unsigned int pad_top, + const unsigned int pad_right, + const unsigned int pad_bottom +) +{ + struct KernelArgs + { + const uint64_t n_channels; + const uint8_t *const *const inptrs; + uint8_t *const *const outptrs; + KernelArgs( + unsigned int channels, + const uint8_t *const *input_ptrs, + uint8_t *const * output_ptrs, + bool, unsigned int, unsigned int, unsigned int, unsigned int + ) : n_channels(channels), + inptrs(input_ptrs), + outptrs(output_ptrs) + { + } + }; + + const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding, + pad_left, pad_top, pad_right, pad_bottom); + + __asm__ __volatile__( + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x15, #0x0\n" + "ptrue p2.b\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "mov x14, #0x0\n" + "ldr x13, [%x[args], %[offsetof_n_channels]]\n" + "whilelt p0.b, x15, x13\n" + "ldp x12, x11, [x21, #0x0]\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ld1b { z30.b }, p0/Z, [x27, x15]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ld1b { z29.b }, p0/Z, [x25, x15]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ld1b { z28.b }, p0/Z, [x24, x15]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ld1b { z27.b }, p0/Z, [x21, x15]\n" + "ldr x20, [x20, #0x40]\n" + "ld1b { z26.b }, p0/Z, [x28, x15]\n" + "ld1b { z25.b }, p0/Z, [x26, x15]\n" + "ld1b { z24.b }, p0/Z, [x23, x15]\n" + "ld1b { z19.b }, p0/Z, [x22, x15]\n" + "ld1b { z23.b }, p0/Z, [x20, x15]\n" + "incw x15\n" + "whilelt p1.b, x15, x13\n" + "b.none 2f\n" + "1:" // Vector: Loop + "movprfx z22, z30\n umax z22.b, p2/M, z22.b, z28.b\n" + "movprfx z21, z28\n umax z21.b, p2/M, z21.b, z27.b\n" + "ld1b { z30.b }, p1/Z, [x27, x15]\n" + "whilelt p0.b, x14, x13\n" + "movprfx z18, z29\n umax z18.b, p2/M, z18.b, z26.b\n" + "movprfx z17, z25\n umax z17.b, p2/M, z17.b, z24.b\n" + "ld1b { z28.b }, p1/Z, [x24, x15]\n" + "movprfx z16, z29\n umax z16.b, p2/M, z16.b, z19.b\n" + "movprfx z20, z24\n umax z20.b, p2/M, z20.b, z23.b\n" + "ld1b { z27.b }, p1/Z, [x21, x15]\n" + "ld1b { z29.b }, p1/Z, [x25, x15]\n" + "movprfx z19, z22\n umax z19.b, p2/M, z19.b, z18.b\n" + "movprfx z18, z17\n umax z18.b, p2/M, z18.b, z22.b\n" + "ld1b { z26.b }, p1/Z, [x28, x15]\n" + "movprfx z17, z16\n umax z17.b, p2/M, z17.b, z21.b\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z20.b\n" + "ld1b { z25.b }, p1/Z, [x26, x15]\n" + "st1b { z19.b }, p0, [x12, x14]\n" + "ld1b { z24.b }, p1/Z, [x23, x15]\n" + "st1b { z18.b }, p0, [x11, x14]\n" + "ld1b { z19.b }, p1/Z, [x22, x15]\n" + "st1b { z17.b }, p0, [x10, x14]\n" + "ld1b { z23.b }, p1/Z, [x20, x15]\n" + "incw x15\n" + "whilelt p1.b, x15, x13\n" + "st1b { z16.b }, p0, [x9, x14]\n" + "incw x14\n" + "b.any 1b\n" + "2:" // Vector: Tail + "movprfx z22, z30\n umax z22.b, p2/M, z22.b, z28.b\n" + "movprfx z21, z28\n umax z21.b, p2/M, z21.b, z27.b\n" + "whilelt p0.b, x14, x13\n" + "movprfx z20, z29\n umax z20.b, p2/M, z20.b, z26.b\n" + "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z24.b\n" + "movprfx z17, z29\n umax z17.b, p2/M, z17.b, z19.b\n" + "movprfx z19, z24\n umax z19.b, p2/M, z19.b, z23.b\n" + "movprfx z16, z22\n umax z16.b, p2/M, z16.b, z20.b\n" + "umax z18.b, p2/M, z18.b, z22.b\n" + "st1b { z16.b }, p0, [x12, x14]\n" + "umax z17.b, p2/M, z17.b, z21.b\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z19.b\n" + "st1b { z18.b }, p0, [x11, x14]\n" + "st1b { z17.b }, p0, [x10, x14]\n" + "st1b { z16.b }, p0, [x9, x14]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..077c8ed2f7 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); + +struct sme_u8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; + sme_u8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..06f13e8111 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + + +void sme_u8_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p2.b, x27, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x0\n" + "mov z3.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "mov z2.b, #0x0\n" + "mov z1.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "umax z4.b, p0/M, z4.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "umax z4.b, p0/M, z4.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z4.b, p0/M, z4.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "umax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x9]\n" + "incb x9, ALL, MUL #4\n" + "st1b { z3.b }, p3, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "st1b { z2.b }, p2, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z1.b }, p1, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z4.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z4.b, p0/M, z4.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z4.b, p0/M, z4.b, z16.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z4.b, p0/M, z4.b, z16.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "st1b { z4.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp new file mode 100644 index 0000000000..bd30a32828 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); + +struct sme_u8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; + sme_u8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8q_nhwc_avg_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..52c52ccdb9 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -0,0 +1,489 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "pooling.hpp" +#include <cstdint> +#include <cstddef> +#include <cstring> +#include <cmath> + + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +namespace { + struct RescaleParams + { + int32_t multiplier, shift; + }; + + constexpr RescaleParams rescale_params[8] = { + {0x40000000, -0}, // 1/2 + {0x55555556, -1}, // 1/3 + {0x40000000, -1}, // 1/4 + {0x66666666, -2}, // 1/5 + {0x55555556, -2}, // 1/6 + {0x49249249, -2}, // 1/7 + {0x40000000, -2}, // 1/8 + {0x71c71c72, -3}, // 1/9 + }; +} + +void sme_u8q_nhwc_avg_generic_depthfirst_impl( + const uint64_t window_cells, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr, + const Requantize32 &qp +) +{ + if (n_valid_cells == 1 && window_cells == 1) + { + // In this case, simply copy from the input to the output + std::memcpy(outptr, *inptrs, n_channels); + return; + } + + // Compute (or look up) the rescale values + int32_t shift_value = 0, rescale_value = 0; + if (2 <= window_cells && window_cells <= 9) + { + auto ¶ms = rescale_params[window_cells - 2]; + rescale_value = params.multiplier; + shift_value = params.shift; + } + else + { + auto f_rescale_value = 1.0f / static_cast<float>(window_cells); + + shift_value = 0; + while (f_rescale_value < 0.5f) + { + shift_value--; + f_rescale_value *= 2.0f; + } + + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) + { + shift_value++; + long_rescale_value >>= 1; + } + rescale_value = static_cast<int32_t>(long_rescale_value); + } + + + // Initialise the accumulators such that the offsets are subtracted for all + // valid inputs. + const int32_t accumulator_init = -qp.input_offset * n_valid_cells; + + // Combine together the rescale value for the requantization and the scaling + // factor for the average pool. + const int32_t shift = qp.per_layer_left_shift - qp.per_layer_right_shift + shift_value; + const int32_t left_shift = shift > 0 ? shift : 0; + const int32_t right_shift = shift <= 0 ? shift : 0; + + int32_t combined_rescale_value = 0; + __asm__ __volatile__ ( + "mov v16.s[0], %w[per_layer_mul]\n" + "mov v17.s[0], %w[rescale_value]\n" + "sqrdmulh s18, s16, s17\n" + "mov %w[combined_rescale_value], v18.s[0]\n" + : [combined_rescale_value] "=r" (combined_rescale_value) + : [per_layer_mul] "r" (qp.per_layer_mul), [rescale_value] "r" (rescale_value) + : "v16", "v17", "v18" + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p2.b, x25, %x[n_channels]\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "ld1rw { z15.s }, p0/Z, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z14.d, z15.d\n" + "mov z13.d, z15.d\n" + "mov z12.d, z15.d\n" + "mov z11.d, z15.d\n" + "mov x22, %x[inptrs]\n" + "mov z10.d, z15.d\n" + "mov z9.d, z15.d\n" + "mov z8.d, z15.d\n" + "mov z7.d, z15.d\n" + "mov z6.d, z15.d\n" + "mov z5.d, z15.d\n" + "mov z4.d, z15.d\n" + "mov z3.d, z15.d\n" + "mov z2.d, z15.d\n" + "mov z1.d, z15.d\n" + "mov z0.d, z15.d\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 2 inputs loop + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 2 inputs tail + ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" + ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" + ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" + ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" + ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" + ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" + ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" + ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + "ld1b { z16.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa13 // ushllb z19.h, z16.b, #0x0\n" + ".inst 0x4508ae12 // ushllt z18.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" + ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" + ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "ld1rw { z19.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482826f // srshl z15.s, p0/M, z15.s, z19.s\n" + ".inst 0x4482826e // srshl z14.s, p0/M, z14.s, z19.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x4482826d // srshl z13.s, p0/M, z13.s, z19.s\n" + ".inst 0x4482826c // srshl z12.s, p0/M, z12.s, z19.s\n" + "ld1rw { z18.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482826b // srshl z11.s, p0/M, z11.s, z19.s\n" + ".inst 0x4482826a // srshl z10.s, p0/M, z10.s, z19.s\n" + "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x44828269 // srshl z9.s, p0/M, z9.s, z19.s\n" + ".inst 0x44828268 // srshl z8.s, p0/M, z8.s, z19.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x44828267 // srshl z7.s, p0/M, z7.s, z19.s\n" + ".inst 0x44828266 // srshl z6.s, p0/M, z6.s, z19.s\n" + ".inst 0x44828265 // srshl z5.s, p0/M, z5.s, z19.s\n" + ".inst 0x44828264 // srshl z4.s, p0/M, z4.s, z19.s\n" + ".inst 0x44828263 // srshl z3.s, p0/M, z3.s, z19.s\n" + ".inst 0x44828262 // srshl z2.s, p0/M, z2.s, z19.s\n" + ".inst 0x44828261 // srshl z1.s, p0/M, z1.s, z19.s\n" + ".inst 0x44828260 // srshl z0.s, p0/M, z0.s, z19.s\n" + ".inst 0x04b275ef // sqrdmulh z15.s, z15.s, z18.s\n" + ".inst 0x04b275ce // sqrdmulh z14.s, z14.s, z18.s\n" + ".inst 0x04b275ad // sqrdmulh z13.s, z13.s, z18.s\n" + ".inst 0x04b2758c // sqrdmulh z12.s, z12.s, z18.s\n" + ".inst 0x04b2756b // sqrdmulh z11.s, z11.s, z18.s\n" + ".inst 0x04b2754a // sqrdmulh z10.s, z10.s, z18.s\n" + ".inst 0x04b27529 // sqrdmulh z9.s, z9.s, z18.s\n" + ".inst 0x04b27508 // sqrdmulh z8.s, z8.s, z18.s\n" + ".inst 0x04b274e7 // sqrdmulh z7.s, z7.s, z18.s\n" + ".inst 0x04b274c6 // sqrdmulh z6.s, z6.s, z18.s\n" + ".inst 0x04b274a5 // sqrdmulh z5.s, z5.s, z18.s\n" + ".inst 0x04b27484 // sqrdmulh z4.s, z4.s, z18.s\n" + ".inst 0x04b27463 // sqrdmulh z3.s, z3.s, z18.s\n" + ".inst 0x04b27442 // sqrdmulh z2.s, z2.s, z18.s\n" + ".inst 0x04b27421 // sqrdmulh z1.s, z1.s, z18.s\n" + ".inst 0x04b27400 // sqrdmulh z0.s, z0.s, z18.s\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" + ".inst 0x4482822b // srshl z11.s, p0/M, z11.s, z17.s\n" + ".inst 0x4482822a // srshl z10.s, p0/M, z10.s, z17.s\n" + ".inst 0x44828229 // srshl z9.s, p0/M, z9.s, z17.s\n" + ".inst 0x44828228 // srshl z8.s, p0/M, z8.s, z17.s\n" + ".inst 0x44828227 // srshl z7.s, p0/M, z7.s, z17.s\n" + ".inst 0x44828226 // srshl z6.s, p0/M, z6.s, z17.s\n" + ".inst 0x44828225 // srshl z5.s, p0/M, z5.s, z17.s\n" + ".inst 0x44828224 // srshl z4.s, p0/M, z4.s, z17.s\n" + ".inst 0x44828223 // srshl z3.s, p0/M, z3.s, z17.s\n" + ".inst 0x44828222 // srshl z2.s, p0/M, z2.s, z17.s\n" + ".inst 0x44828221 // srshl z1.s, p0/M, z1.s, z17.s\n" + ".inst 0x44828220 // srshl z0.s, p0/M, z0.s, z17.s\n" + "add z15.s, z15.s, z16.s\n" + "add z14.s, z14.s, z16.s\n" + "add z13.s, z13.s, z16.s\n" + "add z12.s, z12.s, z16.s\n" + "add z11.s, z11.s, z16.s\n" + "add z10.s, z10.s, z16.s\n" + "add z9.s, z9.s, z16.s\n" + "add z8.s, z8.s, z16.s\n" + "add z7.s, z7.s, z16.s\n" + "add z6.s, z6.s, z16.s\n" + "add z5.s, z5.s, z16.s\n" + "add z4.s, z4.s, z16.s\n" + "add z3.s, z3.s, z16.s\n" + "add z2.s, z2.s, z16.s\n" + "add z1.s, z1.s, z16.s\n" + "add z0.s, z0.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z19.s\n" + "smin z14.s, p0/M, z14.s, z19.s\n" + "trn1 z23.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z19.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "smin z11.s, p0/M, z11.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z19.s\n" + "trn1 z22.h, z11.h, z10.h\n" + "smin z9.s, p0/M, z9.s, z19.s\n" + "smin z8.s, p0/M, z8.s, z19.s\n" + "trn1 z18.h, z9.h, z8.h\n" + "smin z7.s, p0/M, z7.s, z19.s\n" + "smin z6.s, p0/M, z6.s, z19.s\n" + "trn1 z21.h, z7.h, z6.h\n" + "smin z5.s, p0/M, z5.s, z19.s\n" + "smin z4.s, p0/M, z4.s, z19.s\n" + "trn1 z17.h, z5.h, z4.h\n" + "smin z3.s, p0/M, z3.s, z19.s\n" + "smin z2.s, p0/M, z2.s, z19.s\n" + "trn1 z20.h, z3.h, z2.h\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z19.h, z1.h, z0.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "trn1 z17.b, z21.b, z17.b\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x25]\n" + "incb x25, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x27, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "ld1rw { z15.s }, p0/Z, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" + "mov z14.d, z15.d\n" + "mov z13.d, z15.d\n" + "mov z12.d, z15.d\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 2 inputs loop + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 2 inputs tail + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x1\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "ld1rw { z16.s }, p0/Z, [%x[left_shift]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x04b075ef // sqrdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqrdmulh z14.s, z14.s, z16.s\n" + "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b075ad // sqrdmulh z13.s, z13.s, z16.s\n" + ".inst 0x04b0758c // sqrdmulh z12.s, z12.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" + "add z15.s, z15.s, z16.s\n" + "add z14.s, z14.s, z16.s\n" + "add z13.s, z13.s, z16.s\n" + "add z12.s, z12.s, z16.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" + "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" + "trn1 z16.h, z13.h, z12.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [accumulator_init] "r" (&accumulator_init), [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [outptr] "r" (outptr), [quant_params] "r" (&qp), [right_shift] "r" (&right_shift) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp new file mode 100644 index 0000000000..69d627c047 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstdint> + +#pragma once + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + +void sme_u8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); + +struct sme_u8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> +{ + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; + sme_u8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sme_u8q_nhwc_max_generic_depthfirst_impl; } +}; + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp new file mode 100644 index 0000000000..c8e8e7d399 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sme_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "pooling.hpp" +#include <cstdint> +#include <cstddef> + +#if defined(ARM_COMPUTE_ENABLE_SME) + +namespace arm_conv { +namespace pooling { + + +void sme_u8q_nhwc_max_generic_depthfirst_impl( + const uint64_t, + const uint64_t n_valid_cells, + uint64_t n_channels, + const uint8_t *const *const inptrs, + uint8_t *outptr, + const Requantize32 &qp +) +{ + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p2.b, x27, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "ptrue p0.b\n" + "b.none 7f\n" + "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov z3.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "mov z2.b, #0x0\n" + "mov z1.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "beq 3f\n" + "2:" // 4-vectors of channels: 4 inputs loop + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "umax z5.b, p0/M, z5.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "ld1b { z18.b }, p3/Z, [x23, x28]\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "ld1b { z29.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z28.b }, p3/Z, [x20, x28]\n" + "ld1b { z17.b }, p2/Z, [x23, x27]\n" + "ld1b { z27.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z26.b }, p2/Z, [x20, x27]\n" + "ld1b { z16.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" + "bgt 2b\n" + "3:" // 4-vectors of channels: 4 inputs tail + "movprfx z19, z0\n umax z19.b, p0/M, z19.b, z31.b\n" + "umax z23.b, p0/M, z23.b, z30.b\n" + "umax z18.b, p0/M, z18.b, z29.b\n" + "umax z22.b, p0/M, z22.b, z28.b\n" + "umax z17.b, p0/M, z17.b, z27.b\n" + "umax z21.b, p0/M, z21.b, z26.b\n" + "umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "umax z5.b, p0/M, z5.b, z19.b\n" + "umax z3.b, p0/M, z3.b, z18.b\n" + "umax z2.b, p0/M, z2.b, z17.b\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "4:" // 4-vectors of channels: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 6f\n" + "5:" // 4-vectors of channels: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "ld1b { z16.b }, p3/Z, [x20, x28]\n" + "umax z3.b, p0/M, z3.b, z16.b\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z2.b, p0/M, z2.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "umax z1.b, p0/M, z1.b, z16.b\n" + "bgt 5b\n" + "6:" // 4-vectors of channels: Single input loop: End + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1rw { z4.s }, p0/Z, [x20]\n" + ".inst 0x4508a8b7 // ushllb z23.h, z5.b, #0x0\n" + ".inst 0x4508acb9 // ushllt z25.h, z5.b, #0x0\n" + ".inst 0x4508a876 // ushllb z22.h, z3.b, #0x0\n" + ".inst 0x4508ac72 // ushllt z18.h, z3.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z3.s }, p0/Z, [x20]\n" + ".inst 0x4508a855 // ushllb z21.h, z2.b, #0x0\n" + ".inst 0x4508ac51 // ushllt z17.h, z2.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z2.s }, p0/Z, [x20]\n" + ".inst 0x4508a834 // ushllb z20.h, z1.b, #0x0\n" + ".inst 0x4508ac38 // ushllt z24.h, z1.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z19.s }, p0/Z, [x20]\n" + "neg z4.s, p0/M, z4.s\n" + ".inst 0x45974081 // saddwb z1.s, z4.s, z23.h\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x45974497 // saddwt z23.s, z4.s, z23.h\n" + ".inst 0x45994080 // saddwb z0.s, z4.s, z25.h\n" + ".inst 0x4599449f // saddwt z31.s, z4.s, z25.h\n" + ".inst 0x4596409e // saddwb z30.s, z4.s, z22.h\n" + ".inst 0x45964496 // saddwt z22.s, z4.s, z22.h\n" + ".inst 0x4592409d // saddwb z29.s, z4.s, z18.h\n" + ".inst 0x45924492 // saddwt z18.s, z4.s, z18.h\n" + ".inst 0x4595409c // saddwb z28.s, z4.s, z21.h\n" + ".inst 0x45954495 // saddwt z21.s, z4.s, z21.h\n" + ".inst 0x4591409b // saddwb z27.s, z4.s, z17.h\n" + ".inst 0x45914491 // saddwt z17.s, z4.s, z17.h\n" + ".inst 0x4594409a // saddwb z26.s, z4.s, z20.h\n" + ".inst 0x45944494 // saddwt z20.s, z4.s, z20.h\n" + ".inst 0x45984099 // saddwb z25.s, z4.s, z24.h\n" + ".inst 0x45984498 // saddwt z24.s, z4.s, z24.h\n" + ".inst 0x44828061 // srshl z1.s, p0/M, z1.s, z3.s\n" + ".inst 0x44828077 // srshl z23.s, p0/M, z23.s, z3.s\n" + ".inst 0x44828060 // srshl z0.s, p0/M, z0.s, z3.s\n" + ".inst 0x4482807f // srshl z31.s, p0/M, z31.s, z3.s\n" + ".inst 0x4482807e // srshl z30.s, p0/M, z30.s, z3.s\n" + ".inst 0x44828076 // srshl z22.s, p0/M, z22.s, z3.s\n" + ".inst 0x4482807d // srshl z29.s, p0/M, z29.s, z3.s\n" + ".inst 0x44828072 // srshl z18.s, p0/M, z18.s, z3.s\n" + ".inst 0x4482807c // srshl z28.s, p0/M, z28.s, z3.s\n" + ".inst 0x44828075 // srshl z21.s, p0/M, z21.s, z3.s\n" + ".inst 0x4482807b // srshl z27.s, p0/M, z27.s, z3.s\n" + ".inst 0x44828071 // srshl z17.s, p0/M, z17.s, z3.s\n" + ".inst 0x4482807a // srshl z26.s, p0/M, z26.s, z3.s\n" + ".inst 0x44828074 // srshl z20.s, p0/M, z20.s, z3.s\n" + ".inst 0x44828079 // srshl z25.s, p0/M, z25.s, z3.s\n" + ".inst 0x44828078 // srshl z24.s, p0/M, z24.s, z3.s\n" + ".inst 0x04a27421 // sqrdmulh z1.s, z1.s, z2.s\n" + ".inst 0x04a276f7 // sqrdmulh z23.s, z23.s, z2.s\n" + ".inst 0x04a27400 // sqrdmulh z0.s, z0.s, z2.s\n" + ".inst 0x04a277ff // sqrdmulh z31.s, z31.s, z2.s\n" + ".inst 0x04a277de // sqrdmulh z30.s, z30.s, z2.s\n" + ".inst 0x04a276d6 // sqrdmulh z22.s, z22.s, z2.s\n" + ".inst 0x04a277bd // sqrdmulh z29.s, z29.s, z2.s\n" + ".inst 0x04a27652 // sqrdmulh z18.s, z18.s, z2.s\n" + ".inst 0x04a2779c // sqrdmulh z28.s, z28.s, z2.s\n" + ".inst 0x04a276b5 // sqrdmulh z21.s, z21.s, z2.s\n" + ".inst 0x04a2777b // sqrdmulh z27.s, z27.s, z2.s\n" + ".inst 0x04a27631 // sqrdmulh z17.s, z17.s, z2.s\n" + ".inst 0x04a2775a // sqrdmulh z26.s, z26.s, z2.s\n" + ".inst 0x04a27694 // sqrdmulh z20.s, z20.s, z2.s\n" + ".inst 0x04a27739 // sqrdmulh z25.s, z25.s, z2.s\n" + ".inst 0x04a27718 // sqrdmulh z24.s, z24.s, z2.s\n" + ".inst 0x44828261 // srshl z1.s, p0/M, z1.s, z19.s\n" + ".inst 0x44828277 // srshl z23.s, p0/M, z23.s, z19.s\n" + ".inst 0x44828260 // srshl z0.s, p0/M, z0.s, z19.s\n" + ".inst 0x4482827f // srshl z31.s, p0/M, z31.s, z19.s\n" + ".inst 0x4482827e // srshl z30.s, p0/M, z30.s, z19.s\n" + ".inst 0x44828276 // srshl z22.s, p0/M, z22.s, z19.s\n" + ".inst 0x4482827d // srshl z29.s, p0/M, z29.s, z19.s\n" + ".inst 0x44828272 // srshl z18.s, p0/M, z18.s, z19.s\n" + ".inst 0x4482827c // srshl z28.s, p0/M, z28.s, z19.s\n" + ".inst 0x44828275 // srshl z21.s, p0/M, z21.s, z19.s\n" + ".inst 0x4482827b // srshl z27.s, p0/M, z27.s, z19.s\n" + ".inst 0x44828271 // srshl z17.s, p0/M, z17.s, z19.s\n" + ".inst 0x4482827a // srshl z26.s, p0/M, z26.s, z19.s\n" + ".inst 0x44828274 // srshl z20.s, p0/M, z20.s, z19.s\n" + ".inst 0x44828279 // srshl z25.s, p0/M, z25.s, z19.s\n" + ".inst 0x44828278 // srshl z24.s, p0/M, z24.s, z19.s\n" + "add z1.s, z1.s, z16.s\n" + "add z23.s, z23.s, z16.s\n" + "add z0.s, z0.s, z16.s\n" + "add z31.s, z31.s, z16.s\n" + "add z30.s, z30.s, z16.s\n" + "add z22.s, z22.s, z16.s\n" + "add z29.s, z29.s, z16.s\n" + "add z18.s, z18.s, z16.s\n" + "add z28.s, z28.s, z16.s\n" + "add z21.s, z21.s, z16.s\n" + "add z27.s, z27.s, z16.s\n" + "add z17.s, z17.s, z16.s\n" + "add z26.s, z26.s, z16.s\n" + "add z20.s, z20.s, z16.s\n" + "add z25.s, z25.s, z16.s\n" + "add z24.s, z24.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z19.s, #0xff\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smax z30.s, p0/M, z30.s, z16.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z29.s, p0/M, z29.s, z16.s\n" + "smax z18.s, p0/M, z18.s, z16.s\n" + "smax z28.s, p0/M, z28.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z27.s, p0/M, z27.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" + "smax z26.s, p0/M, z26.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z25.s, p0/M, z25.s, z16.s\n" + "smax z24.s, p0/M, z24.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z19.s\n" + "smin z23.s, p0/M, z23.s, z19.s\n" + "smin z0.s, p0/M, z0.s, z19.s\n" + "trn1 z23.h, z1.h, z23.h\n" + "smin z31.s, p0/M, z31.s, z19.s\n" + "smin z30.s, p0/M, z30.s, z19.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "smin z22.s, p0/M, z22.s, z19.s\n" + "smin z29.s, p0/M, z29.s, z19.s\n" + "trn1 z22.h, z30.h, z22.h\n" + "smin z18.s, p0/M, z18.s, z19.s\n" + "smin z28.s, p0/M, z28.s, z19.s\n" + "trn1 z18.h, z29.h, z18.h\n" + "smin z21.s, p0/M, z21.s, z19.s\n" + "smin z27.s, p0/M, z27.s, z19.s\n" + "trn1 z21.h, z28.h, z21.h\n" + "smin z17.s, p0/M, z17.s, z19.s\n" + "smin z26.s, p0/M, z26.s, z19.s\n" + "trn1 z17.h, z27.h, z17.h\n" + "smin z20.s, p0/M, z20.s, z19.s\n" + "smin z25.s, p0/M, z25.s, z19.s\n" + "trn1 z20.h, z26.h, z20.h\n" + "smin z24.s, p0/M, z24.s, z19.s\n" + "trn1 z19.h, z25.h, z24.h\n" + "trn1 z16.b, z23.b, z16.b\n" + "trn1 z18.b, z22.b, z18.b\n" + "trn1 z17.b, z21.b, z17.b\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "incb x9, ALL, MUL #4\n" + "trn1 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p3, [%x[outptr], x28]\n" + "incb x28, ALL, MUL #4\n" + "st1b { z17.b }, p2, [%x[outptr], x27]\n" + "incb x27, ALL, MUL #4\n" + "st1b { z16.b }, p1, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "b.any 1b\n" + "7:" // Single vector of channels + "whilelt p4.b, x9, %x[n_channels]\n" + "b.none 14f\n" + "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z5.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x20, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "ld1b { z0.b }, p4/Z, [x20, x9]\n" + "ldp x21, x20, [x24, #0x10]\n" + "add x24, x24, #0x20\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "beq 10f\n" + "9:" // Single vector of channels: Loop: 4 inputs loop + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "subs x25, x25, #0x1\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z0.b }, p4/Z, [x23, x9]\n" + "ld1b { z31.b }, p4/Z, [x22, x9]\n" + "ld1b { z23.b }, p4/Z, [x21, x9]\n" + "ld1b { z30.b }, p4/Z, [x20, x9]\n" + "bgt 9b\n" + "10:" // Single vector of channels: Loop: 4 inputs tail + "movprfx z16, z0\n umax z16.b, p0/M, z16.b, z31.b\n" + "movprfx z17, z23\n umax z17.b, p0/M, z17.b, z30.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "11:" // Single vector of channels: Loop: After loop + "ands x21, %x[n_valid_cells], #0x3\n" + "beq 13f\n" + "12:" // Single vector of channels: Loop: Single input loop + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "bgt 12b\n" + "13:" // Single vector of channels: Loop: Single input loop: End + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + ".inst 0x4508a8b1 // ushllb z17.h, z5.b, #0x0\n" + ".inst 0x4508acb0 // ushllt z16.h, z5.b, #0x0\n" + "neg z18.s, p0/M, z18.s\n" + ".inst 0x45914257 // saddwb z23.s, z18.s, z17.h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z22.s }, p0/Z, [x20]\n" + ".inst 0x45914655 // saddwt z21.s, z18.s, z17.h\n" + ".inst 0x45904254 // saddwb z20.s, z18.s, z16.h\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z19.s }, p0/Z, [x20]\n" + ".inst 0x45904652 // saddwt z18.s, z18.s, z16.h\n" + ".inst 0x448282d7 // srshl z23.s, p0/M, z23.s, z22.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x448282d5 // srshl z21.s, p0/M, z21.s, z22.s\n" + ".inst 0x448282d4 // srshl z20.s, p0/M, z20.s, z22.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x448282d2 // srshl z18.s, p0/M, z18.s, z22.s\n" + ".inst 0x04b376f7 // sqrdmulh z23.s, z23.s, z19.s\n" + ".inst 0x04b376b5 // sqrdmulh z21.s, z21.s, z19.s\n" + ".inst 0x04b37694 // sqrdmulh z20.s, z20.s, z19.s\n" + ".inst 0x04b37652 // sqrdmulh z18.s, z18.s, z19.s\n" + ".inst 0x44828237 // srshl z23.s, p0/M, z23.s, z17.s\n" + ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" + ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" + ".inst 0x44828232 // srshl z18.s, p0/M, z18.s, z17.s\n" + "add z23.s, z23.s, z16.s\n" + "add z21.s, z21.s, z16.s\n" + "add z20.s, z20.s, z16.s\n" + "add z18.s, z18.s, z16.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z23.s, p0/M, z23.s, z17.s\n" + "smax z21.s, p0/M, z21.s, z17.s\n" + "smax z20.s, p0/M, z20.s, z17.s\n" + "smax z18.s, p0/M, z18.s, z17.s\n" + "smin z23.s, p0/M, z23.s, z16.s\n" + "smin z21.s, p0/M, z21.s, z16.s\n" + "smin z20.s, p0/M, z20.s, z16.s\n" + "trn1 z17.h, z23.h, z21.h\n" + "smin z18.s, p0/M, z18.s, z16.s\n" + "trn1 z16.h, z20.h, z18.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" + "b.any 8b\n" + "14:" // End + ".inst 0xd503467f // SMSTOP\n" + : + : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_input_offset] "I" (offsetof(Requantize32, input_offset)), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [outptr] "r" (outptr), [quant_params] "r" (&qp) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace pooling +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index 8c7a497376..f8293233e6 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst +struct sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; + using Parent = DepthfirstStrategy<__fp16, __fp16>; - typedef void (*kern_type)(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } + sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 3; } - constexpr static unsigned int pool_cols(void) { return 3; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; - - sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 3c1858633b..1ba78f3fba 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -82,126 +82,126 @@ void sve_fp16_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x3, [%x[args], %[offsetof_n_channels]]\n" - "mov x4, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x5, #0x0\n" - "ldr x6, [%x[args], %[offsetof_inptrs]]\n" - "mov x19, #0x4\n" - "add x7, %x[args], %[offsetof_rescale]\n" - "ldp x8, x17, [x20, #0x0]\n" - "ldp x16, x15, [x20, #0x10]\n" - "whilelt p0.h, XZR, x19\n" - "ldp x14, x13, [x6, #0x0]\n" - "whilelt p1.h, x4, x3\n" - "ldp x12, x11, [x6, #0x10]\n" - "ldp x10, x9, [x6, #0x20]\n" - "ldp x28, x27, [x6, #0x30]\n" - "ldp x26, x25, [x6, #0x40]\n" - "ldp x24, x23, [x6, #0x50]\n" - "ldp x22, x21, [x6, #0x60]\n" - "ldp x20, x19, [x6, #0x70]\n" - "ld1rqh { z7.h }, p0/Z, [x7]\n" - "ld1h { z8.h }, p1/Z, [x9, x4, LSL #1]\n" - "ld1h { z6.h }, p1/Z, [x28, x4, LSL #1]\n" - "ld1h { z5.h }, p1/Z, [x25, x4, LSL #1]\n" - "ld1h { z4.h }, p1/Z, [x24, x4, LSL #1]\n" - "ld1h { z3.h }, p1/Z, [x13, x4, LSL #1]\n" - "ld1h { z2.h }, p1/Z, [x12, x4, LSL #1]\n" - "ld1h { z1.h }, p1/Z, [x10, x4, LSL #1]\n" - "ld1h { z0.h }, p1/Z, [x26, x4, LSL #1]\n" - "ld1h { z31.h }, p1/Z, [x27, x4, LSL #1]\n" - "ld1h { z30.h }, p1/Z, [x23, x4, LSL #1]\n" - "ld1h { z29.h }, p1/Z, [x21, x4, LSL #1]\n" - "ld1h { z28.h }, p1/Z, [x20, x4, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x14, x4, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x11, x4, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x22, x4, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x19, x4, LSL #1]\n" - "incw x4\n" - "whilelt p1.h, x4, x3\n" + "ldr x2, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x3, #0x0\n" + "mov x20, #0x4\n" + "ldr x4, [%x[args], %[offsetof_inptrs]]\n" + "ldp x5, x6, [x21, #0x0]\n" + "whilelt p2.h, XZR, x20\n" + "whilelt p0.h, x3, x2\n" + "ldp x7, x8, [x21, #0x10]\n" + "ldp x17, x16, [x4, #0x0]\n" + "add x15, %x[args], %[offsetof_rescale]\n" + "mov x14, #0x0\n" + "ldp x13, x12, [x4, #0x10]\n" + "ldp x11, x10, [x4, #0x20]\n" + "ldp x9, x28, [x4, #0x30]\n" + "ldp x27, x26, [x4, #0x40]\n" + "ldp x25, x24, [x4, #0x50]\n" + "ldp x23, x22, [x4, #0x60]\n" + "ldp x21, x20, [x4, #0x70]\n" + "ld1h { z7.h }, p0/Z, [x10, x3, LSL #1]\n" + "ld1h { z6.h }, p0/Z, [x9, x3, LSL #1]\n" + "ld1h { z5.h }, p0/Z, [x26, x3, LSL #1]\n" + "ld1h { z4.h }, p0/Z, [x25, x3, LSL #1]\n" + "ld1h { z3.h }, p0/Z, [x16, x3, LSL #1]\n" + "ld1h { z2.h }, p0/Z, [x13, x3, LSL #1]\n" + "ld1h { z1.h }, p0/Z, [x11, x3, LSL #1]\n" + "ld1h { z31.h }, p0/Z, [x27, x3, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x28, x3, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x24, x3, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x22, x3, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x21, x3, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x17, x3, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x12, x3, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x3, LSL #1]\n" + "incw x3\n" + "whilelt p1.h, x3, x2\n" + "ld1rqh { z0.h }, p2/Z, [x15]\n" "b.none 2f\n" "1:" // Vector: Loop - "fadd z17.h, z8.h, z6.h\n" - "ld1h { z8.h }, p1/Z, [x9, x4, LSL #1]\n" - "whilelt p0.h, x5, x3\n" + "fadd z17.h, z7.h, z6.h\n" "fadd z16.h, z5.h, z4.h\n" - "ld1h { z6.h }, p1/Z, [x28, x4, LSL #1]\n" + "ld1h { z7.h }, p1/Z, [x10, x3, LSL #1]\n" + "ld1h { z6.h }, p1/Z, [x9, x3, LSL #1]\n" + "fadd z19.h, z17.h, z16.h\n" "fadd z18.h, z3.h, z2.h\n" - "ld1h { z5.h }, p1/Z, [x25, x4, LSL #1]\n" - "fadd z23.h, z1.h, z0.h\n" - "ld1h { z4.h }, p1/Z, [x24, x4, LSL #1]\n" - "fadd z22.h, z31.h, z30.h\n" - "ld1h { z3.h }, p1/Z, [x13, x4, LSL #1]\n" - "fadd z17.h, z17.h, z16.h\n" - "ld1h { z2.h }, p1/Z, [x12, x4, LSL #1]\n" - "fadd z16.h, z29.h, z28.h\n" - "ld1h { z1.h }, p1/Z, [x10, x4, LSL #1]\n" - "fadd z19.h, z27.h, z23.h\n" - "ld1h { z0.h }, p1/Z, [x26, x4, LSL #1]\n" - "fadd z21.h, z18.h, z17.h\n" - "ld1h { z31.h }, p1/Z, [x27, x4, LSL #1]\n" - "fadd z20.h, z16.h, z17.h\n" - "ld1h { z30.h }, p1/Z, [x23, x4, LSL #1]\n" - "fadd z18.h, z26.h, z22.h\n" - "ld1h { z29.h }, p1/Z, [x21, x4, LSL #1]\n" - "fadd z17.h, z25.h, z23.h\n" - "ld1h { z28.h }, p1/Z, [x20, x4, LSL #1]\n" - "fadd z16.h, z24.h, z22.h\n" - "ld1h { z27.h }, p1/Z, [x14, x4, LSL #1]\n" + "ld1h { z5.h }, p1/Z, [x26, x3, LSL #1]\n" + "ld1h { z4.h }, p1/Z, [x25, x3, LSL #1]\n" + "fadd z17.h, z1.h, z31.h\n" + "fadd z22.h, z30.h, z29.h\n" + "ld1h { z3.h }, p1/Z, [x16, x3, LSL #1]\n" + "ld1h { z2.h }, p1/Z, [x13, x3, LSL #1]\n" + "fadd z16.h, z28.h, z27.h\n" + "fadd z21.h, z18.h, z19.h\n" + "ld1h { z1.h }, p1/Z, [x11, x3, LSL #1]\n" + "ld1h { z31.h }, p1/Z, [x27, x3, LSL #1]\n" + "fadd z20.h, z16.h, z19.h\n" + "fadd z19.h, z26.h, z17.h\n" + "ld1h { z30.h }, p1/Z, [x28, x3, LSL #1]\n" + "ld1h { z29.h }, p1/Z, [x24, x3, LSL #1]\n" + "fadd z18.h, z25.h, z22.h\n" + "fadd z17.h, z24.h, z17.h\n" + "ld1h { z28.h }, p1/Z, [x22, x3, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x21, x3, LSL #1]\n" + "fadd z16.h, z23.h, z22.h\n" + "ld1h { z26.h }, p1/Z, [x17, x3, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x12, x3, LSL #1]\n" "fadd z19.h, z21.h, z19.h\n" - "ld1h { z26.h }, p1/Z, [x11, x4, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x23, x3, LSL #1]\n" + "ld1h { z23.h }, p1/Z, [x20, x3, LSL #1]\n" + "incw x3\n" "fadd z18.h, z21.h, z18.h\n" - "ld1h { z25.h }, p1/Z, [x22, x4, LSL #1]\n" "fadd z17.h, z17.h, z20.h\n" - "ld1h { z24.h }, p1/Z, [x19, x4, LSL #1]\n" - "incw x4\n" - "fadd z16.h, z20.h, z16.h\n" - "whilelt p1.h, x4, x3\n" - "fmul z19.h, z19.h, z7.h[0]\n" - "st1h { z19.h }, p0, [x8, x5, LSL #1]\n" - "fmul z18.h, z18.h, z7.h[1]\n" - "fmul z17.h, z17.h, z7.h[2]\n" - "st1h { z18.h }, p0, [x17, x5, LSL #1]\n" - "fmul z16.h, z16.h, z7.h[3]\n" - "st1h { z17.h }, p0, [x16, x5, LSL #1]\n" - "st1h { z16.h }, p0, [x15, x5, LSL #1]\n" - "incw x5\n" + "fadd z16.h, z16.h, z20.h\n" + "whilelt p0.h, x14, x2\n" + "whilelt p1.h, x3, x2\n" + "fmul z19.h, z19.h, z0.h[0]\n" + "fmul z18.h, z18.h, z0.h[1]\n" + "st1h { z19.h }, p0, [x5, x14, LSL #1]\n" + "fmul z17.h, z17.h, z0.h[2]\n" + "fmul z16.h, z16.h, z0.h[3]\n" + "st1h { z18.h }, p0, [x6, x14, LSL #1]\n" + "st1h { z17.h }, p0, [x7, x14, LSL #1]\n" + "st1h { z16.h }, p0, [x8, x14, LSL #1]\n" + "incw x14\n" "b.any 1b\n" "2:" // Vector: Tail - "fadd z17.h, z8.h, z6.h\n" - "whilelt p0.h, x5, x3\n" + "fadd z17.h, z7.h, z6.h\n" "fadd z16.h, z5.h, z4.h\n" + "whilelt p0.h, x14, x2\n" + "fadd z20.h, z17.h, z16.h\n" "fadd z18.h, z3.h, z2.h\n" - "fadd z23.h, z1.h, z0.h\n" - "fadd z17.h, z17.h, z16.h\n" - "fadd z22.h, z31.h, z30.h\n" - "fadd z16.h, z29.h, z28.h\n" - "fadd z21.h, z18.h, z17.h\n" - "fadd z19.h, z27.h, z23.h\n" - "fadd z20.h, z16.h, z17.h\n" - "fadd z18.h, z26.h, z22.h\n" - "fadd z17.h, z25.h, z23.h\n" - "fadd z16.h, z24.h, z22.h\n" - "fadd z19.h, z21.h, z19.h\n" + "fadd z17.h, z1.h, z31.h\n" + "fadd z19.h, z30.h, z29.h\n" + "fadd z16.h, z28.h, z27.h\n" + "fadd z21.h, z18.h, z20.h\n" + "fadd z20.h, z16.h, z20.h\n" + "fadd z16.h, z26.h, z17.h\n" + "fadd z18.h, z25.h, z19.h\n" + "fadd z17.h, z24.h, z17.h\n" + "fadd z19.h, z23.h, z19.h\n" + "fadd z16.h, z21.h, z16.h\n" + "fmul z16.h, z16.h, z0.h[0]\n" + "st1h { z16.h }, p0, [x5, x14, LSL #1]\n" "fadd z18.h, z21.h, z18.h\n" "fadd z17.h, z17.h, z20.h\n" - "fadd z16.h, z20.h, z16.h\n" - "fmul z19.h, z19.h, z7.h[0]\n" - "st1h { z19.h }, p0, [x8, x5, LSL #1]\n" - "fmul z18.h, z18.h, z7.h[1]\n" - "fmul z17.h, z17.h, z7.h[2]\n" - "st1h { z18.h }, p0, [x17, x5, LSL #1]\n" - "fmul z16.h, z16.h, z7.h[3]\n" - "st1h { z17.h }, p0, [x16, x5, LSL #1]\n" - "st1h { z16.h }, p0, [x15, x5, LSL #1]\n" + "fmul z18.h, z18.h, z0.h[1]\n" + "fmul z17.h, z17.h, z0.h[2]\n" + "fadd z16.h, z19.h, z20.h\n" + "fmul z16.h, z16.h, z0.h[3]\n" + "st1h { z18.h }, p0, [x6, x14, LSL #1]\n" + "st1h { z17.h }, p0, [x7, x14, LSL #1]\n" + "st1h { z16.h }, p0, [x8, x14, LSL #1]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "p0", "p1", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst.hpp index 391d47cf41..49231484e6 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { void sve_fp16_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); -struct sve_fp16_nhwc_avg_generic_depthfirst +struct sve_fp16_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = sve_fp16_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; sve_fp16_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_fp16_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp index 84a6acf80d..2bef44ea5c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,9 @@ */ #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -41,88 +42,88 @@ void sve_fp16_nhwc_avg_generic_depthfirst_impl( const auto rescale_value = static_cast<__fp16>(1.0f / static_cast<float>(window_cells)); __asm__ __volatile__( + "mov x9, #0x0\n" + "cnth x28\n" + "cnth x27, ALL, MUL #2\n" + "cnth x26, ALL, MUL #3\n" "ptrue p0.b\n" - "ld1rh { z8.h }, p0/Z, [%x[rescale_ptr]]\n" - "mov x28, #0x0\n" - "cnth x27\n" - "cnth x26, ALL, MUL #2\n" - "cnth x25, ALL, MUL #3\n" - "whilelt p3.h, x28, %x[n_channels]\n" - "whilelt p2.h, x27, %x[n_channels]\n" - "whilelt p1.h, x26, %x[n_channels]\n" - "whilelt p0.h, x25, %x[n_channels]\n" + "whilelt p3.h, x9, %x[n_channels]\n" + "ld1rh { z7.h }, p0/Z, [%x[rescale_ptr]]\n" + "whilelt p2.h, x28, %x[n_channels]\n" + "whilelt p1.h, x27, %x[n_channels]\n" + "whilelt p0.h, x26, %x[n_channels]\n" "b.none 7f\n" "1:" // 4-vectors of channels - "mov z7.b, #0x0\n" - "mov x19, %x[inptrs]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" "mov z6.b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" + "mov x24, %x[inptrs]\n" "mov z4.b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" - "ld1h { z31.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z30.h }, p2/Z, [x22, x27, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x21, x27, LSL #1]\n" - "ld1h { z28.h }, p2/Z, [x20, x27, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x23, x26, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x22, x26, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x21, x26, LSL #1]\n" - "ld1h { z17.h }, p1/Z, [x20, x26, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x23, x25, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x22, x25, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x21, x25, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x20, x25, LSL #1]\n" + "mov z3.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" + "ld1h { z30.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "fadd z23.h, z3.h, z2.h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd z19.h, z1.h, z0.h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd z22.h, z31.h, z30.h\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" + "fadd z23.h, z2.h, z1.h\n" + "fadd z19.h, z0.h, z31.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z22.h, z30.h, z22.h\n" "fadd z18.h, z29.h, z28.h\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" "fadd z21.h, z27.h, z21.h\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" "fadd z17.h, z26.h, z17.h\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" "fadd z20.h, z25.h, z20.h\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" "fadd z16.h, z24.h, z16.h\n" - "ld1h { z31.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" "fadd z19.h, z23.h, z19.h\n" - "ld1h { z30.h }, p2/Z, [x22, x27, LSL #1]\n" "fadd z18.h, z22.h, z18.h\n" - "ld1h { z29.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z30.h }, p2/Z, [x23, x28, LSL #1]\n" + "ld1h { z22.h }, p2/Z, [x22, x28, LSL #1]\n" "fadd z17.h, z21.h, z17.h\n" - "ld1h { z28.h }, p2/Z, [x20, x27, LSL #1]\n" "fadd z16.h, z20.h, z16.h\n" - "ld1h { z27.h }, p1/Z, [x23, x26, LSL #1]\n" - "fadd z7.h, z7.h, z19.h\n" - "ld1h { z21.h }, p1/Z, [x22, x26, LSL #1]\n" - "fadd z6.h, z6.h, z18.h\n" - "ld1h { z26.h }, p1/Z, [x21, x26, LSL #1]\n" - "fadd z5.h, z5.h, z17.h\n" - "ld1h { z17.h }, p1/Z, [x20, x26, LSL #1]\n" - "fadd z4.h, z4.h, z16.h\n" - "ld1h { z25.h }, p0/Z, [x23, x25, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x22, x25, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x21, x25, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x20, x25, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x21, x28, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x20, x28, LSL #1]\n" + "fadd z6.h, z6.h, z19.h\n" + "fadd z5.h, z5.h, z18.h\n" + "ld1h { z27.h }, p1/Z, [x23, x27, LSL #1]\n" + "ld1h { z21.h }, p1/Z, [x22, x27, LSL #1]\n" + "fadd z4.h, z4.h, z17.h\n" + "fadd z3.h, z3.h, z16.h\n" + "ld1h { z26.h }, p1/Z, [x21, x27, LSL #1]\n" + "ld1h { z17.h }, p1/Z, [x20, x27, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x26, LSL #1]\n" + "ld1h { z20.h }, p0/Z, [x22, x26, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x21, x26, LSL #1]\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "fadd z23.h, z3.h, z2.h\n" - "fadd z19.h, z1.h, z0.h\n" - "fadd z22.h, z31.h, z30.h\n" + "fadd z23.h, z2.h, z1.h\n" + "fadd z19.h, z0.h, z31.h\n" + "fadd z22.h, z30.h, z22.h\n" "fadd z18.h, z29.h, z28.h\n" "fadd z21.h, z27.h, z21.h\n" "fadd z17.h, z26.h, z17.h\n" @@ -132,100 +133,99 @@ void sve_fp16_nhwc_avg_generic_depthfirst_impl( "fadd z18.h, z22.h, z18.h\n" "fadd z17.h, z21.h, z17.h\n" "fadd z16.h, z20.h, z16.h\n" - "fadd z7.h, z7.h, z19.h\n" - "fadd z6.h, z6.h, z18.h\n" - "fadd z5.h, z5.h, z17.h\n" - "fadd z4.h, z4.h, z16.h\n" + "fadd z6.h, z6.h, z19.h\n" + "fadd z5.h, z5.h, z18.h\n" + "fadd z4.h, z4.h, z17.h\n" + "fadd z3.h, z3.h, z16.h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "fadd z7.h, z7.h, z3.h\n" - "ld1h { z31.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x23, x26, LSL #1]\n" - "fadd z6.h, z6.h, z31.h\n" - "ld1h { z25.h }, p0/Z, [x23, x25, LSL #1]\n" - "fadd z5.h, z5.h, z27.h\n" - "fadd z4.h, z4.h, z25.h\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fadd z6.h, z6.h, z16.h\n" + "ld1h { z17.h }, p2/Z, [x20, x28, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x20, x27, LSL #1]\n" + "fadd z5.h, z5.h, z17.h\n" + "fadd z4.h, z4.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x20, x26, LSL #1]\n" + "fadd z3.h, z3.h, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "fmul z7.h, z7.h, z8.h\n" - "st1h { z7.h }, p3, [%x[outptr], x28, LSL #1]\n" - "fmul z6.h, z6.h, z8.h\n" + "fmul z6.h, z6.h, z7.h\n" + "fmul z5.h, z5.h, z7.h\n" + "st1h { z6.h }, p3, [%x[outptr], x9, LSL #1]\n" + "fmul z4.h, z4.h, z7.h\n" + "fmul z3.h, z3.h, z7.h\n" + "st1h { z5.h }, p2, [%x[outptr], x28, LSL #1]\n" + "st1h { z4.h }, p1, [%x[outptr], x27, LSL #1]\n" + "inch x9, ALL, MUL #4\n" "inch x28, ALL, MUL #4\n" - "fmul z5.h, z5.h, z8.h\n" - "st1h { z6.h }, p2, [%x[outptr], x27, LSL #1]\n" - "fmul z4.h, z4.h, z8.h\n" - "inch x27, ALL, MUL #4\n" - "st1h { z5.h }, p1, [%x[outptr], x26, LSL #1]\n" + "st1h { z3.h }, p0, [%x[outptr], x26, LSL #1]\n" "inch x26, ALL, MUL #4\n" - "st1h { z4.h }, p0, [%x[outptr], x25, LSL #1]\n" - "inch x25, ALL, MUL #4\n" - "whilelt p0.h, x25, %x[n_channels]\n" + "whilelt p0.h, x26, %x[n_channels]\n" + "inch x27, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.h, x28, %x[n_channels]\n" + "whilelt p3.h, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z7.b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z6.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd z23.h, z3.h, z2.h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd z19.h, z1.h, z0.h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd z19.h, z23.h, z19.h\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "fadd z7.h, z7.h, z19.h\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" + "fadd z17.h, z2.h, z1.h\n" + "fadd z16.h, z0.h, z31.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z16.h, z17.h, z16.h\n" + "subs x25, x25, #0x1\n" + "fadd z6.h, z6.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p3/Z, [x23, x9, LSL #1]\n" + "ld1h { z1.h }, p3/Z, [x22, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x21, x9, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x20, x9, LSL #1]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd z23.h, z3.h, z2.h\n" - "fadd z19.h, z1.h, z0.h\n" - "fadd z19.h, z23.h, z19.h\n" - "fadd z7.h, z7.h, z19.h\n" + "fadd z17.h, z2.h, z1.h\n" + "fadd z16.h, z0.h, z31.h\n" + "fadd z16.h, z17.h, z16.h\n" + "fadd z6.h, z6.h, z16.h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "fadd z7.h, z7.h, z3.h\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p3/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fadd z6.h, z6.h, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "fmul z7.h, z7.h, z8.h\n" - "st1h { z7.h }, p3, [%x[outptr], x28, LSL #1]\n" - "inch x28\n" - "whilelt p3.h, x28, %x[n_channels]\n" + "fmul z6.h, z6.h, z7.h\n" + "st1h { z6.h }, p3, [%x[outptr], x9, LSL #1]\n" + "inch x9\n" + "whilelt p3.h, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value) - : "cc", "memory", "p0", "p1", "p2", "p3", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 5fb297eb49..3691b6cb28 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst +struct sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; + using Parent = DepthfirstStrategy<__fp16, __fp16>; - typedef void (*kern_type)(unsigned int, const __fp16 *const *const, __fp16 *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index f6e23215b8..31bbfd085e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -63,84 +63,84 @@ void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x14, [%x[args], %[offsetof_n_channels]]\n" + "ldr x15, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x14, #0x0\n" + "whilelt p0.h, x14, x15\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x13, x12, [x21, #0x0]\n" "ptrue p2.b\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "mov x12, #0x0\n" - "ldp x11, x10, [x20, #0x0]\n" - "whilelt p1.h, x13, x14\n" - "ldp x9, x28, [x20, #0x10]\n" - "ldp x27, x26, [x19, #0x0]\n" - "ldp x25, x24, [x19, #0x10]\n" - "ldp x23, x22, [x19, #0x20]\n" - "ldp x21, x20, [x19, #0x30]\n" - "ldr x19, [x19, #0x40]\n" - "ld1h { z31.h }, p1/Z, [x26, x13, LSL #1]\n" - "ld1h { z30.h }, p1/Z, [x23, x13, LSL #1]\n" - "ld1h { z29.h }, p1/Z, [x20, x13, LSL #1]\n" - "ld1h { z28.h }, p1/Z, [x24, x13, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x27, x13, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x22, x13, LSL #1]\n" - "ld1h { z25.h }, p1/Z, [x25, x13, LSL #1]\n" - "ld1h { z24.h }, p1/Z, [x21, x13, LSL #1]\n" - "ld1h { z23.h }, p1/Z, [x19, x13, LSL #1]\n" - "incw x13\n" - "whilelt p1.h, x13, x14\n" + "mov x11, #0x0\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ldr x20, [x20, #0x40]\n" + "ld1h { z31.h }, p0/Z, [x27, x14, LSL #1]\n" + "ld1h { z30.h }, p0/Z, [x24, x14, LSL #1]\n" + "ld1h { z29.h }, p0/Z, [x21, x14, LSL #1]\n" + "ld1h { z28.h }, p0/Z, [x25, x14, LSL #1]\n" + "ld1h { z27.h }, p0/Z, [x28, x14, LSL #1]\n" + "ld1h { z26.h }, p0/Z, [x26, x14, LSL #1]\n" + "ld1h { z25.h }, p0/Z, [x23, x14, LSL #1]\n" + "ld1h { z24.h }, p0/Z, [x22, x14, LSL #1]\n" + "ld1h { z23.h }, p0/Z, [x20, x14, LSL #1]\n" + "incw x14\n" + "whilelt p1.h, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop "movprfx z22, z31\n fmax z22.h, p2/M, z22.h, z30.h\n" - "ld1h { z31.h }, p1/Z, [x26, x13, LSL #1]\n" - "whilelt p0.h, x12, x14\n" "movprfx z21, z30\n fmax z21.h, p2/M, z21.h, z29.h\n" - "ld1h { z30.h }, p1/Z, [x23, x13, LSL #1]\n" - "movprfx z18, z28\n fmax z18.h, p2/M, z18.h, z27.h\n" - "ld1h { z29.h }, p1/Z, [x20, x13, LSL #1]\n" - "movprfx z17, z26\n fmax z17.h, p2/M, z17.h, z25.h\n" - "ld1h { z27.h }, p1/Z, [x27, x13, LSL #1]\n" - "movprfx z16, z24\n fmax z16.h, p2/M, z16.h, z28.h\n" - "ld1h { z28.h }, p1/Z, [x24, x13, LSL #1]\n" - "movprfx z20, z26\n fmax z20.h, p2/M, z20.h, z23.h\n" - "ld1h { z26.h }, p1/Z, [x22, x13, LSL #1]\n" - "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z18.h\n" - "ld1h { z25.h }, p1/Z, [x25, x13, LSL #1]\n" - "movprfx z18, z22\n fmax z18.h, p2/M, z18.h, z17.h\n" - "ld1h { z24.h }, p1/Z, [x21, x13, LSL #1]\n" - "movprfx z17, z21\n fmax z17.h, p2/M, z17.h, z16.h\n" - "ld1h { z23.h }, p1/Z, [x19, x13, LSL #1]\n" - "incw x13\n" - "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z20.h\n" - "st1h { z19.h }, p0, [x11, x12, LSL #1]\n" - "whilelt p1.h, x13, x14\n" - "st1h { z18.h }, p0, [x10, x12, LSL #1]\n" - "st1h { z17.h }, p0, [x9, x12, LSL #1]\n" - "st1h { z16.h }, p0, [x28, x12, LSL #1]\n" - "incw x12\n" + "ld1h { z31.h }, p1/Z, [x27, x14, LSL #1]\n" + "ld1h { z30.h }, p1/Z, [x24, x14, LSL #1]\n" + "movprfx z20, z28\n fmax z20.h, p2/M, z20.h, z27.h\n" + "movprfx z19, z26\n fmax z19.h, p2/M, z19.h, z25.h\n" + "ld1h { z29.h }, p1/Z, [x21, x14, LSL #1]\n" + "ld1h { z27.h }, p1/Z, [x28, x14, LSL #1]\n" + "movprfx z17, z28\n fmax z17.h, p2/M, z17.h, z24.h\n" + "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z23.h\n" + "ld1h { z28.h }, p1/Z, [x25, x14, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x26, x14, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x23, x14, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x22, x14, LSL #1]\n" + "whilelt p0.h, x11, x15\n" + "movprfx z16, z22\n fmax z16.h, p2/M, z16.h, z20.h\n" + "ld1h { z23.h }, p1/Z, [x20, x14, LSL #1]\n" + "incw x14\n" + "whilelt p1.h, x14, x15\n" + "st1h { z16.h }, p0, [x13, x11, LSL #1]\n" + "movprfx z16, z19\n fmax z16.h, p2/M, z16.h, z22.h\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" + "st1h { z16.h }, p0, [x12, x11, LSL #1]\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z18.h\n" + "st1h { z17.h }, p0, [x10, x11, LSL #1]\n" + "st1h { z16.h }, p0, [x9, x11, LSL #1]\n" + "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail "movprfx z22, z31\n fmax z22.h, p2/M, z22.h, z30.h\n" - "whilelt p0.h, x12, x14\n" "movprfx z21, z30\n fmax z21.h, p2/M, z21.h, z29.h\n" - "movprfx z18, z28\n fmax z18.h, p2/M, z18.h, z27.h\n" - "movprfx z17, z26\n fmax z17.h, p2/M, z17.h, z25.h\n" - "movprfx z16, z24\n fmax z16.h, p2/M, z16.h, z28.h\n" - "movprfx z20, z26\n fmax z20.h, p2/M, z20.h, z23.h\n" - "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z18.h\n" - "st1h { z19.h }, p0, [x11, x12, LSL #1]\n" - "movprfx z18, z22\n fmax z18.h, p2/M, z18.h, z17.h\n" - "movprfx z17, z21\n fmax z17.h, p2/M, z17.h, z16.h\n" - "st1h { z18.h }, p0, [x10, x12, LSL #1]\n" - "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z20.h\n" - "st1h { z17.h }, p0, [x9, x12, LSL #1]\n" - "st1h { z16.h }, p0, [x28, x12, LSL #1]\n" + "movprfx z20, z28\n fmax z20.h, p2/M, z20.h, z27.h\n" + "movprfx z19, z26\n fmax z19.h, p2/M, z19.h, z25.h\n" + "movprfx z17, z28\n fmax z17.h, p2/M, z17.h, z24.h\n" + "movprfx z18, z25\n fmax z18.h, p2/M, z18.h, z23.h\n" + "whilelt p0.h, x11, x15\n" + "movprfx z16, z22\n fmax z16.h, p2/M, z16.h, z20.h\n" + "st1h { z16.h }, p0, [x13, x11, LSL #1]\n" + "movprfx z16, z19\n fmax z16.h, p2/M, z16.h, z22.h\n" + "fmax z17.h, p2/M, z17.h, z21.h\n" + "st1h { z16.h }, p0, [x12, x11, LSL #1]\n" + "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z18.h\n" + "st1h { z17.h }, p0, [x10, x11, LSL #1]\n" + "st1h { z16.h }, p0, [x9, x11, LSL #1]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst.hpp index 1c17c27619..0ef0a793cc 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { void sve_fp16_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); -struct sve_fp16_nhwc_max_generic_depthfirst +struct sve_fp16_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<__fp16, __fp16> { - typedef __fp16 operand_type; - typedef __fp16 return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const __fp16 *const *const inptrs, __fp16 *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = sve_fp16_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<__fp16, __fp16>; sve_fp16_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_fp16_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp index 58ab915605..1a01412836 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,9 @@ */ #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#if defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) namespace arm_conv { namespace pooling { @@ -39,185 +40,184 @@ void sve_fp16_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "ptrue p4.b\n" - "mov x28, #0x0\n" - "cnth x27\n" - "cnth x26, ALL, MUL #2\n" - "cnth x25, ALL, MUL #3\n" + "mov x9, #0x0\n" + "cnth x28\n" + "cnth x27, ALL, MUL #2\n" + "cnth x26, ALL, MUL #3\n" + "whilelt p4.h, x9, %x[n_channels]\n" "whilelt p3.h, x28, %x[n_channels]\n" "whilelt p2.h, x27, %x[n_channels]\n" "whilelt p1.h, x26, %x[n_channels]\n" - "whilelt p0.h, x25, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.h, #0xfc00\n" "mov z7.h, #0xfc00\n" - "mov x19, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.h, #0xfc00\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "mov z5.h, #0xfc00\n" - "mov z4.h, #0xfc00\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" - "ld1h { z31.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z30.h }, p2/Z, [x22, x27, LSL #1]\n" - "ld1h { z22.h }, p2/Z, [x21, x27, LSL #1]\n" - "ld1h { z29.h }, p2/Z, [x20, x27, LSL #1]\n" - "ld1h { z28.h }, p1/Z, [x23, x26, LSL #1]\n" - "ld1h { z27.h }, p1/Z, [x22, x26, LSL #1]\n" - "ld1h { z21.h }, p1/Z, [x21, x26, LSL #1]\n" - "ld1h { z26.h }, p1/Z, [x20, x26, LSL #1]\n" - "ld1h { z16.h }, p0/Z, [x23, x25, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x22, x25, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x21, x25, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x20, x25, LSL #1]\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" + "ld1h { z0.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x22, x28, LSL #1]\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x22, x27, LSL #1]\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x20, x27, LSL #1]\n" + "ld1h { z26.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "movprfx z19, z3\n fmax z19.h, p4/M, z19.h, z2.h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n fmax z23.h, p4/M, z23.h, z0.h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "movprfx z18, z31\n fmax z18.h, p4/M, z18.h, z30.h\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "fmax z22.h, p4/M, z22.h, z29.h\n" - "movprfx z17, z28\n fmax z17.h, p4/M, z17.h, z27.h\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "fmax z21.h, p4/M, z21.h, z26.h\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "fmax z16.h, p4/M, z16.h, z25.h\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" - "fmax z20.h, p4/M, z20.h, z24.h\n" - "ld1h { z31.h }, p2/Z, [x23, x27, LSL #1]\n" - "fmax z19.h, p4/M, z19.h, z23.h\n" - "ld1h { z30.h }, p2/Z, [x22, x27, LSL #1]\n" - "fmax z18.h, p4/M, z18.h, z22.h\n" - "ld1h { z22.h }, p2/Z, [x21, x27, LSL #1]\n" - "fmax z17.h, p4/M, z17.h, z21.h\n" - "ld1h { z29.h }, p2/Z, [x20, x27, LSL #1]\n" - "fmax z16.h, p4/M, z16.h, z20.h\n" - "ld1h { z28.h }, p1/Z, [x23, x26, LSL #1]\n" - "fmax z7.h, p4/M, z7.h, z19.h\n" - "ld1h { z27.h }, p1/Z, [x22, x26, LSL #1]\n" - "fmax z6.h, p4/M, z6.h, z18.h\n" - "ld1h { z21.h }, p1/Z, [x21, x26, LSL #1]\n" - "fmax z5.h, p4/M, z5.h, z17.h\n" - "ld1h { z26.h }, p1/Z, [x20, x26, LSL #1]\n" - "fmax z4.h, p4/M, z4.h, z16.h\n" - "ld1h { z16.h }, p0/Z, [x23, x25, LSL #1]\n" - "ld1h { z25.h }, p0/Z, [x22, x25, LSL #1]\n" - "ld1h { z20.h }, p0/Z, [x21, x25, LSL #1]\n" - "ld1h { z24.h }, p0/Z, [x20, x25, LSL #1]\n" + "movprfx z19, z4\n fmax z19.h, p0/M, z19.h, z3.h\n" + "movprfx z23, z2\n fmax z23.h, p0/M, z23.h, z1.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "movprfx z18, z0\n fmax z18.h, p0/M, z18.h, z31.h\n" + "fmax z22.h, p0/M, z22.h, z30.h\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "movprfx z17, z29\n fmax z17.h, p0/M, z17.h, z28.h\n" + "fmax z21.h, p0/M, z21.h, z27.h\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" + "movprfx z16, z26\n fmax z16.h, p0/M, z16.h, z25.h\n" + "fmax z20.h, p0/M, z20.h, z24.h\n" + "ld1h { z0.h }, p3/Z, [x23, x28, LSL #1]\n" + "ld1h { z31.h }, p3/Z, [x22, x28, LSL #1]\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z18.h, p0/M, z18.h, z22.h\n" + "ld1h { z22.h }, p3/Z, [x21, x28, LSL #1]\n" + "ld1h { z30.h }, p3/Z, [x20, x28, LSL #1]\n" + "fmax z17.h, p0/M, z17.h, z21.h\n" + "fmax z16.h, p0/M, z16.h, z20.h\n" + "ld1h { z29.h }, p2/Z, [x23, x27, LSL #1]\n" + "ld1h { z28.h }, p2/Z, [x22, x27, LSL #1]\n" + "subs x25, x25, #0x1\n" + "fmax z8.h, p0/M, z8.h, z19.h\n" + "ld1h { z21.h }, p2/Z, [x21, x27, LSL #1]\n" + "ld1h { z27.h }, p2/Z, [x20, x27, LSL #1]\n" + "fmax z7.h, p0/M, z7.h, z18.h\n" + "fmax z6.h, p0/M, z6.h, z17.h\n" + "ld1h { z26.h }, p1/Z, [x23, x26, LSL #1]\n" + "ld1h { z25.h }, p1/Z, [x22, x26, LSL #1]\n" + "fmax z5.h, p0/M, z5.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z20.h }, p1/Z, [x21, x26, LSL #1]\n" + "ld1h { z24.h }, p1/Z, [x20, x26, LSL #1]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "movprfx z19, z3\n fmax z19.h, p4/M, z19.h, z2.h\n" - "movprfx z23, z1\n fmax z23.h, p4/M, z23.h, z0.h\n" - "movprfx z18, z31\n fmax z18.h, p4/M, z18.h, z30.h\n" - "fmax z22.h, p4/M, z22.h, z29.h\n" - "movprfx z17, z28\n fmax z17.h, p4/M, z17.h, z27.h\n" - "fmax z21.h, p4/M, z21.h, z26.h\n" - "fmax z16.h, p4/M, z16.h, z25.h\n" - "fmax z20.h, p4/M, z20.h, z24.h\n" - "fmax z19.h, p4/M, z19.h, z23.h\n" - "fmax z18.h, p4/M, z18.h, z22.h\n" - "fmax z17.h, p4/M, z17.h, z21.h\n" - "fmax z16.h, p4/M, z16.h, z20.h\n" - "fmax z7.h, p4/M, z7.h, z19.h\n" - "fmax z6.h, p4/M, z6.h, z18.h\n" - "fmax z5.h, p4/M, z5.h, z17.h\n" - "fmax z4.h, p4/M, z4.h, z16.h\n" + "movprfx z19, z4\n fmax z19.h, p0/M, z19.h, z3.h\n" + "movprfx z23, z2\n fmax z23.h, p0/M, z23.h, z1.h\n" + "movprfx z18, z0\n fmax z18.h, p0/M, z18.h, z31.h\n" + "fmax z22.h, p0/M, z22.h, z30.h\n" + "movprfx z17, z29\n fmax z17.h, p0/M, z17.h, z28.h\n" + "fmax z21.h, p0/M, z21.h, z27.h\n" + "movprfx z16, z26\n fmax z16.h, p0/M, z16.h, z25.h\n" + "fmax z20.h, p0/M, z20.h, z24.h\n" + "fmax z19.h, p0/M, z19.h, z23.h\n" + "fmax z18.h, p0/M, z18.h, z22.h\n" + "fmax z17.h, p0/M, z17.h, z21.h\n" + "fmax z16.h, p0/M, z16.h, z20.h\n" + "fmax z8.h, p0/M, z8.h, z19.h\n" + "fmax z7.h, p0/M, z7.h, z18.h\n" + "fmax z6.h, p0/M, z6.h, z17.h\n" + "fmax z5.h, p0/M, z5.h, z16.h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "fmax z7.h, p4/M, z7.h, z3.h\n" - "ld1h { z31.h }, p2/Z, [x23, x27, LSL #1]\n" - "ld1h { z28.h }, p1/Z, [x23, x26, LSL #1]\n" - "fmax z6.h, p4/M, z6.h, z31.h\n" - "ld1h { z16.h }, p0/Z, [x23, x25, LSL #1]\n" - "fmax z5.h, p4/M, z5.h, z28.h\n" - "fmax z4.h, p4/M, z4.h, z16.h\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" + "ld1h { z17.h }, p3/Z, [x20, x28, LSL #1]\n" + "ld1h { z16.h }, p2/Z, [x20, x27, LSL #1]\n" + "fmax z7.h, p0/M, z7.h, z17.h\n" + "fmax z6.h, p0/M, z6.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x20, x26, LSL #1]\n" + "fmax z5.h, p0/M, z5.h, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End + "st1h { z8.h }, p4, [%x[outptr], x9, LSL #1]\n" + "inch x9, ALL, MUL #4\n" "st1h { z7.h }, p3, [%x[outptr], x28, LSL #1]\n" "inch x28, ALL, MUL #4\n" "st1h { z6.h }, p2, [%x[outptr], x27, LSL #1]\n" "inch x27, ALL, MUL #4\n" "st1h { z5.h }, p1, [%x[outptr], x26, LSL #1]\n" "inch x26, ALL, MUL #4\n" - "st1h { z4.h }, p0, [%x[outptr], x25, LSL #1]\n" - "inch x25, ALL, MUL #4\n" - "whilelt p0.h, x25, %x[n_channels]\n" + "whilelt p1.h, x26, %x[n_channels]\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.h, x28, %x[n_channels]\n" + "whilelt p4.h, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z7.h, #0xfc00\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.h, #0xfc00\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z3\n fmax z19.h, p4/M, z19.h, z2.h\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n fmax z23.h, p4/M, z23.h, z0.h\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fmax z19.h, p4/M, z19.h, z23.h\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "ld1h { z2.h }, p3/Z, [x22, x28, LSL #1]\n" - "fmax z7.h, p4/M, z7.h, z19.h\n" - "ld1h { z1.h }, p3/Z, [x21, x28, LSL #1]\n" - "ld1h { z0.h }, p3/Z, [x20, x28, LSL #1]\n" + "movprfx z16, z4\n fmax z16.h, p0/M, z16.h, z3.h\n" + "movprfx z17, z2\n fmax z17.h, p0/M, z17.h, z1.h\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "subs x25, x25, #0x1\n" + "ld1h { z4.h }, p4/Z, [x23, x9, LSL #1]\n" + "ld1h { z3.h }, p4/Z, [x22, x9, LSL #1]\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" + "add x24, x24, #0x20\n" + "ld1h { z2.h }, p4/Z, [x21, x9, LSL #1]\n" + "ld1h { z1.h }, p4/Z, [x20, x9, LSL #1]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z3\n fmax z19.h, p4/M, z19.h, z2.h\n" - "movprfx z23, z1\n fmax z23.h, p4/M, z23.h, z0.h\n" - "fmax z19.h, p4/M, z19.h, z23.h\n" - "fmax z7.h, p4/M, z7.h, z19.h\n" + "movprfx z16, z4\n fmax z16.h, p0/M, z16.h, z3.h\n" + "movprfx z17, z2\n fmax z17.h, p0/M, z17.h, z1.h\n" + "fmax z16.h, p0/M, z16.h, z17.h\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1h { z3.h }, p3/Z, [x23, x28, LSL #1]\n" - "fmax z7.h, p4/M, z7.h, z3.h\n" + "ldr x20, [x24], #0x8\n" + "ld1h { z16.h }, p4/Z, [x20, x9, LSL #1]\n" + "subs x21, x21, #0x1\n" + "fmax z8.h, p0/M, z8.h, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "st1h { z7.h }, p3, [%x[outptr], x28, LSL #1]\n" - "inch x28\n" - "whilelt p3.h, x28, %x[n_channels]\n" + "st1h { z8.h }, p4, [%x[outptr], x9, LSL #1]\n" + "inch x9\n" + "whilelt p4.h, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(__ARM_FP16_ARGS) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) && defined(__ARM_FP16_ARGS) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp index 9cbdb8a58d..d5578d617f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst +struct sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; + using Parent = DepthfirstStrategy<float, float>; - typedef void (*kern_type)(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::AVERAGE; + const static auto pool_rows = 3u, pool_cols = 3u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } + sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 3; } - constexpr static unsigned int pool_cols(void) { return 3; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; - - sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp index 50f5da4c3d..c5ea5adea0 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -82,126 +82,126 @@ void sve_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x3, [%x[args], %[offsetof_n_channels]]\n" - "mov x4, #0x0\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x5, #0x0\n" - "ldr x6, [%x[args], %[offsetof_inptrs]]\n" - "mov x19, #0x4\n" - "add x7, %x[args], %[offsetof_rescale]\n" - "ldp x8, x17, [x20, #0x0]\n" - "ldp x16, x15, [x20, #0x10]\n" - "whilelt p0.s, XZR, x19\n" - "ldp x14, x13, [x6, #0x0]\n" - "whilelt p1.s, x4, x3\n" - "ldp x12, x11, [x6, #0x10]\n" - "ldp x10, x9, [x6, #0x20]\n" - "ldp x28, x27, [x6, #0x30]\n" - "ldp x26, x25, [x6, #0x40]\n" - "ldp x24, x23, [x6, #0x50]\n" - "ldp x22, x21, [x6, #0x60]\n" - "ldp x20, x19, [x6, #0x70]\n" - "ld1rqw { z7.s }, p0/Z, [x7]\n" - "ld1w { z8.s }, p1/Z, [x9, x4, LSL #2]\n" - "ld1w { z6.s }, p1/Z, [x28, x4, LSL #2]\n" - "ld1w { z5.s }, p1/Z, [x25, x4, LSL #2]\n" - "ld1w { z4.s }, p1/Z, [x24, x4, LSL #2]\n" - "ld1w { z3.s }, p1/Z, [x13, x4, LSL #2]\n" - "ld1w { z2.s }, p1/Z, [x12, x4, LSL #2]\n" - "ld1w { z1.s }, p1/Z, [x10, x4, LSL #2]\n" - "ld1w { z0.s }, p1/Z, [x26, x4, LSL #2]\n" - "ld1w { z31.s }, p1/Z, [x27, x4, LSL #2]\n" - "ld1w { z30.s }, p1/Z, [x23, x4, LSL #2]\n" - "ld1w { z29.s }, p1/Z, [x21, x4, LSL #2]\n" - "ld1w { z28.s }, p1/Z, [x20, x4, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x14, x4, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x11, x4, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x22, x4, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x19, x4, LSL #2]\n" - "incw x4\n" - "whilelt p1.s, x4, x3\n" + "ldr x2, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x3, #0x0\n" + "mov x20, #0x4\n" + "ldr x4, [%x[args], %[offsetof_inptrs]]\n" + "ldp x5, x6, [x21, #0x0]\n" + "whilelt p2.s, XZR, x20\n" + "whilelt p0.s, x3, x2\n" + "ldp x7, x8, [x21, #0x10]\n" + "ldp x17, x16, [x4, #0x0]\n" + "add x15, %x[args], %[offsetof_rescale]\n" + "mov x14, #0x0\n" + "ldp x13, x12, [x4, #0x10]\n" + "ldp x11, x10, [x4, #0x20]\n" + "ldp x9, x28, [x4, #0x30]\n" + "ldp x27, x26, [x4, #0x40]\n" + "ldp x25, x24, [x4, #0x50]\n" + "ldp x23, x22, [x4, #0x60]\n" + "ldp x21, x20, [x4, #0x70]\n" + "ld1w { z7.s }, p0/Z, [x10, x3, LSL #2]\n" + "ld1w { z6.s }, p0/Z, [x9, x3, LSL #2]\n" + "ld1w { z5.s }, p0/Z, [x26, x3, LSL #2]\n" + "ld1w { z4.s }, p0/Z, [x25, x3, LSL #2]\n" + "ld1w { z3.s }, p0/Z, [x16, x3, LSL #2]\n" + "ld1w { z2.s }, p0/Z, [x13, x3, LSL #2]\n" + "ld1w { z1.s }, p0/Z, [x11, x3, LSL #2]\n" + "ld1w { z31.s }, p0/Z, [x27, x3, LSL #2]\n" + "ld1w { z30.s }, p0/Z, [x28, x3, LSL #2]\n" + "ld1w { z29.s }, p0/Z, [x24, x3, LSL #2]\n" + "ld1w { z28.s }, p0/Z, [x22, x3, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x21, x3, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x17, x3, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x12, x3, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x23, x3, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x3, LSL #2]\n" + "incw x3\n" + "whilelt p1.s, x3, x2\n" + "ld1rqw { z0.s }, p2/Z, [x15]\n" "b.none 2f\n" "1:" // Vector: Loop - "fadd z17.s, z8.s, z6.s\n" - "ld1w { z8.s }, p1/Z, [x9, x4, LSL #2]\n" - "whilelt p0.s, x5, x3\n" + "fadd z17.s, z7.s, z6.s\n" "fadd z16.s, z5.s, z4.s\n" - "ld1w { z6.s }, p1/Z, [x28, x4, LSL #2]\n" + "ld1w { z7.s }, p1/Z, [x10, x3, LSL #2]\n" + "ld1w { z6.s }, p1/Z, [x9, x3, LSL #2]\n" + "fadd z19.s, z17.s, z16.s\n" "fadd z18.s, z3.s, z2.s\n" - "ld1w { z5.s }, p1/Z, [x25, x4, LSL #2]\n" - "fadd z23.s, z1.s, z0.s\n" - "ld1w { z4.s }, p1/Z, [x24, x4, LSL #2]\n" - "fadd z22.s, z31.s, z30.s\n" - "ld1w { z3.s }, p1/Z, [x13, x4, LSL #2]\n" - "fadd z17.s, z17.s, z16.s\n" - "ld1w { z2.s }, p1/Z, [x12, x4, LSL #2]\n" - "fadd z16.s, z29.s, z28.s\n" - "ld1w { z1.s }, p1/Z, [x10, x4, LSL #2]\n" - "fadd z19.s, z27.s, z23.s\n" - "ld1w { z0.s }, p1/Z, [x26, x4, LSL #2]\n" - "fadd z21.s, z18.s, z17.s\n" - "ld1w { z31.s }, p1/Z, [x27, x4, LSL #2]\n" - "fadd z20.s, z16.s, z17.s\n" - "ld1w { z30.s }, p1/Z, [x23, x4, LSL #2]\n" - "fadd z18.s, z26.s, z22.s\n" - "ld1w { z29.s }, p1/Z, [x21, x4, LSL #2]\n" - "fadd z17.s, z25.s, z23.s\n" - "ld1w { z28.s }, p1/Z, [x20, x4, LSL #2]\n" - "fadd z16.s, z24.s, z22.s\n" - "ld1w { z27.s }, p1/Z, [x14, x4, LSL #2]\n" + "ld1w { z5.s }, p1/Z, [x26, x3, LSL #2]\n" + "ld1w { z4.s }, p1/Z, [x25, x3, LSL #2]\n" + "fadd z17.s, z1.s, z31.s\n" + "fadd z22.s, z30.s, z29.s\n" + "ld1w { z3.s }, p1/Z, [x16, x3, LSL #2]\n" + "ld1w { z2.s }, p1/Z, [x13, x3, LSL #2]\n" + "fadd z16.s, z28.s, z27.s\n" + "fadd z21.s, z18.s, z19.s\n" + "ld1w { z1.s }, p1/Z, [x11, x3, LSL #2]\n" + "ld1w { z31.s }, p1/Z, [x27, x3, LSL #2]\n" + "fadd z20.s, z16.s, z19.s\n" + "fadd z19.s, z26.s, z17.s\n" + "ld1w { z30.s }, p1/Z, [x28, x3, LSL #2]\n" + "ld1w { z29.s }, p1/Z, [x24, x3, LSL #2]\n" + "fadd z18.s, z25.s, z22.s\n" + "fadd z17.s, z24.s, z17.s\n" + "ld1w { z28.s }, p1/Z, [x22, x3, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x21, x3, LSL #2]\n" + "fadd z16.s, z23.s, z22.s\n" + "ld1w { z26.s }, p1/Z, [x17, x3, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x12, x3, LSL #2]\n" "fadd z19.s, z21.s, z19.s\n" - "ld1w { z26.s }, p1/Z, [x11, x4, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x23, x3, LSL #2]\n" + "ld1w { z23.s }, p1/Z, [x20, x3, LSL #2]\n" + "incw x3\n" "fadd z18.s, z21.s, z18.s\n" - "ld1w { z25.s }, p1/Z, [x22, x4, LSL #2]\n" "fadd z17.s, z17.s, z20.s\n" - "ld1w { z24.s }, p1/Z, [x19, x4, LSL #2]\n" - "incw x4\n" - "fadd z16.s, z20.s, z16.s\n" - "whilelt p1.s, x4, x3\n" - "fmul z19.s, z19.s, z7.s[0]\n" - "st1w { z19.s }, p0, [x8, x5, LSL #2]\n" - "fmul z18.s, z18.s, z7.s[1]\n" - "fmul z17.s, z17.s, z7.s[2]\n" - "st1w { z18.s }, p0, [x17, x5, LSL #2]\n" - "fmul z16.s, z16.s, z7.s[3]\n" - "st1w { z17.s }, p0, [x16, x5, LSL #2]\n" - "st1w { z16.s }, p0, [x15, x5, LSL #2]\n" - "incw x5\n" + "fadd z16.s, z16.s, z20.s\n" + "whilelt p0.s, x14, x2\n" + "whilelt p1.s, x3, x2\n" + "fmul z19.s, z19.s, z0.s[0]\n" + "fmul z18.s, z18.s, z0.s[1]\n" + "st1w { z19.s }, p0, [x5, x14, LSL #2]\n" + "fmul z17.s, z17.s, z0.s[2]\n" + "fmul z16.s, z16.s, z0.s[3]\n" + "st1w { z18.s }, p0, [x6, x14, LSL #2]\n" + "st1w { z17.s }, p0, [x7, x14, LSL #2]\n" + "st1w { z16.s }, p0, [x8, x14, LSL #2]\n" + "incw x14\n" "b.any 1b\n" "2:" // Vector: Tail - "fadd z17.s, z8.s, z6.s\n" - "whilelt p0.s, x5, x3\n" + "fadd z17.s, z7.s, z6.s\n" "fadd z16.s, z5.s, z4.s\n" + "whilelt p0.s, x14, x2\n" + "fadd z20.s, z17.s, z16.s\n" "fadd z18.s, z3.s, z2.s\n" - "fadd z23.s, z1.s, z0.s\n" - "fadd z17.s, z17.s, z16.s\n" - "fadd z22.s, z31.s, z30.s\n" - "fadd z16.s, z29.s, z28.s\n" - "fadd z21.s, z18.s, z17.s\n" - "fadd z19.s, z27.s, z23.s\n" - "fadd z20.s, z16.s, z17.s\n" - "fadd z18.s, z26.s, z22.s\n" - "fadd z17.s, z25.s, z23.s\n" - "fadd z16.s, z24.s, z22.s\n" - "fadd z19.s, z21.s, z19.s\n" + "fadd z17.s, z1.s, z31.s\n" + "fadd z19.s, z30.s, z29.s\n" + "fadd z16.s, z28.s, z27.s\n" + "fadd z21.s, z18.s, z20.s\n" + "fadd z20.s, z16.s, z20.s\n" + "fadd z16.s, z26.s, z17.s\n" + "fadd z18.s, z25.s, z19.s\n" + "fadd z17.s, z24.s, z17.s\n" + "fadd z19.s, z23.s, z19.s\n" + "fadd z16.s, z21.s, z16.s\n" + "fmul z16.s, z16.s, z0.s[0]\n" + "st1w { z16.s }, p0, [x5, x14, LSL #2]\n" "fadd z18.s, z21.s, z18.s\n" "fadd z17.s, z17.s, z20.s\n" - "fadd z16.s, z20.s, z16.s\n" - "fmul z19.s, z19.s, z7.s[0]\n" - "st1w { z19.s }, p0, [x8, x5, LSL #2]\n" - "fmul z18.s, z18.s, z7.s[1]\n" - "fmul z17.s, z17.s, z7.s[2]\n" - "st1w { z18.s }, p0, [x17, x5, LSL #2]\n" - "fmul z16.s, z16.s, z7.s[3]\n" - "st1w { z17.s }, p0, [x16, x5, LSL #2]\n" - "st1w { z16.s }, p0, [x15, x5, LSL #2]\n" + "fmul z18.s, z18.s, z0.s[1]\n" + "fmul z17.s, z17.s, z0.s[2]\n" + "fadd z16.s, z19.s, z20.s\n" + "fmul z16.s, z16.s, z0.s[3]\n" + "st1w { z18.s }, p0, [x6, x14, LSL #2]\n" + "st1w { z17.s }, p0, [x7, x14, LSL #2]\n" + "st1w { z16.s }, p0, [x8, x14, LSL #2]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals)) - : "cc", "memory", "p0", "p1", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst.hpp index 0daa046a02..a9e6b034e7 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_fp32_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); -struct sve_fp32_nhwc_avg_generic_depthfirst +struct sve_fp32_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = sve_fp32_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<float, float>; sve_fp32_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_fp32_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp index c2f5745adc..7c94894892 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,9 @@ */ #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -41,88 +42,88 @@ void sve_fp32_nhwc_avg_generic_depthfirst_impl( const auto rescale_value = static_cast<float>(1.0f / static_cast<float>(window_cells)); __asm__ __volatile__( + "mov x9, #0x0\n" + "cntw x28\n" + "cntw x27, ALL, MUL #2\n" + "cntw x26, ALL, MUL #3\n" "ptrue p0.b\n" - "ld1rw { z8.s }, p0/Z, [%x[rescale_ptr]]\n" - "mov x28, #0x0\n" - "cntw x27\n" - "cntw x26, ALL, MUL #2\n" - "cntw x25, ALL, MUL #3\n" - "whilelt p3.s, x28, %x[n_channels]\n" - "whilelt p2.s, x27, %x[n_channels]\n" - "whilelt p1.s, x26, %x[n_channels]\n" - "whilelt p0.s, x25, %x[n_channels]\n" + "whilelt p3.s, x9, %x[n_channels]\n" + "ld1rw { z7.s }, p0/Z, [%x[rescale_ptr]]\n" + "whilelt p2.s, x28, %x[n_channels]\n" + "whilelt p1.s, x27, %x[n_channels]\n" + "whilelt p0.s, x26, %x[n_channels]\n" "b.none 7f\n" "1:" // 4-vectors of channels - "mov z7.b, #0x0\n" - "mov x19, %x[inptrs]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" "mov z6.b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" + "mov x24, %x[inptrs]\n" "mov z4.b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" - "ld1w { z31.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z30.s }, p2/Z, [x22, x27, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x21, x27, LSL #2]\n" - "ld1w { z28.s }, p2/Z, [x20, x27, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x23, x26, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x22, x26, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x21, x26, LSL #2]\n" - "ld1w { z17.s }, p1/Z, [x20, x26, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x23, x25, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x22, x25, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x21, x25, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x20, x25, LSL #2]\n" + "mov z3.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" + "ld1w { z30.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "fadd z23.s, z3.s, z2.s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd z19.s, z1.s, z0.s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd z22.s, z31.s, z30.s\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" + "fadd z23.s, z2.s, z1.s\n" + "fadd z19.s, z0.s, z31.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z22.s, z30.s, z22.s\n" "fadd z18.s, z29.s, z28.s\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" "fadd z21.s, z27.s, z21.s\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" "fadd z17.s, z26.s, z17.s\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" "fadd z20.s, z25.s, z20.s\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" "fadd z16.s, z24.s, z16.s\n" - "ld1w { z31.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" "fadd z19.s, z23.s, z19.s\n" - "ld1w { z30.s }, p2/Z, [x22, x27, LSL #2]\n" "fadd z18.s, z22.s, z18.s\n" - "ld1w { z29.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z30.s }, p2/Z, [x23, x28, LSL #2]\n" + "ld1w { z22.s }, p2/Z, [x22, x28, LSL #2]\n" "fadd z17.s, z21.s, z17.s\n" - "ld1w { z28.s }, p2/Z, [x20, x27, LSL #2]\n" "fadd z16.s, z20.s, z16.s\n" - "ld1w { z27.s }, p1/Z, [x23, x26, LSL #2]\n" - "fadd z7.s, z7.s, z19.s\n" - "ld1w { z21.s }, p1/Z, [x22, x26, LSL #2]\n" - "fadd z6.s, z6.s, z18.s\n" - "ld1w { z26.s }, p1/Z, [x21, x26, LSL #2]\n" - "fadd z5.s, z5.s, z17.s\n" - "ld1w { z17.s }, p1/Z, [x20, x26, LSL #2]\n" - "fadd z4.s, z4.s, z16.s\n" - "ld1w { z25.s }, p0/Z, [x23, x25, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x22, x25, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x21, x25, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x20, x25, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x21, x28, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x20, x28, LSL #2]\n" + "fadd z6.s, z6.s, z19.s\n" + "fadd z5.s, z5.s, z18.s\n" + "ld1w { z27.s }, p1/Z, [x23, x27, LSL #2]\n" + "ld1w { z21.s }, p1/Z, [x22, x27, LSL #2]\n" + "fadd z4.s, z4.s, z17.s\n" + "fadd z3.s, z3.s, z16.s\n" + "ld1w { z26.s }, p1/Z, [x21, x27, LSL #2]\n" + "ld1w { z17.s }, p1/Z, [x20, x27, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x26, LSL #2]\n" + "ld1w { z20.s }, p0/Z, [x22, x26, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x21, x26, LSL #2]\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "fadd z23.s, z3.s, z2.s\n" - "fadd z19.s, z1.s, z0.s\n" - "fadd z22.s, z31.s, z30.s\n" + "fadd z23.s, z2.s, z1.s\n" + "fadd z19.s, z0.s, z31.s\n" + "fadd z22.s, z30.s, z22.s\n" "fadd z18.s, z29.s, z28.s\n" "fadd z21.s, z27.s, z21.s\n" "fadd z17.s, z26.s, z17.s\n" @@ -132,100 +133,99 @@ void sve_fp32_nhwc_avg_generic_depthfirst_impl( "fadd z18.s, z22.s, z18.s\n" "fadd z17.s, z21.s, z17.s\n" "fadd z16.s, z20.s, z16.s\n" - "fadd z7.s, z7.s, z19.s\n" - "fadd z6.s, z6.s, z18.s\n" - "fadd z5.s, z5.s, z17.s\n" - "fadd z4.s, z4.s, z16.s\n" + "fadd z6.s, z6.s, z19.s\n" + "fadd z5.s, z5.s, z18.s\n" + "fadd z4.s, z4.s, z17.s\n" + "fadd z3.s, z3.s, z16.s\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "fadd z7.s, z7.s, z3.s\n" - "ld1w { z31.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x23, x26, LSL #2]\n" - "fadd z6.s, z6.s, z31.s\n" - "ld1w { z25.s }, p0/Z, [x23, x25, LSL #2]\n" - "fadd z5.s, z5.s, z27.s\n" - "fadd z4.s, z4.s, z25.s\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fadd z6.s, z6.s, z16.s\n" + "ld1w { z17.s }, p2/Z, [x20, x28, LSL #2]\n" + "ld1w { z16.s }, p1/Z, [x20, x27, LSL #2]\n" + "fadd z5.s, z5.s, z17.s\n" + "fadd z4.s, z4.s, z16.s\n" + "ld1w { z16.s }, p0/Z, [x20, x26, LSL #2]\n" + "fadd z3.s, z3.s, z16.s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "fmul z7.s, z7.s, z8.s\n" - "st1w { z7.s }, p3, [%x[outptr], x28, LSL #2]\n" - "fmul z6.s, z6.s, z8.s\n" + "fmul z6.s, z6.s, z7.s\n" + "fmul z5.s, z5.s, z7.s\n" + "st1w { z6.s }, p3, [%x[outptr], x9, LSL #2]\n" + "fmul z4.s, z4.s, z7.s\n" + "fmul z3.s, z3.s, z7.s\n" + "st1w { z5.s }, p2, [%x[outptr], x28, LSL #2]\n" + "st1w { z4.s }, p1, [%x[outptr], x27, LSL #2]\n" + "incw x9, ALL, MUL #4\n" "incw x28, ALL, MUL #4\n" - "fmul z5.s, z5.s, z8.s\n" - "st1w { z6.s }, p2, [%x[outptr], x27, LSL #2]\n" - "fmul z4.s, z4.s, z8.s\n" - "incw x27, ALL, MUL #4\n" - "st1w { z5.s }, p1, [%x[outptr], x26, LSL #2]\n" + "st1w { z3.s }, p0, [%x[outptr], x26, LSL #2]\n" "incw x26, ALL, MUL #4\n" - "st1w { z4.s }, p0, [%x[outptr], x25, LSL #2]\n" - "incw x25, ALL, MUL #4\n" - "whilelt p0.s, x25, %x[n_channels]\n" + "whilelt p0.s, x26, %x[n_channels]\n" + "incw x27, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.s, x28, %x[n_channels]\n" + "whilelt p3.s, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z7.b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z6.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "fadd z23.s, z3.s, z2.s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "fadd z19.s, z1.s, z0.s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fadd z19.s, z23.s, z19.s\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "fadd z7.s, z7.s, z19.s\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" + "fadd z17.s, z2.s, z1.s\n" + "fadd z16.s, z0.s, z31.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fadd z16.s, z17.s, z16.s\n" + "subs x25, x25, #0x1\n" + "fadd z6.s, z6.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p3/Z, [x23, x9, LSL #2]\n" + "ld1w { z1.s }, p3/Z, [x22, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x21, x9, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x20, x9, LSL #2]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "fadd z23.s, z3.s, z2.s\n" - "fadd z19.s, z1.s, z0.s\n" - "fadd z19.s, z23.s, z19.s\n" - "fadd z7.s, z7.s, z19.s\n" + "fadd z17.s, z2.s, z1.s\n" + "fadd z16.s, z0.s, z31.s\n" + "fadd z16.s, z17.s, z16.s\n" + "fadd z6.s, z6.s, z16.s\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "fadd z7.s, z7.s, z3.s\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p3/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fadd z6.s, z6.s, z16.s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "fmul z7.s, z7.s, z8.s\n" - "st1w { z7.s }, p3, [%x[outptr], x28, LSL #2]\n" - "incw x28\n" - "whilelt p3.s, x28, %x[n_channels]\n" + "fmul z6.s, z6.s, z7.s\n" + "st1w { z6.s }, p3, [%x[outptr], x9, LSL #2]\n" + "incw x9\n" + "whilelt p3.s, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value) - : "cc", "memory", "p0", "p1", "p2", "p3", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 086f49e957..b97e3623c4 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst +struct sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; + using Parent = DepthfirstStrategy<float, float>; - typedef void (*kern_type)(unsigned int, const float *const *const, float *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 250cc24226..d9cebd1363 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -63,84 +63,84 @@ void sve_fp32_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x14, [%x[args], %[offsetof_n_channels]]\n" + "ldr x15, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x14, #0x0\n" + "whilelt p0.s, x14, x15\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x13, x12, [x21, #0x0]\n" "ptrue p2.b\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "mov x12, #0x0\n" - "ldp x11, x10, [x20, #0x0]\n" - "whilelt p1.s, x13, x14\n" - "ldp x9, x28, [x20, #0x10]\n" - "ldp x27, x26, [x19, #0x0]\n" - "ldp x25, x24, [x19, #0x10]\n" - "ldp x23, x22, [x19, #0x20]\n" - "ldp x21, x20, [x19, #0x30]\n" - "ldr x19, [x19, #0x40]\n" - "ld1w { z31.s }, p1/Z, [x26, x13, LSL #2]\n" - "ld1w { z30.s }, p1/Z, [x23, x13, LSL #2]\n" - "ld1w { z29.s }, p1/Z, [x20, x13, LSL #2]\n" - "ld1w { z28.s }, p1/Z, [x24, x13, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x27, x13, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x22, x13, LSL #2]\n" - "ld1w { z25.s }, p1/Z, [x25, x13, LSL #2]\n" - "ld1w { z24.s }, p1/Z, [x21, x13, LSL #2]\n" - "ld1w { z23.s }, p1/Z, [x19, x13, LSL #2]\n" - "incw x13\n" - "whilelt p1.s, x13, x14\n" + "mov x11, #0x0\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ldr x20, [x20, #0x40]\n" + "ld1w { z31.s }, p0/Z, [x27, x14, LSL #2]\n" + "ld1w { z30.s }, p0/Z, [x24, x14, LSL #2]\n" + "ld1w { z29.s }, p0/Z, [x21, x14, LSL #2]\n" + "ld1w { z28.s }, p0/Z, [x25, x14, LSL #2]\n" + "ld1w { z27.s }, p0/Z, [x28, x14, LSL #2]\n" + "ld1w { z26.s }, p0/Z, [x26, x14, LSL #2]\n" + "ld1w { z25.s }, p0/Z, [x23, x14, LSL #2]\n" + "ld1w { z24.s }, p0/Z, [x22, x14, LSL #2]\n" + "ld1w { z23.s }, p0/Z, [x20, x14, LSL #2]\n" + "incw x14\n" + "whilelt p1.s, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop "movprfx z22, z31\n fmax z22.s, p2/M, z22.s, z30.s\n" - "ld1w { z31.s }, p1/Z, [x26, x13, LSL #2]\n" - "whilelt p0.s, x12, x14\n" "movprfx z21, z30\n fmax z21.s, p2/M, z21.s, z29.s\n" - "ld1w { z30.s }, p1/Z, [x23, x13, LSL #2]\n" - "movprfx z18, z28\n fmax z18.s, p2/M, z18.s, z27.s\n" - "ld1w { z29.s }, p1/Z, [x20, x13, LSL #2]\n" - "movprfx z17, z26\n fmax z17.s, p2/M, z17.s, z25.s\n" - "ld1w { z27.s }, p1/Z, [x27, x13, LSL #2]\n" - "movprfx z16, z24\n fmax z16.s, p2/M, z16.s, z28.s\n" - "ld1w { z28.s }, p1/Z, [x24, x13, LSL #2]\n" - "movprfx z20, z26\n fmax z20.s, p2/M, z20.s, z23.s\n" - "ld1w { z26.s }, p1/Z, [x22, x13, LSL #2]\n" - "movprfx z19, z22\n fmax z19.s, p2/M, z19.s, z18.s\n" - "ld1w { z25.s }, p1/Z, [x25, x13, LSL #2]\n" - "movprfx z18, z22\n fmax z18.s, p2/M, z18.s, z17.s\n" - "ld1w { z24.s }, p1/Z, [x21, x13, LSL #2]\n" - "movprfx z17, z21\n fmax z17.s, p2/M, z17.s, z16.s\n" - "ld1w { z23.s }, p1/Z, [x19, x13, LSL #2]\n" - "incw x13\n" - "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z20.s\n" - "st1w { z19.s }, p0, [x11, x12, LSL #2]\n" - "whilelt p1.s, x13, x14\n" - "st1w { z18.s }, p0, [x10, x12, LSL #2]\n" - "st1w { z17.s }, p0, [x9, x12, LSL #2]\n" - "st1w { z16.s }, p0, [x28, x12, LSL #2]\n" - "incw x12\n" + "ld1w { z31.s }, p1/Z, [x27, x14, LSL #2]\n" + "ld1w { z30.s }, p1/Z, [x24, x14, LSL #2]\n" + "movprfx z20, z28\n fmax z20.s, p2/M, z20.s, z27.s\n" + "movprfx z19, z26\n fmax z19.s, p2/M, z19.s, z25.s\n" + "ld1w { z29.s }, p1/Z, [x21, x14, LSL #2]\n" + "ld1w { z27.s }, p1/Z, [x28, x14, LSL #2]\n" + "movprfx z17, z28\n fmax z17.s, p2/M, z17.s, z24.s\n" + "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z23.s\n" + "ld1w { z28.s }, p1/Z, [x25, x14, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x26, x14, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x23, x14, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x22, x14, LSL #2]\n" + "whilelt p0.s, x11, x15\n" + "movprfx z16, z22\n fmax z16.s, p2/M, z16.s, z20.s\n" + "ld1w { z23.s }, p1/Z, [x20, x14, LSL #2]\n" + "incw x14\n" + "whilelt p1.s, x14, x15\n" + "st1w { z16.s }, p0, [x13, x11, LSL #2]\n" + "movprfx z16, z19\n fmax z16.s, p2/M, z16.s, z22.s\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" + "st1w { z16.s }, p0, [x12, x11, LSL #2]\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z18.s\n" + "st1w { z17.s }, p0, [x10, x11, LSL #2]\n" + "st1w { z16.s }, p0, [x9, x11, LSL #2]\n" + "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail "movprfx z22, z31\n fmax z22.s, p2/M, z22.s, z30.s\n" - "whilelt p0.s, x12, x14\n" "movprfx z21, z30\n fmax z21.s, p2/M, z21.s, z29.s\n" - "movprfx z18, z28\n fmax z18.s, p2/M, z18.s, z27.s\n" - "movprfx z17, z26\n fmax z17.s, p2/M, z17.s, z25.s\n" - "movprfx z16, z24\n fmax z16.s, p2/M, z16.s, z28.s\n" - "movprfx z20, z26\n fmax z20.s, p2/M, z20.s, z23.s\n" - "movprfx z19, z22\n fmax z19.s, p2/M, z19.s, z18.s\n" - "st1w { z19.s }, p0, [x11, x12, LSL #2]\n" - "movprfx z18, z22\n fmax z18.s, p2/M, z18.s, z17.s\n" - "movprfx z17, z21\n fmax z17.s, p2/M, z17.s, z16.s\n" - "st1w { z18.s }, p0, [x10, x12, LSL #2]\n" - "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z20.s\n" - "st1w { z17.s }, p0, [x9, x12, LSL #2]\n" - "st1w { z16.s }, p0, [x28, x12, LSL #2]\n" + "movprfx z20, z28\n fmax z20.s, p2/M, z20.s, z27.s\n" + "movprfx z19, z26\n fmax z19.s, p2/M, z19.s, z25.s\n" + "movprfx z17, z28\n fmax z17.s, p2/M, z17.s, z24.s\n" + "movprfx z18, z25\n fmax z18.s, p2/M, z18.s, z23.s\n" + "whilelt p0.s, x11, x15\n" + "movprfx z16, z22\n fmax z16.s, p2/M, z16.s, z20.s\n" + "st1w { z16.s }, p0, [x13, x11, LSL #2]\n" + "movprfx z16, z19\n fmax z16.s, p2/M, z16.s, z22.s\n" + "fmax z17.s, p2/M, z17.s, z21.s\n" + "st1w { z16.s }, p0, [x12, x11, LSL #2]\n" + "movprfx z16, z21\n fmax z16.s, p2/M, z16.s, z18.s\n" + "st1w { z17.s }, p0, [x10, x11, LSL #2]\n" + "st1w { z16.s }, p0, [x9, x11, LSL #2]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst.hpp index 17e3e5f0ba..5f6535072b 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_fp32_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); -struct sve_fp32_nhwc_max_generic_depthfirst +struct sve_fp32_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<float, float> { - typedef float operand_type; - typedef float return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const float *const *const inptrs, float *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = sve_fp32_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<float, float>; sve_fp32_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_fp32_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp index 8166379ce4..87fc75adda 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp32_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,9 @@ */ #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -39,185 +40,184 @@ void sve_fp32_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "ptrue p4.b\n" - "mov x28, #0x0\n" - "cntw x27\n" - "cntw x26, ALL, MUL #2\n" - "cntw x25, ALL, MUL #3\n" + "mov x9, #0x0\n" + "cntw x28\n" + "cntw x27, ALL, MUL #2\n" + "cntw x26, ALL, MUL #3\n" + "whilelt p4.s, x9, %x[n_channels]\n" "whilelt p3.s, x28, %x[n_channels]\n" "whilelt p2.s, x27, %x[n_channels]\n" "whilelt p1.s, x26, %x[n_channels]\n" - "whilelt p0.s, x25, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.s, #0xff800000\n" "mov z7.s, #0xff800000\n" - "mov x19, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.s, #0xff800000\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "mov z5.s, #0xff800000\n" - "mov z4.s, #0xff800000\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" - "ld1w { z31.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z30.s }, p2/Z, [x22, x27, LSL #2]\n" - "ld1w { z22.s }, p2/Z, [x21, x27, LSL #2]\n" - "ld1w { z29.s }, p2/Z, [x20, x27, LSL #2]\n" - "ld1w { z28.s }, p1/Z, [x23, x26, LSL #2]\n" - "ld1w { z27.s }, p1/Z, [x22, x26, LSL #2]\n" - "ld1w { z21.s }, p1/Z, [x21, x26, LSL #2]\n" - "ld1w { z26.s }, p1/Z, [x20, x26, LSL #2]\n" - "ld1w { z16.s }, p0/Z, [x23, x25, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x22, x25, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x21, x25, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x20, x25, LSL #2]\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" + "ld1w { z0.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x22, x28, LSL #2]\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x22, x27, LSL #2]\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x20, x27, LSL #2]\n" + "ld1w { z26.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "movprfx z19, z3\n fmax z19.s, p4/M, z19.s, z2.s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n fmax z23.s, p4/M, z23.s, z0.s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "movprfx z18, z31\n fmax z18.s, p4/M, z18.s, z30.s\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "fmax z22.s, p4/M, z22.s, z29.s\n" - "movprfx z17, z28\n fmax z17.s, p4/M, z17.s, z27.s\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "fmax z21.s, p4/M, z21.s, z26.s\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "fmax z16.s, p4/M, z16.s, z25.s\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" - "fmax z20.s, p4/M, z20.s, z24.s\n" - "ld1w { z31.s }, p2/Z, [x23, x27, LSL #2]\n" - "fmax z19.s, p4/M, z19.s, z23.s\n" - "ld1w { z30.s }, p2/Z, [x22, x27, LSL #2]\n" - "fmax z18.s, p4/M, z18.s, z22.s\n" - "ld1w { z22.s }, p2/Z, [x21, x27, LSL #2]\n" - "fmax z17.s, p4/M, z17.s, z21.s\n" - "ld1w { z29.s }, p2/Z, [x20, x27, LSL #2]\n" - "fmax z16.s, p4/M, z16.s, z20.s\n" - "ld1w { z28.s }, p1/Z, [x23, x26, LSL #2]\n" - "fmax z7.s, p4/M, z7.s, z19.s\n" - "ld1w { z27.s }, p1/Z, [x22, x26, LSL #2]\n" - "fmax z6.s, p4/M, z6.s, z18.s\n" - "ld1w { z21.s }, p1/Z, [x21, x26, LSL #2]\n" - "fmax z5.s, p4/M, z5.s, z17.s\n" - "ld1w { z26.s }, p1/Z, [x20, x26, LSL #2]\n" - "fmax z4.s, p4/M, z4.s, z16.s\n" - "ld1w { z16.s }, p0/Z, [x23, x25, LSL #2]\n" - "ld1w { z25.s }, p0/Z, [x22, x25, LSL #2]\n" - "ld1w { z20.s }, p0/Z, [x21, x25, LSL #2]\n" - "ld1w { z24.s }, p0/Z, [x20, x25, LSL #2]\n" + "movprfx z19, z4\n fmax z19.s, p0/M, z19.s, z3.s\n" + "movprfx z23, z2\n fmax z23.s, p0/M, z23.s, z1.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "movprfx z18, z0\n fmax z18.s, p0/M, z18.s, z31.s\n" + "fmax z22.s, p0/M, z22.s, z30.s\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "movprfx z17, z29\n fmax z17.s, p0/M, z17.s, z28.s\n" + "fmax z21.s, p0/M, z21.s, z27.s\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" + "movprfx z16, z26\n fmax z16.s, p0/M, z16.s, z25.s\n" + "fmax z20.s, p0/M, z20.s, z24.s\n" + "ld1w { z0.s }, p3/Z, [x23, x28, LSL #2]\n" + "ld1w { z31.s }, p3/Z, [x22, x28, LSL #2]\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z18.s, p0/M, z18.s, z22.s\n" + "ld1w { z22.s }, p3/Z, [x21, x28, LSL #2]\n" + "ld1w { z30.s }, p3/Z, [x20, x28, LSL #2]\n" + "fmax z17.s, p0/M, z17.s, z21.s\n" + "fmax z16.s, p0/M, z16.s, z20.s\n" + "ld1w { z29.s }, p2/Z, [x23, x27, LSL #2]\n" + "ld1w { z28.s }, p2/Z, [x22, x27, LSL #2]\n" + "subs x25, x25, #0x1\n" + "fmax z8.s, p0/M, z8.s, z19.s\n" + "ld1w { z21.s }, p2/Z, [x21, x27, LSL #2]\n" + "ld1w { z27.s }, p2/Z, [x20, x27, LSL #2]\n" + "fmax z7.s, p0/M, z7.s, z18.s\n" + "fmax z6.s, p0/M, z6.s, z17.s\n" + "ld1w { z26.s }, p1/Z, [x23, x26, LSL #2]\n" + "ld1w { z25.s }, p1/Z, [x22, x26, LSL #2]\n" + "fmax z5.s, p0/M, z5.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z20.s }, p1/Z, [x21, x26, LSL #2]\n" + "ld1w { z24.s }, p1/Z, [x20, x26, LSL #2]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "movprfx z19, z3\n fmax z19.s, p4/M, z19.s, z2.s\n" - "movprfx z23, z1\n fmax z23.s, p4/M, z23.s, z0.s\n" - "movprfx z18, z31\n fmax z18.s, p4/M, z18.s, z30.s\n" - "fmax z22.s, p4/M, z22.s, z29.s\n" - "movprfx z17, z28\n fmax z17.s, p4/M, z17.s, z27.s\n" - "fmax z21.s, p4/M, z21.s, z26.s\n" - "fmax z16.s, p4/M, z16.s, z25.s\n" - "fmax z20.s, p4/M, z20.s, z24.s\n" - "fmax z19.s, p4/M, z19.s, z23.s\n" - "fmax z18.s, p4/M, z18.s, z22.s\n" - "fmax z17.s, p4/M, z17.s, z21.s\n" - "fmax z16.s, p4/M, z16.s, z20.s\n" - "fmax z7.s, p4/M, z7.s, z19.s\n" - "fmax z6.s, p4/M, z6.s, z18.s\n" - "fmax z5.s, p4/M, z5.s, z17.s\n" - "fmax z4.s, p4/M, z4.s, z16.s\n" + "movprfx z19, z4\n fmax z19.s, p0/M, z19.s, z3.s\n" + "movprfx z23, z2\n fmax z23.s, p0/M, z23.s, z1.s\n" + "movprfx z18, z0\n fmax z18.s, p0/M, z18.s, z31.s\n" + "fmax z22.s, p0/M, z22.s, z30.s\n" + "movprfx z17, z29\n fmax z17.s, p0/M, z17.s, z28.s\n" + "fmax z21.s, p0/M, z21.s, z27.s\n" + "movprfx z16, z26\n fmax z16.s, p0/M, z16.s, z25.s\n" + "fmax z20.s, p0/M, z20.s, z24.s\n" + "fmax z19.s, p0/M, z19.s, z23.s\n" + "fmax z18.s, p0/M, z18.s, z22.s\n" + "fmax z17.s, p0/M, z17.s, z21.s\n" + "fmax z16.s, p0/M, z16.s, z20.s\n" + "fmax z8.s, p0/M, z8.s, z19.s\n" + "fmax z7.s, p0/M, z7.s, z18.s\n" + "fmax z6.s, p0/M, z6.s, z17.s\n" + "fmax z5.s, p0/M, z5.s, z16.s\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "fmax z7.s, p4/M, z7.s, z3.s\n" - "ld1w { z31.s }, p2/Z, [x23, x27, LSL #2]\n" - "ld1w { z28.s }, p1/Z, [x23, x26, LSL #2]\n" - "fmax z6.s, p4/M, z6.s, z31.s\n" - "ld1w { z16.s }, p0/Z, [x23, x25, LSL #2]\n" - "fmax z5.s, p4/M, z5.s, z28.s\n" - "fmax z4.s, p4/M, z4.s, z16.s\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" + "ld1w { z17.s }, p3/Z, [x20, x28, LSL #2]\n" + "ld1w { z16.s }, p2/Z, [x20, x27, LSL #2]\n" + "fmax z7.s, p0/M, z7.s, z17.s\n" + "fmax z6.s, p0/M, z6.s, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20, x26, LSL #2]\n" + "fmax z5.s, p0/M, z5.s, z16.s\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End + "st1w { z8.s }, p4, [%x[outptr], x9, LSL #2]\n" + "incw x9, ALL, MUL #4\n" "st1w { z7.s }, p3, [%x[outptr], x28, LSL #2]\n" "incw x28, ALL, MUL #4\n" "st1w { z6.s }, p2, [%x[outptr], x27, LSL #2]\n" "incw x27, ALL, MUL #4\n" "st1w { z5.s }, p1, [%x[outptr], x26, LSL #2]\n" "incw x26, ALL, MUL #4\n" - "st1w { z4.s }, p0, [%x[outptr], x25, LSL #2]\n" - "incw x25, ALL, MUL #4\n" - "whilelt p0.s, x25, %x[n_channels]\n" + "whilelt p1.s, x26, %x[n_channels]\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.s, x28, %x[n_channels]\n" + "whilelt p4.s, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z7.s, #0xff800000\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.s, #0xff800000\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z3\n fmax z19.s, p4/M, z19.s, z2.s\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n fmax z23.s, p4/M, z23.s, z0.s\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "fmax z19.s, p4/M, z19.s, z23.s\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "ld1w { z2.s }, p3/Z, [x22, x28, LSL #2]\n" - "fmax z7.s, p4/M, z7.s, z19.s\n" - "ld1w { z1.s }, p3/Z, [x21, x28, LSL #2]\n" - "ld1w { z0.s }, p3/Z, [x20, x28, LSL #2]\n" + "movprfx z16, z4\n fmax z16.s, p0/M, z16.s, z3.s\n" + "movprfx z17, z2\n fmax z17.s, p0/M, z17.s, z1.s\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "subs x25, x25, #0x1\n" + "ld1w { z4.s }, p4/Z, [x23, x9, LSL #2]\n" + "ld1w { z3.s }, p4/Z, [x22, x9, LSL #2]\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" + "add x24, x24, #0x20\n" + "ld1w { z2.s }, p4/Z, [x21, x9, LSL #2]\n" + "ld1w { z1.s }, p4/Z, [x20, x9, LSL #2]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z3\n fmax z19.s, p4/M, z19.s, z2.s\n" - "movprfx z23, z1\n fmax z23.s, p4/M, z23.s, z0.s\n" - "fmax z19.s, p4/M, z19.s, z23.s\n" - "fmax z7.s, p4/M, z7.s, z19.s\n" + "movprfx z16, z4\n fmax z16.s, p0/M, z16.s, z3.s\n" + "movprfx z17, z2\n fmax z17.s, p0/M, z17.s, z1.s\n" + "fmax z16.s, p0/M, z16.s, z17.s\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1w { z3.s }, p3/Z, [x23, x28, LSL #2]\n" - "fmax z7.s, p4/M, z7.s, z3.s\n" + "ldr x20, [x24], #0x8\n" + "ld1w { z16.s }, p4/Z, [x20, x9, LSL #2]\n" + "subs x21, x21, #0x1\n" + "fmax z8.s, p0/M, z8.s, z16.s\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "st1w { z7.s }, p3, [%x[outptr], x28, LSL #2]\n" - "incw x28\n" - "whilelt p3.s, x28, %x[n_channels]\n" + "st1w { z8.s }, p4, [%x[outptr], x9, LSL #2]\n" + "incw x9\n" + "whilelt p4.s, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst.hpp index 2ae38b5b2f..dd2ff4fd2e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_s8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); -struct sve_s8_nhwc_avg_generic_depthfirst +struct sve_s8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = sve_s8_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; sve_s8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_s8_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp index 2ea5b90561..7925905e64 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,11 +23,12 @@ */ #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -84,30 +85,31 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } __asm__ __volatile__( - "ptrue p4.b\n" - "mov x26, #0x0\n" - "cntb x25\n" - "cntb x24, ALL, MUL #2\n" - "cntb x23, ALL, MUL #3\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" "whilelt p3.b, x26, %x[n_channels]\n" "whilelt p2.b, x25, %x[n_channels]\n" "whilelt p1.b, x24, %x[n_channels]\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" - "mov x19, %x[inptrs]\n" "mov z14.s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -122,43 +124,43 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( "mov z2.s, #0x0\n" "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" - "subs x22, x22, #0x1\n" ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" @@ -198,219 +200,218 @@ void sve_s8_nhwc_avg_generic_depthfirst_impl( ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508a3f1 // sshllb z17.h, z31.b, #0x0\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - ".inst 0x4508a7f0 // sshllt z16.h, z31.b, #0x0\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" - ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" - ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" - ".inst 0x4508a3b0 // sshllb z16.h, z29.b, #0x0\n" - ".inst 0x4590416b // saddwb z11.s, z11.s, z16.h\n" - ".inst 0x4590454a // saddwt z10.s, z10.s, z16.h\n" - ".inst 0x4508a7b0 // sshllt z16.h, z29.b, #0x0\n" - ".inst 0x45904129 // saddwb z9.s, z9.s, z16.h\n" - ".inst 0x45904508 // saddwt z8.s, z8.s, z16.h\n" - ".inst 0x4508a370 // sshllb z16.h, z27.b, #0x0\n" - ".inst 0x459040e7 // saddwb z7.s, z7.s, z16.h\n" - ".inst 0x459044c6 // saddwt z6.s, z6.s, z16.h\n" - ".inst 0x4508a770 // sshllt z16.h, z27.b, #0x0\n" - ".inst 0x459040a5 // saddwb z5.s, z5.s, z16.h\n" - ".inst 0x45904484 // saddwt z4.s, z4.s, z16.h\n" - ".inst 0x4508a330 // sshllb z16.h, z25.b, #0x0\n" - ".inst 0x45904063 // saddwb z3.s, z3.s, z16.h\n" - ".inst 0x45904442 // saddwt z2.s, z2.s, z16.h\n" - ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a233 // sshllb z19.h, z17.b, #0x0\n" + ".inst 0x4508a632 // sshllt z18.h, z17.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "mov z20.s, #0x7f\n" - "ld1rw { z17.s }, p4/Z, [%x[rescale_ptr]]\n" - "ld1rw { z16.s }, p4/Z, [%x[shift_ptr]]\n" - "not z19.s, p4/M, z20.s\n" + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" ".inst 0x04b1756b // sqdmulh z11.s, z11.s, z17.s\n" ".inst 0x04b1754a // sqdmulh z10.s, z10.s, z17.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" ".inst 0x04b17529 // sqdmulh z9.s, z9.s, z17.s\n" ".inst 0x04b17508 // sqdmulh z8.s, z8.s, z17.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" ".inst 0x04b174e7 // sqdmulh z7.s, z7.s, z17.s\n" ".inst 0x04b174c6 // sqdmulh z6.s, z6.s, z17.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" ".inst 0x04b174a5 // sqdmulh z5.s, z5.s, z17.s\n" ".inst 0x04b17484 // sqdmulh z4.s, z4.s, z17.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" ".inst 0x04b17463 // sqdmulh z3.s, z3.s, z17.s\n" ".inst 0x04b17442 // sqdmulh z2.s, z2.s, z17.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" ".inst 0x04b17421 // sqdmulh z1.s, z1.s, z17.s\n" ".inst 0x04b17400 // sqdmulh z0.s, z0.s, z17.s\n" - ".inst 0x4482920f // srshl z15.s, p4/M, z15.s, z16.s\n" - ".inst 0x4482920e // srshl z14.s, p4/M, z14.s, z16.s\n" - ".inst 0x4482920d // srshl z13.s, p4/M, z13.s, z16.s\n" - ".inst 0x4482920c // srshl z12.s, p4/M, z12.s, z16.s\n" - ".inst 0x4482920b // srshl z11.s, p4/M, z11.s, z16.s\n" - ".inst 0x4482920a // srshl z10.s, p4/M, z10.s, z16.s\n" - ".inst 0x44829209 // srshl z9.s, p4/M, z9.s, z16.s\n" - ".inst 0x44829208 // srshl z8.s, p4/M, z8.s, z16.s\n" - ".inst 0x44829207 // srshl z7.s, p4/M, z7.s, z16.s\n" - ".inst 0x44829206 // srshl z6.s, p4/M, z6.s, z16.s\n" - ".inst 0x44829205 // srshl z5.s, p4/M, z5.s, z16.s\n" - ".inst 0x44829204 // srshl z4.s, p4/M, z4.s, z16.s\n" - ".inst 0x44829203 // srshl z3.s, p4/M, z3.s, z16.s\n" - ".inst 0x44829202 // srshl z2.s, p4/M, z2.s, z16.s\n" - ".inst 0x44829201 // srshl z1.s, p4/M, z1.s, z16.s\n" - ".inst 0x44829200 // srshl z0.s, p4/M, z0.s, z16.s\n" - "smax z15.s, p4/M, z15.s, z19.s\n" - "smax z14.s, p4/M, z14.s, z19.s\n" - "smax z13.s, p4/M, z13.s, z19.s\n" - "smax z12.s, p4/M, z12.s, z19.s\n" - "smin z15.s, p4/M, z15.s, z20.s\n" - "smin z14.s, p4/M, z14.s, z20.s\n" - "smin z13.s, p4/M, z13.s, z20.s\n" - "smin z12.s, p4/M, z12.s, z20.s\n" - "smax z11.s, p4/M, z11.s, z19.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "smin z13.s, p0/M, z13.s, z18.s\n" "trn1 z17.h, z15.h, z14.h\n" - "smax z10.s, p4/M, z10.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" + "smin z11.s, p0/M, z11.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" - "smin z11.s, p4/M, z11.s, z20.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "smin z10.s, p4/M, z10.s, z20.s\n" - "incb x26, ALL, MUL #4\n" - "smax z9.s, p4/M, z9.s, z19.s\n" - "smax z8.s, p4/M, z8.s, z19.s\n" - "smax z7.s, p4/M, z7.s, z19.s\n" - "smax z6.s, p4/M, z6.s, z19.s\n" - "trn1 z18.h, z11.h, z10.h\n" - "smin z9.s, p4/M, z9.s, z20.s\n" - "smin z8.s, p4/M, z8.s, z20.s\n" - "smin z7.s, p4/M, z7.s, z20.s\n" - "smin z6.s, p4/M, z6.s, z20.s\n" - "smax z5.s, p4/M, z5.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z18.s\n" + "smin z9.s, p0/M, z9.s, z18.s\n" + "trn1 z17.h, z11.h, z10.h\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "smin z8.s, p0/M, z8.s, z18.s\n" + "smin z7.s, p0/M, z7.s, z18.s\n" "trn1 z16.h, z9.h, z8.h\n" - "smax z4.s, p4/M, z4.s, z19.s\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z6.s, p0/M, z6.s, z18.s\n" + "smin z5.s, p0/M, z5.s, z18.s\n" "trn1 z17.h, z7.h, z6.h\n" - "trn1 z16.b, z18.b, z16.b\n" - "st1b { z16.b }, p2, [%x[outptr], x25]\n" - "smin z5.s, p4/M, z5.s, z20.s\n" - "incb x25, ALL, MUL #4\n" - "smin z4.s, p4/M, z4.s, z20.s\n" - "smax z3.s, p4/M, z3.s, z19.s\n" - "smax z2.s, p4/M, z2.s, z19.s\n" - "smax z1.s, p4/M, z1.s, z19.s\n" - "smax z0.s, p4/M, z0.s, z19.s\n" + "st1b { z16.b }, p3, [%x[outptr], x26]\n" + "smin z4.s, p0/M, z4.s, z18.s\n" + "smin z3.s, p0/M, z3.s, z18.s\n" "trn1 z16.h, z5.h, z4.h\n" - "smin z3.s, p4/M, z3.s, z20.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p1, [%x[outptr], x24]\n" - "smin z2.s, p4/M, z2.s, z20.s\n" - "incb x24, ALL, MUL #4\n" - "smin z1.s, p4/M, z1.s, z20.s\n" - "smin z0.s, p4/M, z0.s, z20.s\n" + "smin z2.s, p0/M, z2.s, z18.s\n" + "smin z1.s, p0/M, z1.s, z18.s\n" "trn1 z17.h, z3.h, z2.h\n" + "st1b { z16.b }, p2, [%x[outptr], x25]\n" + "smin z0.s, p0/M, z0.s, z18.s\n" "trn1 z16.h, z1.h, z0.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p0, [%x[outptr], x23]\n" - "incb x23, ALL, MUL #4\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "incb x27, ALL, MUL #4\n" + "incb x26, ALL, MUL #4\n" + "incb x25, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" - "mov x19, %x[inptrs]\n" "mov z14.s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - "subs x22, x22, #0x1\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508a3f1 // sshllb z17.h, z31.b, #0x0\n" - ".inst 0x4508a7f0 // sshllt z16.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "mov z20.s, #0x7f\n" - "ld1rw { z17.s }, p4/Z, [%x[rescale_ptr]]\n" - "ld1rw { z16.s }, p4/Z, [%x[shift_ptr]]\n" - "not z19.s, p4/M, z20.s\n" + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" - ".inst 0x4482920f // srshl z15.s, p4/M, z15.s, z16.s\n" - ".inst 0x4482920e // srshl z14.s, p4/M, z14.s, z16.s\n" - ".inst 0x4482920d // srshl z13.s, p4/M, z13.s, z16.s\n" - ".inst 0x4482920c // srshl z12.s, p4/M, z12.s, z16.s\n" - "smax z15.s, p4/M, z15.s, z19.s\n" - "smax z14.s, p4/M, z14.s, z19.s\n" - "smax z13.s, p4/M, z13.s, z19.s\n" - "smax z12.s, p4/M, z12.s, z19.s\n" - "smin z15.s, p4/M, z15.s, z20.s\n" - "smin z14.s, p4/M, z14.s, z20.s\n" - "smin z13.s, p4/M, z13.s, z20.s\n" - "smin z12.s, p4/M, z12.s, z20.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "smin z13.s, p0/M, z13.s, z18.s\n" "trn1 z17.h, z15.h, z14.h\n" + "smin z12.s, p0/M, z12.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "incb x26\n" - "whilelt p3.b, x26, %x[n_channels]\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 071e79c93d..ac842ac623 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const int8_t *const *const, int8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst +struct sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<int8_t, int8_t> { - typedef int8_t operand_type; - typedef int8_t return_type; + using Parent = DepthfirstStrategy<int8_t, int8_t>; - typedef void (*kern_type)(unsigned int, const int8_t *const *const, int8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index bdf3f53292..5681cc1f3d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -63,84 +63,84 @@ void sve_s8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x14, [%x[args], %[offsetof_n_channels]]\n" + "ldr x15, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x14, #0x0\n" + "whilelt p0.b, x14, x15\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x13, x12, [x21, #0x0]\n" "ptrue p2.b\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "mov x12, #0x0\n" - "ldp x11, x10, [x20, #0x0]\n" - "whilelt p1.b, x13, x14\n" - "ldp x9, x28, [x20, #0x10]\n" - "ldp x27, x26, [x19, #0x0]\n" - "ldp x25, x24, [x19, #0x10]\n" - "ldp x23, x22, [x19, #0x20]\n" - "ldp x21, x20, [x19, #0x30]\n" - "ldr x19, [x19, #0x40]\n" - "ld1b { z31.b }, p1/Z, [x26, x13]\n" - "ld1b { z30.b }, p1/Z, [x23, x13]\n" - "ld1b { z29.b }, p1/Z, [x20, x13]\n" - "ld1b { z28.b }, p1/Z, [x24, x13]\n" - "ld1b { z27.b }, p1/Z, [x27, x13]\n" - "ld1b { z26.b }, p1/Z, [x22, x13]\n" - "ld1b { z25.b }, p1/Z, [x25, x13]\n" - "ld1b { z24.b }, p1/Z, [x21, x13]\n" - "ld1b { z23.b }, p1/Z, [x19, x13]\n" - "incw x13\n" - "whilelt p1.b, x13, x14\n" + "mov x11, #0x0\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ldr x20, [x20, #0x40]\n" + "ld1b { z31.b }, p0/Z, [x27, x14]\n" + "ld1b { z30.b }, p0/Z, [x24, x14]\n" + "ld1b { z29.b }, p0/Z, [x21, x14]\n" + "ld1b { z28.b }, p0/Z, [x25, x14]\n" + "ld1b { z27.b }, p0/Z, [x28, x14]\n" + "ld1b { z26.b }, p0/Z, [x26, x14]\n" + "ld1b { z25.b }, p0/Z, [x23, x14]\n" + "ld1b { z24.b }, p0/Z, [x22, x14]\n" + "ld1b { z23.b }, p0/Z, [x20, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop "movprfx z22, z31\n smax z22.b, p2/M, z22.b, z30.b\n" - "ld1b { z31.b }, p1/Z, [x26, x13]\n" - "whilelt p0.b, x12, x14\n" "movprfx z21, z30\n smax z21.b, p2/M, z21.b, z29.b\n" - "ld1b { z30.b }, p1/Z, [x23, x13]\n" - "movprfx z18, z28\n smax z18.b, p2/M, z18.b, z27.b\n" - "ld1b { z29.b }, p1/Z, [x20, x13]\n" - "movprfx z17, z26\n smax z17.b, p2/M, z17.b, z25.b\n" - "ld1b { z27.b }, p1/Z, [x27, x13]\n" - "movprfx z16, z24\n smax z16.b, p2/M, z16.b, z28.b\n" - "ld1b { z28.b }, p1/Z, [x24, x13]\n" - "movprfx z20, z26\n smax z20.b, p2/M, z20.b, z23.b\n" - "ld1b { z26.b }, p1/Z, [x22, x13]\n" - "movprfx z19, z22\n smax z19.b, p2/M, z19.b, z18.b\n" - "ld1b { z25.b }, p1/Z, [x25, x13]\n" - "movprfx z18, z22\n smax z18.b, p2/M, z18.b, z17.b\n" - "ld1b { z24.b }, p1/Z, [x21, x13]\n" - "movprfx z17, z21\n smax z17.b, p2/M, z17.b, z16.b\n" - "ld1b { z23.b }, p1/Z, [x19, x13]\n" - "incw x13\n" - "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z20.b\n" - "st1b { z19.b }, p0, [x11, x12]\n" - "whilelt p1.b, x13, x14\n" - "st1b { z18.b }, p0, [x10, x12]\n" - "st1b { z17.b }, p0, [x9, x12]\n" - "st1b { z16.b }, p0, [x28, x12]\n" - "incw x12\n" + "ld1b { z31.b }, p1/Z, [x27, x14]\n" + "ld1b { z30.b }, p1/Z, [x24, x14]\n" + "movprfx z20, z28\n smax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n smax z19.b, p2/M, z19.b, z25.b\n" + "ld1b { z29.b }, p1/Z, [x21, x14]\n" + "ld1b { z27.b }, p1/Z, [x28, x14]\n" + "movprfx z17, z28\n smax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z23.b\n" + "ld1b { z28.b }, p1/Z, [x25, x14]\n" + "ld1b { z26.b }, p1/Z, [x26, x14]\n" + "ld1b { z25.b }, p1/Z, [x23, x14]\n" + "ld1b { z24.b }, p1/Z, [x22, x14]\n" + "whilelt p0.b, x11, x15\n" + "movprfx z16, z22\n smax z16.b, p2/M, z16.b, z20.b\n" + "ld1b { z23.b }, p1/Z, [x20, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x15\n" + "st1b { z16.b }, p0, [x13, x11]\n" + "movprfx z16, z19\n smax z16.b, p2/M, z16.b, z22.b\n" + "smax z17.b, p2/M, z17.b, z21.b\n" + "st1b { z16.b }, p0, [x12, x11]\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z18.b\n" + "st1b { z17.b }, p0, [x10, x11]\n" + "st1b { z16.b }, p0, [x9, x11]\n" + "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail "movprfx z22, z31\n smax z22.b, p2/M, z22.b, z30.b\n" - "whilelt p0.b, x12, x14\n" "movprfx z21, z30\n smax z21.b, p2/M, z21.b, z29.b\n" - "movprfx z18, z28\n smax z18.b, p2/M, z18.b, z27.b\n" - "movprfx z17, z26\n smax z17.b, p2/M, z17.b, z25.b\n" - "movprfx z16, z24\n smax z16.b, p2/M, z16.b, z28.b\n" - "movprfx z20, z26\n smax z20.b, p2/M, z20.b, z23.b\n" - "movprfx z19, z22\n smax z19.b, p2/M, z19.b, z18.b\n" - "st1b { z19.b }, p0, [x11, x12]\n" - "movprfx z18, z22\n smax z18.b, p2/M, z18.b, z17.b\n" - "movprfx z17, z21\n smax z17.b, p2/M, z17.b, z16.b\n" - "st1b { z18.b }, p0, [x10, x12]\n" - "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z20.b\n" - "st1b { z17.b }, p0, [x9, x12]\n" - "st1b { z16.b }, p0, [x28, x12]\n" + "movprfx z20, z28\n smax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n smax z19.b, p2/M, z19.b, z25.b\n" + "movprfx z17, z28\n smax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n smax z18.b, p2/M, z18.b, z23.b\n" + "whilelt p0.b, x11, x15\n" + "movprfx z16, z22\n smax z16.b, p2/M, z16.b, z20.b\n" + "st1b { z16.b }, p0, [x13, x11]\n" + "movprfx z16, z19\n smax z16.b, p2/M, z16.b, z22.b\n" + "smax z17.b, p2/M, z17.b, z21.b\n" + "st1b { z16.b }, p0, [x12, x11]\n" + "movprfx z16, z21\n smax z16.b, p2/M, z16.b, z18.b\n" + "st1b { z17.b }, p0, [x10, x11]\n" + "st1b { z16.b }, p0, [x9, x11]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst.hpp index 428902ad61..2ee5bc0527 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_s8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); -struct sve_s8_nhwc_max_generic_depthfirst +struct sve_s8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = sve_s8_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t>; sve_s8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_s8_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp index 3e88c8729c..da9e1408f9 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,9 @@ */ #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -39,185 +40,184 @@ void sve_s8_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "ptrue p4.b\n" - "mov x28, #0x0\n" - "cntb x27\n" - "cntb x26, ALL, MUL #2\n" - "cntb x25, ALL, MUL #3\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" "whilelt p3.b, x28, %x[n_channels]\n" "whilelt p2.b, x27, %x[n_channels]\n" "whilelt p1.b, x26, %x[n_channels]\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.b, #0x80\n" "mov z7.b, #0x80\n" - "mov x19, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x80\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x80\n" - "mov z4.b, #0x80\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "movprfx z18, z31\n smax z18.b, p4/M, z18.b, z30.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "smax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n smax z17.b, p4/M, z17.b, z27.b\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "smax z21.b, p4/M, z21.b, z26.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "smax z16.b, p4/M, z16.b, z25.b\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "smax z20.b, p4/M, z20.b, z24.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "smax z18.b, p4/M, z18.b, z22.b\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "smax z17.b, p4/M, z17.b, z21.b\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "smax z16.b, p4/M, z16.b, z20.b\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "smax z7.b, p4/M, z7.b, z19.b\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "smax z6.b, p4/M, z6.b, z18.b\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "smax z5.b, p4/M, z5.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "smax z4.b, p4/M, z4.b, z16.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "movprfx z18, z0\n smax z18.b, p0/M, z18.b, z31.b\n" + "smax z22.b, p0/M, z22.b, z30.b\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "movprfx z17, z29\n smax z17.b, p0/M, z17.b, z28.b\n" + "smax z21.b, p0/M, z21.b, z27.b\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "movprfx z16, z26\n smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "subs x25, x25, #0x1\n" + "smax z8.b, p0/M, z8.b, z19.b\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "smax z7.b, p0/M, z7.b, z18.b\n" + "smax z6.b, p0/M, z6.b, z17.b\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "smax z5.b, p0/M, z5.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "movprfx z18, z31\n smax z18.b, p4/M, z18.b, z30.b\n" - "smax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n smax z17.b, p4/M, z17.b, z27.b\n" - "smax z21.b, p4/M, z21.b, z26.b\n" - "smax z16.b, p4/M, z16.b, z25.b\n" - "smax z20.b, p4/M, z20.b, z24.b\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "smax z18.b, p4/M, z18.b, z22.b\n" - "smax z17.b, p4/M, z17.b, z21.b\n" - "smax z16.b, p4/M, z16.b, z20.b\n" - "smax z7.b, p4/M, z7.b, z19.b\n" - "smax z6.b, p4/M, z6.b, z18.b\n" - "smax z5.b, p4/M, z5.b, z17.b\n" - "smax z4.b, p4/M, z4.b, z16.b\n" + "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" + "movprfx z18, z0\n smax z18.b, p0/M, z18.b, z31.b\n" + "smax z22.b, p0/M, z22.b, z30.b\n" + "movprfx z17, z29\n smax z17.b, p0/M, z17.b, z28.b\n" + "smax z21.b, p0/M, z21.b, z27.b\n" + "movprfx z16, z26\n smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "smax z8.b, p0/M, z8.b, z19.b\n" + "smax z7.b, p0/M, z7.b, z18.b\n" + "smax z6.b, p0/M, z6.b, z17.b\n" + "smax z5.b, p0/M, z5.b, z16.b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "smax z7.b, p4/M, z7.b, z3.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "smax z6.b, p4/M, z6.b, z31.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "smax z5.b, p4/M, z5.b, z28.b\n" - "smax z4.b, p4/M, z4.b, z16.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z7.b, p0/M, z7.b, z17.b\n" + "smax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "smax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End + "st1b { z8.b }, p4, [%x[outptr], x9]\n" + "incb x9, ALL, MUL #4\n" "st1b { z7.b }, p3, [%x[outptr], x28]\n" "incb x28, ALL, MUL #4\n" "st1b { z6.b }, p2, [%x[outptr], x27]\n" "incb x27, ALL, MUL #4\n" "st1b { z5.b }, p1, [%x[outptr], x26]\n" "incb x26, ALL, MUL #4\n" - "st1b { z4.b }, p0, [%x[outptr], x25]\n" - "incb x25, ALL, MUL #4\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z7.b, #0x80\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.b, #0x80\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "smax z7.b, p4/M, z7.b, z19.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "subs x25, x25, #0x1\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "smax z7.b, p4/M, z7.b, z19.b\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "smax z7.b, p4/M, z7.b, z3.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "st1b { z7.b }, p3, [%x[outptr], x28]\n" - "incb x28\n" - "whilelt p3.b, x28, %x[n_channels]\n" + "st1b { z8.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst.hpp index 1242eaf530..6f34faa121 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_s8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); -struct sve_s8q_nhwc_avg_generic_depthfirst +struct sve_s8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = sve_s8q_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; sve_s8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_s8q_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp index 928eb412b5..19a3b112ad 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,11 +24,12 @@ #include "pooling.hpp" #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -86,12 +87,13 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } // Combine together the rescale value for the requantization and the scaling @@ -112,21 +114,21 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( ); __asm__ __volatile__( - "ptrue p4.b\n" - "mov x26, #0x0\n" - "cntb x25\n" - "cntb x24, ALL, MUL #2\n" - "cntb x23, ALL, MUL #3\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" "whilelt p3.b, x26, %x[n_channels]\n" "whilelt p2.b, x25, %x[n_channels]\n" "whilelt p1.b, x24, %x[n_channels]\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" - "mov x19, %x[inptrs]\n" "mov z14.s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -141,43 +143,43 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( "mov z2.s, #0x0\n" "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" ".inst 0x455c03b5 // saddlb z21.h, z29.b, z28.b\n" - "subs x22, x22, #0x1\n" ".inst 0x455c07b4 // saddlt z20.h, z29.b, z28.b\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0373 // saddlb z19.h, z27.b, z26.b\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" ".inst 0x455a0772 // saddlt z18.h, z27.b, z26.b\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580331 // saddlb z17.h, z25.b, z24.b\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" ".inst 0x45580730 // saddlt z16.h, z25.b, z24.b\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" @@ -217,241 +219,240 @@ void sve_s8q_nhwc_avg_generic_depthfirst_impl( ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508a3f1 // sshllb z17.h, z31.b, #0x0\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - ".inst 0x4508a7f0 // sshllt z16.h, z31.b, #0x0\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" - ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" - ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" - ".inst 0x4508a3b0 // sshllb z16.h, z29.b, #0x0\n" - ".inst 0x4590416b // saddwb z11.s, z11.s, z16.h\n" - ".inst 0x4590454a // saddwt z10.s, z10.s, z16.h\n" - ".inst 0x4508a7b0 // sshllt z16.h, z29.b, #0x0\n" - ".inst 0x45904129 // saddwb z9.s, z9.s, z16.h\n" - ".inst 0x45904508 // saddwt z8.s, z8.s, z16.h\n" - ".inst 0x4508a370 // sshllb z16.h, z27.b, #0x0\n" - ".inst 0x459040e7 // saddwb z7.s, z7.s, z16.h\n" - ".inst 0x459044c6 // saddwt z6.s, z6.s, z16.h\n" - ".inst 0x4508a770 // sshllt z16.h, z27.b, #0x0\n" - ".inst 0x459040a5 // saddwb z5.s, z5.s, z16.h\n" - ".inst 0x45904484 // saddwt z4.s, z4.s, z16.h\n" - ".inst 0x4508a330 // sshllb z16.h, z25.b, #0x0\n" - ".inst 0x45904063 // saddwb z3.s, z3.s, z16.h\n" - ".inst 0x45904442 // saddwt z2.s, z2.s, z16.h\n" - ".inst 0x4508a730 // sshllt z16.h, z25.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a217 // sshllb z23.h, z16.b, #0x0\n" + ".inst 0x4508a616 // sshllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508a215 // sshllb z21.h, z16.b, #0x0\n" + ".inst 0x4508a614 // sshllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508a233 // sshllb z19.h, z17.b, #0x0\n" + ".inst 0x4508a632 // sshllt z18.h, z17.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" + ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" + ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" + ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595416b // saddwb z11.s, z11.s, z21.h\n" + ".inst 0x4595454a // saddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944129 // saddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944508 // saddwt z8.s, z8.s, z20.h\n" + ".inst 0x459340e7 // saddwb z7.s, z7.s, z19.h\n" + ".inst 0x459344c6 // saddwt z6.s, z6.s, z19.h\n" + ".inst 0x459240a5 // saddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924484 // saddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914063 // saddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914442 // saddwt z2.s, z2.s, z17.h\n" ".inst 0x45904021 // saddwb z1.s, z1.s, z16.h\n" ".inst 0x45904400 // saddwt z0.s, z0.s, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "mov z20.s, #0x7f\n" - "ld1rw { z18.s }, p4/Z, [%x[combined_rescale_value]]\n" - "ld1rw { z17.s }, p4/Z, [%x[left_shift]]\n" - "not z19.s, p4/M, z20.s\n" - "ld1rw { z16.s }, p4/Z, [%x[right_shift]]\n" - ".inst 0x4482922f // srshl z15.s, p4/M, z15.s, z17.s\n" - ".inst 0x4482922e // srshl z14.s, p4/M, z14.s, z17.s\n" - ".inst 0x4482922d // srshl z13.s, p4/M, z13.s, z17.s\n" - ".inst 0x4482922c // srshl z12.s, p4/M, z12.s, z17.s\n" - ".inst 0x4482922b // srshl z11.s, p4/M, z11.s, z17.s\n" - ".inst 0x04b275ef // sqrdmulh z15.s, z15.s, z18.s\n" - ".inst 0x04b275ce // sqrdmulh z14.s, z14.s, z18.s\n" - ".inst 0x04b275ad // sqrdmulh z13.s, z13.s, z18.s\n" - ".inst 0x04b2758c // sqrdmulh z12.s, z12.s, z18.s\n" - ".inst 0x04b2756b // sqrdmulh z11.s, z11.s, z18.s\n" - ".inst 0x4482920f // srshl z15.s, p4/M, z15.s, z16.s\n" - ".inst 0x4482920e // srshl z14.s, p4/M, z14.s, z16.s\n" - ".inst 0x4482920d // srshl z13.s, p4/M, z13.s, z16.s\n" - ".inst 0x4482920c // srshl z12.s, p4/M, z12.s, z16.s\n" - ".inst 0x4482920b // srshl z11.s, p4/M, z11.s, z16.s\n" - ".inst 0x4482922a // srshl z10.s, p4/M, z10.s, z17.s\n" - ".inst 0x44829229 // srshl z9.s, p4/M, z9.s, z17.s\n" - ".inst 0x44829228 // srshl z8.s, p4/M, z8.s, z17.s\n" - ".inst 0x44829227 // srshl z7.s, p4/M, z7.s, z17.s\n" - ".inst 0x04b2754a // sqrdmulh z10.s, z10.s, z18.s\n" - ".inst 0x04b27529 // sqrdmulh z9.s, z9.s, z18.s\n" - ".inst 0x04b27508 // sqrdmulh z8.s, z8.s, z18.s\n" - ".inst 0x04b274e7 // sqrdmulh z7.s, z7.s, z18.s\n" - ".inst 0x4482920a // srshl z10.s, p4/M, z10.s, z16.s\n" - ".inst 0x44829209 // srshl z9.s, p4/M, z9.s, z16.s\n" - ".inst 0x44829208 // srshl z8.s, p4/M, z8.s, z16.s\n" - ".inst 0x44829207 // srshl z7.s, p4/M, z7.s, z16.s\n" - ".inst 0x44829226 // srshl z6.s, p4/M, z6.s, z17.s\n" - ".inst 0x44829225 // srshl z5.s, p4/M, z5.s, z17.s\n" - ".inst 0x44829224 // srshl z4.s, p4/M, z4.s, z17.s\n" - ".inst 0x44829223 // srshl z3.s, p4/M, z3.s, z17.s\n" - ".inst 0x04b274c6 // sqrdmulh z6.s, z6.s, z18.s\n" - ".inst 0x04b274a5 // sqrdmulh z5.s, z5.s, z18.s\n" - ".inst 0x04b27484 // sqrdmulh z4.s, z4.s, z18.s\n" - ".inst 0x04b27463 // sqrdmulh z3.s, z3.s, z18.s\n" - ".inst 0x44829206 // srshl z6.s, p4/M, z6.s, z16.s\n" - ".inst 0x44829205 // srshl z5.s, p4/M, z5.s, z16.s\n" - ".inst 0x44829204 // srshl z4.s, p4/M, z4.s, z16.s\n" - ".inst 0x44829203 // srshl z3.s, p4/M, z3.s, z16.s\n" - ".inst 0x44829222 // srshl z2.s, p4/M, z2.s, z17.s\n" - ".inst 0x44829221 // srshl z1.s, p4/M, z1.s, z17.s\n" - ".inst 0x44829220 // srshl z0.s, p4/M, z0.s, z17.s\n" - "smax z15.s, p4/M, z15.s, z19.s\n" - ".inst 0x04b27442 // sqrdmulh z2.s, z2.s, z18.s\n" - ".inst 0x04b27421 // sqrdmulh z1.s, z1.s, z18.s\n" - ".inst 0x04b27400 // sqrdmulh z0.s, z0.s, z18.s\n" - "smin z15.s, p4/M, z15.s, z20.s\n" - ".inst 0x44829202 // srshl z2.s, p4/M, z2.s, z16.s\n" - ".inst 0x44829201 // srshl z1.s, p4/M, z1.s, z16.s\n" - ".inst 0x44829200 // srshl z0.s, p4/M, z0.s, z16.s\n" - "smax z14.s, p4/M, z14.s, z19.s\n" - "smax z13.s, p4/M, z13.s, z19.s\n" - "smax z12.s, p4/M, z12.s, z19.s\n" - "smax z11.s, p4/M, z11.s, z19.s\n" - "smin z14.s, p4/M, z14.s, z20.s\n" - "smin z13.s, p4/M, z13.s, z20.s\n" - "smin z12.s, p4/M, z12.s, z20.s\n" - "smin z11.s, p4/M, z11.s, z20.s\n" + "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" + ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" + ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" + ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" + ".inst 0x4482824b // srshl z11.s, p0/M, z11.s, z18.s\n" + ".inst 0x4482824a // srshl z10.s, p0/M, z10.s, z18.s\n" + ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" + ".inst 0x44828249 // srshl z9.s, p0/M, z9.s, z18.s\n" + ".inst 0x44828248 // srshl z8.s, p0/M, z8.s, z18.s\n" + ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" + ".inst 0x04b1756b // sqrdmulh z11.s, z11.s, z17.s\n" + ".inst 0x44828247 // srshl z7.s, p0/M, z7.s, z18.s\n" + ".inst 0x44828246 // srshl z6.s, p0/M, z6.s, z18.s\n" + ".inst 0x04b1754a // sqrdmulh z10.s, z10.s, z17.s\n" + ".inst 0x04b17529 // sqrdmulh z9.s, z9.s, z17.s\n" + ".inst 0x44828245 // srshl z5.s, p0/M, z5.s, z18.s\n" + ".inst 0x44828244 // srshl z4.s, p0/M, z4.s, z18.s\n" + ".inst 0x04b17508 // sqrdmulh z8.s, z8.s, z17.s\n" + ".inst 0x04b174e7 // sqrdmulh z7.s, z7.s, z17.s\n" + ".inst 0x44828243 // srshl z3.s, p0/M, z3.s, z18.s\n" + ".inst 0x44828242 // srshl z2.s, p0/M, z2.s, z18.s\n" + ".inst 0x04b174c6 // sqrdmulh z6.s, z6.s, z17.s\n" + ".inst 0x04b174a5 // sqrdmulh z5.s, z5.s, z17.s\n" + ".inst 0x44828241 // srshl z1.s, p0/M, z1.s, z18.s\n" + ".inst 0x44828240 // srshl z0.s, p0/M, z0.s, z18.s\n" + ".inst 0x04b17484 // sqrdmulh z4.s, z4.s, z17.s\n" + ".inst 0x04b17463 // sqrdmulh z3.s, z3.s, z17.s\n" + ".inst 0x04b17442 // sqrdmulh z2.s, z2.s, z17.s\n" + ".inst 0x04b17421 // sqrdmulh z1.s, z1.s, z17.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x04b17400 // sqrdmulh z0.s, z0.s, z17.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "smin z13.s, p0/M, z13.s, z18.s\n" "trn1 z17.h, z15.h, z14.h\n" - "smax z10.s, p4/M, z10.s, z19.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" + "smin z11.s, p0/M, z11.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" - "smax z9.s, p4/M, z9.s, z19.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "smin z10.s, p4/M, z10.s, z20.s\n" - "incb x26, ALL, MUL #4\n" - "smin z9.s, p4/M, z9.s, z20.s\n" - "smax z8.s, p4/M, z8.s, z19.s\n" - "smax z7.s, p4/M, z7.s, z19.s\n" - "smax z6.s, p4/M, z6.s, z19.s\n" - "trn1 z18.h, z11.h, z10.h\n" - "smin z8.s, p4/M, z8.s, z20.s\n" - "smin z7.s, p4/M, z7.s, z20.s\n" - "smin z6.s, p4/M, z6.s, z20.s\n" - "smax z5.s, p4/M, z5.s, z19.s\n" + "smin z10.s, p0/M, z10.s, z18.s\n" + "smin z9.s, p0/M, z9.s, z18.s\n" + "trn1 z17.h, z11.h, z10.h\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "smin z8.s, p0/M, z8.s, z18.s\n" + "smin z7.s, p0/M, z7.s, z18.s\n" "trn1 z16.h, z9.h, z8.h\n" - "smax z4.s, p4/M, z4.s, z19.s\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z6.s, p0/M, z6.s, z18.s\n" + "smin z5.s, p0/M, z5.s, z18.s\n" "trn1 z17.h, z7.h, z6.h\n" - "trn1 z16.b, z18.b, z16.b\n" - "st1b { z16.b }, p2, [%x[outptr], x25]\n" - "smin z5.s, p4/M, z5.s, z20.s\n" - "incb x25, ALL, MUL #4\n" - "smin z4.s, p4/M, z4.s, z20.s\n" - "smax z3.s, p4/M, z3.s, z19.s\n" - "smax z2.s, p4/M, z2.s, z19.s\n" - "smax z1.s, p4/M, z1.s, z19.s\n" - "smax z0.s, p4/M, z0.s, z19.s\n" + "st1b { z16.b }, p3, [%x[outptr], x26]\n" + "smin z4.s, p0/M, z4.s, z18.s\n" + "smin z3.s, p0/M, z3.s, z18.s\n" "trn1 z16.h, z5.h, z4.h\n" - "smin z3.s, p4/M, z3.s, z20.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p1, [%x[outptr], x24]\n" - "smin z2.s, p4/M, z2.s, z20.s\n" - "incb x24, ALL, MUL #4\n" - "smin z1.s, p4/M, z1.s, z20.s\n" - "smin z0.s, p4/M, z0.s, z20.s\n" + "smin z2.s, p0/M, z2.s, z18.s\n" + "smin z1.s, p0/M, z1.s, z18.s\n" "trn1 z17.h, z3.h, z2.h\n" + "st1b { z16.b }, p2, [%x[outptr], x25]\n" + "smin z0.s, p0/M, z0.s, z18.s\n" "trn1 z16.h, z1.h, z0.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p0, [%x[outptr], x23]\n" - "incb x23, ALL, MUL #4\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "incb x27, ALL, MUL #4\n" + "incb x26, ALL, MUL #4\n" + "incb x25, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" - "mov x19, %x[inptrs]\n" "mov z14.s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - "subs x22, x22, #0x1\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e03f7 // saddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e07f6 // saddlt z22.h, z31.b, z30.b\n" - ".inst 0x459741ef // saddwb z15.s, z15.s, z23.h\n" - ".inst 0x459745ce // saddwt z14.s, z14.s, z23.h\n" - ".inst 0x459641ad // saddwb z13.s, z13.s, z22.h\n" - ".inst 0x4596458c // saddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e03f1 // saddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e07f0 // saddlt z16.h, z31.b, z30.b\n" + ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" + ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" + ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" + ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508a3f1 // sshllb z17.h, z31.b, #0x0\n" - ".inst 0x4508a7f0 // sshllt z16.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508a211 // sshllb z17.h, z16.b, #0x0\n" + ".inst 0x4508a610 // sshllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" ".inst 0x459141ef // saddwb z15.s, z15.s, z17.h\n" ".inst 0x459145ce // saddwt z14.s, z14.s, z17.h\n" ".inst 0x459041ad // saddwb z13.s, z13.s, z16.h\n" ".inst 0x4590458c // saddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "mov z20.s, #0x7f\n" - "ld1rw { z18.s }, p4/Z, [%x[combined_rescale_value]]\n" - "ld1rw { z17.s }, p4/Z, [%x[left_shift]]\n" - "not z19.s, p4/M, z20.s\n" - "ld1rw { z16.s }, p4/Z, [%x[right_shift]]\n" - ".inst 0x4482922f // srshl z15.s, p4/M, z15.s, z17.s\n" - ".inst 0x4482922e // srshl z14.s, p4/M, z14.s, z17.s\n" - ".inst 0x4482922d // srshl z13.s, p4/M, z13.s, z17.s\n" - ".inst 0x4482922c // srshl z12.s, p4/M, z12.s, z17.s\n" - ".inst 0x04b275ef // sqrdmulh z15.s, z15.s, z18.s\n" - ".inst 0x04b275ce // sqrdmulh z14.s, z14.s, z18.s\n" - ".inst 0x04b275ad // sqrdmulh z13.s, z13.s, z18.s\n" - ".inst 0x04b2758c // sqrdmulh z12.s, z12.s, z18.s\n" - ".inst 0x4482920f // srshl z15.s, p4/M, z15.s, z16.s\n" - ".inst 0x4482920e // srshl z14.s, p4/M, z14.s, z16.s\n" - ".inst 0x4482920d // srshl z13.s, p4/M, z13.s, z16.s\n" - ".inst 0x4482920c // srshl z12.s, p4/M, z12.s, z16.s\n" - "smax z15.s, p4/M, z15.s, z19.s\n" - "smax z14.s, p4/M, z14.s, z19.s\n" - "smax z13.s, p4/M, z13.s, z19.s\n" - "smax z12.s, p4/M, z12.s, z19.s\n" - "smin z15.s, p4/M, z15.s, z20.s\n" - "smin z14.s, p4/M, z14.s, z20.s\n" - "smin z13.s, p4/M, z13.s, z20.s\n" - "smin z12.s, p4/M, z12.s, z20.s\n" + "ld1rw { z16.s }, p0/Z, [%x[left_shift]]\n" + "ld1rw { z17.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b175ef // sqrdmulh z15.s, z15.s, z17.s\n" + ".inst 0x04b175ce // sqrdmulh z14.s, z14.s, z17.s\n" + ".inst 0x04b175ad // sqrdmulh z13.s, z13.s, z17.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x04b1758c // sqrdmulh z12.s, z12.s, z17.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" + "smin z13.s, p0/M, z13.s, z18.s\n" "trn1 z17.h, z15.h, z14.h\n" + "smin z12.s, p0/M, z12.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "incb x26\n" - "whilelt p3.b, x26, %x[n_channels]\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [right_shift] "r" (&right_shift) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst.hpp index 84aa0d3d6b..fc06ed09f6 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_s8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); -struct sve_s8q_nhwc_max_generic_depthfirst +struct sve_s8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32> { - typedef int8_t operand_type; - typedef int8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const int8_t *const *const inptrs, int8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = sve_s8q_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<int8_t, int8_t, Requantize32>; sve_s8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_s8q_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp index 3717f8cb30..4fc1532d5a 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_s8q_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,8 +24,9 @@ #include "pooling.hpp" #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -41,346 +42,345 @@ void sve_s8q_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "ptrue p4.b\n" - "mov x28, #0x0\n" - "cntb x27\n" - "cntb x26, ALL, MUL #2\n" - "cntb x25, ALL, MUL #3\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" "whilelt p3.b, x28, %x[n_channels]\n" "whilelt p2.b, x27, %x[n_channels]\n" "whilelt p1.b, x26, %x[n_channels]\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x80\n" - "mov x19, %x[inptrs]\n" "mov z7.b, #0x80\n" - "lsr x24, %x[n_valid_cells], #0x2\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x80\n" "mov z5.b, #0x80\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "movprfx z18, z31\n smax z18.b, p4/M, z18.b, z30.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "smax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n smax z17.b, p4/M, z17.b, z27.b\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "smax z21.b, p4/M, z21.b, z26.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "smax z16.b, p4/M, z16.b, z25.b\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "smax z20.b, p4/M, z20.b, z24.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "smax z18.b, p4/M, z18.b, z22.b\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "smax z17.b, p4/M, z17.b, z21.b\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "smax z16.b, p4/M, z16.b, z20.b\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "smax z8.b, p4/M, z8.b, z19.b\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "smax z7.b, p4/M, z7.b, z18.b\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "smax z6.b, p4/M, z6.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "smax z5.b, p4/M, z5.b, z16.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "movprfx z18, z0\n smax z18.b, p0/M, z18.b, z31.b\n" + "smax z22.b, p0/M, z22.b, z30.b\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "movprfx z17, z29\n smax z17.b, p0/M, z17.b, z28.b\n" + "smax z21.b, p0/M, z21.b, z27.b\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "movprfx z16, z26\n smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "subs x25, x25, #0x1\n" + "smax z8.b, p0/M, z8.b, z19.b\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "smax z7.b, p0/M, z7.b, z18.b\n" + "smax z6.b, p0/M, z6.b, z17.b\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "smax z5.b, p0/M, z5.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "movprfx z18, z31\n smax z18.b, p4/M, z18.b, z30.b\n" - "smax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n smax z17.b, p4/M, z17.b, z27.b\n" - "smax z21.b, p4/M, z21.b, z26.b\n" - "smax z16.b, p4/M, z16.b, z25.b\n" - "smax z20.b, p4/M, z20.b, z24.b\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "smax z18.b, p4/M, z18.b, z22.b\n" - "smax z17.b, p4/M, z17.b, z21.b\n" - "smax z16.b, p4/M, z16.b, z20.b\n" - "smax z8.b, p4/M, z8.b, z19.b\n" - "smax z7.b, p4/M, z7.b, z18.b\n" - "smax z6.b, p4/M, z6.b, z17.b\n" - "smax z5.b, p4/M, z5.b, z16.b\n" + "movprfx z19, z4\n smax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n smax z23.b, p0/M, z23.b, z1.b\n" + "movprfx z18, z0\n smax z18.b, p0/M, z18.b, z31.b\n" + "smax z22.b, p0/M, z22.b, z30.b\n" + "movprfx z17, z29\n smax z17.b, p0/M, z17.b, z28.b\n" + "smax z21.b, p0/M, z21.b, z27.b\n" + "movprfx z16, z26\n smax z16.b, p0/M, z16.b, z25.b\n" + "smax z20.b, p0/M, z20.b, z24.b\n" + "smax z19.b, p0/M, z19.b, z23.b\n" + "smax z18.b, p0/M, z18.b, z22.b\n" + "smax z17.b, p0/M, z17.b, z21.b\n" + "smax z16.b, p0/M, z16.b, z20.b\n" + "smax z8.b, p0/M, z8.b, z19.b\n" + "smax z7.b, p0/M, z7.b, z18.b\n" + "smax z6.b, p0/M, z6.b, z17.b\n" + "smax z5.b, p0/M, z5.b, z16.b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "smax z8.b, p4/M, z8.b, z3.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "smax z7.b, p4/M, z7.b, z31.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "smax z6.b, p4/M, z6.b, z28.b\n" - "smax z5.b, p4/M, z5.b, z16.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "smax z7.b, p0/M, z7.b, z17.b\n" + "smax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "smax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "mov z4.s, #0x7f\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1rw { z3.s }, p4/Z, [x19]\n" ".inst 0x4508a111 // sshllb z17.h, z8.b, #0x0\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - ".inst 0x4508a510 // sshllt z16.h, z8.b, #0x0\n" - "ld1rw { z2.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - ".inst 0x4508a0f2 // sshllb z18.h, z7.b, #0x0\n" - "ld1rw { z1.s }, p4/Z, [x19]\n" - ".inst 0x4508a4f7 // sshllt z23.h, z7.b, #0x0\n" - ".inst 0x4508a0d6 // sshllb z22.h, z6.b, #0x0\n" - ".inst 0x4508a4d5 // sshllt z21.h, z6.b, #0x0\n" - ".inst 0x4508a0b4 // sshllb z20.h, z5.b, #0x0\n" - ".inst 0x4508a4b3 // sshllt z19.h, z5.b, #0x0\n" - ".inst 0x4510a220 // sshllb z0.s, z17.h, #0x0\n" + ".inst 0x4508a517 // sshllt z23.h, z8.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z4.s }, p0/Z, [x20]\n" + ".inst 0x4508a0f6 // sshllb z22.h, z7.b, #0x0\n" + ".inst 0x4508a4f5 // sshllt z21.h, z7.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z3.s }, p0/Z, [x20]\n" + ".inst 0x4508a0d4 // sshllb z20.h, z6.b, #0x0\n" + ".inst 0x4508a4d3 // sshllt z19.h, z6.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z2.s }, p0/Z, [x20]\n" + ".inst 0x4508a0b2 // sshllb z18.h, z5.b, #0x0\n" + ".inst 0x4508a4b0 // sshllt z16.h, z5.b, #0x0\n" + ".inst 0x4510a221 // sshllb z1.s, z17.h, #0x0\n" ".inst 0x4510a631 // sshllt z17.s, z17.h, #0x0\n" - ".inst 0x4510a21f // sshllb z31.s, z16.h, #0x0\n" - ".inst 0x4510a610 // sshllt z16.s, z16.h, #0x0\n" - ".inst 0x4510a25e // sshllb z30.s, z18.h, #0x0\n" - ".inst 0x4510a652 // sshllt z18.s, z18.h, #0x0\n" - ".inst 0x4510a2fd // sshllb z29.s, z23.h, #0x0\n" - ".inst 0x4510a6fc // sshllt z28.s, z23.h, #0x0\n" - ".inst 0x4510a2db // sshllb z27.s, z22.h, #0x0\n" - ".inst 0x4510a6da // sshllt z26.s, z22.h, #0x0\n" - ".inst 0x4510a2b9 // sshllb z25.s, z21.h, #0x0\n" - ".inst 0x4510a6b8 // sshllt z24.s, z21.h, #0x0\n" - ".inst 0x4510a297 // sshllb z23.s, z20.h, #0x0\n" - ".inst 0x4510a696 // sshllt z22.s, z20.h, #0x0\n" - ".inst 0x4510a275 // sshllb z21.s, z19.h, #0x0\n" - ".inst 0x4510a674 // sshllt z20.s, z19.h, #0x0\n" - ".inst 0x44829040 // srshl z0.s, p4/M, z0.s, z2.s\n" - ".inst 0x44829051 // srshl z17.s, p4/M, z17.s, z2.s\n" - ".inst 0x4482905f // srshl z31.s, p4/M, z31.s, z2.s\n" - ".inst 0x44829050 // srshl z16.s, p4/M, z16.s, z2.s\n" - ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" + ".inst 0x44828081 // srshl z1.s, p0/M, z1.s, z4.s\n" + ".inst 0x44828091 // srshl z17.s, p0/M, z17.s, z4.s\n" + ".inst 0x4510a2e0 // sshllb z0.s, z23.h, #0x0\n" + ".inst 0x4510a6ff // sshllt z31.s, z23.h, #0x0\n" + ".inst 0x44828080 // srshl z0.s, p0/M, z0.s, z4.s\n" + ".inst 0x4482809f // srshl z31.s, p0/M, z31.s, z4.s\n" + ".inst 0x4510a2de // sshllb z30.s, z22.h, #0x0\n" + ".inst 0x4510a6dd // sshllt z29.s, z22.h, #0x0\n" + ".inst 0x4482809e // srshl z30.s, p0/M, z30.s, z4.s\n" + ".inst 0x4482809d // srshl z29.s, p0/M, z29.s, z4.s\n" + ".inst 0x4510a2bc // sshllb z28.s, z21.h, #0x0\n" + ".inst 0x4510a6bb // sshllt z27.s, z21.h, #0x0\n" + ".inst 0x4482809c // srshl z28.s, p0/M, z28.s, z4.s\n" + ".inst 0x4482809b // srshl z27.s, p0/M, z27.s, z4.s\n" + ".inst 0x4510a29a // sshllb z26.s, z20.h, #0x0\n" + ".inst 0x4510a699 // sshllt z25.s, z20.h, #0x0\n" + ".inst 0x4482809a // srshl z26.s, p0/M, z26.s, z4.s\n" + ".inst 0x44828099 // srshl z25.s, p0/M, z25.s, z4.s\n" + ".inst 0x4510a278 // sshllb z24.s, z19.h, #0x0\n" + ".inst 0x4510a677 // sshllt z23.s, z19.h, #0x0\n" + ".inst 0x44828098 // srshl z24.s, p0/M, z24.s, z4.s\n" + ".inst 0x44828097 // srshl z23.s, p0/M, z23.s, z4.s\n" + ".inst 0x4510a256 // sshllb z22.s, z18.h, #0x0\n" + ".inst 0x4510a655 // sshllt z21.s, z18.h, #0x0\n" + ".inst 0x44828096 // srshl z22.s, p0/M, z22.s, z4.s\n" + ".inst 0x44828095 // srshl z21.s, p0/M, z21.s, z4.s\n" + ".inst 0x4510a214 // sshllb z20.s, z16.h, #0x0\n" + ".inst 0x4510a613 // sshllt z19.s, z16.h, #0x0\n" + ".inst 0x44828094 // srshl z20.s, p0/M, z20.s, z4.s\n" + ".inst 0x44828093 // srshl z19.s, p0/M, z19.s, z4.s\n" + ".inst 0x04a37421 // sqrdmulh z1.s, z1.s, z3.s\n" ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" + ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" + ".inst 0x44828051 // srshl z17.s, p0/M, z17.s, z2.s\n" + ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" - ".inst 0x04a37610 // sqrdmulh z16.s, z16.s, z3.s\n" - ".inst 0x44829020 // srshl z0.s, p4/M, z0.s, z1.s\n" - ".inst 0x44829031 // srshl z17.s, p4/M, z17.s, z1.s\n" - ".inst 0x4482903f // srshl z31.s, p4/M, z31.s, z1.s\n" - ".inst 0x44829030 // srshl z16.s, p4/M, z16.s, z1.s\n" - ".inst 0x4482905e // srshl z30.s, p4/M, z30.s, z2.s\n" - ".inst 0x44829052 // srshl z18.s, p4/M, z18.s, z2.s\n" - ".inst 0x4482905d // srshl z29.s, p4/M, z29.s, z2.s\n" - ".inst 0x4482905c // srshl z28.s, p4/M, z28.s, z2.s\n" + ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" + ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" ".inst 0x04a377de // sqrdmulh z30.s, z30.s, z3.s\n" - ".inst 0x04a37652 // sqrdmulh z18.s, z18.s, z3.s\n" ".inst 0x04a377bd // sqrdmulh z29.s, z29.s, z3.s\n" + ".inst 0x4482805e // srshl z30.s, p0/M, z30.s, z2.s\n" + ".inst 0x4482805d // srshl z29.s, p0/M, z29.s, z2.s\n" ".inst 0x04a3779c // sqrdmulh z28.s, z28.s, z3.s\n" - ".inst 0x4482903e // srshl z30.s, p4/M, z30.s, z1.s\n" - ".inst 0x44829032 // srshl z18.s, p4/M, z18.s, z1.s\n" - ".inst 0x4482903d // srshl z29.s, p4/M, z29.s, z1.s\n" - ".inst 0x4482903c // srshl z28.s, p4/M, z28.s, z1.s\n" - ".inst 0x4482905b // srshl z27.s, p4/M, z27.s, z2.s\n" - ".inst 0x4482905a // srshl z26.s, p4/M, z26.s, z2.s\n" - ".inst 0x44829059 // srshl z25.s, p4/M, z25.s, z2.s\n" - ".inst 0x44829058 // srshl z24.s, p4/M, z24.s, z2.s\n" ".inst 0x04a3777b // sqrdmulh z27.s, z27.s, z3.s\n" + ".inst 0x4482805c // srshl z28.s, p0/M, z28.s, z2.s\n" + ".inst 0x4482805b // srshl z27.s, p0/M, z27.s, z2.s\n" ".inst 0x04a3775a // sqrdmulh z26.s, z26.s, z3.s\n" ".inst 0x04a37739 // sqrdmulh z25.s, z25.s, z3.s\n" + ".inst 0x4482805a // srshl z26.s, p0/M, z26.s, z2.s\n" + ".inst 0x44828059 // srshl z25.s, p0/M, z25.s, z2.s\n" ".inst 0x04a37718 // sqrdmulh z24.s, z24.s, z3.s\n" - ".inst 0x4482903b // srshl z27.s, p4/M, z27.s, z1.s\n" - ".inst 0x4482903a // srshl z26.s, p4/M, z26.s, z1.s\n" - ".inst 0x44829039 // srshl z25.s, p4/M, z25.s, z1.s\n" - ".inst 0x44829038 // srshl z24.s, p4/M, z24.s, z1.s\n" - ".inst 0x44829057 // srshl z23.s, p4/M, z23.s, z2.s\n" - ".inst 0x44829056 // srshl z22.s, p4/M, z22.s, z2.s\n" - ".inst 0x44829055 // srshl z21.s, p4/M, z21.s, z2.s\n" - ".inst 0x44829054 // srshl z20.s, p4/M, z20.s, z2.s\n" ".inst 0x04a376f7 // sqrdmulh z23.s, z23.s, z3.s\n" + ".inst 0x44828058 // srshl z24.s, p0/M, z24.s, z2.s\n" + ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" ".inst 0x04a376d6 // sqrdmulh z22.s, z22.s, z3.s\n" ".inst 0x04a376b5 // sqrdmulh z21.s, z21.s, z3.s\n" + ".inst 0x44828056 // srshl z22.s, p0/M, z22.s, z2.s\n" + ".inst 0x44828055 // srshl z21.s, p0/M, z21.s, z2.s\n" ".inst 0x04a37694 // sqrdmulh z20.s, z20.s, z3.s\n" - ".inst 0x44829037 // srshl z23.s, p4/M, z23.s, z1.s\n" - ".inst 0x44829036 // srshl z22.s, p4/M, z22.s, z1.s\n" - ".inst 0x44829035 // srshl z21.s, p4/M, z21.s, z1.s\n" - ".inst 0x44829034 // srshl z20.s, p4/M, z20.s, z1.s\n" - "not z19.s, p4/M, z4.s\n" - "smax z0.s, p4/M, z0.s, z19.s\n" - "smax z17.s, p4/M, z17.s, z19.s\n" - "smax z31.s, p4/M, z31.s, z19.s\n" - "smax z16.s, p4/M, z16.s, z19.s\n" - "smin z0.s, p4/M, z0.s, z4.s\n" - "smin z17.s, p4/M, z17.s, z4.s\n" - "smin z31.s, p4/M, z31.s, z4.s\n" - "smin z16.s, p4/M, z16.s, z4.s\n" - "smax z30.s, p4/M, z30.s, z19.s\n" - "trn1 z17.h, z0.h, z17.h\n" - "smax z18.s, p4/M, z18.s, z19.s\n" - "trn1 z16.h, z31.h, z16.h\n" - "smin z30.s, p4/M, z30.s, z4.s\n" + ".inst 0x04a37673 // sqrdmulh z19.s, z19.s, z3.s\n" + ".inst 0x44828054 // srshl z20.s, p0/M, z20.s, z2.s\n" + ".inst 0x44828053 // srshl z19.s, p0/M, z19.s, z2.s\n" + "mov z18.s, #0x7f\n" + "not z16.s, p0/M, z18.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "smax z30.s, p0/M, z30.s, z16.s\n" + "smax z29.s, p0/M, z29.s, z16.s\n" + "smax z28.s, p0/M, z28.s, z16.s\n" + "smax z27.s, p0/M, z27.s, z16.s\n" + "smax z26.s, p0/M, z26.s, z16.s\n" + "smax z25.s, p0/M, z25.s, z16.s\n" + "smax z24.s, p0/M, z24.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z18.s\n" + "smin z17.s, p0/M, z17.s, z18.s\n" + "smin z0.s, p0/M, z0.s, z18.s\n" + "trn1 z17.h, z1.h, z17.h\n" + "smin z31.s, p0/M, z31.s, z18.s\n" + "smin z30.s, p0/M, z30.s, z18.s\n" + "trn1 z16.h, z0.h, z31.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z29.s, p0/M, z29.s, z18.s\n" + "smin z28.s, p0/M, z28.s, z18.s\n" + "trn1 z17.h, z30.h, z29.h\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "smin z27.s, p0/M, z27.s, z18.s\n" + "smin z26.s, p0/M, z26.s, z18.s\n" + "trn1 z16.h, z28.h, z27.h\n" "trn1 z16.b, z17.b, z16.b\n" + "smin z25.s, p0/M, z25.s, z18.s\n" + "smin z24.s, p0/M, z24.s, z18.s\n" + "trn1 z17.h, z26.h, z25.h\n" "st1b { z16.b }, p3, [%x[outptr], x28]\n" - "smin z18.s, p4/M, z18.s, z4.s\n" - "incb x28, ALL, MUL #4\n" - "smax z29.s, p4/M, z29.s, z19.s\n" - "smax z28.s, p4/M, z28.s, z19.s\n" - "smax z27.s, p4/M, z27.s, z19.s\n" - "smax z26.s, p4/M, z26.s, z19.s\n" - "trn1 z18.h, z30.h, z18.h\n" - "smin z29.s, p4/M, z29.s, z4.s\n" - "smin z28.s, p4/M, z28.s, z4.s\n" - "smin z27.s, p4/M, z27.s, z4.s\n" - "smin z26.s, p4/M, z26.s, z4.s\n" - "smax z25.s, p4/M, z25.s, z19.s\n" - "trn1 z16.h, z29.h, z28.h\n" - "smax z24.s, p4/M, z24.s, z19.s\n" - "trn1 z17.h, z27.h, z26.h\n" - "trn1 z16.b, z18.b, z16.b\n" + "smin z23.s, p0/M, z23.s, z18.s\n" + "smin z22.s, p0/M, z22.s, z18.s\n" + "trn1 z16.h, z24.h, z23.h\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z21.s, p0/M, z21.s, z18.s\n" + "smin z20.s, p0/M, z20.s, z18.s\n" + "trn1 z17.h, z22.h, z21.h\n" "st1b { z16.b }, p2, [%x[outptr], x27]\n" - "smin z25.s, p4/M, z25.s, z4.s\n" - "incb x27, ALL, MUL #4\n" - "smin z24.s, p4/M, z24.s, z4.s\n" - "smax z23.s, p4/M, z23.s, z19.s\n" - "smax z22.s, p4/M, z22.s, z19.s\n" - "smax z21.s, p4/M, z21.s, z19.s\n" - "smax z20.s, p4/M, z20.s, z19.s\n" - "trn1 z16.h, z25.h, z24.h\n" - "smin z23.s, p4/M, z23.s, z4.s\n" + "smin z19.s, p0/M, z19.s, z18.s\n" + "trn1 z16.h, z20.h, z19.h\n" "trn1 z16.b, z17.b, z16.b\n" "st1b { z16.b }, p1, [%x[outptr], x26]\n" - "smin z22.s, p4/M, z22.s, z4.s\n" "incb x26, ALL, MUL #4\n" - "smin z21.s, p4/M, z21.s, z4.s\n" - "smin z20.s, p4/M, z20.s, z4.s\n" - "trn1 z17.h, z23.h, z22.h\n" - "trn1 z16.h, z21.h, z20.h\n" - "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p0, [%x[outptr], x25]\n" - "incb x25, ALL, MUL #4\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "incb x9, ALL, MUL #4\n" + "incb x28, ALL, MUL #4\n" + "incb x27, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop + "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x80\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "smax z8.b, p4/M, z8.b, z19.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "subs x25, x25, #0x1\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "smax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z3\n smax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n smax z23.b, p4/M, z23.b, z0.b\n" - "smax z19.b, p4/M, z19.b, z23.b\n" - "smax z8.b, p4/M, z8.b, z19.b\n" + "movprfx z16, z4\n smax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n smax z17.b, p0/M, z17.b, z1.b\n" + "smax z16.b, p0/M, z16.b, z17.b\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "smax z8.b, p4/M, z8.b, z3.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "smax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "mov z4.s, #0x7f\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - "ld1rw { z3.s }, p4/Z, [x19]\n" ".inst 0x4508a111 // sshllb z17.h, z8.b, #0x0\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - ".inst 0x4508a510 // sshllt z16.h, z8.b, #0x0\n" - "ld1rw { z2.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - ".inst 0x4510a220 // sshllb z0.s, z17.h, #0x0\n" - "ld1rw { z1.s }, p4/Z, [x19]\n" - ".inst 0x4510a631 // sshllt z17.s, z17.h, #0x0\n" - ".inst 0x4510a21f // sshllb z31.s, z16.h, #0x0\n" - ".inst 0x4510a610 // sshllt z16.s, z16.h, #0x0\n" - ".inst 0x44829040 // srshl z0.s, p4/M, z0.s, z2.s\n" - ".inst 0x44829051 // srshl z17.s, p4/M, z17.s, z2.s\n" - ".inst 0x4482905f // srshl z31.s, p4/M, z31.s, z2.s\n" - ".inst 0x44829050 // srshl z16.s, p4/M, z16.s, z2.s\n" - ".inst 0x04a37400 // sqrdmulh z0.s, z0.s, z3.s\n" - ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" - ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" - ".inst 0x04a37610 // sqrdmulh z16.s, z16.s, z3.s\n" - ".inst 0x44829020 // srshl z0.s, p4/M, z0.s, z1.s\n" - ".inst 0x44829031 // srshl z17.s, p4/M, z17.s, z1.s\n" - ".inst 0x4482903f // srshl z31.s, p4/M, z31.s, z1.s\n" - ".inst 0x44829030 // srshl z16.s, p4/M, z16.s, z1.s\n" - "not z19.s, p4/M, z4.s\n" - "smax z0.s, p4/M, z0.s, z19.s\n" - "smax z17.s, p4/M, z17.s, z19.s\n" - "smax z31.s, p4/M, z31.s, z19.s\n" - "smax z16.s, p4/M, z16.s, z19.s\n" - "smin z0.s, p4/M, z0.s, z4.s\n" - "smin z17.s, p4/M, z17.s, z4.s\n" - "smin z31.s, p4/M, z31.s, z4.s\n" - "smin z16.s, p4/M, z16.s, z4.s\n" - "trn1 z17.h, z0.h, z17.h\n" - "trn1 z16.h, z31.h, z16.h\n" + ".inst 0x4508a512 // sshllt z18.h, z8.b, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x4510a236 // sshllb z22.s, z17.h, #0x0\n" + ".inst 0x4510a635 // sshllt z21.s, z17.h, #0x0\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x4510a254 // sshllb z20.s, z18.h, #0x0\n" + ".inst 0x4510a653 // sshllt z19.s, z18.h, #0x0\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" + ".inst 0x04b176d6 // sqrdmulh z22.s, z22.s, z17.s\n" + ".inst 0x04b176b5 // sqrdmulh z21.s, z21.s, z17.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x04b17694 // sqrdmulh z20.s, z20.s, z17.s\n" + ".inst 0x04b17673 // sqrdmulh z19.s, z19.s, z17.s\n" + "mov z18.s, #0x7f\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" + "not z16.s, p0/M, z18.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smin z22.s, p0/M, z22.s, z18.s\n" + "smin z21.s, p0/M, z21.s, z18.s\n" + "smin z20.s, p0/M, z20.s, z18.s\n" + "trn1 z17.h, z22.h, z21.h\n" + "smin z19.s, p0/M, z19.s, z18.s\n" + "trn1 z16.h, z20.h, z19.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x28]\n" - "incb x28\n" - "whilelt p3.b, x28, %x[n_channels]\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [outptr] "r" (outptr), [quant_params] "r" (&qp) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst.hpp index 299e55c9be..714530bc43 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_u8_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); -struct sve_u8_nhwc_avg_generic_depthfirst +struct sve_u8_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = sve_u8_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; sve_u8_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_u8_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp index 51a69a42be..f3f4950a1f 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,11 +23,12 @@ */ #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -84,30 +85,31 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } __asm__ __volatile__( - "ptrue p4.b\n" - "mov x26, #0x0\n" - "cntb x25\n" - "cntb x24, ALL, MUL #2\n" - "cntb x23, ALL, MUL #3\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" "whilelt p3.b, x26, %x[n_channels]\n" "whilelt p2.b, x25, %x[n_channels]\n" "whilelt p1.b, x24, %x[n_channels]\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" - "mov x19, %x[inptrs]\n" "mov z14.s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" "mov z11.s, #0x0\n" @@ -122,43 +124,43 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( "mov z2.s, #0x0\n" "mov z1.s, #0x0\n" "mov z0.s, #0x0\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" - "subs x22, x22, #0x1\n" ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" @@ -198,219 +200,218 @@ void sve_u8_nhwc_avg_generic_depthfirst_impl( ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508abf1 // ushllb z17.h, z31.b, #0x0\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - ".inst 0x4508aff0 // ushllt z16.h, z31.b, #0x0\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" - ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" - ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" - ".inst 0x4508abb0 // ushllb z16.h, z29.b, #0x0\n" - ".inst 0x4590496b // uaddwb z11.s, z11.s, z16.h\n" - ".inst 0x45904d4a // uaddwt z10.s, z10.s, z16.h\n" - ".inst 0x4508afb0 // ushllt z16.h, z29.b, #0x0\n" - ".inst 0x45904929 // uaddwb z9.s, z9.s, z16.h\n" - ".inst 0x45904d08 // uaddwt z8.s, z8.s, z16.h\n" - ".inst 0x4508ab70 // ushllb z16.h, z27.b, #0x0\n" - ".inst 0x459048e7 // uaddwb z7.s, z7.s, z16.h\n" - ".inst 0x45904cc6 // uaddwt z6.s, z6.s, z16.h\n" - ".inst 0x4508af70 // ushllt z16.h, z27.b, #0x0\n" - ".inst 0x459048a5 // uaddwb z5.s, z5.s, z16.h\n" - ".inst 0x45904c84 // uaddwt z4.s, z4.s, z16.h\n" - ".inst 0x4508ab30 // ushllb z16.h, z25.b, #0x0\n" - ".inst 0x45904863 // uaddwb z3.s, z3.s, z16.h\n" - ".inst 0x45904c42 // uaddwt z2.s, z2.s, z16.h\n" - ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa33 // ushllb z19.h, z17.b, #0x0\n" + ".inst 0x4508ae32 // ushllt z18.h, z17.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "mov z20.s, #0x0\n" - "ld1rw { z17.s }, p4/Z, [%x[rescale_ptr]]\n" - "mov z19.s, #0xff\n" - "ld1rw { z16.s }, p4/Z, [%x[shift_ptr]]\n" + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" ".inst 0x04b1756b // sqdmulh z11.s, z11.s, z17.s\n" ".inst 0x04b1754a // sqdmulh z10.s, z10.s, z17.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" ".inst 0x04b17529 // sqdmulh z9.s, z9.s, z17.s\n" ".inst 0x04b17508 // sqdmulh z8.s, z8.s, z17.s\n" + ".inst 0x4482820b // srshl z11.s, p0/M, z11.s, z16.s\n" + ".inst 0x4482820a // srshl z10.s, p0/M, z10.s, z16.s\n" ".inst 0x04b174e7 // sqdmulh z7.s, z7.s, z17.s\n" ".inst 0x04b174c6 // sqdmulh z6.s, z6.s, z17.s\n" + ".inst 0x44828209 // srshl z9.s, p0/M, z9.s, z16.s\n" + ".inst 0x44828208 // srshl z8.s, p0/M, z8.s, z16.s\n" ".inst 0x04b174a5 // sqdmulh z5.s, z5.s, z17.s\n" ".inst 0x04b17484 // sqdmulh z4.s, z4.s, z17.s\n" + ".inst 0x44828207 // srshl z7.s, p0/M, z7.s, z16.s\n" + ".inst 0x44828206 // srshl z6.s, p0/M, z6.s, z16.s\n" ".inst 0x04b17463 // sqdmulh z3.s, z3.s, z17.s\n" ".inst 0x04b17442 // sqdmulh z2.s, z2.s, z17.s\n" + ".inst 0x44828205 // srshl z5.s, p0/M, z5.s, z16.s\n" + ".inst 0x44828204 // srshl z4.s, p0/M, z4.s, z16.s\n" ".inst 0x04b17421 // sqdmulh z1.s, z1.s, z17.s\n" ".inst 0x04b17400 // sqdmulh z0.s, z0.s, z17.s\n" - ".inst 0x4482920f // srshl z15.s, p4/M, z15.s, z16.s\n" - ".inst 0x4482920e // srshl z14.s, p4/M, z14.s, z16.s\n" - ".inst 0x4482920d // srshl z13.s, p4/M, z13.s, z16.s\n" - ".inst 0x4482920c // srshl z12.s, p4/M, z12.s, z16.s\n" - ".inst 0x4482920b // srshl z11.s, p4/M, z11.s, z16.s\n" - ".inst 0x4482920a // srshl z10.s, p4/M, z10.s, z16.s\n" - ".inst 0x44829209 // srshl z9.s, p4/M, z9.s, z16.s\n" - ".inst 0x44829208 // srshl z8.s, p4/M, z8.s, z16.s\n" - ".inst 0x44829207 // srshl z7.s, p4/M, z7.s, z16.s\n" - ".inst 0x44829206 // srshl z6.s, p4/M, z6.s, z16.s\n" - ".inst 0x44829205 // srshl z5.s, p4/M, z5.s, z16.s\n" - ".inst 0x44829204 // srshl z4.s, p4/M, z4.s, z16.s\n" - ".inst 0x44829203 // srshl z3.s, p4/M, z3.s, z16.s\n" - ".inst 0x44829202 // srshl z2.s, p4/M, z2.s, z16.s\n" - ".inst 0x44829201 // srshl z1.s, p4/M, z1.s, z16.s\n" - ".inst 0x44829200 // srshl z0.s, p4/M, z0.s, z16.s\n" - "smax z15.s, p4/M, z15.s, z20.s\n" - "smax z14.s, p4/M, z14.s, z20.s\n" - "smax z13.s, p4/M, z13.s, z20.s\n" - "smax z12.s, p4/M, z12.s, z20.s\n" - "smin z15.s, p4/M, z15.s, z19.s\n" - "smin z14.s, p4/M, z14.s, z19.s\n" - "smin z13.s, p4/M, z13.s, z19.s\n" - "smin z12.s, p4/M, z12.s, z19.s\n" - "smax z11.s, p4/M, z11.s, z20.s\n" + ".inst 0x44828203 // srshl z3.s, p0/M, z3.s, z16.s\n" + ".inst 0x44828202 // srshl z2.s, p0/M, z2.s, z16.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + "mov z16.s, #0x0\n" + "mov z18.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" "trn1 z17.h, z15.h, z14.h\n" - "smax z10.s, p4/M, z10.s, z20.s\n" + "smin z13.s, p0/M, z13.s, z18.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" - "smin z11.s, p4/M, z11.s, z19.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "smin z10.s, p4/M, z10.s, z19.s\n" - "incb x26, ALL, MUL #4\n" - "smax z9.s, p4/M, z9.s, z20.s\n" - "smax z8.s, p4/M, z8.s, z20.s\n" - "smax z7.s, p4/M, z7.s, z20.s\n" - "smax z6.s, p4/M, z6.s, z20.s\n" - "trn1 z18.h, z11.h, z10.h\n" - "smin z9.s, p4/M, z9.s, z19.s\n" - "smin z8.s, p4/M, z8.s, z19.s\n" - "smin z7.s, p4/M, z7.s, z19.s\n" - "smin z6.s, p4/M, z6.s, z19.s\n" - "smax z5.s, p4/M, z5.s, z20.s\n" + "smin z11.s, p0/M, z11.s, z18.s\n" + "smin z10.s, p0/M, z10.s, z18.s\n" + "trn1 z17.h, z11.h, z10.h\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "smin z9.s, p0/M, z9.s, z18.s\n" + "smin z8.s, p0/M, z8.s, z18.s\n" "trn1 z16.h, z9.h, z8.h\n" - "smax z4.s, p4/M, z4.s, z20.s\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z7.s, p0/M, z7.s, z18.s\n" + "smin z6.s, p0/M, z6.s, z18.s\n" "trn1 z17.h, z7.h, z6.h\n" - "trn1 z16.b, z18.b, z16.b\n" - "st1b { z16.b }, p2, [%x[outptr], x25]\n" - "smin z5.s, p4/M, z5.s, z19.s\n" - "incb x25, ALL, MUL #4\n" - "smin z4.s, p4/M, z4.s, z19.s\n" - "smax z3.s, p4/M, z3.s, z20.s\n" - "smax z2.s, p4/M, z2.s, z20.s\n" - "smax z1.s, p4/M, z1.s, z20.s\n" - "smax z0.s, p4/M, z0.s, z20.s\n" + "st1b { z16.b }, p3, [%x[outptr], x26]\n" + "smin z5.s, p0/M, z5.s, z18.s\n" + "smin z4.s, p0/M, z4.s, z18.s\n" "trn1 z16.h, z5.h, z4.h\n" - "smin z3.s, p4/M, z3.s, z19.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p1, [%x[outptr], x24]\n" - "smin z2.s, p4/M, z2.s, z19.s\n" - "incb x24, ALL, MUL #4\n" - "smin z1.s, p4/M, z1.s, z19.s\n" - "smin z0.s, p4/M, z0.s, z19.s\n" + "smin z3.s, p0/M, z3.s, z18.s\n" + "smin z2.s, p0/M, z2.s, z18.s\n" "trn1 z17.h, z3.h, z2.h\n" + "st1b { z16.b }, p2, [%x[outptr], x25]\n" + "smin z1.s, p0/M, z1.s, z18.s\n" + "smin z0.s, p0/M, z0.s, z18.s\n" "trn1 z16.h, z1.h, z0.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p0, [%x[outptr], x23]\n" - "incb x23, ALL, MUL #4\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "incb x27, ALL, MUL #4\n" + "incb x26, ALL, MUL #4\n" + "incb x25, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z15.s, #0x0\n" - "mov x19, %x[inptrs]\n" "mov z14.s, #0x0\n" - "lsr x22, %x[n_valid_cells], #0x1\n" + "mov x22, %x[inptrs]\n" "mov z13.s, #0x0\n" "mov z12.s, #0x0\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - "subs x22, x22, #0x1\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508abf1 // ushllb z17.h, z31.b, #0x0\n" - ".inst 0x4508aff0 // ushllt z16.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "mov z20.s, #0x0\n" - "ld1rw { z17.s }, p4/Z, [%x[rescale_ptr]]\n" - "mov z19.s, #0xff\n" - "ld1rw { z16.s }, p4/Z, [%x[shift_ptr]]\n" + "ld1rw { z17.s }, p0/Z, [%x[rescale_ptr]]\n" + "ld1rw { z16.s }, p0/Z, [%x[shift_ptr]]\n" ".inst 0x04b175ef // sqdmulh z15.s, z15.s, z17.s\n" ".inst 0x04b175ce // sqdmulh z14.s, z14.s, z17.s\n" ".inst 0x04b175ad // sqdmulh z13.s, z13.s, z17.s\n" ".inst 0x04b1758c // sqdmulh z12.s, z12.s, z17.s\n" - ".inst 0x4482920f // srshl z15.s, p4/M, z15.s, z16.s\n" - ".inst 0x4482920e // srshl z14.s, p4/M, z14.s, z16.s\n" - ".inst 0x4482920d // srshl z13.s, p4/M, z13.s, z16.s\n" - ".inst 0x4482920c // srshl z12.s, p4/M, z12.s, z16.s\n" - "smax z15.s, p4/M, z15.s, z20.s\n" - "smax z14.s, p4/M, z14.s, z20.s\n" - "smax z13.s, p4/M, z13.s, z20.s\n" - "smax z12.s, p4/M, z12.s, z20.s\n" - "smin z15.s, p4/M, z15.s, z19.s\n" - "smin z14.s, p4/M, z14.s, z19.s\n" - "smin z13.s, p4/M, z13.s, z19.s\n" - "smin z12.s, p4/M, z12.s, z19.s\n" + ".inst 0x4482820f // srshl z15.s, p0/M, z15.s, z16.s\n" + ".inst 0x4482820e // srshl z14.s, p0/M, z14.s, z16.s\n" + ".inst 0x4482820d // srshl z13.s, p0/M, z13.s, z16.s\n" + ".inst 0x4482820c // srshl z12.s, p0/M, z12.s, z16.s\n" + "mov z17.s, #0x0\n" + "mov z16.s, #0xff\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" "trn1 z16.h, z13.h, z12.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "incb x26\n" - "whilelt p3.b, x26, %x[n_channels]\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr), [rescale_ptr] "r" (&rescale_value), [shift_ptr] "r" (&shift_value) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp index 06df1515ad..eae83b99fe 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,37 +24,28 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(unsigned int, const uint8_t *const *const, uint8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); -struct sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst +struct sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst : public DepthfirstStrategy<uint8_t, uint8_t> { - typedef uint8_t operand_type; - typedef uint8_t return_type; + using Parent = DepthfirstStrategy<uint8_t, uint8_t>; - typedef void (*kern_type)(unsigned int, const uint8_t *const *const, uint8_t *const *const, bool, unsigned int, unsigned int, unsigned int, unsigned int); + const static auto pooling_type = PoolingType::MAX; + const static auto pool_rows = 2u, pool_cols = 2u; + const static auto stride_rows = 1u, stride_cols = 1u; - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } + sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) + : Parent(pool_rows, pool_cols, stride_rows, stride_cols, 2, 2) {} - constexpr static unsigned int pool_rows(void) { return 2; } - constexpr static unsigned int pool_cols(void) { return 2; } - - constexpr static unsigned int stride_rows(void) { return 1; } - constexpr static unsigned int stride_cols(void) { return 1; } - - constexpr static unsigned int out_rows(void) { return 2; } - constexpr static unsigned int out_cols(void) { return 2; } - - kern_type kernel = sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; - - sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst(const CPUInfo *) {} + Parent::KernelType get_kernel(void) const { return sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index e921f345d5..8612555bfb 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,7 +26,7 @@ #include <cstddef> #include <cstdint> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -63,84 +63,84 @@ void sve_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl( pad_left, pad_top, pad_right, pad_bottom); __asm__ __volatile__( - "ldr x14, [%x[args], %[offsetof_n_channels]]\n" + "ldr x15, [%x[args], %[offsetof_n_channels]]\n" + "ldr x21, [%x[args], %[offsetof_outptrs]]\n" + "mov x14, #0x0\n" + "whilelt p0.b, x14, x15\n" + "ldr x20, [%x[args], %[offsetof_inptrs]]\n" + "ldp x13, x12, [x21, #0x0]\n" "ptrue p2.b\n" - "ldr x20, [%x[args], %[offsetof_outptrs]]\n" - "mov x13, #0x0\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" - "mov x12, #0x0\n" - "ldp x11, x10, [x20, #0x0]\n" - "whilelt p1.b, x13, x14\n" - "ldp x9, x28, [x20, #0x10]\n" - "ldp x27, x26, [x19, #0x0]\n" - "ldp x25, x24, [x19, #0x10]\n" - "ldp x23, x22, [x19, #0x20]\n" - "ldp x21, x20, [x19, #0x30]\n" - "ldr x19, [x19, #0x40]\n" - "ld1b { z31.b }, p1/Z, [x26, x13]\n" - "ld1b { z30.b }, p1/Z, [x23, x13]\n" - "ld1b { z29.b }, p1/Z, [x20, x13]\n" - "ld1b { z28.b }, p1/Z, [x24, x13]\n" - "ld1b { z27.b }, p1/Z, [x27, x13]\n" - "ld1b { z26.b }, p1/Z, [x22, x13]\n" - "ld1b { z25.b }, p1/Z, [x25, x13]\n" - "ld1b { z24.b }, p1/Z, [x21, x13]\n" - "ld1b { z23.b }, p1/Z, [x19, x13]\n" - "incw x13\n" - "whilelt p1.b, x13, x14\n" + "mov x11, #0x0\n" + "ldp x10, x9, [x21, #0x10]\n" + "ldp x28, x27, [x20, #0x0]\n" + "ldp x26, x25, [x20, #0x10]\n" + "ldp x24, x23, [x20, #0x20]\n" + "ldp x22, x21, [x20, #0x30]\n" + "ldr x20, [x20, #0x40]\n" + "ld1b { z31.b }, p0/Z, [x27, x14]\n" + "ld1b { z30.b }, p0/Z, [x24, x14]\n" + "ld1b { z29.b }, p0/Z, [x21, x14]\n" + "ld1b { z28.b }, p0/Z, [x25, x14]\n" + "ld1b { z27.b }, p0/Z, [x28, x14]\n" + "ld1b { z26.b }, p0/Z, [x26, x14]\n" + "ld1b { z25.b }, p0/Z, [x23, x14]\n" + "ld1b { z24.b }, p0/Z, [x22, x14]\n" + "ld1b { z23.b }, p0/Z, [x20, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x15\n" "b.none 2f\n" "1:" // Vector: Loop "movprfx z22, z31\n umax z22.b, p2/M, z22.b, z30.b\n" - "ld1b { z31.b }, p1/Z, [x26, x13]\n" - "whilelt p0.b, x12, x14\n" "movprfx z21, z30\n umax z21.b, p2/M, z21.b, z29.b\n" - "ld1b { z30.b }, p1/Z, [x23, x13]\n" - "movprfx z18, z28\n umax z18.b, p2/M, z18.b, z27.b\n" - "ld1b { z29.b }, p1/Z, [x20, x13]\n" - "movprfx z17, z26\n umax z17.b, p2/M, z17.b, z25.b\n" - "ld1b { z27.b }, p1/Z, [x27, x13]\n" - "movprfx z16, z24\n umax z16.b, p2/M, z16.b, z28.b\n" - "ld1b { z28.b }, p1/Z, [x24, x13]\n" - "movprfx z20, z26\n umax z20.b, p2/M, z20.b, z23.b\n" - "ld1b { z26.b }, p1/Z, [x22, x13]\n" - "movprfx z19, z22\n umax z19.b, p2/M, z19.b, z18.b\n" - "ld1b { z25.b }, p1/Z, [x25, x13]\n" - "movprfx z18, z22\n umax z18.b, p2/M, z18.b, z17.b\n" - "ld1b { z24.b }, p1/Z, [x21, x13]\n" - "movprfx z17, z21\n umax z17.b, p2/M, z17.b, z16.b\n" - "ld1b { z23.b }, p1/Z, [x19, x13]\n" - "incw x13\n" - "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z20.b\n" - "st1b { z19.b }, p0, [x11, x12]\n" - "whilelt p1.b, x13, x14\n" - "st1b { z18.b }, p0, [x10, x12]\n" - "st1b { z17.b }, p0, [x9, x12]\n" - "st1b { z16.b }, p0, [x28, x12]\n" - "incw x12\n" + "ld1b { z31.b }, p1/Z, [x27, x14]\n" + "ld1b { z30.b }, p1/Z, [x24, x14]\n" + "movprfx z20, z28\n umax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n umax z19.b, p2/M, z19.b, z25.b\n" + "ld1b { z29.b }, p1/Z, [x21, x14]\n" + "ld1b { z27.b }, p1/Z, [x28, x14]\n" + "movprfx z17, z28\n umax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z23.b\n" + "ld1b { z28.b }, p1/Z, [x25, x14]\n" + "ld1b { z26.b }, p1/Z, [x26, x14]\n" + "ld1b { z25.b }, p1/Z, [x23, x14]\n" + "ld1b { z24.b }, p1/Z, [x22, x14]\n" + "whilelt p0.b, x11, x15\n" + "movprfx z16, z22\n umax z16.b, p2/M, z16.b, z20.b\n" + "ld1b { z23.b }, p1/Z, [x20, x14]\n" + "incw x14\n" + "whilelt p1.b, x14, x15\n" + "st1b { z16.b }, p0, [x13, x11]\n" + "movprfx z16, z19\n umax z16.b, p2/M, z16.b, z22.b\n" + "umax z17.b, p2/M, z17.b, z21.b\n" + "st1b { z16.b }, p0, [x12, x11]\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z18.b\n" + "st1b { z17.b }, p0, [x10, x11]\n" + "st1b { z16.b }, p0, [x9, x11]\n" + "incw x11\n" "b.any 1b\n" "2:" // Vector: Tail "movprfx z22, z31\n umax z22.b, p2/M, z22.b, z30.b\n" - "whilelt p0.b, x12, x14\n" "movprfx z21, z30\n umax z21.b, p2/M, z21.b, z29.b\n" - "movprfx z18, z28\n umax z18.b, p2/M, z18.b, z27.b\n" - "movprfx z17, z26\n umax z17.b, p2/M, z17.b, z25.b\n" - "movprfx z16, z24\n umax z16.b, p2/M, z16.b, z28.b\n" - "movprfx z20, z26\n umax z20.b, p2/M, z20.b, z23.b\n" - "movprfx z19, z22\n umax z19.b, p2/M, z19.b, z18.b\n" - "st1b { z19.b }, p0, [x11, x12]\n" - "movprfx z18, z22\n umax z18.b, p2/M, z18.b, z17.b\n" - "movprfx z17, z21\n umax z17.b, p2/M, z17.b, z16.b\n" - "st1b { z18.b }, p0, [x10, x12]\n" - "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z20.b\n" - "st1b { z17.b }, p0, [x9, x12]\n" - "st1b { z16.b }, p0, [x28, x12]\n" + "movprfx z20, z28\n umax z20.b, p2/M, z20.b, z27.b\n" + "movprfx z19, z26\n umax z19.b, p2/M, z19.b, z25.b\n" + "movprfx z17, z28\n umax z17.b, p2/M, z17.b, z24.b\n" + "movprfx z18, z25\n umax z18.b, p2/M, z18.b, z23.b\n" + "whilelt p0.b, x11, x15\n" + "movprfx z16, z22\n umax z16.b, p2/M, z16.b, z20.b\n" + "st1b { z16.b }, p0, [x13, x11]\n" + "movprfx z16, z19\n umax z16.b, p2/M, z16.b, z22.b\n" + "umax z17.b, p2/M, z17.b, z21.b\n" + "st1b { z16.b }, p0, [x12, x11]\n" + "movprfx z16, z21\n umax z16.b, p2/M, z16.b, z18.b\n" + "st1b { z17.b }, p0, [x10, x11]\n" + "st1b { z16.b }, p0, [x9, x11]\n" : : [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)) - : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst.hpp index 59cd4b9c78..9f3c3a435d 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_u8_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); -struct sve_u8_nhwc_max_generic_depthfirst +struct sve_u8_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = sve_u8_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t>; sve_u8_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_u8_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp index 164847480b..be0eb398ae 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,8 +23,9 @@ */ #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -39,185 +40,184 @@ void sve_u8_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "ptrue p4.b\n" - "mov x28, #0x0\n" - "cntb x27\n" - "cntb x26, ALL, MUL #2\n" - "cntb x25, ALL, MUL #3\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" "whilelt p3.b, x28, %x[n_channels]\n" "whilelt p2.b, x27, %x[n_channels]\n" "whilelt p1.b, x26, %x[n_channels]\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.b, #0x0\n" "mov z7.b, #0x0\n" - "mov x19, %x[inptrs]\n" + "mov x24, %x[inptrs]\n" "mov z6.b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" "mov z5.b, #0x0\n" - "mov z4.b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "movprfx z18, z31\n umax z18.b, p4/M, z18.b, z30.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "umax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n umax z17.b, p4/M, z17.b, z27.b\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "umax z21.b, p4/M, z21.b, z26.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "umax z16.b, p4/M, z16.b, z25.b\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "umax z20.b, p4/M, z20.b, z24.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "umax z18.b, p4/M, z18.b, z22.b\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "umax z17.b, p4/M, z17.b, z21.b\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "umax z16.b, p4/M, z16.b, z20.b\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "umax z7.b, p4/M, z7.b, z19.b\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "umax z6.b, p4/M, z6.b, z18.b\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "umax z5.b, p4/M, z5.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "umax z4.b, p4/M, z4.b, z16.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "movprfx z18, z0\n umax z18.b, p0/M, z18.b, z31.b\n" + "umax z22.b, p0/M, z22.b, z30.b\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "movprfx z17, z29\n umax z17.b, p0/M, z17.b, z28.b\n" + "umax z21.b, p0/M, z21.b, z27.b\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "movprfx z16, z26\n umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "subs x25, x25, #0x1\n" + "umax z8.b, p0/M, z8.b, z19.b\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "umax z7.b, p0/M, z7.b, z18.b\n" + "umax z6.b, p0/M, z6.b, z17.b\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "movprfx z18, z31\n umax z18.b, p4/M, z18.b, z30.b\n" - "umax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n umax z17.b, p4/M, z17.b, z27.b\n" - "umax z21.b, p4/M, z21.b, z26.b\n" - "umax z16.b, p4/M, z16.b, z25.b\n" - "umax z20.b, p4/M, z20.b, z24.b\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "umax z18.b, p4/M, z18.b, z22.b\n" - "umax z17.b, p4/M, z17.b, z21.b\n" - "umax z16.b, p4/M, z16.b, z20.b\n" - "umax z7.b, p4/M, z7.b, z19.b\n" - "umax z6.b, p4/M, z6.b, z18.b\n" - "umax z5.b, p4/M, z5.b, z17.b\n" - "umax z4.b, p4/M, z4.b, z16.b\n" + "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" + "movprfx z18, z0\n umax z18.b, p0/M, z18.b, z31.b\n" + "umax z22.b, p0/M, z22.b, z30.b\n" + "movprfx z17, z29\n umax z17.b, p0/M, z17.b, z28.b\n" + "umax z21.b, p0/M, z21.b, z27.b\n" + "movprfx z16, z26\n umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "umax z8.b, p0/M, z8.b, z19.b\n" + "umax z7.b, p0/M, z7.b, z18.b\n" + "umax z6.b, p0/M, z6.b, z17.b\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "umax z7.b, p4/M, z7.b, z3.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "umax z6.b, p4/M, z6.b, z31.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "umax z5.b, p4/M, z5.b, z28.b\n" - "umax z4.b, p4/M, z4.b, z16.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z7.b, p0/M, z7.b, z17.b\n" + "umax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End + "st1b { z8.b }, p4, [%x[outptr], x9]\n" + "incb x9, ALL, MUL #4\n" "st1b { z7.b }, p3, [%x[outptr], x28]\n" "incb x28, ALL, MUL #4\n" "st1b { z6.b }, p2, [%x[outptr], x27]\n" "incb x27, ALL, MUL #4\n" "st1b { z5.b }, p1, [%x[outptr], x26]\n" "incb x26, ALL, MUL #4\n" - "st1b { z4.b }, p0, [%x[outptr], x25]\n" - "incb x25, ALL, MUL #4\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "whilelt p1.b, x26, %x[n_channels]\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z7.b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "umax z7.b, p4/M, z7.b, z19.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "subs x25, x25, #0x1\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "umax z7.b, p4/M, z7.b, z19.b\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "umax z7.b, p4/M, z7.b, z3.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "st1b { z7.b }, p3, [%x[outptr], x28]\n" - "incb x28\n" - "whilelt p3.b, x28, %x[n_channels]\n" + "st1b { z8.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [outptr] "r" (outptr) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst.hpp index f6fc1a58c1..f9d25a1b45 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_u8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); -struct sve_u8q_nhwc_avg_generic_depthfirst +struct sve_u8q_nhwc_avg_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t window_cells, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::AVERAGE; } - - - kern_type kernel = sve_u8q_nhwc_avg_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; sve_u8q_nhwc_avg_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_u8q_nhwc_avg_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp index 373848ad2b..e8339a2cd9 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,11 +24,12 @@ #include "pooling.hpp" #include <cstdint> +#include <cstddef> #include <cstring> #include <cmath> -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -86,12 +87,13 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( f_rescale_value *= 2.0f; } - rescale_value = static_cast<int32_t>(round(f_rescale_value * static_cast<float>(1ll << 31))); - if (static_cast<int64_t>(rescale_value) == (1ll << 31)) + int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31)); + if (long_rescale_value == (1ll << 31)) { shift_value++; - rescale_value >>= 1; + long_rescale_value >>= 1; } + rescale_value = static_cast<int32_t>(long_rescale_value); } @@ -117,24 +119,24 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( ); __asm__ __volatile__( - "ptrue p4.b\n" - "mov x26, #0x0\n" - "cntb x25\n" - "cntb x24, ALL, MUL #2\n" - "cntb x23, ALL, MUL #3\n" + "mov x27, #0x0\n" + "cntb x26\n" + "cntb x25, ALL, MUL #2\n" + "cntb x24, ALL, MUL #3\n" + "whilelt p4.b, x27, %x[n_channels]\n" "whilelt p3.b, x26, %x[n_channels]\n" "whilelt p2.b, x25, %x[n_channels]\n" "whilelt p1.b, x24, %x[n_channels]\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels - "ld1rw { z15.s }, p4/Z, [%x[accumulator_init]]\n" + "ld1rw { z15.s }, p0/Z, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z14.d, z15.d\n" - "mov x19, %x[inptrs]\n" "mov z13.d, z15.d\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "mov z12.d, z15.d\n" "mov z11.d, z15.d\n" + "mov x22, %x[inptrs]\n" "mov z10.d, z15.d\n" "mov z9.d, z15.d\n" "mov z8.d, z15.d\n" @@ -146,43 +148,43 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( "mov z2.d, z15.d\n" "mov z1.d, z15.d\n" "mov z0.d, z15.d\n" - "cbz x22, 4f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "cbz x23, 4f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" "beq 3f\n" "2:" // 4-vectors of channels: 2 inputs loop ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" ".inst 0x455c0bb5 // uaddlb z21.h, z29.b, z28.b\n" - "subs x22, x22, #0x1\n" ".inst 0x455c0fb4 // uaddlt z20.h, z29.b, z28.b\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" ".inst 0x455a0b73 // uaddlb z19.h, z27.b, z26.b\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" ".inst 0x455a0f72 // uaddlt z18.h, z27.b, z26.b\n" - "ld1b { z28.b }, p2/Z, [x20, x25]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" + "ld1b { z29.b }, p3/Z, [x21, x26]\n" ".inst 0x45580b31 // uaddlb z17.h, z25.b, z24.b\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" ".inst 0x45580f30 // uaddlt z16.h, z25.b, z24.b\n" - "ld1b { z26.b }, p1/Z, [x20, x24]\n" + "ld1b { z28.b }, p3/Z, [x20, x26]\n" + "ld1b { z27.b }, p2/Z, [x21, x25]\n" ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z24.b }, p0/Z, [x20, x23]\n" + "ld1b { z26.b }, p2/Z, [x20, x25]\n" + "ld1b { z25.b }, p1/Z, [x21, x24]\n" ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + "ld1b { z24.b }, p1/Z, [x20, x24]\n" ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" @@ -222,265 +224,264 @@ void sve_u8q_nhwc_avg_generic_depthfirst_impl( ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508abf1 // ushllb z17.h, z31.b, #0x0\n" - "ld1b { z29.b }, p2/Z, [x21, x25]\n" - ".inst 0x4508aff0 // ushllt z16.h, z31.b, #0x0\n" - "ld1b { z27.b }, p1/Z, [x21, x24]\n" - ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" - "ld1b { z25.b }, p0/Z, [x21, x23]\n" - ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" - ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" - ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" - ".inst 0x4508abb0 // ushllb z16.h, z29.b, #0x0\n" - ".inst 0x4590496b // uaddwb z11.s, z11.s, z16.h\n" - ".inst 0x45904d4a // uaddwt z10.s, z10.s, z16.h\n" - ".inst 0x4508afb0 // ushllt z16.h, z29.b, #0x0\n" - ".inst 0x45904929 // uaddwb z9.s, z9.s, z16.h\n" - ".inst 0x45904d08 // uaddwt z8.s, z8.s, z16.h\n" - ".inst 0x4508ab70 // ushllb z16.h, z27.b, #0x0\n" - ".inst 0x459048e7 // uaddwb z7.s, z7.s, z16.h\n" - ".inst 0x45904cc6 // uaddwt z6.s, z6.s, z16.h\n" - ".inst 0x4508af70 // ushllt z16.h, z27.b, #0x0\n" - ".inst 0x459048a5 // uaddwb z5.s, z5.s, z16.h\n" - ".inst 0x45904c84 // uaddwt z4.s, z4.s, z16.h\n" - ".inst 0x4508ab30 // ushllb z16.h, z25.b, #0x0\n" - ".inst 0x45904863 // uaddwb z3.s, z3.s, z16.h\n" - ".inst 0x45904c42 // uaddwt z2.s, z2.s, z16.h\n" - ".inst 0x4508af30 // ushllt z16.h, z25.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa17 // ushllb z23.h, z16.b, #0x0\n" + ".inst 0x4508ae16 // ushllt z22.h, z16.b, #0x0\n" + "ld1b { z16.b }, p3/Z, [x20, x26]\n" + "ld1b { z17.b }, p2/Z, [x20, x25]\n" + ".inst 0x4508aa15 // ushllb z21.h, z16.b, #0x0\n" + ".inst 0x4508ae14 // ushllt z20.h, z16.b, #0x0\n" + "ld1b { z16.b }, p1/Z, [x20, x24]\n" + ".inst 0x4508aa33 // ushllb z19.h, z17.b, #0x0\n" + ".inst 0x4508ae32 // ushllt z18.h, z17.b, #0x0\n" + "subs x21, x21, #0x1\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" + ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" + ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" + ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x4595496b // uaddwb z11.s, z11.s, z21.h\n" + ".inst 0x45954d4a // uaddwt z10.s, z10.s, z21.h\n" + ".inst 0x45944929 // uaddwb z9.s, z9.s, z20.h\n" + ".inst 0x45944d08 // uaddwt z8.s, z8.s, z20.h\n" + ".inst 0x459348e7 // uaddwb z7.s, z7.s, z19.h\n" + ".inst 0x45934cc6 // uaddwt z6.s, z6.s, z19.h\n" + ".inst 0x459248a5 // uaddwb z5.s, z5.s, z18.h\n" + ".inst 0x45924c84 // uaddwt z4.s, z4.s, z18.h\n" + ".inst 0x45914863 // uaddwb z3.s, z3.s, z17.h\n" + ".inst 0x45914c42 // uaddwt z2.s, z2.s, z17.h\n" ".inst 0x45904821 // uaddwb z1.s, z1.s, z16.h\n" ".inst 0x45904c00 // uaddwt z0.s, z0.s, z16.h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "mov z21.s, #0x0\n" - "ld1rw { z20.s }, p4/Z, [%x[combined_rescale_value]]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "mov z19.s, #0xff\n" - "ld1rw { z18.s }, p4/Z, [%x[left_shift]]\n" - "ld1rw { z17.s }, p4/Z, [%x[right_shift]]\n" - ".inst 0x4482924f // srshl z15.s, p4/M, z15.s, z18.s\n" - "ld1rw { z16.s }, p4/Z, [x19]\n" - ".inst 0x4482924e // srshl z14.s, p4/M, z14.s, z18.s\n" - ".inst 0x4482924d // srshl z13.s, p4/M, z13.s, z18.s\n" - ".inst 0x4482924c // srshl z12.s, p4/M, z12.s, z18.s\n" - ".inst 0x4482924b // srshl z11.s, p4/M, z11.s, z18.s\n" - ".inst 0x04b475ef // sqrdmulh z15.s, z15.s, z20.s\n" - ".inst 0x04b475ce // sqrdmulh z14.s, z14.s, z20.s\n" - ".inst 0x04b475ad // sqrdmulh z13.s, z13.s, z20.s\n" - ".inst 0x04b4758c // sqrdmulh z12.s, z12.s, z20.s\n" - ".inst 0x04b4756b // sqrdmulh z11.s, z11.s, z20.s\n" - ".inst 0x4482922f // srshl z15.s, p4/M, z15.s, z17.s\n" - ".inst 0x4482922e // srshl z14.s, p4/M, z14.s, z17.s\n" - ".inst 0x4482922d // srshl z13.s, p4/M, z13.s, z17.s\n" - ".inst 0x4482922c // srshl z12.s, p4/M, z12.s, z17.s\n" + "ld1rw { z18.s }, p0/Z, [%x[left_shift]]\n" + "ld1rw { z16.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482824f // srshl z15.s, p0/M, z15.s, z18.s\n" + ".inst 0x4482824e // srshl z14.s, p0/M, z14.s, z18.s\n" + ".inst 0x4482824d // srshl z13.s, p0/M, z13.s, z18.s\n" + ".inst 0x4482824c // srshl z12.s, p0/M, z12.s, z18.s\n" + "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b075ef // sqrdmulh z15.s, z15.s, z16.s\n" + ".inst 0x4482824b // srshl z11.s, p0/M, z11.s, z18.s\n" + ".inst 0x4482824a // srshl z10.s, p0/M, z10.s, z18.s\n" + ".inst 0x04b075ce // sqrdmulh z14.s, z14.s, z16.s\n" + ".inst 0x04b075ad // sqrdmulh z13.s, z13.s, z16.s\n" + ".inst 0x44828249 // srshl z9.s, p0/M, z9.s, z18.s\n" + ".inst 0x44828248 // srshl z8.s, p0/M, z8.s, z18.s\n" + ".inst 0x04b0758c // sqrdmulh z12.s, z12.s, z16.s\n" + ".inst 0x04b0756b // sqrdmulh z11.s, z11.s, z16.s\n" + ".inst 0x44828247 // srshl z7.s, p0/M, z7.s, z18.s\n" + ".inst 0x44828246 // srshl z6.s, p0/M, z6.s, z18.s\n" + ".inst 0x04b0754a // sqrdmulh z10.s, z10.s, z16.s\n" + ".inst 0x04b07529 // sqrdmulh z9.s, z9.s, z16.s\n" + ".inst 0x44828245 // srshl z5.s, p0/M, z5.s, z18.s\n" + ".inst 0x44828244 // srshl z4.s, p0/M, z4.s, z18.s\n" + ".inst 0x04b07508 // sqrdmulh z8.s, z8.s, z16.s\n" + ".inst 0x04b074e7 // sqrdmulh z7.s, z7.s, z16.s\n" + ".inst 0x44828243 // srshl z3.s, p0/M, z3.s, z18.s\n" + ".inst 0x44828242 // srshl z2.s, p0/M, z2.s, z18.s\n" + ".inst 0x04b074c6 // sqrdmulh z6.s, z6.s, z16.s\n" + ".inst 0x04b074a5 // sqrdmulh z5.s, z5.s, z16.s\n" + ".inst 0x44828241 // srshl z1.s, p0/M, z1.s, z18.s\n" + ".inst 0x44828240 // srshl z0.s, p0/M, z0.s, z18.s\n" + ".inst 0x04b07484 // sqrdmulh z4.s, z4.s, z16.s\n" + ".inst 0x04b07463 // sqrdmulh z3.s, z3.s, z16.s\n" + ".inst 0x04b07442 // sqrdmulh z2.s, z2.s, z16.s\n" + ".inst 0x04b07421 // sqrdmulh z1.s, z1.s, z16.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x04b07400 // sqrdmulh z0.s, z0.s, z16.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" + ".inst 0x4482822b // srshl z11.s, p0/M, z11.s, z17.s\n" "add z15.s, z15.s, z16.s\n" "add z14.s, z14.s, z16.s\n" + ".inst 0x4482822a // srshl z10.s, p0/M, z10.s, z17.s\n" + ".inst 0x44828229 // srshl z9.s, p0/M, z9.s, z17.s\n" "add z13.s, z13.s, z16.s\n" "add z12.s, z12.s, z16.s\n" - ".inst 0x4482922b // srshl z11.s, p4/M, z11.s, z17.s\n" - ".inst 0x4482924a // srshl z10.s, p4/M, z10.s, z18.s\n" - ".inst 0x44829249 // srshl z9.s, p4/M, z9.s, z18.s\n" - ".inst 0x44829248 // srshl z8.s, p4/M, z8.s, z18.s\n" + ".inst 0x44828228 // srshl z8.s, p0/M, z8.s, z17.s\n" + ".inst 0x44828227 // srshl z7.s, p0/M, z7.s, z17.s\n" "add z11.s, z11.s, z16.s\n" - ".inst 0x04b4754a // sqrdmulh z10.s, z10.s, z20.s\n" - ".inst 0x04b47529 // sqrdmulh z9.s, z9.s, z20.s\n" - ".inst 0x04b47508 // sqrdmulh z8.s, z8.s, z20.s\n" - ".inst 0x44829247 // srshl z7.s, p4/M, z7.s, z18.s\n" - ".inst 0x4482922a // srshl z10.s, p4/M, z10.s, z17.s\n" - ".inst 0x44829229 // srshl z9.s, p4/M, z9.s, z17.s\n" - ".inst 0x44829228 // srshl z8.s, p4/M, z8.s, z17.s\n" - ".inst 0x04b474e7 // sqrdmulh z7.s, z7.s, z20.s\n" "add z10.s, z10.s, z16.s\n" + ".inst 0x44828226 // srshl z6.s, p0/M, z6.s, z17.s\n" + ".inst 0x44828225 // srshl z5.s, p0/M, z5.s, z17.s\n" "add z9.s, z9.s, z16.s\n" "add z8.s, z8.s, z16.s\n" - ".inst 0x44829227 // srshl z7.s, p4/M, z7.s, z17.s\n" - ".inst 0x44829246 // srshl z6.s, p4/M, z6.s, z18.s\n" - ".inst 0x44829245 // srshl z5.s, p4/M, z5.s, z18.s\n" - ".inst 0x44829244 // srshl z4.s, p4/M, z4.s, z18.s\n" + ".inst 0x44828224 // srshl z4.s, p0/M, z4.s, z17.s\n" + ".inst 0x44828223 // srshl z3.s, p0/M, z3.s, z17.s\n" "add z7.s, z7.s, z16.s\n" - ".inst 0x04b474c6 // sqrdmulh z6.s, z6.s, z20.s\n" - ".inst 0x04b474a5 // sqrdmulh z5.s, z5.s, z20.s\n" - ".inst 0x04b47484 // sqrdmulh z4.s, z4.s, z20.s\n" - ".inst 0x44829243 // srshl z3.s, p4/M, z3.s, z18.s\n" - ".inst 0x44829226 // srshl z6.s, p4/M, z6.s, z17.s\n" - ".inst 0x44829225 // srshl z5.s, p4/M, z5.s, z17.s\n" - ".inst 0x44829224 // srshl z4.s, p4/M, z4.s, z17.s\n" - ".inst 0x04b47463 // sqrdmulh z3.s, z3.s, z20.s\n" "add z6.s, z6.s, z16.s\n" + ".inst 0x44828222 // srshl z2.s, p0/M, z2.s, z17.s\n" + ".inst 0x44828221 // srshl z1.s, p0/M, z1.s, z17.s\n" "add z5.s, z5.s, z16.s\n" "add z4.s, z4.s, z16.s\n" - ".inst 0x44829223 // srshl z3.s, p4/M, z3.s, z17.s\n" - ".inst 0x44829242 // srshl z2.s, p4/M, z2.s, z18.s\n" - ".inst 0x44829241 // srshl z1.s, p4/M, z1.s, z18.s\n" - ".inst 0x44829240 // srshl z0.s, p4/M, z0.s, z18.s\n" + ".inst 0x44828220 // srshl z0.s, p0/M, z0.s, z17.s\n" "add z3.s, z3.s, z16.s\n" - ".inst 0x04b47442 // sqrdmulh z2.s, z2.s, z20.s\n" - ".inst 0x04b47421 // sqrdmulh z1.s, z1.s, z20.s\n" - ".inst 0x04b47400 // sqrdmulh z0.s, z0.s, z20.s\n" - "smax z15.s, p4/M, z15.s, z21.s\n" - ".inst 0x44829222 // srshl z2.s, p4/M, z2.s, z17.s\n" - ".inst 0x44829221 // srshl z1.s, p4/M, z1.s, z17.s\n" - ".inst 0x44829220 // srshl z0.s, p4/M, z0.s, z17.s\n" - "smin z15.s, p4/M, z15.s, z19.s\n" "add z2.s, z2.s, z16.s\n" "add z1.s, z1.s, z16.s\n" "add z0.s, z0.s, z16.s\n" - "smax z14.s, p4/M, z14.s, z21.s\n" - "smax z13.s, p4/M, z13.s, z21.s\n" - "smax z12.s, p4/M, z12.s, z21.s\n" - "smax z11.s, p4/M, z11.s, z21.s\n" - "smin z14.s, p4/M, z14.s, z19.s\n" - "smin z13.s, p4/M, z13.s, z19.s\n" - "smin z12.s, p4/M, z12.s, z19.s\n" - "smin z11.s, p4/M, z11.s, z19.s\n" + "mov z16.s, #0x0\n" + "smax z15.s, p0/M, z15.s, z16.s\n" + "smax z14.s, p0/M, z14.s, z16.s\n" + "mov z18.s, #0xff\n" + "smax z13.s, p0/M, z13.s, z16.s\n" + "smax z12.s, p0/M, z12.s, z16.s\n" + "smax z11.s, p0/M, z11.s, z16.s\n" + "smax z10.s, p0/M, z10.s, z16.s\n" + "smax z9.s, p0/M, z9.s, z16.s\n" + "smax z8.s, p0/M, z8.s, z16.s\n" + "smax z7.s, p0/M, z7.s, z16.s\n" + "smax z6.s, p0/M, z6.s, z16.s\n" + "smax z5.s, p0/M, z5.s, z16.s\n" + "smax z4.s, p0/M, z4.s, z16.s\n" + "smax z3.s, p0/M, z3.s, z16.s\n" + "smax z2.s, p0/M, z2.s, z16.s\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smin z15.s, p0/M, z15.s, z18.s\n" + "smin z14.s, p0/M, z14.s, z18.s\n" "trn1 z17.h, z15.h, z14.h\n" - "smax z10.s, p4/M, z10.s, z21.s\n" + "smin z13.s, p0/M, z13.s, z18.s\n" + "smin z12.s, p0/M, z12.s, z18.s\n" "trn1 z16.h, z13.h, z12.h\n" - "smax z9.s, p4/M, z9.s, z21.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "smin z10.s, p4/M, z10.s, z19.s\n" - "incb x26, ALL, MUL #4\n" - "smin z9.s, p4/M, z9.s, z19.s\n" - "smax z8.s, p4/M, z8.s, z21.s\n" - "smax z7.s, p4/M, z7.s, z21.s\n" - "smax z6.s, p4/M, z6.s, z21.s\n" - "trn1 z18.h, z11.h, z10.h\n" - "smin z8.s, p4/M, z8.s, z19.s\n" - "smin z7.s, p4/M, z7.s, z19.s\n" - "smin z6.s, p4/M, z6.s, z19.s\n" - "smax z5.s, p4/M, z5.s, z21.s\n" + "smin z11.s, p0/M, z11.s, z18.s\n" + "smin z10.s, p0/M, z10.s, z18.s\n" + "trn1 z17.h, z11.h, z10.h\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "smin z9.s, p0/M, z9.s, z18.s\n" + "smin z8.s, p0/M, z8.s, z18.s\n" "trn1 z16.h, z9.h, z8.h\n" - "smax z4.s, p4/M, z4.s, z21.s\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z7.s, p0/M, z7.s, z18.s\n" + "smin z6.s, p0/M, z6.s, z18.s\n" "trn1 z17.h, z7.h, z6.h\n" - "trn1 z16.b, z18.b, z16.b\n" - "st1b { z16.b }, p2, [%x[outptr], x25]\n" - "smin z5.s, p4/M, z5.s, z19.s\n" - "incb x25, ALL, MUL #4\n" - "smin z4.s, p4/M, z4.s, z19.s\n" - "smax z3.s, p4/M, z3.s, z21.s\n" - "smax z2.s, p4/M, z2.s, z21.s\n" - "smax z1.s, p4/M, z1.s, z21.s\n" - "smax z0.s, p4/M, z0.s, z21.s\n" + "st1b { z16.b }, p3, [%x[outptr], x26]\n" + "smin z5.s, p0/M, z5.s, z18.s\n" + "smin z4.s, p0/M, z4.s, z18.s\n" "trn1 z16.h, z5.h, z4.h\n" - "smin z3.s, p4/M, z3.s, z19.s\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p1, [%x[outptr], x24]\n" - "smin z2.s, p4/M, z2.s, z19.s\n" - "incb x24, ALL, MUL #4\n" - "smin z1.s, p4/M, z1.s, z19.s\n" - "smin z0.s, p4/M, z0.s, z19.s\n" + "smin z3.s, p0/M, z3.s, z18.s\n" + "smin z2.s, p0/M, z2.s, z18.s\n" "trn1 z17.h, z3.h, z2.h\n" + "st1b { z16.b }, p2, [%x[outptr], x25]\n" + "smin z1.s, p0/M, z1.s, z18.s\n" + "smin z0.s, p0/M, z0.s, z18.s\n" "trn1 z16.h, z1.h, z0.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p0, [%x[outptr], x23]\n" - "incb x23, ALL, MUL #4\n" - "whilelt p0.b, x23, %x[n_channels]\n" + "st1b { z16.b }, p1, [%x[outptr], x24]\n" + "incb x24, ALL, MUL #4\n" + "whilelt p1.b, x24, %x[n_channels]\n" + "incb x27, ALL, MUL #4\n" + "incb x26, ALL, MUL #4\n" + "incb x25, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x26, %x[n_channels]\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "ld1rw { z15.s }, p4/Z, [%x[accumulator_init]]\n" + "ld1rw { z15.s }, p0/Z, [%x[accumulator_init]]\n" + "lsr x23, %x[n_valid_cells], #0x1\n" "mov z14.d, z15.d\n" - "mov x19, %x[inptrs]\n" "mov z13.d, z15.d\n" - "lsr x22, %x[n_valid_cells], #0x1\n" "mov z12.d, z15.d\n" - "cbz x22, 11f\n" - "ldp x21, x20, [x19, #0x0]\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - "add x19, x19, #0x10\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - "subs x22, x22, #0x1\n" + "mov x22, %x[inptrs]\n" + "cbz x23, 11f\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - "subs x22, x22, #0x1\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - "ld1b { z30.b }, p3/Z, [x20, x26]\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + "ldp x21, x20, [x22, #0x0]\n" + "subs x23, x23, #0x1\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + "add x22, x22, #0x10\n" + "ld1b { z31.b }, p4/Z, [x21, x27]\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" + "ld1b { z30.b }, p4/Z, [x20, x27]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail - ".inst 0x455e0bf7 // uaddlb z23.h, z31.b, z30.b\n" - ".inst 0x455e0ff6 // uaddlt z22.h, z31.b, z30.b\n" - ".inst 0x459749ef // uaddwb z15.s, z15.s, z23.h\n" - ".inst 0x45974dce // uaddwt z14.s, z14.s, z23.h\n" - ".inst 0x459649ad // uaddwb z13.s, z13.s, z22.h\n" - ".inst 0x45964d8c // uaddwt z12.s, z12.s, z22.h\n" + ".inst 0x455e0bf1 // uaddlb z17.h, z31.b, z30.b\n" + ".inst 0x455e0ff0 // uaddlt z16.h, z31.b, z30.b\n" + ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" + ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" + ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" + ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x1\n" + "ands x21, %x[n_valid_cells], #0x1\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x21, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z31.b }, p3/Z, [x21, x26]\n" - ".inst 0x4508abf1 // ushllb z17.h, z31.b, #0x0\n" - ".inst 0x4508aff0 // ushllt z16.h, z31.b, #0x0\n" + "ldr x20, [x22], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x27]\n" + ".inst 0x4508aa11 // ushllb z17.h, z16.b, #0x0\n" + ".inst 0x4508ae10 // ushllt z16.h, z16.b, #0x0\n" + "subs x21, x21, #0x1\n" ".inst 0x459149ef // uaddwb z15.s, z15.s, z17.h\n" ".inst 0x45914dce // uaddwt z14.s, z14.s, z17.h\n" ".inst 0x459049ad // uaddwb z13.s, z13.s, z16.h\n" ".inst 0x45904d8c // uaddwt z12.s, z12.s, z16.h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "mov z21.s, #0x0\n" - "ld1rw { z20.s }, p4/Z, [%x[combined_rescale_value]]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - "mov z19.s, #0xff\n" - "ld1rw { z18.s }, p4/Z, [%x[left_shift]]\n" - "ld1rw { z17.s }, p4/Z, [%x[right_shift]]\n" - ".inst 0x4482924f // srshl z15.s, p4/M, z15.s, z18.s\n" - "ld1rw { z16.s }, p4/Z, [x19]\n" - ".inst 0x4482924e // srshl z14.s, p4/M, z14.s, z18.s\n" - ".inst 0x4482924d // srshl z13.s, p4/M, z13.s, z18.s\n" - ".inst 0x4482924c // srshl z12.s, p4/M, z12.s, z18.s\n" - ".inst 0x04b475ef // sqrdmulh z15.s, z15.s, z20.s\n" - ".inst 0x04b475ce // sqrdmulh z14.s, z14.s, z20.s\n" - ".inst 0x04b475ad // sqrdmulh z13.s, z13.s, z20.s\n" - ".inst 0x04b4758c // sqrdmulh z12.s, z12.s, z20.s\n" - ".inst 0x4482922f // srshl z15.s, p4/M, z15.s, z17.s\n" - ".inst 0x4482922e // srshl z14.s, p4/M, z14.s, z17.s\n" - ".inst 0x4482922d // srshl z13.s, p4/M, z13.s, z17.s\n" - ".inst 0x4482922c // srshl z12.s, p4/M, z12.s, z17.s\n" + "ld1rw { z17.s }, p0/Z, [%x[left_shift]]\n" + "ld1rw { z16.s }, p0/Z, [%x[combined_rescale_value]]\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" + "ld1rw { z17.s }, p0/Z, [%x[right_shift]]\n" + ".inst 0x04b075ef // sqrdmulh z15.s, z15.s, z16.s\n" + ".inst 0x04b075ce // sqrdmulh z14.s, z14.s, z16.s\n" + ".inst 0x04b075ad // sqrdmulh z13.s, z13.s, z16.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x4482822f // srshl z15.s, p0/M, z15.s, z17.s\n" + ".inst 0x04b0758c // sqrdmulh z12.s, z12.s, z16.s\n" + ".inst 0x4482822e // srshl z14.s, p0/M, z14.s, z17.s\n" + ".inst 0x4482822d // srshl z13.s, p0/M, z13.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x4482822c // srshl z12.s, p0/M, z12.s, z17.s\n" "add z15.s, z15.s, z16.s\n" "add z14.s, z14.s, z16.s\n" "add z13.s, z13.s, z16.s\n" "add z12.s, z12.s, z16.s\n" - "smax z15.s, p4/M, z15.s, z21.s\n" - "smax z14.s, p4/M, z14.s, z21.s\n" - "smax z13.s, p4/M, z13.s, z21.s\n" - "smax z12.s, p4/M, z12.s, z21.s\n" - "smin z15.s, p4/M, z15.s, z19.s\n" - "smin z14.s, p4/M, z14.s, z19.s\n" - "smin z13.s, p4/M, z13.s, z19.s\n" - "smin z12.s, p4/M, z12.s, z19.s\n" + "mov z17.s, #0x0\n" + "smax z15.s, p0/M, z15.s, z17.s\n" + "smax z14.s, p0/M, z14.s, z17.s\n" + "mov z16.s, #0xff\n" + "smax z13.s, p0/M, z13.s, z17.s\n" + "smax z12.s, p0/M, z12.s, z17.s\n" + "smin z15.s, p0/M, z15.s, z16.s\n" + "smin z14.s, p0/M, z14.s, z16.s\n" "trn1 z17.h, z15.h, z14.h\n" + "smin z13.s, p0/M, z13.s, z16.s\n" + "smin z12.s, p0/M, z12.s, z16.s\n" "trn1 z16.h, z13.h, z12.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x26]\n" - "incb x26\n" - "whilelt p3.b, x26, %x[n_channels]\n" + "st1b { z16.b }, p4, [%x[outptr], x27]\n" + "incb x27\n" + "whilelt p4.b, x27, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [accumulator_init] "r" (&accumulator_init), [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [outptr] "r" (outptr), [quant_params] "r" (&qp), [right_shift] "r" (&right_shift) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst.hpp index c3c0edd0d5..eece6c0578 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -26,29 +26,21 @@ #pragma once -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { void sve_u8q_nhwc_max_generic_depthfirst_impl(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); -struct sve_u8q_nhwc_max_generic_depthfirst +struct sve_u8q_nhwc_max_generic_depthfirst : IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32> { - typedef uint8_t operand_type; - typedef uint8_t return_type; - - typedef void (*kern_type)(const uint64_t, const uint64_t n_valid_cells, uint64_t n_channels, const uint8_t *const *const inptrs, uint8_t *outptr, const Requantize32 &qp); - - constexpr static PoolingType pooling_type(void) { return PoolingType::MAX; } - - - kern_type kernel = sve_u8q_nhwc_max_generic_depthfirst_impl; - + using Parent = IGenericDepthfirstStrategy<uint8_t, uint8_t, Requantize32>; sve_u8q_nhwc_max_generic_depthfirst(const CPUInfo *) {} + typename Parent::KernelType get_kernel(void) const override { return sve_u8q_nhwc_max_generic_depthfirst_impl; } }; } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp index c1c1d29613..94522cdaaa 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_u8q_nhwc_max_generic_depthfirst/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -24,8 +24,9 @@ #include "pooling.hpp" #include <cstdint> +#include <cstddef> -#if defined(__ARM_FEATURE_SVE) && defined(SVE2) +#if defined(ARM_COMPUTE_ENABLE_SVE) namespace arm_conv { namespace pooling { @@ -41,376 +42,375 @@ void sve_u8q_nhwc_max_generic_depthfirst_impl( ) { __asm__ __volatile__( - "ptrue p4.b\n" - "mov x28, #0x0\n" - "cntb x27\n" - "cntb x26, ALL, MUL #2\n" - "cntb x25, ALL, MUL #3\n" + "mov x9, #0x0\n" + "cntb x28\n" + "cntb x27, ALL, MUL #2\n" + "cntb x26, ALL, MUL #3\n" + "whilelt p4.b, x9, %x[n_channels]\n" "whilelt p3.b, x28, %x[n_channels]\n" "whilelt p2.b, x27, %x[n_channels]\n" "whilelt p1.b, x26, %x[n_channels]\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "ptrue p0.b\n" "b.none 7f\n" "1:" // 4-vectors of channels - "mov z10.b, #0x0\n" - "mov x19, %x[inptrs]\n" - "mov z9.b, #0x0\n" - "lsr x24, %x[n_valid_cells], #0x2\n" + "lsr x25, %x[n_valid_cells], #0x2\n" "mov z8.b, #0x0\n" "mov z7.b, #0x0\n" - "cbz x24, 4f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "mov x24, %x[inptrs]\n" + "mov z6.b, #0x0\n" + "mov z5.b, #0x0\n" + "cbz x25, 4f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "beq 3f\n" "2:" // 4-vectors of channels: 4 inputs loop - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "movprfx z18, z31\n umax z18.b, p4/M, z18.b, z30.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "umax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n umax z17.b, p4/M, z17.b, z27.b\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "umax z21.b, p4/M, z21.b, z26.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "umax z16.b, p4/M, z16.b, z25.b\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" - "umax z20.b, p4/M, z20.b, z24.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z30.b }, p2/Z, [x22, x27]\n" - "umax z18.b, p4/M, z18.b, z22.b\n" - "ld1b { z22.b }, p2/Z, [x21, x27]\n" - "umax z17.b, p4/M, z17.b, z21.b\n" - "ld1b { z29.b }, p2/Z, [x20, x27]\n" - "umax z16.b, p4/M, z16.b, z20.b\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "umax z10.b, p4/M, z10.b, z19.b\n" - "ld1b { z27.b }, p1/Z, [x22, x26]\n" - "umax z9.b, p4/M, z9.b, z18.b\n" - "ld1b { z21.b }, p1/Z, [x21, x26]\n" - "umax z8.b, p4/M, z8.b, z17.b\n" - "ld1b { z26.b }, p1/Z, [x20, x26]\n" - "umax z7.b, p4/M, z7.b, z16.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "ld1b { z25.b }, p0/Z, [x22, x25]\n" - "ld1b { z20.b }, p0/Z, [x21, x25]\n" - "ld1b { z24.b }, p0/Z, [x20, x25]\n" + "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "movprfx z18, z0\n umax z18.b, p0/M, z18.b, z31.b\n" + "umax z22.b, p0/M, z22.b, z30.b\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "movprfx z17, z29\n umax z17.b, p0/M, z17.b, z28.b\n" + "umax z21.b, p0/M, z21.b, z27.b\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" + "movprfx z16, z26\n umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "ld1b { z0.b }, p3/Z, [x23, x28]\n" + "ld1b { z31.b }, p3/Z, [x22, x28]\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "ld1b { z22.b }, p3/Z, [x21, x28]\n" + "ld1b { z30.b }, p3/Z, [x20, x28]\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "ld1b { z29.b }, p2/Z, [x23, x27]\n" + "ld1b { z28.b }, p2/Z, [x22, x27]\n" + "subs x25, x25, #0x1\n" + "umax z8.b, p0/M, z8.b, z19.b\n" + "ld1b { z21.b }, p2/Z, [x21, x27]\n" + "ld1b { z27.b }, p2/Z, [x20, x27]\n" + "umax z7.b, p0/M, z7.b, z18.b\n" + "umax z6.b, p0/M, z6.b, z17.b\n" + "ld1b { z26.b }, p1/Z, [x23, x26]\n" + "ld1b { z25.b }, p1/Z, [x22, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z20.b }, p1/Z, [x21, x26]\n" + "ld1b { z24.b }, p1/Z, [x20, x26]\n" "bgt 2b\n" "3:" // 4-vectors of channels: 4 inputs tail - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "movprfx z18, z31\n umax z18.b, p4/M, z18.b, z30.b\n" - "umax z22.b, p4/M, z22.b, z29.b\n" - "movprfx z17, z28\n umax z17.b, p4/M, z17.b, z27.b\n" - "umax z21.b, p4/M, z21.b, z26.b\n" - "umax z16.b, p4/M, z16.b, z25.b\n" - "umax z20.b, p4/M, z20.b, z24.b\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "umax z18.b, p4/M, z18.b, z22.b\n" - "umax z17.b, p4/M, z17.b, z21.b\n" - "umax z16.b, p4/M, z16.b, z20.b\n" - "umax z10.b, p4/M, z10.b, z19.b\n" - "umax z9.b, p4/M, z9.b, z18.b\n" - "umax z8.b, p4/M, z8.b, z17.b\n" - "umax z7.b, p4/M, z7.b, z16.b\n" + "movprfx z19, z4\n umax z19.b, p0/M, z19.b, z3.b\n" + "movprfx z23, z2\n umax z23.b, p0/M, z23.b, z1.b\n" + "movprfx z18, z0\n umax z18.b, p0/M, z18.b, z31.b\n" + "umax z22.b, p0/M, z22.b, z30.b\n" + "movprfx z17, z29\n umax z17.b, p0/M, z17.b, z28.b\n" + "umax z21.b, p0/M, z21.b, z27.b\n" + "movprfx z16, z26\n umax z16.b, p0/M, z16.b, z25.b\n" + "umax z20.b, p0/M, z20.b, z24.b\n" + "umax z19.b, p0/M, z19.b, z23.b\n" + "umax z18.b, p0/M, z18.b, z22.b\n" + "umax z17.b, p0/M, z17.b, z21.b\n" + "umax z16.b, p0/M, z16.b, z20.b\n" + "umax z8.b, p0/M, z8.b, z19.b\n" + "umax z7.b, p0/M, z7.b, z18.b\n" + "umax z6.b, p0/M, z6.b, z17.b\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "4:" // 4-vectors of channels: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 6f\n" "5:" // 4-vectors of channels: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "umax z10.b, p4/M, z10.b, z3.b\n" - "ld1b { z31.b }, p2/Z, [x23, x27]\n" - "ld1b { z28.b }, p1/Z, [x23, x26]\n" - "umax z9.b, p4/M, z9.b, z31.b\n" - "ld1b { z16.b }, p0/Z, [x23, x25]\n" - "umax z8.b, p4/M, z8.b, z28.b\n" - "umax z7.b, p4/M, z7.b, z16.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "ld1b { z17.b }, p3/Z, [x20, x28]\n" + "ld1b { z16.b }, p2/Z, [x20, x27]\n" + "umax z7.b, p0/M, z7.b, z17.b\n" + "umax z6.b, p0/M, z6.b, z16.b\n" + "ld1b { z16.b }, p1/Z, [x20, x26]\n" + "umax z5.b, p0/M, z5.b, z16.b\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "mov z6.s, #0x0\n" - "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1rw { z5.s }, p4/Z, [x19]\n" - "mov z4.s, #0xff\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - ".inst 0x4508a951 // ushllb z17.h, z10.b, #0x0\n" - "ld1rw { z3.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - ".inst 0x4508ad50 // ushllt z16.h, z10.b, #0x0\n" - "ld1rw { z2.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - ".inst 0x4508a937 // ushllb z23.h, z9.b, #0x0\n" - "ld1rw { z1.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - ".inst 0x4508ad36 // ushllt z22.h, z9.b, #0x0\n" - "ld1rw { z0.s }, p4/Z, [x19]\n" - ".inst 0x4508a912 // ushllb z18.h, z8.b, #0x0\n" - ".inst 0x4508ad15 // ushllt z21.h, z8.b, #0x0\n" - ".inst 0x4508a8f4 // ushllb z20.h, z7.b, #0x0\n" - ".inst 0x4508acf3 // ushllt z19.h, z7.b, #0x0\n" - "neg z5.s, p4/M, z5.s\n" - ".inst 0x459140bf // saddwb z31.s, z5.s, z17.h\n" - ".inst 0x459144b1 // saddwt z17.s, z5.s, z17.h\n" - ".inst 0x459040be // saddwb z30.s, z5.s, z16.h\n" - ".inst 0x459044b0 // saddwt z16.s, z5.s, z16.h\n" - ".inst 0x459740bd // saddwb z29.s, z5.s, z23.h\n" - ".inst 0x459744bc // saddwt z28.s, z5.s, z23.h\n" - ".inst 0x459640bb // saddwb z27.s, z5.s, z22.h\n" - ".inst 0x459644ba // saddwt z26.s, z5.s, z22.h\n" - ".inst 0x459240b9 // saddwb z25.s, z5.s, z18.h\n" - ".inst 0x459244b2 // saddwt z18.s, z5.s, z18.h\n" - ".inst 0x459540b8 // saddwb z24.s, z5.s, z21.h\n" - ".inst 0x459544b7 // saddwt z23.s, z5.s, z21.h\n" - ".inst 0x459440b6 // saddwb z22.s, z5.s, z20.h\n" - ".inst 0x459444b5 // saddwt z21.s, z5.s, z20.h\n" - ".inst 0x459340b4 // saddwb z20.s, z5.s, z19.h\n" - ".inst 0x459344b3 // saddwt z19.s, z5.s, z19.h\n" - ".inst 0x4482905f // srshl z31.s, p4/M, z31.s, z2.s\n" - ".inst 0x44829051 // srshl z17.s, p4/M, z17.s, z2.s\n" - ".inst 0x4482905e // srshl z30.s, p4/M, z30.s, z2.s\n" - ".inst 0x44829050 // srshl z16.s, p4/M, z16.s, z2.s\n" - ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" - ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" - ".inst 0x04a377de // sqrdmulh z30.s, z30.s, z3.s\n" - ".inst 0x04a37610 // sqrdmulh z16.s, z16.s, z3.s\n" - ".inst 0x4482903f // srshl z31.s, p4/M, z31.s, z1.s\n" - ".inst 0x44829031 // srshl z17.s, p4/M, z17.s, z1.s\n" - ".inst 0x4482903e // srshl z30.s, p4/M, z30.s, z1.s\n" - ".inst 0x44829030 // srshl z16.s, p4/M, z16.s, z1.s\n" - "add z31.s, z31.s, z0.s\n" - "add z17.s, z17.s, z0.s\n" - "add z30.s, z30.s, z0.s\n" - "add z16.s, z16.s, z0.s\n" - ".inst 0x4482905d // srshl z29.s, p4/M, z29.s, z2.s\n" - ".inst 0x4482905c // srshl z28.s, p4/M, z28.s, z2.s\n" - ".inst 0x4482905b // srshl z27.s, p4/M, z27.s, z2.s\n" - ".inst 0x4482905a // srshl z26.s, p4/M, z26.s, z2.s\n" - ".inst 0x04a377bd // sqrdmulh z29.s, z29.s, z3.s\n" - ".inst 0x04a3779c // sqrdmulh z28.s, z28.s, z3.s\n" - ".inst 0x04a3777b // sqrdmulh z27.s, z27.s, z3.s\n" - ".inst 0x04a3775a // sqrdmulh z26.s, z26.s, z3.s\n" - ".inst 0x4482903d // srshl z29.s, p4/M, z29.s, z1.s\n" - ".inst 0x4482903c // srshl z28.s, p4/M, z28.s, z1.s\n" - ".inst 0x4482903b // srshl z27.s, p4/M, z27.s, z1.s\n" - ".inst 0x4482903a // srshl z26.s, p4/M, z26.s, z1.s\n" - "add z29.s, z29.s, z0.s\n" - "add z28.s, z28.s, z0.s\n" - "add z27.s, z27.s, z0.s\n" - "add z26.s, z26.s, z0.s\n" - ".inst 0x44829059 // srshl z25.s, p4/M, z25.s, z2.s\n" - ".inst 0x44829052 // srshl z18.s, p4/M, z18.s, z2.s\n" - "smax z31.s, p4/M, z31.s, z6.s\n" - "smax z17.s, p4/M, z17.s, z6.s\n" - ".inst 0x04a37739 // sqrdmulh z25.s, z25.s, z3.s\n" - ".inst 0x04a37652 // sqrdmulh z18.s, z18.s, z3.s\n" - "smin z31.s, p4/M, z31.s, z4.s\n" - "smin z17.s, p4/M, z17.s, z4.s\n" - ".inst 0x44829039 // srshl z25.s, p4/M, z25.s, z1.s\n" - ".inst 0x44829032 // srshl z18.s, p4/M, z18.s, z1.s\n" - "smax z30.s, p4/M, z30.s, z6.s\n" - "trn1 z17.h, z31.h, z17.h\n" - "add z25.s, z25.s, z0.s\n" - "add z18.s, z18.s, z0.s\n" - ".inst 0x44829058 // srshl z24.s, p4/M, z24.s, z2.s\n" - ".inst 0x44829057 // srshl z23.s, p4/M, z23.s, z2.s\n" - "smin z30.s, p4/M, z30.s, z4.s\n" - "smax z16.s, p4/M, z16.s, z6.s\n" - ".inst 0x04a37718 // sqrdmulh z24.s, z24.s, z3.s\n" - ".inst 0x04a376f7 // sqrdmulh z23.s, z23.s, z3.s\n" - "smax z29.s, p4/M, z29.s, z6.s\n" - "smin z16.s, p4/M, z16.s, z4.s\n" - ".inst 0x44829038 // srshl z24.s, p4/M, z24.s, z1.s\n" - ".inst 0x44829037 // srshl z23.s, p4/M, z23.s, z1.s\n" - "smin z29.s, p4/M, z29.s, z4.s\n" - "trn1 z16.h, z30.h, z16.h\n" - "add z24.s, z24.s, z0.s\n" - "add z23.s, z23.s, z0.s\n" + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1rw { z3.s }, p0/Z, [x20]\n" + ".inst 0x4508a911 // ushllb z17.h, z8.b, #0x0\n" + ".inst 0x4508ad18 // ushllt z24.h, z8.b, #0x0\n" + ".inst 0x4508a8f7 // ushllb z23.h, z7.b, #0x0\n" + ".inst 0x4508acf6 // ushllt z22.h, z7.b, #0x0\n" + "neg z3.s, p0/M, z3.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + ".inst 0x4508a8d5 // ushllb z21.h, z6.b, #0x0\n" + ".inst 0x4508acd4 // ushllt z20.h, z6.b, #0x0\n" + "ld1rw { z2.s }, p0/Z, [x20]\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + ".inst 0x4508a8b3 // ushllb z19.h, z5.b, #0x0\n" + ".inst 0x4508acb0 // ushllt z16.h, z5.b, #0x0\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + ".inst 0x45914061 // saddwb z1.s, z3.s, z17.h\n" + ".inst 0x45914471 // saddwt z17.s, z3.s, z17.h\n" + ".inst 0x44828041 // srshl z1.s, p0/M, z1.s, z2.s\n" + ".inst 0x44828051 // srshl z17.s, p0/M, z17.s, z2.s\n" + ".inst 0x45984060 // saddwb z0.s, z3.s, z24.h\n" + ".inst 0x4598447f // saddwt z31.s, z3.s, z24.h\n" + ".inst 0x44828040 // srshl z0.s, p0/M, z0.s, z2.s\n" + ".inst 0x4482805f // srshl z31.s, p0/M, z31.s, z2.s\n" + ".inst 0x4597407e // saddwb z30.s, z3.s, z23.h\n" + ".inst 0x4597447d // saddwt z29.s, z3.s, z23.h\n" + ".inst 0x4482805e // srshl z30.s, p0/M, z30.s, z2.s\n" + ".inst 0x4482805d // srshl z29.s, p0/M, z29.s, z2.s\n" + ".inst 0x4596407c // saddwb z28.s, z3.s, z22.h\n" + ".inst 0x4596447b // saddwt z27.s, z3.s, z22.h\n" + ".inst 0x4482805c // srshl z28.s, p0/M, z28.s, z2.s\n" + ".inst 0x4482805b // srshl z27.s, p0/M, z27.s, z2.s\n" + ".inst 0x4595407a // saddwb z26.s, z3.s, z21.h\n" + ".inst 0x45954479 // saddwt z25.s, z3.s, z21.h\n" + ".inst 0x4482805a // srshl z26.s, p0/M, z26.s, z2.s\n" + ".inst 0x44828059 // srshl z25.s, p0/M, z25.s, z2.s\n" + ".inst 0x45944078 // saddwb z24.s, z3.s, z20.h\n" + ".inst 0x45944477 // saddwt z23.s, z3.s, z20.h\n" + ".inst 0x44828058 // srshl z24.s, p0/M, z24.s, z2.s\n" + ".inst 0x44828057 // srshl z23.s, p0/M, z23.s, z2.s\n" + ".inst 0x45934076 // saddwb z22.s, z3.s, z19.h\n" + ".inst 0x45934475 // saddwt z21.s, z3.s, z19.h\n" + ".inst 0x44828056 // srshl z22.s, p0/M, z22.s, z2.s\n" + ".inst 0x44828055 // srshl z21.s, p0/M, z21.s, z2.s\n" + ".inst 0x45904074 // saddwb z20.s, z3.s, z16.h\n" + ".inst 0x45904473 // saddwt z19.s, z3.s, z16.h\n" + ".inst 0x44828054 // srshl z20.s, p0/M, z20.s, z2.s\n" + ".inst 0x44828053 // srshl z19.s, p0/M, z19.s, z2.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x04b27421 // sqrdmulh z1.s, z1.s, z18.s\n" + ".inst 0x04b27631 // sqrdmulh z17.s, z17.s, z18.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x04b27400 // sqrdmulh z0.s, z0.s, z18.s\n" + ".inst 0x04b277ff // sqrdmulh z31.s, z31.s, z18.s\n" + ".inst 0x44828201 // srshl z1.s, p0/M, z1.s, z16.s\n" + ".inst 0x44828211 // srshl z17.s, p0/M, z17.s, z16.s\n" + ".inst 0x04b277de // sqrdmulh z30.s, z30.s, z18.s\n" + ".inst 0x04b277bd // sqrdmulh z29.s, z29.s, z18.s\n" + ".inst 0x44828200 // srshl z0.s, p0/M, z0.s, z16.s\n" + ".inst 0x4482821f // srshl z31.s, p0/M, z31.s, z16.s\n" + ".inst 0x04b2779c // sqrdmulh z28.s, z28.s, z18.s\n" + ".inst 0x04b2777b // sqrdmulh z27.s, z27.s, z18.s\n" + ".inst 0x4482821e // srshl z30.s, p0/M, z30.s, z16.s\n" + ".inst 0x4482821d // srshl z29.s, p0/M, z29.s, z16.s\n" + ".inst 0x04b2775a // sqrdmulh z26.s, z26.s, z18.s\n" + ".inst 0x04b27739 // sqrdmulh z25.s, z25.s, z18.s\n" + ".inst 0x4482821c // srshl z28.s, p0/M, z28.s, z16.s\n" + ".inst 0x4482821b // srshl z27.s, p0/M, z27.s, z16.s\n" + ".inst 0x04b27718 // sqrdmulh z24.s, z24.s, z18.s\n" + ".inst 0x04b276f7 // sqrdmulh z23.s, z23.s, z18.s\n" + ".inst 0x4482821a // srshl z26.s, p0/M, z26.s, z16.s\n" + ".inst 0x44828219 // srshl z25.s, p0/M, z25.s, z16.s\n" + ".inst 0x04b276d6 // sqrdmulh z22.s, z22.s, z18.s\n" + ".inst 0x04b276b5 // sqrdmulh z21.s, z21.s, z18.s\n" + ".inst 0x44828218 // srshl z24.s, p0/M, z24.s, z16.s\n" + ".inst 0x44828217 // srshl z23.s, p0/M, z23.s, z16.s\n" + ".inst 0x04b27694 // sqrdmulh z20.s, z20.s, z18.s\n" + ".inst 0x04b27673 // sqrdmulh z19.s, z19.s, z18.s\n" + ".inst 0x44828216 // srshl z22.s, p0/M, z22.s, z16.s\n" + ".inst 0x44828215 // srshl z21.s, p0/M, z21.s, z16.s\n" + ".inst 0x44828214 // srshl z20.s, p0/M, z20.s, z16.s\n" + ".inst 0x44828213 // srshl z19.s, p0/M, z19.s, z16.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + "add z1.s, z1.s, z16.s\n" + "add z17.s, z17.s, z16.s\n" + "add z0.s, z0.s, z16.s\n" + "add z31.s, z31.s, z16.s\n" + "add z30.s, z30.s, z16.s\n" + "add z29.s, z29.s, z16.s\n" + "add z28.s, z28.s, z16.s\n" + "add z27.s, z27.s, z16.s\n" + "add z26.s, z26.s, z16.s\n" + "add z25.s, z25.s, z16.s\n" + "add z24.s, z24.s, z16.s\n" + "add z23.s, z23.s, z16.s\n" + "add z22.s, z22.s, z16.s\n" + "add z21.s, z21.s, z16.s\n" + "add z20.s, z20.s, z16.s\n" + "add z19.s, z19.s, z16.s\n" + "mov z16.s, #0x0\n" + "smax z1.s, p0/M, z1.s, z16.s\n" + "smax z17.s, p0/M, z17.s, z16.s\n" + "smax z0.s, p0/M, z0.s, z16.s\n" + "smax z31.s, p0/M, z31.s, z16.s\n" + "mov z18.s, #0xff\n" + "smax z30.s, p0/M, z30.s, z16.s\n" + "smax z29.s, p0/M, z29.s, z16.s\n" + "smax z28.s, p0/M, z28.s, z16.s\n" + "smax z27.s, p0/M, z27.s, z16.s\n" + "smax z26.s, p0/M, z26.s, z16.s\n" + "smax z25.s, p0/M, z25.s, z16.s\n" + "smax z24.s, p0/M, z24.s, z16.s\n" + "smax z23.s, p0/M, z23.s, z16.s\n" + "smax z22.s, p0/M, z22.s, z16.s\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smin z1.s, p0/M, z1.s, z18.s\n" + "smin z17.s, p0/M, z17.s, z18.s\n" + "trn1 z17.h, z1.h, z17.h\n" + "smin z0.s, p0/M, z0.s, z18.s\n" + "smin z31.s, p0/M, z31.s, z18.s\n" + "trn1 z16.h, z0.h, z31.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x28]\n" - ".inst 0x44829056 // srshl z22.s, p4/M, z22.s, z2.s\n" - "incb x28, ALL, MUL #4\n" - ".inst 0x44829055 // srshl z21.s, p4/M, z21.s, z2.s\n" - ".inst 0x44829054 // srshl z20.s, p4/M, z20.s, z2.s\n" - ".inst 0x44829053 // srshl z19.s, p4/M, z19.s, z2.s\n" - "smax z28.s, p4/M, z28.s, z6.s\n" - ".inst 0x04a376d6 // sqrdmulh z22.s, z22.s, z3.s\n" - ".inst 0x04a376b5 // sqrdmulh z21.s, z21.s, z3.s\n" - ".inst 0x04a37694 // sqrdmulh z20.s, z20.s, z3.s\n" - ".inst 0x04a37673 // sqrdmulh z19.s, z19.s, z3.s\n" - ".inst 0x44829036 // srshl z22.s, p4/M, z22.s, z1.s\n" - ".inst 0x44829035 // srshl z21.s, p4/M, z21.s, z1.s\n" - ".inst 0x44829034 // srshl z20.s, p4/M, z20.s, z1.s\n" - ".inst 0x44829033 // srshl z19.s, p4/M, z19.s, z1.s\n" - "add z22.s, z22.s, z0.s\n" - "add z21.s, z21.s, z0.s\n" - "add z20.s, z20.s, z0.s\n" - "add z19.s, z19.s, z0.s\n" - "smax z27.s, p4/M, z27.s, z6.s\n" - "smax z26.s, p4/M, z26.s, z6.s\n" - "smax z25.s, p4/M, z25.s, z6.s\n" - "smin z28.s, p4/M, z28.s, z4.s\n" - "smin z27.s, p4/M, z27.s, z4.s\n" - "smin z26.s, p4/M, z26.s, z4.s\n" - "smin z25.s, p4/M, z25.s, z4.s\n" - "trn1 z17.h, z29.h, z28.h\n" - "smax z18.s, p4/M, z18.s, z6.s\n" - "trn1 z16.h, z27.h, z26.h\n" - "smax z24.s, p4/M, z24.s, z6.s\n" + "smin z30.s, p0/M, z30.s, z18.s\n" + "smin z29.s, p0/M, z29.s, z18.s\n" + "trn1 z17.h, z30.h, z29.h\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "smin z28.s, p0/M, z28.s, z18.s\n" + "smin z27.s, p0/M, z27.s, z18.s\n" + "trn1 z16.h, z28.h, z27.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p2, [%x[outptr], x27]\n" - "smin z18.s, p4/M, z18.s, z4.s\n" - "incb x27, ALL, MUL #4\n" - "smin z24.s, p4/M, z24.s, z4.s\n" - "smax z23.s, p4/M, z23.s, z6.s\n" - "smax z22.s, p4/M, z22.s, z6.s\n" - "smax z21.s, p4/M, z21.s, z6.s\n" - "trn1 z18.h, z25.h, z18.h\n" - "smin z23.s, p4/M, z23.s, z4.s\n" - "smin z22.s, p4/M, z22.s, z4.s\n" - "smin z21.s, p4/M, z21.s, z4.s\n" - "smax z20.s, p4/M, z20.s, z6.s\n" + "smin z26.s, p0/M, z26.s, z18.s\n" + "smin z25.s, p0/M, z25.s, z18.s\n" + "trn1 z17.h, z26.h, z25.h\n" + "st1b { z16.b }, p3, [%x[outptr], x28]\n" + "smin z24.s, p0/M, z24.s, z18.s\n" + "smin z23.s, p0/M, z23.s, z18.s\n" "trn1 z16.h, z24.h, z23.h\n" - "smax z19.s, p4/M, z19.s, z6.s\n" + "trn1 z16.b, z17.b, z16.b\n" + "smin z22.s, p0/M, z22.s, z18.s\n" + "smin z21.s, p0/M, z21.s, z18.s\n" "trn1 z17.h, z22.h, z21.h\n" - "trn1 z16.b, z18.b, z16.b\n" - "st1b { z16.b }, p1, [%x[outptr], x26]\n" - "smin z20.s, p4/M, z20.s, z4.s\n" - "incb x26, ALL, MUL #4\n" - "smin z19.s, p4/M, z19.s, z4.s\n" + "st1b { z16.b }, p2, [%x[outptr], x27]\n" + "smin z20.s, p0/M, z20.s, z18.s\n" + "smin z19.s, p0/M, z19.s, z18.s\n" "trn1 z16.h, z20.h, z19.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p0, [%x[outptr], x25]\n" - "incb x25, ALL, MUL #4\n" - "whilelt p0.b, x25, %x[n_channels]\n" + "st1b { z16.b }, p1, [%x[outptr], x26]\n" + "incb x26, ALL, MUL #4\n" + "whilelt p1.b, x26, %x[n_channels]\n" + "incb x9, ALL, MUL #4\n" + "incb x28, ALL, MUL #4\n" + "incb x27, ALL, MUL #4\n" "b.any 1b\n" "7:" // Single vector of channels - "whilelt p3.b, x28, %x[n_channels]\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.none 14f\n" "8:" // Single vector of channels: Loop - "mov z10.b, #0x0\n" - "mov x19, %x[inptrs]\n" - "lsr x24, %x[n_valid_cells], #0x2\n" - "cbz x24, 11f\n" - "ldp x23, x22, [x19, #0x0]\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "subs x24, x24, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "lsr x25, %x[n_valid_cells], #0x2\n" + "mov z8.b, #0x0\n" + "mov x24, %x[inptrs]\n" + "cbz x25, 11f\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "subs x25, x25, #0x1\n" + "add x24, x24, #0x20\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 4 inputs loop - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "ldp x23, x22, [x19, #0x0]\n" - "subs x24, x24, #0x1\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "ldp x21, x20, [x19, #0x10]\n" - "add x19, x19, #0x20\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "ld1b { z2.b }, p3/Z, [x22, x28]\n" - "umax z10.b, p4/M, z10.b, z19.b\n" - "ld1b { z1.b }, p3/Z, [x21, x28]\n" - "ld1b { z0.b }, p3/Z, [x20, x28]\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "ldp x23, x22, [x24, #0x0]\n" + "ldp x21, x20, [x24, #0x10]\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "subs x25, x25, #0x1\n" + "ld1b { z4.b }, p4/Z, [x23, x9]\n" + "ld1b { z3.b }, p4/Z, [x22, x9]\n" + "umax z8.b, p0/M, z8.b, z16.b\n" + "add x24, x24, #0x20\n" + "ld1b { z2.b }, p4/Z, [x21, x9]\n" + "ld1b { z1.b }, p4/Z, [x20, x9]\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 4 inputs tail - "movprfx z19, z3\n umax z19.b, p4/M, z19.b, z2.b\n" - "movprfx z23, z1\n umax z23.b, p4/M, z23.b, z0.b\n" - "umax z19.b, p4/M, z19.b, z23.b\n" - "umax z10.b, p4/M, z10.b, z19.b\n" + "movprfx z16, z4\n umax z16.b, p0/M, z16.b, z3.b\n" + "movprfx z17, z2\n umax z17.b, p0/M, z17.b, z1.b\n" + "umax z16.b, p0/M, z16.b, z17.b\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "11:" // Single vector of channels: Loop: After loop - "ands x20, %x[n_valid_cells], #0x3\n" + "ands x21, %x[n_valid_cells], #0x3\n" "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop - "ldr x23, [x19], #0x8\n" - "subs x20, x20, #0x1\n" - "ld1b { z3.b }, p3/Z, [x23, x28]\n" - "umax z10.b, p4/M, z10.b, z3.b\n" + "ldr x20, [x24], #0x8\n" + "ld1b { z16.b }, p4/Z, [x20, x9]\n" + "subs x21, x21, #0x1\n" + "umax z8.b, p0/M, z8.b, z16.b\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "mov z6.s, #0x0\n" - "add x19, %x[quant_params], %[offsetof_qp_input_offset]\n" - "ld1rw { z5.s }, p4/Z, [x19]\n" - "mov z4.s, #0xff\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" - ".inst 0x4508a951 // ushllb z17.h, z10.b, #0x0\n" - "ld1rw { z3.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" - ".inst 0x4508ad50 // ushllt z16.h, z10.b, #0x0\n" - "ld1rw { z2.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" - "neg z5.s, p4/M, z5.s\n" - "ld1rw { z1.s }, p4/Z, [x19]\n" - "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n" - ".inst 0x459140bf // saddwb z31.s, z5.s, z17.h\n" - "ld1rw { z0.s }, p4/Z, [x19]\n" - ".inst 0x459144b1 // saddwt z17.s, z5.s, z17.h\n" - ".inst 0x459040be // saddwb z30.s, z5.s, z16.h\n" - ".inst 0x459044b0 // saddwt z16.s, z5.s, z16.h\n" - ".inst 0x4482905f // srshl z31.s, p4/M, z31.s, z2.s\n" - ".inst 0x44829051 // srshl z17.s, p4/M, z17.s, z2.s\n" - ".inst 0x4482905e // srshl z30.s, p4/M, z30.s, z2.s\n" - ".inst 0x44829050 // srshl z16.s, p4/M, z16.s, z2.s\n" - ".inst 0x04a377ff // sqrdmulh z31.s, z31.s, z3.s\n" - ".inst 0x04a37631 // sqrdmulh z17.s, z17.s, z3.s\n" - ".inst 0x04a377de // sqrdmulh z30.s, z30.s, z3.s\n" - ".inst 0x04a37610 // sqrdmulh z16.s, z16.s, z3.s\n" - ".inst 0x4482903f // srshl z31.s, p4/M, z31.s, z1.s\n" - ".inst 0x44829031 // srshl z17.s, p4/M, z17.s, z1.s\n" - ".inst 0x4482903e // srshl z30.s, p4/M, z30.s, z1.s\n" - ".inst 0x44829030 // srshl z16.s, p4/M, z16.s, z1.s\n" - "add z31.s, z31.s, z0.s\n" - "add z17.s, z17.s, z0.s\n" - "add z30.s, z30.s, z0.s\n" - "add z16.s, z16.s, z0.s\n" - "smax z31.s, p4/M, z31.s, z6.s\n" - "smax z17.s, p4/M, z17.s, z6.s\n" - "smax z30.s, p4/M, z30.s, z6.s\n" - "smax z16.s, p4/M, z16.s, z6.s\n" - "smin z31.s, p4/M, z31.s, z4.s\n" - "smin z17.s, p4/M, z17.s, z4.s\n" - "smin z30.s, p4/M, z30.s, z4.s\n" - "smin z16.s, p4/M, z16.s, z4.s\n" - "trn1 z17.h, z31.h, z17.h\n" - "trn1 z16.h, z30.h, z16.h\n" + "add x20, %x[quant_params], %[offsetof_qp_input_offset]\n" + "ld1rw { z18.s }, p0/Z, [x20]\n" + ".inst 0x4508a911 // ushllb z17.h, z8.b, #0x0\n" + ".inst 0x4508ad10 // ushllt z16.h, z8.b, #0x0\n" + "neg z18.s, p0/M, z18.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_left_shift]\n" + ".inst 0x45914255 // saddwb z21.s, z18.s, z17.h\n" + ".inst 0x45914654 // saddwt z20.s, z18.s, z17.h\n" + ".inst 0x45904253 // saddwb z19.s, z18.s, z16.h\n" + ".inst 0x45904652 // saddwt z18.s, z18.s, z16.h\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_mul]\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" + ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" + ".inst 0x04b076b5 // sqrdmulh z21.s, z21.s, z16.s\n" + ".inst 0x44828233 // srshl z19.s, p0/M, z19.s, z17.s\n" + ".inst 0x44828232 // srshl z18.s, p0/M, z18.s, z17.s\n" + ".inst 0x04b07694 // sqrdmulh z20.s, z20.s, z16.s\n" + ".inst 0x04b07673 // sqrdmulh z19.s, z19.s, z16.s\n" + "add x20, %x[quant_params], %[offsetof_qp_per_layer_right_shift]\n" + "ld1rw { z17.s }, p0/Z, [x20]\n" + ".inst 0x04b07652 // sqrdmulh z18.s, z18.s, z16.s\n" + "add x20, %x[quant_params], %[offsetof_qp_output_offset]\n" + ".inst 0x44828235 // srshl z21.s, p0/M, z21.s, z17.s\n" + ".inst 0x44828234 // srshl z20.s, p0/M, z20.s, z17.s\n" + "ld1rw { z16.s }, p0/Z, [x20]\n" + "add z21.s, z21.s, z16.s\n" + ".inst 0x44828233 // srshl z19.s, p0/M, z19.s, z17.s\n" + ".inst 0x44828232 // srshl z18.s, p0/M, z18.s, z17.s\n" + "add z20.s, z20.s, z16.s\n" + "add z19.s, z19.s, z16.s\n" + "add z18.s, z18.s, z16.s\n" + "mov z16.s, #0x0\n" + "smax z21.s, p0/M, z21.s, z16.s\n" + "smax z20.s, p0/M, z20.s, z16.s\n" + "smax z19.s, p0/M, z19.s, z16.s\n" + "smax z18.s, p0/M, z18.s, z16.s\n" + "mov z16.s, #0xff\n" + "smin z21.s, p0/M, z21.s, z16.s\n" + "smin z20.s, p0/M, z20.s, z16.s\n" + "trn1 z17.h, z21.h, z20.h\n" + "smin z19.s, p0/M, z19.s, z16.s\n" + "smin z18.s, p0/M, z18.s, z16.s\n" + "trn1 z16.h, z19.h, z18.h\n" "trn1 z16.b, z17.b, z16.b\n" - "st1b { z16.b }, p3, [%x[outptr], x28]\n" - "incb x28\n" - "whilelt p3.b, x28, %x[n_channels]\n" + "st1b { z16.b }, p4, [%x[outptr], x9]\n" + "incb x9\n" + "whilelt p4.b, x9, %x[n_channels]\n" "b.any 8b\n" "14:" // End - : : [inptrs] "r" (inptrs), [n_channels] "r" (n_channels), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_input_offset] "I" (offsetof(Requantize32, input_offset)), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [offsetof_qp_per_layer_left_shift] "I" (offsetof(Requantize32, per_layer_left_shift)), [offsetof_qp_per_layer_mul] "I" (offsetof(Requantize32, per_layer_mul)), [offsetof_qp_per_layer_right_shift] "I" (offsetof(Requantize32, per_layer_right_shift)), [outptr] "r" (outptr), [quant_params] "r" (&qp) - : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "x9", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } } // namespace pooling } // namespace arm_conv -#endif // defined(__ARM_FEATURE_SVE) && defined(SVE2) +#endif // defined(ARM_COMPUTE_ENABLE_SVE) |