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path: root/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp
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Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp295
1 files changed, 149 insertions, 146 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp
index ff8d7d8ba1..cf0047638e 100644
--- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp
+++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst/generic.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021-2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -26,6 +26,8 @@
#include <cstddef>
#include <cstdint>
+#if defined(__aarch64__)
+
namespace arm_conv {
namespace pooling {
@@ -80,172 +82,173 @@ void a64_fp32_nhwc_avg_3x3_s1_output2x2_depthfirst_impl(
pad_left, pad_top, pad_right, pad_bottom);
__asm__ __volatile__(
- "ldr x4, [%x[args], %[offsetof_n_channels]]\n"
+ "ldr q7, [%x[args], %[offsetof_rescale]]\n"
+ "ldr x3, [%x[args], %[offsetof_n_channels]]\n"
+ "cmp x3, #0x4\n"
+ "mov x4, #0x0\n"
+ "ldr x21, [%x[args], %[offsetof_outptrs]]\n"
+ "ldr x20, [%x[args], %[offsetof_inptrs]]\n"
"mov x5, #0x0\n"
- "ldr x20, [%x[args], %[offsetof_outptrs]]\n"
- "mov x6, #0x0\n"
- "ldr x19, [%x[args], %[offsetof_inptrs]]\n"
- "cmp x4, #0x4\n"
- "ldp x7, x8, [x20, #0x0]\n"
- "ldp x17, x16, [x20, #0x10]\n"
- "ldp x15, x14, [x19, #0x0]\n"
- "ldp x13, x12, [x19, #0x10]\n"
- "ldp x11, x10, [x19, #0x20]\n"
- "ldp x9, x28, [x19, #0x30]\n"
- "ldp x27, x26, [x19, #0x40]\n"
- "ldp x25, x24, [x19, #0x50]\n"
- "ldp x23, x22, [x19, #0x60]\n"
- "ldp x21, x20, [x19, #0x70]\n"
- "ldr q8, [%x[args], %[offsetof_rescale]]\n"
+ "ldp x6, x7, [x21, #0x0]\n"
+ "ldp x8, x17, [x21, #0x10]\n"
+ "ldp x16, x15, [x20, #0x0]\n"
+ "ldp x14, x13, [x20, #0x10]\n"
+ "ldp x12, x11, [x20, #0x20]\n"
+ "ldp x10, x9, [x20, #0x30]\n"
+ "ldp x28, x27, [x20, #0x40]\n"
+ "ldp x26, x25, [x20, #0x50]\n"
+ "ldp x24, x23, [x20, #0x60]\n"
+ "ldp x22, x21, [x20, #0x70]\n"
"blt 3f\n"
- "ldr q7, [x10, x5]\n"
- "lsr x19, x4, #0x2\n"
- "ldr q6, [x9, x5]\n"
- "sub x4, x4, x19, LSL #2\n"
- "ldr q5, [x26, x5]\n"
- "subs x19, x19, #0x1\n"
- "ldr q4, [x25, x5]\n"
- "ldr q3, [x14, x5]\n"
- "ldr q2, [x13, x5]\n"
- "ldr q1, [x11, x5]\n"
- "ldr q0, [x27, x5]\n"
- "ldr q31, [x28, x5]\n"
- "ldr q30, [x24, x5]\n"
- "ldr q29, [x22, x5]\n"
- "ldr q28, [x21, x5]\n"
- "ldr q27, [x15, x5]\n"
- "ldr q26, [x12, x5]\n"
- "ldr q25, [x23, x5]\n"
- "ldr q24, [x20, x5]\n"
- "add x5, x5, #0x10\n"
+ "ldr q6, [x11, x4]\n"
+ "ldr q5, [x10, x4]\n"
+ "lsr x20, x3, #0x2\n"
+ "sub x3, x3, x20, LSL #2\n"
+ "ldr q4, [x27, x4]\n"
+ "ldr q3, [x26, x4]\n"
+ "subs x20, x20, #0x1\n"
+ "ldr q2, [x15, x4]\n"
+ "ldr q1, [x14, x4]\n"
+ "ldr q0, [x12, x4]\n"
+ "ldr q31, [x28, x4]\n"
+ "ldr q30, [x9, x4]\n"
+ "ldr q29, [x25, x4]\n"
+ "ldr q28, [x23, x4]\n"
+ "ldr q27, [x22, x4]\n"
+ "ldr q26, [x16, x4]\n"
+ "ldr q25, [x13, x4]\n"
+ "ldr q24, [x24, x4]\n"
+ "ldr q23, [x21, x4]\n"
+ "add x4, x4, #0x10\n"
"beq 2f\n"
"1:" // Vector: Loop
- "fadd v17.4s, v7.4s, v6.4s\n"
- "ldr q7, [x10, x5]\n"
- "subs x19, x19, #0x1\n"
- "fadd v16.4s, v5.4s, v4.4s\n"
- "ldr q6, [x9, x5]\n"
- "fadd v18.4s, v3.4s, v2.4s\n"
- "ldr q5, [x26, x5]\n"
- "fadd v23.4s, v1.4s, v0.4s\n"
- "ldr q4, [x25, x5]\n"
- "fadd v22.4s, v31.4s, v30.4s\n"
- "ldr q3, [x14, x5]\n"
- "fadd v17.4s, v17.4s, v16.4s\n"
- "ldr q2, [x13, x5]\n"
- "fadd v16.4s, v29.4s, v28.4s\n"
- "ldr q1, [x11, x5]\n"
- "fadd v19.4s, v27.4s, v23.4s\n"
- "ldr q0, [x27, x5]\n"
- "fadd v21.4s, v18.4s, v17.4s\n"
- "ldr q31, [x28, x5]\n"
- "fadd v20.4s, v16.4s, v17.4s\n"
- "ldr q30, [x24, x5]\n"
- "fadd v18.4s, v26.4s, v22.4s\n"
- "ldr q29, [x22, x5]\n"
- "fadd v17.4s, v25.4s, v23.4s\n"
- "ldr q28, [x21, x5]\n"
- "fadd v16.4s, v24.4s, v22.4s\n"
- "ldr q27, [x15, x5]\n"
+ "fadd v17.4s, v6.4s, v5.4s\n"
+ "ldr q6, [x11, x4]\n"
+ "ldr q5, [x10, x4]\n"
+ "fadd v16.4s, v4.4s, v3.4s\n"
+ "ldr q4, [x27, x4]\n"
+ "ldr q3, [x26, x4]\n"
+ "fadd v19.4s, v17.4s, v16.4s\n"
+ "fadd v18.4s, v2.4s, v1.4s\n"
+ "ldr q2, [x15, x4]\n"
+ "ldr q1, [x14, x4]\n"
+ "fadd v17.4s, v0.4s, v31.4s\n"
+ "fadd v22.4s, v30.4s, v29.4s\n"
+ "ldr q0, [x12, x4]\n"
+ "ldr q31, [x28, x4]\n"
+ "fadd v16.4s, v28.4s, v27.4s\n"
+ "fadd v21.4s, v18.4s, v19.4s\n"
+ "ldr q30, [x9, x4]\n"
+ "ldr q29, [x25, x4]\n"
+ "fadd v20.4s, v16.4s, v19.4s\n"
+ "fadd v19.4s, v26.4s, v17.4s\n"
+ "ldr q28, [x23, x4]\n"
+ "ldr q27, [x22, x4]\n"
+ "fadd v18.4s, v25.4s, v22.4s\n"
+ "fadd v17.4s, v24.4s, v17.4s\n"
+ "ldr q26, [x16, x4]\n"
+ "ldr q25, [x13, x4]\n"
+ "fadd v16.4s, v23.4s, v22.4s\n"
"fadd v19.4s, v21.4s, v19.4s\n"
- "ldr q26, [x12, x5]\n"
+ "ldr q24, [x24, x4]\n"
+ "ldr q23, [x21, x4]\n"
"fadd v18.4s, v21.4s, v18.4s\n"
- "ldr q25, [x23, x5]\n"
"fadd v17.4s, v17.4s, v20.4s\n"
- "ldr q24, [x20, x5]\n"
+ "fadd v16.4s, v16.4s, v20.4s\n"
+ "subs x20, x20, #0x1\n"
+ "fmul v19.4s, v19.4s, v7.s[0]\n"
+ "add x4, x4, #0x10\n"
+ "fmul v18.4s, v18.4s, v7.s[1]\n"
+ "fmul v17.4s, v17.4s, v7.s[2]\n"
+ "str q19, [x6, x5]\n"
+ "fmul v16.4s, v16.4s, v7.s[3]\n"
+ "str q18, [x7, x5]\n"
+ "str q17, [x8, x5]\n"
+ "str q16, [x17, x5]\n"
"add x5, x5, #0x10\n"
- "fadd v16.4s, v20.4s, v16.4s\n"
- "fmul v19.4s, v19.4s, v8.s[0]\n"
- "str q19, [x7, x6]\n"
- "fmul v18.4s, v18.4s, v8.s[1]\n"
- "fmul v17.4s, v17.4s, v8.s[2]\n"
- "str q18, [x8, x6]\n"
- "fmul v16.4s, v16.4s, v8.s[3]\n"
- "str q17, [x17, x6]\n"
- "str q16, [x16, x6]\n"
- "add x6, x6, #0x10\n"
"bgt 1b\n"
"2:" // Vector: Tail
- "fadd v17.4s, v7.4s, v6.4s\n"
- "fadd v16.4s, v5.4s, v4.4s\n"
- "fadd v18.4s, v3.4s, v2.4s\n"
- "fadd v23.4s, v1.4s, v0.4s\n"
- "fadd v17.4s, v17.4s, v16.4s\n"
- "fadd v22.4s, v31.4s, v30.4s\n"
- "fadd v16.4s, v29.4s, v28.4s\n"
- "fadd v21.4s, v18.4s, v17.4s\n"
- "fadd v19.4s, v27.4s, v23.4s\n"
- "fadd v20.4s, v16.4s, v17.4s\n"
- "fadd v18.4s, v26.4s, v22.4s\n"
- "fadd v17.4s, v25.4s, v23.4s\n"
- "fadd v16.4s, v24.4s, v22.4s\n"
+ "fadd v17.4s, v6.4s, v5.4s\n"
+ "fadd v16.4s, v4.4s, v3.4s\n"
+ "fadd v19.4s, v17.4s, v16.4s\n"
+ "fadd v18.4s, v2.4s, v1.4s\n"
+ "fadd v17.4s, v0.4s, v31.4s\n"
+ "fadd v22.4s, v30.4s, v29.4s\n"
+ "fadd v16.4s, v28.4s, v27.4s\n"
+ "fadd v21.4s, v18.4s, v19.4s\n"
+ "fadd v20.4s, v16.4s, v19.4s\n"
+ "fadd v19.4s, v26.4s, v17.4s\n"
+ "fadd v18.4s, v25.4s, v22.4s\n"
+ "fadd v17.4s, v24.4s, v17.4s\n"
+ "fadd v16.4s, v23.4s, v22.4s\n"
"fadd v19.4s, v21.4s, v19.4s\n"
"fadd v18.4s, v21.4s, v18.4s\n"
"fadd v17.4s, v17.4s, v20.4s\n"
- "fadd v16.4s, v20.4s, v16.4s\n"
- "fmul v19.4s, v19.4s, v8.s[0]\n"
- "str q19, [x7, x6]\n"
- "fmul v18.4s, v18.4s, v8.s[1]\n"
- "fmul v17.4s, v17.4s, v8.s[2]\n"
- "str q18, [x8, x6]\n"
- "fmul v16.4s, v16.4s, v8.s[3]\n"
- "str q17, [x17, x6]\n"
- "str q16, [x16, x6]\n"
- "add x6, x6, #0x10\n"
- "cbz x4, 4f\n"
+ "fadd v16.4s, v16.4s, v20.4s\n"
+ "fmul v19.4s, v19.4s, v7.s[0]\n"
+ "str q19, [x6, x5]\n"
+ "fmul v18.4s, v18.4s, v7.s[1]\n"
+ "fmul v17.4s, v17.4s, v7.s[2]\n"
+ "str q18, [x7, x5]\n"
+ "fmul v16.4s, v16.4s, v7.s[3]\n"
+ "str q17, [x8, x5]\n"
+ "str q16, [x17, x5]\n"
+ "add x5, x5, #0x10\n"
+ "cbz x3, 4f\n"
"3:" // Oddments
- "ldr s7, [x10, x5]\n"
- "subs x4, x4, #0x1\n"
- "ldr s6, [x9, x5]\n"
- "fadd v17.4s, v7.4s, v6.4s\n"
- "ldr s5, [x26, x5]\n"
- "ldr s4, [x25, x5]\n"
- "fadd v16.4s, v5.4s, v4.4s\n"
- "ldr s3, [x14, x5]\n"
- "ldr s2, [x13, x5]\n"
- "fadd v17.4s, v17.4s, v16.4s\n"
- "ldr s1, [x11, x5]\n"
- "ldr s0, [x27, x5]\n"
- "fadd v18.4s, v3.4s, v2.4s\n"
- "ldr s31, [x28, x5]\n"
- "fadd v23.4s, v1.4s, v0.4s\n"
- "ldr s30, [x24, x5]\n"
- "fadd v21.4s, v18.4s, v17.4s\n"
- "ldr s29, [x22, x5]\n"
- "ldr s28, [x21, x5]\n"
- "fadd v22.4s, v31.4s, v30.4s\n"
- "ldr s27, [x15, x5]\n"
- "ldr s26, [x12, x5]\n"
- "fadd v16.4s, v29.4s, v28.4s\n"
- "ldr s25, [x23, x5]\n"
- "fadd v20.4s, v16.4s, v17.4s\n"
- "ldr s24, [x20, x5]\n"
- "add x5, x5, #0x4\n"
- "fadd v19.4s, v27.4s, v23.4s\n"
- "fadd v18.4s, v26.4s, v22.4s\n"
- "fadd v17.4s, v25.4s, v23.4s\n"
- "fadd v16.4s, v24.4s, v22.4s\n"
- "fadd v19.4s, v21.4s, v19.4s\n"
- "fadd v18.4s, v21.4s, v18.4s\n"
+ "ldr s17, [x11, x4]\n"
+ "ldr s16, [x10, x4]\n"
+ "fadd v18.4s, v17.4s, v16.4s\n"
+ "subs x3, x3, #0x1\n"
+ "ldr s17, [x27, x4]\n"
+ "ldr s16, [x26, x4]\n"
+ "fadd v16.4s, v17.4s, v16.4s\n"
+ "fadd v18.4s, v18.4s, v16.4s\n"
+ "ldr s17, [x15, x4]\n"
+ "ldr s16, [x14, x4]\n"
+ "fadd v16.4s, v17.4s, v16.4s\n"
+ "fadd v23.4s, v16.4s, v18.4s\n"
+ "ldr s17, [x12, x4]\n"
+ "ldr s16, [x28, x4]\n"
+ "fadd v22.4s, v17.4s, v16.4s\n"
+ "ldr s17, [x9, x4]\n"
+ "ldr s16, [x25, x4]\n"
+ "fadd v21.4s, v17.4s, v16.4s\n"
+ "ldr s17, [x23, x4]\n"
+ "ldr s16, [x22, x4]\n"
+ "fadd v16.4s, v17.4s, v16.4s\n"
+ "fadd v20.4s, v16.4s, v18.4s\n"
+ "ldr s17, [x16, x4]\n"
+ "ldr s16, [x13, x4]\n"
+ "fadd v19.4s, v17.4s, v22.4s\n"
+ "fadd v18.4s, v16.4s, v21.4s\n"
+ "ldr s17, [x24, x4]\n"
+ "ldr s16, [x21, x4]\n"
+ "fadd v17.4s, v17.4s, v22.4s\n"
+ "fadd v16.4s, v16.4s, v21.4s\n"
+ "fadd v19.4s, v23.4s, v19.4s\n"
+ "fadd v18.4s, v23.4s, v18.4s\n"
+ "add x4, x4, #0x4\n"
"fadd v17.4s, v17.4s, v20.4s\n"
- "fadd v16.4s, v20.4s, v16.4s\n"
- "fmul v19.4s, v19.4s, v8.s[0]\n"
- "str s19, [x7, x6]\n"
- "fmul v18.4s, v18.4s, v8.s[1]\n"
- "fmul v17.4s, v17.4s, v8.s[2]\n"
- "str s18, [x8, x6]\n"
- "fmul v16.4s, v16.4s, v8.s[3]\n"
- "str s17, [x17, x6]\n"
- "str s16, [x16, x6]\n"
- "add x6, x6, #0x4\n"
+ "fadd v16.4s, v16.4s, v20.4s\n"
+ "fmul v19.4s, v19.4s, v7.s[0]\n"
+ "fmul v18.4s, v18.4s, v7.s[1]\n"
+ "str s19, [x6, x5]\n"
+ "fmul v17.4s, v17.4s, v7.s[2]\n"
+ "fmul v16.4s, v16.4s, v7.s[3]\n"
+ "str s18, [x7, x5]\n"
+ "str s17, [x8, x5]\n"
+ "str s16, [x17, x5]\n"
+ "add x5, x5, #0x4\n"
"bgt 3b\n"
"4:" // End
-
:
: [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs)), [offsetof_rescale] "I" (offsetof(KernelArgs, rescale_vals))
- : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
} // namespace pooling
} // namespace arm_conv
+
+#endif // defined(__aarch64__)
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-03 23:59:50 +0000