aboutsummaryrefslogtreecommitdiff
path: root/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst/generic.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst/generic.cpp527
1 files changed, 527 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst/generic.cpp
new file mode 100644
index 0000000000..8ac79f82fa
--- /dev/null
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_generic_output9_mla_depthfirst/generic.cpp
@@ -0,0 +1,527 @@
+/*
+ * Copyright (c) 2021 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <cstddef>
+#include <cstdint>
+
+#if defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
+
+namespace arm_conv {
+namespace depthwise {
+
+void a64_fp16_nhwc_generic_output9_mla_depthfirst_impl(
+ const __fp16 *const *const inptrs,
+ __fp16 *const *const outptrs,
+ const void *params,
+ const void *bias,
+ const unsigned int n_points,
+ const unsigned int n_channels,
+ const __fp16 activation_min,
+ const __fp16 activation_max
+)
+{
+ const __fp16 minmax_vals[2] = { activation_min, activation_max };
+
+ __asm__ __volatile__(
+ "ld1r { v4.8h }, [%x[minmax_vals]]\n"
+ "add x19, %x[minmax_vals], #0x2\n"
+ "mov x11, #0x0\n"
+ "ld1r { v3.8h }, [x19]\n"
+ "lsr x10, %x[n_channels], #0x3\n"
+ "cbz x10, 5f\n"
+ "1:" // Channel loop
+ "movi v25.16b, #0x0\n"
+ "cbz %x[bias], 2f\n"
+ "ldr q25, [%x[bias], x11]\n"
+ "2:" // Channel loop: Load bias: Done
+ "mov v24.16b, v25.16b\n"
+ "ldr q23, [%x[params], #0x0]\n"
+ "mov x20, %x[inptrs]\n"
+ "mov v22.16b, v25.16b\n"
+ "ldp x9, x28, [x20], #0x10\n"
+ "subs x19, %x[n_points], #0x1\n"
+ "mov v21.16b, v25.16b\n"
+ "ldr q2, [x9, x11]\n"
+ "mov v20.16b, v25.16b\n"
+ "add %x[params], %x[params], #0x10\n"
+ "mov v19.16b, v25.16b\n"
+ "ldr q1, [x28, x11]\n"
+ "mov v18.16b, v25.16b\n"
+ "ldp x27, x26, [x20], #0x10\n"
+ "mov v17.16b, v25.16b\n"
+ "ldr q0, [x27, x11]\n"
+ "mov v16.16b, v25.16b\n"
+ "ldr q31, [x26, x11]\n"
+ "ldp x25, x24, [x20], #0x10\n"
+ "ldr q30, [x25, x11]\n"
+ "ldr q29, [x24, x11]\n"
+ "ldp x23, x22, [x20], #0x10\n"
+ "ldr q28, [x23, x11]\n"
+ "ldr q27, [x22, x11]\n"
+ "ldr x21, [x20], #0x8\n"
+ "ldr q26, [x21, x11]\n"
+ "ble 4f\n"
+ "3:" // Channel loop: Planar loop
+ "fmla v25.8h, v2.8h, v23.8h\n"
+ "ldp x9, x28, [x20], #0x10\n"
+ "subs x19, x19, #0x1\n"
+ "fmla v24.8h, v1.8h, v23.8h\n"
+ "ldr q2, [x9, x11]\n"
+ "fmla v22.8h, v0.8h, v23.8h\n"
+ "fmla v21.8h, v31.8h, v23.8h\n"
+ "ldr q1, [x28, x11]\n"
+ "fmla v20.8h, v30.8h, v23.8h\n"
+ "ldp x27, x26, [x20], #0x10\n"
+ "fmla v19.8h, v29.8h, v23.8h\n"
+ "fmla v18.8h, v28.8h, v23.8h\n"
+ "ldr q0, [x27, x11]\n"
+ "fmla v17.8h, v27.8h, v23.8h\n"
+ "fmla v16.8h, v26.8h, v23.8h\n"
+ "ldr q23, [%x[params], #0x0]\n"
+ "add %x[params], %x[params], #0x10\n"
+ "ldr q31, [x26, x11]\n"
+ "ldp x25, x24, [x20], #0x10\n"
+ "ldr q30, [x25, x11]\n"
+ "ldr q29, [x24, x11]\n"
+ "ldp x23, x22, [x20], #0x10\n"
+ "ldr q28, [x23, x11]\n"
+ "ldr q27, [x22, x11]\n"
+ "ldr x21, [x20], #0x8\n"
+ "ldr q26, [x21, x11]\n"
+ "bgt 3b\n"
+ "4:" // Channel loop: Planar tail
+ "fmla v25.8h, v2.8h, v23.8h\n"
+ "ldp x27, x26, [%x[outptrs], #0x0]\n"
+ "fmla v24.8h, v1.8h, v23.8h\n"
+ "ldp x25, x24, [%x[outptrs], #0x10]\n"
+ "fmla v22.8h, v0.8h, v23.8h\n"
+ "ldp x23, x22, [%x[outptrs], #0x20]\n"
+ "fmla v21.8h, v31.8h, v23.8h\n"
+ "ldp x21, x20, [%x[outptrs], #0x30]\n"
+ "fmla v20.8h, v30.8h, v23.8h\n"
+ "ldr x19, [%x[outptrs], #0x40]\n"
+ "fmla v19.8h, v29.8h, v23.8h\n"
+ "fmla v18.8h, v28.8h, v23.8h\n"
+ "fmla v17.8h, v27.8h, v23.8h\n"
+ "fmla v16.8h, v26.8h, v23.8h\n"
+ "fmax v25.8h, v25.8h, v4.8h\n"
+ "fmax v24.8h, v24.8h, v4.8h\n"
+ "fmax v22.8h, v22.8h, v4.8h\n"
+ "fmin v25.8h, v25.8h, v3.8h\n"
+ "str q25, [x27, x11]\n"
+ "fmin v24.8h, v24.8h, v3.8h\n"
+ "fmin v22.8h, v22.8h, v3.8h\n"
+ "str q24, [x26, x11]\n"
+ "fmax v21.8h, v21.8h, v4.8h\n"
+ "fmax v20.8h, v20.8h, v4.8h\n"
+ "str q22, [x25, x11]\n"
+ "fmax v19.8h, v19.8h, v4.8h\n"
+ "fmax v18.8h, v18.8h, v4.8h\n"
+ "fmin v21.8h, v21.8h, v3.8h\n"
+ "str q21, [x24, x11]\n"
+ "fmin v20.8h, v20.8h, v3.8h\n"
+ "fmin v19.8h, v19.8h, v3.8h\n"
+ "str q20, [x23, x11]\n"
+ "fmin v18.8h, v18.8h, v3.8h\n"
+ "fmax v17.8h, v17.8h, v4.8h\n"
+ "str q19, [x22, x11]\n"
+ "fmax v16.8h, v16.8h, v4.8h\n"
+ "str q18, [x21, x11]\n"
+ "fmin v17.8h, v17.8h, v3.8h\n"
+ "fmin v16.8h, v16.8h, v3.8h\n"
+ "str q17, [x20, x11]\n"
+ "str q16, [x19, x11]\n"
+ "add x11, x11, #0x10\n"
+ "cmp x11, x10, LSL #4\n"
+ "blt 1b\n"
+ "5:" // Oddments
+ "tst %x[n_channels], #0x7\n"
+ "beq 25f\n"
+ "movi v25.16b, #0x0\n"
+ "cbz %x[bias], 10f\n"
+ "add x19, %x[bias], x11\n"
+ "tbz %x[n_channels], #2, 7f\n"
+ "ld1 { v25.d }[0], [x19], #0x8\n"
+ "tbz %x[n_channels], #1, 6f\n"
+ "ld1 { v25.s }[2], [x19], #0x4\n"
+ "tbz %x[n_channels], #0, 9f\n"
+ "ld1 { v25.h }[6], [x19], #0x2\n"
+ "b 9f\n"
+ "6:" // Oddments: Load bias: Bit 2: Bit 1: Unset
+ "tbz %x[n_channels], #0, 9f\n"
+ "ld1 { v25.h }[4], [x19], #0x2\n"
+ "b 9f\n"
+ "7:" // Oddments: Load bias: Bit 2: Unset
+ "tbz %x[n_channels], #1, 8f\n"
+ "ld1 { v25.s }[0], [x19], #0x4\n"
+ "tbz %x[n_channels], #0, 9f\n"
+ "ld1 { v25.h }[2], [x19], #0x2\n"
+ "b 9f\n"
+ "8:" // Oddments: Load bias: Bit 2: Unset: Bit 1: Unset
+ "tbz %x[n_channels], #0, 9f\n"
+ "ld1 { v25.h }[0], [x19], #0x2\n"
+ "9:" // Oddments: Load bias: Bit 2: End
+
+ "10:" // Oddments: Load bias: Done
+ "mov v24.16b, v25.16b\n"
+ "ldr q23, [%x[params], #0x0]\n"
+ "mov x20, %x[inptrs]\n"
+ "mov v22.16b, v25.16b\n"
+ "ldp x9, x28, [x20], #0x10\n"
+ "add %x[params], %x[params], #0x10\n"
+ "mov v21.16b, v25.16b\n"
+ "ldp x27, x26, [x20], #0x10\n"
+ "mov v20.16b, v25.16b\n"
+ "add x9, x9, x11\n"
+ "mov v19.16b, v25.16b\n"
+ "ldp x25, x24, [x20], #0x10\n"
+ "mov v18.16b, v25.16b\n"
+ "add x28, x28, x11\n"
+ "mov v17.16b, v25.16b\n"
+ "ldp x23, x22, [x20], #0x10\n"
+ "mov v16.16b, v25.16b\n"
+ "add x27, x27, x11\n"
+ "ldr x21, [x20], #0x8\n"
+ "add x26, x26, x11\n"
+ "add x25, x25, x11\n"
+ "add x24, x24, x11\n"
+ "add x23, x23, x11\n"
+ "add x22, x22, x11\n"
+ "add x21, x21, x11\n"
+ "tbz %x[n_channels], #2, 12f\n"
+ "ldr d2, [x9], #0x8\n"
+ "ldr d1, [x28], #0x8\n"
+ "ldr d0, [x27], #0x8\n"
+ "ldr d31, [x26], #0x8\n"
+ "ldr d30, [x25], #0x8\n"
+ "ldr d29, [x24], #0x8\n"
+ "ldr d28, [x23], #0x8\n"
+ "ldr d27, [x22], #0x8\n"
+ "ldr d26, [x21], #0x8\n"
+ "tbz %x[n_channels], #1, 11f\n"
+ "ld1 { v2.s }[2], [x9], #0x4\n"
+ "ld1 { v1.s }[2], [x28], #0x4\n"
+ "ld1 { v0.s }[2], [x27], #0x4\n"
+ "ld1 { v31.s }[2], [x26], #0x4\n"
+ "ld1 { v30.s }[2], [x25], #0x4\n"
+ "ld1 { v29.s }[2], [x24], #0x4\n"
+ "ld1 { v28.s }[2], [x23], #0x4\n"
+ "ld1 { v27.s }[2], [x22], #0x4\n"
+ "ld1 { v26.s }[2], [x21], #0x4\n"
+ "tbz %x[n_channels], #0, 14f\n"
+ "ld1 { v2.h }[6], [x9], #0x2\n"
+ "ld1 { v1.h }[6], [x28], #0x2\n"
+ "ld1 { v0.h }[6], [x27], #0x2\n"
+ "ld1 { v31.h }[6], [x26], #0x2\n"
+ "ld1 { v30.h }[6], [x25], #0x2\n"
+ "ld1 { v29.h }[6], [x24], #0x2\n"
+ "ld1 { v28.h }[6], [x23], #0x2\n"
+ "ld1 { v27.h }[6], [x22], #0x2\n"
+ "ld1 { v26.h }[6], [x21], #0x2\n"
+ "b 14f\n"
+ "11:" // Oddments: Load: Bit 2: Bit 1: Unset
+ "tbz %x[n_channels], #0, 14f\n"
+ "ld1 { v2.h }[4], [x9], #0x2\n"
+ "ld1 { v1.h }[4], [x28], #0x2\n"
+ "ld1 { v0.h }[4], [x27], #0x2\n"
+ "ld1 { v31.h }[4], [x26], #0x2\n"
+ "ld1 { v30.h }[4], [x25], #0x2\n"
+ "ld1 { v29.h }[4], [x24], #0x2\n"
+ "ld1 { v28.h }[4], [x23], #0x2\n"
+ "ld1 { v27.h }[4], [x22], #0x2\n"
+ "ld1 { v26.h }[4], [x21], #0x2\n"
+ "b 14f\n"
+ "12:" // Oddments: Load: Bit 2: Unset
+ "tbz %x[n_channels], #1, 13f\n"
+ "ldr s2, [x9], #0x4\n"
+ "ldr s1, [x28], #0x4\n"
+ "ldr s0, [x27], #0x4\n"
+ "ldr s31, [x26], #0x4\n"
+ "ldr s30, [x25], #0x4\n"
+ "ldr s29, [x24], #0x4\n"
+ "ldr s28, [x23], #0x4\n"
+ "ldr s27, [x22], #0x4\n"
+ "ldr s26, [x21], #0x4\n"
+ "tbz %x[n_channels], #0, 14f\n"
+ "ld1 { v2.h }[2], [x9], #0x2\n"
+ "ld1 { v1.h }[2], [x28], #0x2\n"
+ "ld1 { v0.h }[2], [x27], #0x2\n"
+ "ld1 { v31.h }[2], [x26], #0x2\n"
+ "ld1 { v30.h }[2], [x25], #0x2\n"
+ "ld1 { v29.h }[2], [x24], #0x2\n"
+ "ld1 { v28.h }[2], [x23], #0x2\n"
+ "ld1 { v27.h }[2], [x22], #0x2\n"
+ "ld1 { v26.h }[2], [x21], #0x2\n"
+ "b 14f\n"
+ "13:" // Oddments: Load: Bit 2: Unset: Bit 1: Unset
+ "tbz %x[n_channels], #0, 14f\n"
+ "ldr h2, [x9], #0x2\n"
+ "ldr h1, [x28], #0x2\n"
+ "ldr h0, [x27], #0x2\n"
+ "ldr h31, [x26], #0x2\n"
+ "ldr h30, [x25], #0x2\n"
+ "ldr h29, [x24], #0x2\n"
+ "ldr h28, [x23], #0x2\n"
+ "ldr h27, [x22], #0x2\n"
+ "ldr h26, [x21], #0x2\n"
+ "14:" // Oddments: Load: Bit 2: End
+ "subs x19, %x[n_points], #0x1\n"
+ "ble 20f\n"
+ "15:" // Oddments: Planar loop
+ "fmla v25.8h, v2.8h, v23.8h\n"
+ "ldp x9, x28, [x20], #0x10\n"
+ "add x9, x9, x11\n"
+ "fmla v24.8h, v1.8h, v23.8h\n"
+ "ldp x27, x26, [x20], #0x10\n"
+ "fmla v22.8h, v0.8h, v23.8h\n"
+ "ldp x25, x24, [x20], #0x10\n"
+ "fmla v21.8h, v31.8h, v23.8h\n"
+ "add x28, x28, x11\n"
+ "fmla v20.8h, v30.8h, v23.8h\n"
+ "ldp x23, x22, [x20], #0x10\n"
+ "fmla v19.8h, v29.8h, v23.8h\n"
+ "add x27, x27, x11\n"
+ "fmla v18.8h, v28.8h, v23.8h\n"
+ "ldr x21, [x20], #0x8\n"
+ "fmla v17.8h, v27.8h, v23.8h\n"
+ "add x26, x26, x11\n"
+ "fmla v16.8h, v26.8h, v23.8h\n"
+ "ldr q23, [%x[params], #0x0]\n"
+ "add x25, x25, x11\n"
+ "add x24, x24, x11\n"
+ "add x23, x23, x11\n"
+ "add x22, x22, x11\n"
+ "add x21, x21, x11\n"
+ "add %x[params], %x[params], #0x10\n"
+ "tbz %x[n_channels], #2, 17f\n"
+ "ldr d2, [x9], #0x8\n"
+ "ldr d1, [x28], #0x8\n"
+ "ldr d0, [x27], #0x8\n"
+ "ldr d31, [x26], #0x8\n"
+ "ldr d30, [x25], #0x8\n"
+ "ldr d29, [x24], #0x8\n"
+ "ldr d28, [x23], #0x8\n"
+ "ldr d27, [x22], #0x8\n"
+ "ldr d26, [x21], #0x8\n"
+ "tbz %x[n_channels], #1, 16f\n"
+ "ld1 { v2.s }[2], [x9], #0x4\n"
+ "ld1 { v1.s }[2], [x28], #0x4\n"
+ "ld1 { v0.s }[2], [x27], #0x4\n"
+ "ld1 { v31.s }[2], [x26], #0x4\n"
+ "ld1 { v30.s }[2], [x25], #0x4\n"
+ "ld1 { v29.s }[2], [x24], #0x4\n"
+ "ld1 { v28.s }[2], [x23], #0x4\n"
+ "ld1 { v27.s }[2], [x22], #0x4\n"
+ "ld1 { v26.s }[2], [x21], #0x4\n"
+ "tbz %x[n_channels], #0, 19f\n"
+ "ld1 { v2.h }[6], [x9], #0x2\n"
+ "ld1 { v1.h }[6], [x28], #0x2\n"
+ "ld1 { v0.h }[6], [x27], #0x2\n"
+ "ld1 { v31.h }[6], [x26], #0x2\n"
+ "ld1 { v30.h }[6], [x25], #0x2\n"
+ "ld1 { v29.h }[6], [x24], #0x2\n"
+ "ld1 { v28.h }[6], [x23], #0x2\n"
+ "ld1 { v27.h }[6], [x22], #0x2\n"
+ "ld1 { v26.h }[6], [x21], #0x2\n"
+ "b 19f\n"
+ "16:" // Oddments: Planar loop: Load: Bit 2: Bit 1: Unset
+ "tbz %x[n_channels], #0, 19f\n"
+ "ld1 { v2.h }[4], [x9], #0x2\n"
+ "ld1 { v1.h }[4], [x28], #0x2\n"
+ "ld1 { v0.h }[4], [x27], #0x2\n"
+ "ld1 { v31.h }[4], [x26], #0x2\n"
+ "ld1 { v30.h }[4], [x25], #0x2\n"
+ "ld1 { v29.h }[4], [x24], #0x2\n"
+ "ld1 { v28.h }[4], [x23], #0x2\n"
+ "ld1 { v27.h }[4], [x22], #0x2\n"
+ "ld1 { v26.h }[4], [x21], #0x2\n"
+ "b 19f\n"
+ "17:" // Oddments: Planar loop: Load: Bit 2: Unset
+ "tbz %x[n_channels], #1, 18f\n"
+ "ldr s2, [x9], #0x4\n"
+ "ldr s1, [x28], #0x4\n"
+ "ldr s0, [x27], #0x4\n"
+ "ldr s31, [x26], #0x4\n"
+ "ldr s30, [x25], #0x4\n"
+ "ldr s29, [x24], #0x4\n"
+ "ldr s28, [x23], #0x4\n"
+ "ldr s27, [x22], #0x4\n"
+ "ldr s26, [x21], #0x4\n"
+ "tbz %x[n_channels], #0, 19f\n"
+ "ld1 { v2.h }[2], [x9], #0x2\n"
+ "ld1 { v1.h }[2], [x28], #0x2\n"
+ "ld1 { v0.h }[2], [x27], #0x2\n"
+ "ld1 { v31.h }[2], [x26], #0x2\n"
+ "ld1 { v30.h }[2], [x25], #0x2\n"
+ "ld1 { v29.h }[2], [x24], #0x2\n"
+ "ld1 { v28.h }[2], [x23], #0x2\n"
+ "ld1 { v27.h }[2], [x22], #0x2\n"
+ "ld1 { v26.h }[2], [x21], #0x2\n"
+ "b 19f\n"
+ "18:" // Oddments: Planar loop: Load: Bit 2: Unset: Bit 1: Unset
+ "tbz %x[n_channels], #0, 19f\n"
+ "ldr h2, [x9], #0x2\n"
+ "ldr h1, [x28], #0x2\n"
+ "ldr h0, [x27], #0x2\n"
+ "ldr h31, [x26], #0x2\n"
+ "ldr h30, [x25], #0x2\n"
+ "ldr h29, [x24], #0x2\n"
+ "ldr h28, [x23], #0x2\n"
+ "ldr h27, [x22], #0x2\n"
+ "ldr h26, [x21], #0x2\n"
+ "19:" // Oddments: Planar loop: Load: Bit 2: End
+ "subs x19, x19, #0x1\n"
+ "bgt 15b\n"
+ "20:" // Oddments: Planar tail
+ "fmla v25.8h, v2.8h, v23.8h\n"
+ "ldp x27, x26, [%x[outptrs], #0x0]\n"
+ "add x27, x27, x11\n"
+ "fmla v24.8h, v1.8h, v23.8h\n"
+ "ldp x25, x24, [%x[outptrs], #0x10]\n"
+ "fmla v22.8h, v0.8h, v23.8h\n"
+ "ldp x23, x22, [%x[outptrs], #0x20]\n"
+ "add x26, x26, x11\n"
+ "fmla v21.8h, v31.8h, v23.8h\n"
+ "ldp x21, x20, [%x[outptrs], #0x30]\n"
+ "fmla v20.8h, v30.8h, v23.8h\n"
+ "ldr x19, [%x[outptrs], #0x40]\n"
+ "add x25, x25, x11\n"
+ "fmla v19.8h, v29.8h, v23.8h\n"
+ "add x24, x24, x11\n"
+ "fmla v18.8h, v28.8h, v23.8h\n"
+ "add x23, x23, x11\n"
+ "fmla v17.8h, v27.8h, v23.8h\n"
+ "add x22, x22, x11\n"
+ "fmla v16.8h, v26.8h, v23.8h\n"
+ "add x21, x21, x11\n"
+ "fmax v25.8h, v25.8h, v4.8h\n"
+ "add x20, x20, x11\n"
+ "fmax v24.8h, v24.8h, v4.8h\n"
+ "add x19, x19, x11\n"
+ "fmax v22.8h, v22.8h, v4.8h\n"
+ "fmin v25.8h, v25.8h, v3.8h\n"
+ "fmin v24.8h, v24.8h, v3.8h\n"
+ "fmin v22.8h, v22.8h, v3.8h\n"
+ "fmax v21.8h, v21.8h, v4.8h\n"
+ "fmax v20.8h, v20.8h, v4.8h\n"
+ "fmax v19.8h, v19.8h, v4.8h\n"
+ "fmin v21.8h, v21.8h, v3.8h\n"
+ "fmin v20.8h, v20.8h, v3.8h\n"
+ "fmin v19.8h, v19.8h, v3.8h\n"
+ "fmax v18.8h, v18.8h, v4.8h\n"
+ "fmax v17.8h, v17.8h, v4.8h\n"
+ "fmax v16.8h, v16.8h, v4.8h\n"
+ "fmin v18.8h, v18.8h, v3.8h\n"
+ "fmin v17.8h, v17.8h, v3.8h\n"
+ "fmin v16.8h, v16.8h, v3.8h\n"
+ "tbz %x[n_channels], #2, 22f\n"
+ "st1 { v25.d }[0], [x27], #0x8\n"
+ "st1 { v24.d }[0], [x26], #0x8\n"
+ "st1 { v22.d }[0], [x25], #0x8\n"
+ "st1 { v21.d }[0], [x24], #0x8\n"
+ "st1 { v20.d }[0], [x23], #0x8\n"
+ "st1 { v19.d }[0], [x22], #0x8\n"
+ "st1 { v18.d }[0], [x21], #0x8\n"
+ "st1 { v17.d }[0], [x20], #0x8\n"
+ "st1 { v16.d }[0], [x19], #0x8\n"
+ "tbz %x[n_channels], #1, 21f\n"
+ "st1 { v25.s }[2], [x27], #0x4\n"
+ "st1 { v24.s }[2], [x26], #0x4\n"
+ "st1 { v22.s }[2], [x25], #0x4\n"
+ "st1 { v21.s }[2], [x24], #0x4\n"
+ "st1 { v20.s }[2], [x23], #0x4\n"
+ "st1 { v19.s }[2], [x22], #0x4\n"
+ "st1 { v18.s }[2], [x21], #0x4\n"
+ "st1 { v17.s }[2], [x20], #0x4\n"
+ "st1 { v16.s }[2], [x19], #0x4\n"
+ "tbz %x[n_channels], #0, 24f\n"
+ "st1 { v25.h }[6], [x27], #0x2\n"
+ "st1 { v24.h }[6], [x26], #0x2\n"
+ "st1 { v22.h }[6], [x25], #0x2\n"
+ "st1 { v21.h }[6], [x24], #0x2\n"
+ "st1 { v20.h }[6], [x23], #0x2\n"
+ "st1 { v19.h }[6], [x22], #0x2\n"
+ "st1 { v18.h }[6], [x21], #0x2\n"
+ "st1 { v17.h }[6], [x20], #0x2\n"
+ "st1 { v16.h }[6], [x19], #0x2\n"
+ "b 24f\n"
+ "21:" // Oddments: Store: Bit 2: Bit 1: Unset
+ "tbz %x[n_channels], #0, 24f\n"
+ "st1 { v25.h }[4], [x27], #0x2\n"
+ "st1 { v24.h }[4], [x26], #0x2\n"
+ "st1 { v22.h }[4], [x25], #0x2\n"
+ "st1 { v21.h }[4], [x24], #0x2\n"
+ "st1 { v20.h }[4], [x23], #0x2\n"
+ "st1 { v19.h }[4], [x22], #0x2\n"
+ "st1 { v18.h }[4], [x21], #0x2\n"
+ "st1 { v17.h }[4], [x20], #0x2\n"
+ "st1 { v16.h }[4], [x19], #0x2\n"
+ "b 24f\n"
+ "22:" // Oddments: Store: Bit 2: Unset
+ "tbz %x[n_channels], #1, 23f\n"
+ "st1 { v25.s }[0], [x27], #0x4\n"
+ "st1 { v24.s }[0], [x26], #0x4\n"
+ "st1 { v22.s }[0], [x25], #0x4\n"
+ "st1 { v21.s }[0], [x24], #0x4\n"
+ "st1 { v20.s }[0], [x23], #0x4\n"
+ "st1 { v19.s }[0], [x22], #0x4\n"
+ "st1 { v18.s }[0], [x21], #0x4\n"
+ "st1 { v17.s }[0], [x20], #0x4\n"
+ "st1 { v16.s }[0], [x19], #0x4\n"
+ "tbz %x[n_channels], #0, 24f\n"
+ "st1 { v25.h }[2], [x27], #0x2\n"
+ "st1 { v24.h }[2], [x26], #0x2\n"
+ "st1 { v22.h }[2], [x25], #0x2\n"
+ "st1 { v21.h }[2], [x24], #0x2\n"
+ "st1 { v20.h }[2], [x23], #0x2\n"
+ "st1 { v19.h }[2], [x22], #0x2\n"
+ "st1 { v18.h }[2], [x21], #0x2\n"
+ "st1 { v17.h }[2], [x20], #0x2\n"
+ "st1 { v16.h }[2], [x19], #0x2\n"
+ "b 24f\n"
+ "23:" // Oddments: Store: Bit 2: Unset: Bit 1: Unset
+ "tbz %x[n_channels], #0, 24f\n"
+ "st1 { v25.h }[0], [x27], #0x2\n"
+ "st1 { v24.h }[0], [x26], #0x2\n"
+ "st1 { v22.h }[0], [x25], #0x2\n"
+ "st1 { v21.h }[0], [x24], #0x2\n"
+ "st1 { v20.h }[0], [x23], #0x2\n"
+ "st1 { v19.h }[0], [x22], #0x2\n"
+ "st1 { v18.h }[0], [x21], #0x2\n"
+ "st1 { v17.h }[0], [x20], #0x2\n"
+ "st1 { v16.h }[0], [x19], #0x2\n"
+ "24:" // Oddments: Store: Bit 2: End
+
+ "25:" // End
+
+ : [params] "+&r" (params)
+ : [bias] "r" (bias), [inptrs] "r" (inptrs), [minmax_vals] "r" (minmax_vals), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [outptrs] "r" (outptrs)
+ : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ );
+}
+
+} // namespace depthwise
+} // namespace arm_conv
+
+#endif // defined(__ARM_FP16_ARGS) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
generated by cgit v1.2.1 (git 2.23.0) at 2024-04-27 08:31:32 +0000