First commit of tosa serialize passes

Signed-off-by: Kevin Cheng <kevin.cheng@arm.com>
Change-Id: I1551017706f6e8af604792f48cdeb49b4da7ef0d

3 files changed, 172 insertions, 0 deletions

diff --git a/include/SerializationPasses.h b/include/SerializationPasses.h
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+++ b/include/SerializationPasses.h
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+
+// Copyright (c) 2020-2021, ARM Limited.
+//
+//    Licensed under the Apache License, Version 2.0 with LLVM Exceptions
+//    (the "License"); you may not use this file except in compliance with
+//    the License. You may obtain a copy of the License at
+//
+//         https://llvm.org/LICENSE.txt
+//
+//    Unless required by applicable law or agreed to in writing, software
+//    distributed under the License is distributed on an "AS IS" BASIS,
+//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//    See the License for the specific language governing permissions and
+//    limitations under the License.
+
+#ifndef INCLUDE_SERIALIZATION_PASSES_H
+#define INCLUDE_SERIALIZATION_PASSES_H
+
+#include <memory>
+
+#include "mlir/Pass/Pass.h" // from @llvm-project
+
+namespace mlir {
+namespace tosa {
+
+std::unique_ptr<OperationPass<FuncOp>> createTosaSerializePass();
+
+#define GEN_PASS_REGISTRATION
+#include "SerializationPasses.h.inc"
+
+} // namespace tosa
+} // namespace mlir
+
+#endif // INCLUDE_SERIALIZATION_PASSES_H
diff --git a/include/SerializationPasses.td b/include/SerializationPasses.td
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+++ b/include/SerializationPasses.td
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+// Copyright (c) 2020-2021, ARM Limited.
+//
+//    Licensed under the Apache License, Version 2.0 with LLVM Exceptions 
+//    (the "License"); you may not use this file except in compliance with 
+//    the License. You may obtain a copy of the License at
+//
+//         https://llvm.org/LICENSE.txt
+//
+//    Unless required by applicable law or agreed to in writing, software
+//    distributed under the License is distributed on an "AS IS" BASIS,
+//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//    See the License for the specific language governing permissions and
+//    limitations under the License.
+
+include "mlir/Pass/PassBase.td"
+
+def TosaSerializationPass : Pass<"tosa-serialize", "FuncOp"> {
+  let summary = "Generate TOSA flatbuffer serialized form";
+  let constructor = "createTosaSerializePass()";
+}
+
diff --git a/include/operator.def b/include/operator.def
new file mode 100644
index 0000000..85bb5c9
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+++ b/include/operator.def
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+
+// Copyright (c) 2020-2021, ARM Limited.
+//
+//    Licensed under the Apache License, Version 2.0 with LLVM Exceptions 
+//    (the "License"); you may not use this file except in compliance with 
+//    the License. You may obtain a copy of the License at
+//
+//         https://llvm.org/LICENSE.txt
+//
+//    Unless required by applicable law or agreed to in writing, software
+//    distributed under the License is distributed on an "AS IS" BASIS,
+//    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+//    See the License for the specific language governing permissions and
+//    limitations under the License.
+
+/*
+  Syntax:
+    DEF_OPERATOR(MLIR_OP)
+
+  Description:
+    MLIR_OP: the operator class type, must match mlir/include/mlir/Dialect/Tosa/IR/tosa_ops.td in llvm-project repo
+*/
+
+/* tensor operators */
+DEF_OPERATOR(ArgMax)
+DEF_OPERATOR(AvgPool2d)
+DEF_OPERATOR(Conv2D)
+DEF_OPERATOR(Conv3D)
+DEF_OPERATOR(DepthwiseConv2D)
+DEF_OPERATOR(FullyConnected)
+DEF_OPERATOR(MatMul)
+DEF_OPERATOR(MaxPool2d)
+DEF_OPERATOR(TransposeConv2D)
+
+/* activation */
+DEF_OPERATOR(Clamp)
+DEF_OPERATOR(Sigmoid)
+DEF_OPERATOR(Tanh)
+
+/* elementwise - binary */
+DEF_OPERATOR(Add)
+DEF_OPERATOR(ArithmeticRightShift)
+DEF_OPERATOR(BitwiseAnd)
+DEF_OPERATOR(BitwiseOr)
+DEF_OPERATOR(BitwiseXor)
+DEF_OPERATOR(Div)
+DEF_OPERATOR(LogicalAnd)
+DEF_OPERATOR(LogicalLeftShift)
+DEF_OPERATOR(LogicalRightShift)
+DEF_OPERATOR(LogicalOr)
+DEF_OPERATOR(LogicalXor)
+DEF_OPERATOR(Maximum)
+DEF_OPERATOR(Minimum)
+DEF_OPERATOR(Mul)
+DEF_OPERATOR(Pow)
+DEF_OPERATOR(Sub)
+DEF_OPERATOR(Table)
+
+/* elementwise - unary */
+DEF_OPERATOR(Abs)
+DEF_OPERATOR(BitwiseNot)
+DEF_OPERATOR(Ceil)
+DEF_OPERATOR(Clz)
+DEF_OPERATOR(Exp)
+DEF_OPERATOR(Floor)
+DEF_OPERATOR(Log)
+DEF_OPERATOR(LogicalNot)
+DEF_OPERATOR(Negate)
+DEF_OPERATOR(Reciprocal)
+DEF_OPERATOR(Rsqrt)
+
+/* elementwise - ternary */
+DEF_OPERATOR(Select)
+
+/* logical */
+DEF_OPERATOR(Equal)
+DEF_OPERATOR(Greater)
+DEF_OPERATOR(GreaterEqual)
+
+/* reduction */
+DEF_OPERATOR(ReduceAny)
+DEF_OPERATOR(ReduceAll)
+DEF_OPERATOR(ReduceMax)
+DEF_OPERATOR(ReduceMin)
+DEF_OPERATOR(ReduceProd)
+DEF_OPERATOR(ReduceSum)
+
+/* memory operation */
+DEF_OPERATOR(Concat)
+DEF_OPERATOR(Pad)
+DEF_OPERATOR(Reshape)
+DEF_OPERATOR(Reverse)
+DEF_OPERATOR(Slice)
+DEF_OPERATOR(Tile)
+DEF_OPERATOR(Transpose)
+
+/* gather/scatter */
+DEF_OPERATOR(Gather)
+DEF_OPERATOR(Scatter)
+
+/* image */
+DEF_OPERATOR(Resize)
+
+/* quantization */
+DEF_OPERATOR(Cast)
+DEF_OPERATOR(Rescale)
+
+/* data nodes */
+DEF_OPERATOR(Const)
+DEF_OPERATOR(Identity)
+
+/* custom operations */
+DEF_OPERATOR(Custom)
+
+/* control flow operators */
+DEF_OPERATOR(If)
+DEF_OPERATOR(While)