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authorKshitij Sisodia <kshitij.sisodia@arm.com>2022-06-10 17:19:22 +0100
committerKshitij Sisodia <kshitij.sisodia@arm.com>2022-06-10 17:19:22 +0100
commitff57034bc65054d8c39950ba3960f8463211f081 (patch)
tree4dcb8c7b4c36f0042850a5af189e1c82c02ae6b4 /source/hal/source/platform/mps3/source/platform_drivers.c
parent19c91fe392903a7367c53cfe83278eb6a465b3d6 (diff)
downloadml-embedded-evaluation-kit-ff57034bc65054d8c39950ba3960f8463211f081.tar.gz
MLCE-864: Enabling I-Cache and D-Cache for MPS322.05
Both supported implementation on MPS3 (Arm Corstone-300 and Arm Corstone-310) will now have caches enabled. Also including a minor change left over from refactoring of code for HAL components. Change-Id: Ie5768cd26eef9083a817bca7c87ff691dae67fca
Diffstat (limited to 'source/hal/source/platform/mps3/source/platform_drivers.c')
-rw-r--r--source/hal/source/platform/mps3/source/platform_drivers.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c
index 801cd0b..7c5de6d 100644
--- a/source/hal/source/platform/mps3/source/platform_drivers.c
+++ b/source/hal/source/platform/mps3/source/platform_drivers.c
@@ -65,6 +65,16 @@ int platform_init(void)
return err;
}
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ info("Enabling I-cache.\n");
+ SCB_EnableICache();
+#endif /* __ICACHE_PRESENT */
+
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ info("Enabling D-cache.\n");
+ SCB_EnableDCache();
+#endif /* __DCACHE_PRESENT */
+
#if defined(ARM_NPU)
#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)