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| author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2022-06-10 17:19:22 +0100 |
|---|---|---|
| committer | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2022-06-10 17:19:22 +0100 |
| commit | ff57034bc65054d8c39950ba3960f8463211f081 (patch) | |
| tree | 4dcb8c7b4c36f0042850a5af189e1c82c02ae6b4 | |
| parent | 19c91fe392903a7367c53cfe83278eb6a465b3d6 (diff) | |
| download | ml-embedded-evaluation-kit-ff57034bc65054d8c39950ba3960f8463211f081.tar.gz | |
MLCE-864: Enabling I-Cache and D-Cache for MPS322.05
Both supported implementation on MPS3 (Arm Corstone-300 and
Arm Corstone-310) will now have caches enabled.
Also including a minor change left over from refactoring of
code for HAL components.
Change-Id: Ie5768cd26eef9083a817bca7c87ff691dae67fca
| -rw-r--r-- | source/hal/source/components/lcd/source/lcd_img.c | 31 | ||||
| -rw-r--r-- | source/hal/source/platform/mps3/source/platform_drivers.c | 10 |
2 files changed, 12 insertions, 29 deletions
diff --git a/source/hal/source/components/lcd/source/lcd_img.c b/source/hal/source/components/lcd/source/lcd_img.c index 92069c2..d438324 100644 --- a/source/hal/source/components/lcd/source/lcd_img.c +++ b/source/hal/source/components/lcd/source/lcd_img.c @@ -24,36 +24,9 @@ static int show_title(void) { - char title[128]; - int status = 0; - - /* LCD title string */ -#if defined(CPU_CORTEX_M55) - const char* cpu_name = "Arm Cortex-M55"; -#elif defined (ARMv81MML_DSP_DP_MVE_FP) - const char* cpu_name = "ARMv8.1-M CPU"; -#else /* defined(CPU_CORTEX_M55) */ - const char* cpu_name = "Arm CPU"; -#endif /* defined(CPU_CORTEX_M55) */ - + const char title[] = "Arm ML embedded code samples"; lcd_set_text_color(White); - - /* First line */ - snprintf(title, sizeof(title), "Arm ML embedded code samples"); - - if (0 != (status = lcd_display_text( - title, strlen(title), 10, 0, false))) { - return status; - } - - /* Second line */ -#if defined (ARM_NPU) - snprintf(title, sizeof(title), "%s + Arm Ethos-U NPU", cpu_name); -#else /* defined (ARM_NPU) */ - snprintf(title, sizeof(title), "%s", cpu_name); -#endif /* defined (ARM_NPU) */ - - return lcd_display_text(title, strlen(title), 10, 20, false); + return lcd_display_text(title, strlen(title), 10, 0, false); } int lcd_init(void) diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c index 801cd0b..7c5de6d 100644 --- a/source/hal/source/platform/mps3/source/platform_drivers.c +++ b/source/hal/source/platform/mps3/source/platform_drivers.c @@ -65,6 +65,16 @@ int platform_init(void) return err; } +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + info("Enabling I-cache.\n"); + SCB_EnableICache(); +#endif /* __ICACHE_PRESENT */ + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + info("Enabling D-cache.\n"); + SCB_EnableDCache(); +#endif /* __DCACHE_PRESENT */ + #if defined(ARM_NPU) #if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) |