From ff57034bc65054d8c39950ba3960f8463211f081 Mon Sep 17 00:00:00 2001 From: Kshitij Sisodia Date: Fri, 10 Jun 2022 17:19:22 +0100 Subject: MLCE-864: Enabling I-Cache and D-Cache for MPS3 Both supported implementation on MPS3 (Arm Corstone-300 and Arm Corstone-310) will now have caches enabled. Also including a minor change left over from refactoring of code for HAL components. Change-Id: Ie5768cd26eef9083a817bca7c87ff691dae67fca --- source/hal/source/platform/mps3/source/platform_drivers.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'source/hal/source/platform/mps3/source/platform_drivers.c') diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c index 801cd0b..7c5de6d 100644 --- a/source/hal/source/platform/mps3/source/platform_drivers.c +++ b/source/hal/source/platform/mps3/source/platform_drivers.c @@ -65,6 +65,16 @@ int platform_init(void) return err; } +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + info("Enabling I-cache.\n"); + SCB_EnableICache(); +#endif /* __ICACHE_PRESENT */ + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + info("Enabling D-cache.\n"); + SCB_EnableDCache(); +#endif /* __DCACHE_PRESENT */ + #if defined(ARM_NPU) #if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) -- cgit v1.2.1