1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
|
/*
* Copyright (c) 2021 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <cstddef>
#include <cstdint>
namespace arm_conv {
namespace pooling {
void a64_u8_nhwc_max_2x2_s1_output2x2_depthfirst_impl(
const unsigned int n_channels,
const uint8_t *const *const inptrs,
uint8_t *const *const outptrs,
const bool exclude_padding,
const unsigned int pad_left,
const unsigned int pad_top,
const unsigned int pad_right,
const unsigned int pad_bottom
)
{
struct KernelArgs
{
const uint64_t n_channels;
const uint8_t *const *const inptrs;
uint8_t *const *const outptrs;
KernelArgs(
unsigned int channels,
const uint8_t *const *input_ptrs,
uint8_t *const * output_ptrs,
bool, unsigned int, unsigned int, unsigned int, unsigned int
) : n_channels(channels),
inptrs(input_ptrs),
outptrs(output_ptrs)
{
}
};
const KernelArgs args(n_channels, inptrs, outptrs, exclude_padding,
pad_left, pad_top, pad_right, pad_bottom);
__asm__ __volatile__(
"ldr x15, [%x[args], %[offsetof_n_channels]]\n"
"mov x14, #0x0\n"
"ldr x20, [%x[args], %[offsetof_outptrs]]\n"
"mov x13, #0x0\n"
"ldr x19, [%x[args], %[offsetof_inptrs]]\n"
"cmp x15, #0x10\n"
"ldp x12, x11, [x20, #0x0]\n"
"ldp x10, x9, [x20, #0x10]\n"
"ldp x28, x27, [x19, #0x0]\n"
"ldp x26, x25, [x19, #0x10]\n"
"ldp x24, x23, [x19, #0x20]\n"
"ldp x22, x21, [x19, #0x30]\n"
"ldr x20, [x19, #0x40]\n"
"blt 3f\n"
"ldr q30, [x27, x14]\n"
"lsr x19, x15, #0x4\n"
"ldr q29, [x24, x14]\n"
"sub x15, x15, x19, LSL #4\n"
"ldr q28, [x21, x14]\n"
"subs x19, x19, #0x1\n"
"ldr q27, [x25, x14]\n"
"ldr q26, [x28, x14]\n"
"ldr q25, [x23, x14]\n"
"ldr q24, [x26, x14]\n"
"ldr q23, [x22, x14]\n"
"ldr q22, [x20, x14]\n"
"add x14, x14, #0x10\n"
"beq 2f\n"
"1:" // Vector: Loop
"umax v21.16b, v30.16b, v29.16b\n"
"ldr q30, [x27, x14]\n"
"subs x19, x19, #0x1\n"
"umax v20.16b, v29.16b, v28.16b\n"
"ldr q29, [x24, x14]\n"
"umax v19.16b, v27.16b, v26.16b\n"
"ldr q28, [x21, x14]\n"
"umax v18.16b, v25.16b, v24.16b\n"
"ldr q26, [x28, x14]\n"
"umax v17.16b, v23.16b, v27.16b\n"
"ldr q27, [x25, x14]\n"
"umax v16.16b, v25.16b, v22.16b\n"
"ldr q25, [x23, x14]\n"
"umax v19.16b, v21.16b, v19.16b\n"
"ldr q24, [x26, x14]\n"
"umax v18.16b, v21.16b, v18.16b\n"
"ldr q23, [x22, x14]\n"
"umax v17.16b, v20.16b, v17.16b\n"
"ldr q22, [x20, x14]\n"
"add x14, x14, #0x10\n"
"umax v16.16b, v20.16b, v16.16b\n"
"str q19, [x12, x13]\n"
"str q18, [x11, x13]\n"
"str q17, [x10, x13]\n"
"str q16, [x9, x13]\n"
"add x13, x13, #0x10\n"
"bgt 1b\n"
"2:" // Vector: Tail
"umax v21.16b, v30.16b, v29.16b\n"
"umax v20.16b, v29.16b, v28.16b\n"
"umax v19.16b, v27.16b, v26.16b\n"
"umax v18.16b, v25.16b, v24.16b\n"
"umax v17.16b, v23.16b, v27.16b\n"
"umax v16.16b, v25.16b, v22.16b\n"
"umax v19.16b, v21.16b, v19.16b\n"
"str q19, [x12, x13]\n"
"umax v18.16b, v21.16b, v18.16b\n"
"umax v17.16b, v20.16b, v17.16b\n"
"str q18, [x11, x13]\n"
"umax v16.16b, v20.16b, v16.16b\n"
"str q17, [x10, x13]\n"
"str q16, [x9, x13]\n"
"add x13, x13, #0x10\n"
"cbz x15, 4f\n"
"3:" // Oddments
"ldr b30, [x27, x14]\n"
"subs x15, x15, #0x1\n"
"ldr b29, [x24, x14]\n"
"umax v21.16b, v30.16b, v29.16b\n"
"ldr b28, [x21, x14]\n"
"ldr b27, [x25, x14]\n"
"umax v20.16b, v29.16b, v28.16b\n"
"ldr b26, [x28, x14]\n"
"ldr b25, [x23, x14]\n"
"umax v19.16b, v27.16b, v26.16b\n"
"ldr b24, [x26, x14]\n"
"ldr b23, [x22, x14]\n"
"umax v19.16b, v21.16b, v19.16b\n"
"ldr b22, [x20, x14]\n"
"add x14, x14, #0x1\n"
"umax v18.16b, v25.16b, v24.16b\n"
"str b19, [x12, x13]\n"
"umax v17.16b, v23.16b, v27.16b\n"
"umax v16.16b, v25.16b, v22.16b\n"
"umax v18.16b, v21.16b, v18.16b\n"
"str b18, [x11, x13]\n"
"umax v17.16b, v20.16b, v17.16b\n"
"umax v16.16b, v20.16b, v16.16b\n"
"str b17, [x10, x13]\n"
"str b16, [x9, x13]\n"
"add x13, x13, #0x1\n"
"bgt 3b\n"
"4:" // End
:
: [args] "r" (&args), [offsetof_inptrs] "I" (offsetof(KernelArgs, inptrs)), [offsetof_n_channels] "I" (offsetof(KernelArgs, n_channels)), [offsetof_outptrs] "I" (offsetof(KernelArgs, outptrs))
: "cc", "memory", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
} // namespace pooling
} // namespace arm_conv
|
