diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/transforms')
17 files changed, 2946 insertions, 1 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/transforms/list-sve.hpp b/src/core/NEON/kernels/arm_gemm/transforms/list-sve.hpp index 895177b6cc..c066c01bab 100644 --- a/src/core/NEON/kernels/arm_gemm/transforms/list-sve.hpp +++ b/src/core/NEON/kernels/arm_gemm/transforms/list-sve.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,6 +21,24 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ +#ifdef ARM_COMPUTE_ENABLE_SME +#include "sme_transpose_interleave_16VL_1x4.hpp" +#include "sme_transpose_interleave_16VL_2x2_fp32bf16.hpp" +#include "sme_transpose_interleave_16VL_2x2.hpp" +#include "sme_transpose_interleave_16VL.hpp" +#include "sme_transpose_interleave_1VL_1x4.hpp" +#include "sme_transpose_interleave_1VL_2x2_fp32bf16.hpp" +#include "sme_transpose_interleave_1VL_2x2.hpp" +#include "sme_transpose_interleave_1VL.hpp" +#include "sme_transpose_interleave_2VL_1x4.hpp" +#include "sme_transpose_interleave_2VL_2x2.hpp" +#include "sme_transpose_interleave_2VL_2x2_fp32bf16.hpp" +#include "sme_transpose_interleave_2VL.hpp" +#include "sme_transpose_interleave_4VL_1x4.hpp" +#include "sme_transpose_interleave_4VL_2x2.hpp" +#include "sme_transpose_interleave_4VL_2x2_fp32bf16.hpp" +#include "sme_transpose_interleave_4VL.hpp" +#endif // ARM_COMPUTE_ENABLE_SME #include "sve_transpose_interleave_12VL_2x4_fp32bf16.hpp" #include "sve_transpose_interleave_1VL_1x4.hpp" #include "sve_transpose_interleave_1VL.hpp" diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL.hpp new file mode 100644 index 0000000000..3475d30abc --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL.hpp @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_16VL(uint32_t *out, const uint32_t *in, size_t width, size_t in_stride, size_t height) +{ + size_t out_stride = 16 * height * sme::get_vector_length<uint8_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p7.b\n" + "1:" // Main row loop: Head + "mov x22, %x[in]\n" + "add %x[in], x22, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x1\n" + "mov x20, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x19, x20\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z31.s }, p0/Z, [x22]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z30.s }, p0/Z, [x22, #1, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z29.s }, p0/Z, [x22, #2, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z28.s }, p0/Z, [x22, #3, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z27.s }, p0/Z, [x22, #4, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z26.s }, p0/Z, [x22, #5, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z25.s }, p0/Z, [x22, #6, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z24.s }, p0/Z, [x22, #7, MUL VL]\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "decw x19\n" + "whilelt p6.s, XZR, x19\n" + "decw x19\n" + "whilelt p5.s, XZR, x19\n" + "decw x19\n" + "whilelt p4.s, XZR, x19\n" + "decw x19\n" + "whilelt p3.s, XZR, x19\n" + "decw x19\n" + "whilelt p2.s, XZR, x19\n" + "decw x19\n" + "whilelt p1.s, XZR, x19\n" + "decw x19\n" + "addvl x22, x22, #16\n" + "ld1w { z23.s }, p0/Z, [x22, #-8, MUL VL]\n" + "whilelt p0.s, XZR, x19\n" + "mov x19, x21\n" + "ld1w { z22.s }, p6/Z, [x22, #-7, MUL VL]\n" + "decw x20, ALL, MUL #16\n" + "ld1w { z21.s }, p5/Z, [x22, #-6, MUL VL]\n" + "cmp x20, #0x0\n" + "ld1w { z20.s }, p4/Z, [x22, #-5, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "ld1w { z19.s }, p3/Z, [x22, #-4, MUL VL]\n" + "ld1w { z18.s }, p2/Z, [x22, #-3, MUL VL]\n" + "ld1w { z17.s }, p1/Z, [x22, #-2, MUL VL]\n" + "ld1w { z16.s }, p0/Z, [x22, #-1, MUL VL]\n" + "st1w { z31.s }, p7, [x19]\n" + "st1w { z30.s }, p7, [x19, #1, MUL VL]\n" + "st1w { z29.s }, p7, [x19, #2, MUL VL]\n" + "st1w { z28.s }, p7, [x19, #3, MUL VL]\n" + "st1w { z27.s }, p7, [x19, #4, MUL VL]\n" + "st1w { z26.s }, p7, [x19, #5, MUL VL]\n" + "st1w { z25.s }, p7, [x19, #6, MUL VL]\n" + "st1w { z24.s }, p7, [x19, #7, MUL VL]\n" + "addvl x19, x19, #16\n" + "st1w { z23.s }, p7, [x19, #-8, MUL VL]\n" + "st1w { z22.s }, p7, [x19, #-7, MUL VL]\n" + "st1w { z21.s }, p7, [x19, #-6, MUL VL]\n" + "st1w { z20.s }, p7, [x19, #-5, MUL VL]\n" + "st1w { z19.s }, p7, [x19, #-4, MUL VL]\n" + "st1w { z18.s }, p7, [x19, #-3, MUL VL]\n" + "st1w { z17.s }, p7, [x19, #-2, MUL VL]\n" + "st1w { z16.s }, p7, [x19, #-1, MUL VL]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #16\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<16, 1, true, VLType::SME>( + float *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_16VL( + reinterpret_cast<uint32_t *>(out), + reinterpret_cast<const uint32_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(float) / 4, + stride * sizeof(float), + (kmax-k0) + ); +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_1x4.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_1x4.hpp new file mode 100644 index 0000000000..fc3c4ab0fc --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_1x4.hpp @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_16VL_1x4(uint8_t *out, const uint8_t *in, size_t width, size_t in_stride, size_t height) +{ + uint8_t *pad_row = reinterpret_cast<uint8_t *>(alloca(width * sizeof(uint8_t))); + + if (height % 4) { + memset(pad_row, 0, width * sizeof(uint8_t)); + } + + size_t out_stride = 16 * roundup<size_t>(height, 4) * sme::get_vector_length<uint32_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p4.b\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "cmp %x[height], #0x3\n" + "add %x[in], x22, %x[in_stride]\n" + "csel x22, x22, %x[pad_row], GT\n" + "csel x23, x23, %x[pad_row], GE\n" + "cmp %x[height], #0x1\n" + "mov x21, %x[out]\n" + "csel x24, x24, %x[pad_row], GT\n" + "sub %x[height], %x[height], #0x4\n" + "mov x20, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x19, x20\n" + "whilelt p3.b, XZR, x19\n" + "ld1b { z20.b }, p3/Z, [x25]\n" + "decb x19\n" + "whilelt p2.b, XZR, x19\n" + "ld1b { z18.b }, p2/Z, [x25, #1, MUL VL]\n" + "decb x19\n" + "whilelt p1.b, XZR, x19\n" + "ld1b { z17.b }, p3/Z, [x24]\n" + "decb x19\n" + "whilelt p0.b, XZR, x19\n" + "ld1b { z19.b }, p2/Z, [x24, #1, MUL VL]\n" + "ld1b { z16.b }, p3/Z, [x23]\n" + "zip1 z25.b, z20.b, z16.b\n" + "zip2 z24.b, z20.b, z16.b\n" + "mov x19, x21\n" + "ld1b { z16.b }, p2/Z, [x23, #1, MUL VL]\n" + "zip1 z22.b, z18.b, z16.b\n" + "zip2 z21.b, z18.b, z16.b\n" + "decw x20, ALL, MUL #16\n" + "ld1b { z16.b }, p3/Z, [x22]\n" + "zip1 z18.b, z17.b, z16.b\n" + "zip2 z17.b, z17.b, z16.b\n" + "cmp x20, #0x0\n" + "ld1b { z16.b }, p2/Z, [x22, #1, MUL VL]\n" + "zip1 z20.b, z19.b, z16.b\n" + "zip2 z16.b, z19.b, z16.b\n" + "add x21, x21, %x[out_stride]\n" + "ld1b { z19.b }, p1/Z, [x25, #2, MUL VL]\n" + "zip1 z23.b, z25.b, z18.b\n" + "zip2 z0.b, z25.b, z18.b\n" + "ld1b { z18.b }, p0/Z, [x25, #3, MUL VL]\n" + "zip1 z31.b, z24.b, z17.b\n" + "zip2 z30.b, z24.b, z17.b\n" + "addvl x25, x25, #4\n" + "ld1b { z17.b }, p1/Z, [x24, #2, MUL VL]\n" + "zip1 z29.b, z22.b, z20.b\n" + "zip2 z28.b, z22.b, z20.b\n" + "ld1b { z22.b }, p0/Z, [x24, #3, MUL VL]\n" + "zip1 z27.b, z21.b, z16.b\n" + "zip2 z26.b, z21.b, z16.b\n" + "addvl x24, x24, #4\n" + "ld1b { z16.b }, p1/Z, [x23, #2, MUL VL]\n" + "zip1 z21.b, z19.b, z16.b\n" + "zip2 z20.b, z19.b, z16.b\n" + "ld1b { z16.b }, p0/Z, [x23, #3, MUL VL]\n" + "zip1 z25.b, z18.b, z16.b\n" + "zip2 z24.b, z18.b, z16.b\n" + "addvl x23, x23, #4\n" + "ld1b { z16.b }, p1/Z, [x22, #2, MUL VL]\n" + "zip1 z19.b, z17.b, z16.b\n" + "zip2 z18.b, z17.b, z16.b\n" + "ld1b { z16.b }, p0/Z, [x22, #3, MUL VL]\n" + "zip1 z17.b, z22.b, z16.b\n" + "zip2 z16.b, z22.b, z16.b\n" + "addvl x22, x22, #4\n" + "st1b { z23.b }, p4, [x19]\n" + "zip1 z23.b, z21.b, z19.b\n" + "zip2 z22.b, z21.b, z19.b\n" + "st1b { z0.b }, p4, [x19, #1, MUL VL]\n" + "zip1 z21.b, z20.b, z18.b\n" + "zip2 z20.b, z20.b, z18.b\n" + "st1b { z31.b }, p4, [x19, #2, MUL VL]\n" + "zip1 z19.b, z25.b, z17.b\n" + "zip2 z18.b, z25.b, z17.b\n" + "st1b { z30.b }, p4, [x19, #3, MUL VL]\n" + "zip1 z17.b, z24.b, z16.b\n" + "zip2 z16.b, z24.b, z16.b\n" + "st1b { z29.b }, p4, [x19, #4, MUL VL]\n" + "st1b { z28.b }, p4, [x19, #5, MUL VL]\n" + "st1b { z27.b }, p4, [x19, #6, MUL VL]\n" + "st1b { z26.b }, p4, [x19, #7, MUL VL]\n" + "addvl x19, x19, #16\n" + "st1b { z23.b }, p4, [x19, #-8, MUL VL]\n" + "st1b { z22.b }, p4, [x19, #-7, MUL VL]\n" + "st1b { z21.b }, p4, [x19, #-6, MUL VL]\n" + "st1b { z20.b }, p4, [x19, #-5, MUL VL]\n" + "st1b { z19.b }, p4, [x19, #-4, MUL VL]\n" + "st1b { z18.b }, p4, [x19, #-3, MUL VL]\n" + "st1b { z17.b }, p4, [x19, #-2, MUL VL]\n" + "st1b { z16.b }, p4, [x19, #-1, MUL VL]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #16\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<16, 4, true, VLType::SME>( + uint8_t *out, const uint8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_16VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(uint8_t) / 1, + stride * sizeof(uint8_t), + (kmax-k0) + ); +} + +template<> +void Transform<16, 4, true, VLType::SME>( + int8_t *out, const int8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_16VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(int8_t) / 1, + stride * sizeof(int8_t), + (kmax-k0) + ); +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_2x2.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_2x2.hpp new file mode 100644 index 0000000000..af1649fc8a --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_2x2.hpp @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_16VL_2x2(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + uint16_t *pad_row = reinterpret_cast<uint16_t *>(alloca(width * sizeof(uint16_t))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(uint16_t)); + } + + size_t out_stride = 16 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p5.b\n" + "1:" // Main row loop: Head + "mov x23, %x[in]\n" + "add x22, x23, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "add %x[in], x22, %x[in_stride]\n" + "mov x21, %x[out]\n" + "csel x22, x22, %x[pad_row], GT\n" + "sub %x[height], %x[height], #0x2\n" + "mov x20, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x19, x20\n" + "whilelt p2.h, XZR, x19\n" + "ld1h { z17.h }, p2/Z, [x23]\n" + "dech x19\n" + "whilelt p1.h, XZR, x19\n" + "ld1h { z19.h }, p1/Z, [x23, #1, MUL VL]\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z21.h }, p0/Z, [x23, #2, MUL VL]\n" + "dech x19\n" + "whilelt p4.h, XZR, x19\n" + "ld1h { z20.h }, p4/Z, [x23, #3, MUL VL]\n" + "dech x19\n" + "whilelt p3.h, XZR, x19\n" + "ld1h { z16.h }, p2/Z, [x22]\n" + "zip1 z0.h, z17.h, z16.h\n" + "dech x19\n" + "whilelt p2.h, XZR, x19\n" + "ld1h { z18.h }, p1/Z, [x22, #1, MUL VL]\n" + "zip2 z31.h, z17.h, z16.h\n" + "dech x19\n" + "whilelt p1.h, XZR, x19\n" + "ld1h { z17.h }, p0/Z, [x22, #2, MUL VL]\n" + "zip1 z30.h, z19.h, z18.h\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z16.h }, p4/Z, [x22, #3, MUL VL]\n" + "zip2 z29.h, z19.h, z18.h\n" + "ld1h { z19.h }, p3/Z, [x23, #4, MUL VL]\n" + "mov x19, x21\n" + "decw x20, ALL, MUL #16\n" + "zip1 z28.h, z21.h, z17.h\n" + "ld1h { z18.h }, p2/Z, [x23, #5, MUL VL]\n" + "zip2 z27.h, z21.h, z17.h\n" + "zip1 z26.h, z20.h, z16.h\n" + "cmp x20, #0x0\n" + "ld1h { z17.h }, p1/Z, [x23, #6, MUL VL]\n" + "zip2 z25.h, z20.h, z16.h\n" + "add x21, x21, %x[out_stride]\n" + "ld1h { z24.h }, p0/Z, [x23, #7, MUL VL]\n" + "addvl x23, x23, #8\n" + "ld1h { z16.h }, p3/Z, [x22, #4, MUL VL]\n" + "zip1 z23.h, z19.h, z16.h\n" + "zip2 z22.h, z19.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x22, #5, MUL VL]\n" + "zip1 z21.h, z18.h, z16.h\n" + "zip2 z20.h, z18.h, z16.h\n" + "ld1h { z16.h }, p1/Z, [x22, #6, MUL VL]\n" + "zip1 z19.h, z17.h, z16.h\n" + "zip2 z18.h, z17.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x22, #7, MUL VL]\n" + "st1h { z0.h }, p5, [x19]\n" + "addvl x22, x22, #8\n" + "zip1 z17.h, z24.h, z16.h\n" + "st1h { z31.h }, p5, [x19, #1, MUL VL]\n" + "zip2 z16.h, z24.h, z16.h\n" + "st1h { z30.h }, p5, [x19, #2, MUL VL]\n" + "st1h { z29.h }, p5, [x19, #3, MUL VL]\n" + "st1h { z28.h }, p5, [x19, #4, MUL VL]\n" + "st1h { z27.h }, p5, [x19, #5, MUL VL]\n" + "st1h { z26.h }, p5, [x19, #6, MUL VL]\n" + "st1h { z25.h }, p5, [x19, #7, MUL VL]\n" + "addvl x19, x19, #16\n" + "st1h { z23.h }, p5, [x19, #-8, MUL VL]\n" + "st1h { z22.h }, p5, [x19, #-7, MUL VL]\n" + "st1h { z21.h }, p5, [x19, #-6, MUL VL]\n" + "st1h { z20.h }, p5, [x19, #-5, MUL VL]\n" + "st1h { z19.h }, p5, [x19, #-4, MUL VL]\n" + "st1h { z18.h }, p5, [x19, #-3, MUL VL]\n" + "st1h { z17.h }, p5, [x19, #-2, MUL VL]\n" + "st1h { z16.h }, p5, [x19, #-1, MUL VL]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #16\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<16, 2, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_16VL_2x2( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +#endif // __ARM_FEATURE_SVE diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_2x2_fp32bf16.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_2x2_fp32bf16.hpp new file mode 100644 index 0000000000..11c3bcc253 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_16VL_2x2_fp32bf16.hpp @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_16VL_2x2_fp32bf16(bfloat16 *out, const float *in, size_t width, size_t in_stride, size_t height) +{ + float *pad_row = reinterpret_cast<float *>(alloca(width * sizeof(float))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(float)); + } + + size_t out_stride = 16 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p7.b\n" + "1:" // Main row loop: Head + "mov x24, %x[in]\n" + "add x23, x24, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "add %x[in], x23, %x[in_stride]\n" + "mov x22, %x[out]\n" + "csel x23, x23, %x[pad_row], GT\n" + "sub %x[height], %x[height], #0x2\n" + "mov x21, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x20, x21\n" + "whilelt p1.s, XZR, x20\n" + "ld1w { z16.s }, p1/Z, [x24]\n" + ".inst 0x658abe00 // bfcvt z0.h, p7/M, z16.s\n" + "decw x20\n" + "whilelt p0.s, XZR, x20\n" + "ld1w { z16.s }, p0/Z, [x24, #1, MUL VL]\n" + ".inst 0x658abe1f // bfcvt z31.h, p7/M, z16.s\n" + "decw x20\n" + "whilelt p6.s, XZR, x20\n" + "ld1w { z16.s }, p6/Z, [x24, #2, MUL VL]\n" + ".inst 0x658abe1e // bfcvt z30.h, p7/M, z16.s\n" + "decw x20\n" + "whilelt p5.s, XZR, x20\n" + "ld1w { z16.s }, p5/Z, [x24, #3, MUL VL]\n" + ".inst 0x658abe1d // bfcvt z29.h, p7/M, z16.s\n" + "decw x20\n" + "whilelt p4.s, XZR, x20\n" + "ld1w { z16.s }, p4/Z, [x24, #4, MUL VL]\n" + ".inst 0x658abe1c // bfcvt z28.h, p7/M, z16.s\n" + "decw x20\n" + "whilelt p3.s, XZR, x20\n" + "ld1w { z16.s }, p3/Z, [x24, #5, MUL VL]\n" + ".inst 0x658abe1b // bfcvt z27.h, p7/M, z16.s\n" + "decw x20\n" + "whilelt p2.s, XZR, x20\n" + "ld1w { z16.s }, p2/Z, [x24, #6, MUL VL]\n" + ".inst 0x658abe1a // bfcvt z26.h, p7/M, z16.s\n" + "decw x20\n" + "ld1w { z16.s }, p1/Z, [x23]\n" + "whilelt p1.s, XZR, x20\n" + ".inst 0x648abe00 // bfcvtnt z0.h, p7/M, z16.s\n" + "decw x20\n" + "ld1w { z16.s }, p1/Z, [x24, #7, MUL VL]\n" + "addvl x24, x24, #16\n" + ".inst 0x658abe19 // bfcvt z25.h, p7/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x23, #1, MUL VL]\n" + "whilelt p0.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe1f // bfcvtnt z31.h, p7/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x24, #-8, MUL VL]\n" + ".inst 0x658abe18 // bfcvt z24.h, p7/M, z16.s\n" + "mov x19, x22\n" + "decw x21, ALL, MUL #16\n" + "ld1w { z16.s }, p6/Z, [x23, #2, MUL VL]\n" + "whilelt p6.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe1e // bfcvtnt z30.h, p7/M, z16.s\n" + "ld1w { z16.s }, p6/Z, [x24, #-7, MUL VL]\n" + ".inst 0x658abe17 // bfcvt z23.h, p7/M, z16.s\n" + "add x22, x22, %x[out_stride]\n" + "ld1w { z16.s }, p5/Z, [x23, #3, MUL VL]\n" + "whilelt p5.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe1d // bfcvtnt z29.h, p7/M, z16.s\n" + "ld1w { z16.s }, p5/Z, [x24, #-6, MUL VL]\n" + ".inst 0x658abe16 // bfcvt z22.h, p7/M, z16.s\n" + "ld1w { z16.s }, p4/Z, [x23, #4, MUL VL]\n" + "whilelt p4.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe1c // bfcvtnt z28.h, p7/M, z16.s\n" + "ld1w { z16.s }, p4/Z, [x24, #-5, MUL VL]\n" + ".inst 0x658abe15 // bfcvt z21.h, p7/M, z16.s\n" + "ld1w { z16.s }, p3/Z, [x23, #5, MUL VL]\n" + "whilelt p3.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe1b // bfcvtnt z27.h, p7/M, z16.s\n" + "ld1w { z16.s }, p3/Z, [x24, #-4, MUL VL]\n" + ".inst 0x658abe14 // bfcvt z20.h, p7/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23, #6, MUL VL]\n" + "whilelt p2.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe1a // bfcvtnt z26.h, p7/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #-3, MUL VL]\n" + ".inst 0x658abe13 // bfcvt z19.h, p7/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x23, #7, MUL VL]\n" + "whilelt p1.s, XZR, x20\n" + "decw x20\n" + ".inst 0x648abe19 // bfcvtnt z25.h, p7/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #-2, MUL VL]\n" + "addvl x23, x23, #16\n" + ".inst 0x658abe12 // bfcvt z18.h, p7/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x23, #-8, MUL VL]\n" + "whilelt p0.s, XZR, x20\n" + "cmp x21, #0x0\n" + ".inst 0x648abe18 // bfcvtnt z24.h, p7/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x24, #-1, MUL VL]\n" + ".inst 0x658abe11 // bfcvt z17.h, p7/M, z16.s\n" + "ld1w { z16.s }, p6/Z, [x23, #-7, MUL VL]\n" + ".inst 0x648abe17 // bfcvtnt z23.h, p7/M, z16.s\n" + "ld1w { z16.s }, p5/Z, [x23, #-6, MUL VL]\n" + ".inst 0x648abe16 // bfcvtnt z22.h, p7/M, z16.s\n" + "ld1w { z16.s }, p4/Z, [x23, #-5, MUL VL]\n" + ".inst 0x648abe15 // bfcvtnt z21.h, p7/M, z16.s\n" + "ld1w { z16.s }, p3/Z, [x23, #-4, MUL VL]\n" + ".inst 0x648abe14 // bfcvtnt z20.h, p7/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23, #-3, MUL VL]\n" + ".inst 0x648abe13 // bfcvtnt z19.h, p7/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x23, #-2, MUL VL]\n" + ".inst 0x648abe12 // bfcvtnt z18.h, p7/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x23, #-1, MUL VL]\n" + "st1h { z0.h }, p7, [x19]\n" + ".inst 0x648abe11 // bfcvtnt z17.h, p7/M, z16.s\n" + "st1h { z31.h }, p7, [x19, #1, MUL VL]\n" + "st1h { z30.h }, p7, [x19, #2, MUL VL]\n" + "st1h { z29.h }, p7, [x19, #3, MUL VL]\n" + "st1h { z28.h }, p7, [x19, #4, MUL VL]\n" + "st1h { z27.h }, p7, [x19, #5, MUL VL]\n" + "st1h { z26.h }, p7, [x19, #6, MUL VL]\n" + "st1h { z25.h }, p7, [x19, #7, MUL VL]\n" + "addvl x19, x19, #16\n" + "st1h { z24.h }, p7, [x19, #-8, MUL VL]\n" + "st1h { z23.h }, p7, [x19, #-7, MUL VL]\n" + "st1h { z22.h }, p7, [x19, #-6, MUL VL]\n" + "st1h { z21.h }, p7, [x19, #-5, MUL VL]\n" + "st1h { z20.h }, p7, [x19, #-4, MUL VL]\n" + "st1h { z19.h }, p7, [x19, #-3, MUL VL]\n" + "st1h { z18.h }, p7, [x19, #-2, MUL VL]\n" + "st1h { z17.h }, p7, [x19, #-1, MUL VL]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #16\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace +template<> +void Transform<16, 2, true, VLType::SME>( + bfloat16 *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_16VL_2x2_fp32bf16( + out, + in + k0 * stride + x0, + (xmax-x0), + stride * sizeof(float), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL.hpp new file mode 100644 index 0000000000..3e0da36359 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL.hpp @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_1VL(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + size_t out_stride = 1 * height * sme::get_vector_length<uint8_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p1.b\n" + "blt 6f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "mov x22, %x[width]\n" + "cnth x20, ALL, MUL #4\n" + "add x19, x23, %x[in_stride]\n" + "cmp x22, x20\n" + "add %x[in], x19, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1h { z31.h }, p1/Z, [x25]\n" + "sub x22, x22, x20\n" + "cmp x22, x20\n" + "ld1h { z30.h }, p1/Z, [x25, #1, MUL VL]\n" + "ld1h { z29.h }, p1/Z, [x25, #2, MUL VL]\n" + "ld1h { z28.h }, p1/Z, [x25, #3, MUL VL]\n" + "addvl x25, x25, #4\n" + "ld1h { z27.h }, p1/Z, [x24]\n" + "ld1h { z26.h }, p1/Z, [x24, #1, MUL VL]\n" + "ld1h { z25.h }, p1/Z, [x24, #2, MUL VL]\n" + "ld1h { z24.h }, p1/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + "ld1h { z23.h }, p1/Z, [x23]\n" + "ld1h { z22.h }, p1/Z, [x23, #1, MUL VL]\n" + "ld1h { z21.h }, p1/Z, [x23, #2, MUL VL]\n" + "ld1h { z20.h }, p1/Z, [x23, #3, MUL VL]\n" + "addvl x23, x23, #4\n" + "ld1h { z19.h }, p1/Z, [x19]\n" + "ld1h { z18.h }, p1/Z, [x19, #1, MUL VL]\n" + "ld1h { z17.h }, p1/Z, [x19, #2, MUL VL]\n" + "ld1h { z16.h }, p1/Z, [x19, #3, MUL VL]\n" + "st1h { z31.h }, p1, [x21]\n" + "addvl x19, x19, #4\n" + "st1h { z27.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z23.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z19.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z30.h }, p1, [x21]\n" + "st1h { z26.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z22.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z18.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z29.h }, p1, [x21]\n" + "st1h { z25.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z21.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z17.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z28.h }, p1, [x21]\n" + "st1h { z24.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z20.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z16.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x22, 5f\n" + "4:" // Main row loop: Column loop + "whilelt p0.h, XZR, x22\n" + "dech x22\n" + "ld1h { z19.h }, p0/Z, [x25]\n" + "cmp x22, #0x0\n" + "addvl x25, x25, #1\n" + "ld1h { z18.h }, p0/Z, [x24]\n" + "addvl x24, x24, #1\n" + "ld1h { z17.h }, p0/Z, [x23]\n" + "addvl x23, x23, #1\n" + "ld1h { z16.h }, p0/Z, [x19]\n" + "addvl x19, x19, #1\n" + "st1h { z19.h }, p1, [x21]\n" + "st1h { z18.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z17.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z16.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #4\n" + "bge 1b\n" + "cbz %x[height], 12f\n" + "6:" // Main loop skip + "7:" // Tail row loop: Head + "mov x20, %x[width]\n" + "cnth x19, ALL, MUL #4\n" + "mov x25, %x[in]\n" + "cmp x20, x19\n" + "add %x[in], x25, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x1\n" + "blt 9f\n" + "8:" // Tail row loop: Unroll column loop + "ld1h { z19.h }, p1/Z, [x25]\n" + "sub x20, x20, x19\n" + "cmp x20, x19\n" + "ld1h { z18.h }, p1/Z, [x25, #1, MUL VL]\n" + "ld1h { z17.h }, p1/Z, [x25, #2, MUL VL]\n" + "ld1h { z16.h }, p1/Z, [x25, #3, MUL VL]\n" + "st1h { z19.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "addvl x25, x25, #4\n" + "st1h { z18.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z17.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z16.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "bge 8b\n" + "9:" // Tail row loop: Unroll column loop skip + "cbz x20, 11f\n" + "10:" // Tail row loop: Column loop + "whilelt p0.h, XZR, x20\n" + "dech x20\n" + "ld1h { z16.h }, p0/Z, [x25]\n" + "st1h { z16.h }, p1, [x21]\n" + "cmp x20, #0x0\n" + "addvl x25, x25, #1\n" + "add x21, x21, %x[out_stride]\n" + "bgt 10b\n" + "11:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #1\n" + "bge 7b\n" + "12:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<1, 1, true, VLType::SME>( + float *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(float) / 2, + stride * sizeof(float), + (kmax-k0) + ); +} + +template<> +void Transform<1, 1, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +template<> +void Transform<1, 1, true, VLType::SME>( + __fp16 *out, const __fp16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(__fp16) / 2, + stride * sizeof(__fp16), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_1x4.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_1x4.hpp new file mode 100644 index 0000000000..4c5d3d31ec --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_1x4.hpp @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_1VL_1x4(uint8_t *out, const uint8_t *in, size_t width, size_t in_stride, size_t height) +{ + uint8_t *pad_row = reinterpret_cast<uint8_t *>(alloca(width * sizeof(uint8_t))); + + if (height % 4) { + memset(pad_row, 0, width * sizeof(uint8_t)); + } + + size_t out_stride = 1 * roundup<size_t>(height, 4) * sme::get_vector_length<uint32_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p1.b\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "cmp %x[height], #0x3\n" + "add %x[in], x22, %x[in_stride]\n" + "csel x22, x22, %x[pad_row], GT\n" + "csel x23, x23, %x[pad_row], GE\n" + "cmp %x[height], #0x1\n" + "mov x21, %x[width]\n" + "cntb x20\n" + "csel x24, x24, %x[pad_row], GT\n" + "cmp x21, x20\n" + "mov x19, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1b { z17.b }, p1/Z, [x25]\n" + "sub x21, x21, x20\n" + "cmp x21, x20\n" + "ld1b { z18.b }, p1/Z, [x24]\n" + "addvl x25, x25, #1\n" + "addvl x24, x24, #1\n" + "ld1b { z16.b }, p1/Z, [x23]\n" + "zip1 z20.b, z17.b, z16.b\n" + "zip2 z19.b, z17.b, z16.b\n" + "addvl x23, x23, #1\n" + "ld1b { z16.b }, p1/Z, [x22]\n" + "zip1 z17.b, z18.b, z16.b\n" + "zip2 z18.b, z18.b, z16.b\n" + "addvl x22, x22, #1\n" + "zip1 z16.b, z20.b, z17.b\n" + "st1b { z16.b }, p1, [x19]\n" + "add x19, x19, %x[out_stride]\n" + "zip2 z16.b, z20.b, z17.b\n" + "st1b { z16.b }, p1, [x19]\n" + "add x19, x19, %x[out_stride]\n" + "zip1 z17.b, z19.b, z18.b\n" + "zip2 z16.b, z19.b, z18.b\n" + "st1b { z17.b }, p1, [x19]\n" + "add x19, x19, %x[out_stride]\n" + "st1b { z16.b }, p1, [x19]\n" + "add x19, x19, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x21, 5f\n" + "4:" // Main row loop: Column loop + "whilelt p0.b, XZR, x21\n" + "ld1b { z17.b }, p0/Z, [x25]\n" + "decw x21\n" + "ld1b { z18.b }, p0/Z, [x24]\n" + "cmp x21, #0x0\n" + "incd x25, ALL, MUL #2\n" + "ld1b { z16.b }, p0/Z, [x23]\n" + "zip1 z17.b, z17.b, z16.b\n" + "incd x24, ALL, MUL #2\n" + "incd x23, ALL, MUL #2\n" + "ld1b { z16.b }, p0/Z, [x22]\n" + "zip1 z16.b, z18.b, z16.b\n" + "incd x22, ALL, MUL #2\n" + "zip1 z16.b, z17.b, z16.b\n" + "st1b { z16.b }, p1, [x19]\n" + "add x19, x19, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #1\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<1, 4, true, VLType::SME>( + uint8_t *out, const uint8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(uint8_t) / 1, + stride * sizeof(uint8_t), + (kmax-k0) + ); +} + +template<> +void Transform<1, 4, true, VLType::SME>( + int8_t *out, const int8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(int8_t) / 1, + stride * sizeof(int8_t), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_2x2.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_2x2.hpp new file mode 100644 index 0000000000..3fc4b06835 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_2x2.hpp @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_1VL_2x2(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + uint16_t *pad_row = reinterpret_cast<uint16_t *>(alloca(width * sizeof(uint16_t))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(uint16_t)); + } + + size_t out_stride = 1 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p1.b\n" + "blt 6f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "mov x22, %x[width]\n" + "cnth x20, ALL, MUL #2\n" + "add x19, x23, %x[in_stride]\n" + "cmp x22, x20\n" + "add %x[in], x19, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1h { z17.h }, p1/Z, [x25]\n" + "sub x22, x22, x20\n" + "cmp x22, x20\n" + "ld1h { z16.h }, p1/Z, [x24]\n" + "zip1 z24.h, z17.h, z16.h\n" + "zip2 z23.h, z17.h, z16.h\n" + "ld1h { z17.h }, p1/Z, [x23]\n" + "ld1h { z16.h }, p1/Z, [x19]\n" + "zip1 z22.h, z17.h, z16.h\n" + "zip2 z21.h, z17.h, z16.h\n" + "ld1h { z17.h }, p1/Z, [x25, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "ld1h { z16.h }, p1/Z, [x24, #1, MUL VL]\n" + "zip1 z20.h, z17.h, z16.h\n" + "addvl x24, x24, #2\n" + "zip2 z19.h, z17.h, z16.h\n" + "ld1h { z18.h }, p1/Z, [x23, #1, MUL VL]\n" + "addvl x23, x23, #2\n" + "ld1h { z16.h }, p1/Z, [x19, #1, MUL VL]\n" + "st1h { z24.h }, p1, [x21]\n" + "zip1 z17.h, z18.h, z16.h\n" + "addvl x19, x19, #2\n" + "st1h { z22.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "zip2 z16.h, z18.h, z16.h\n" + "st1h { z23.h }, p1, [x21]\n" + "st1h { z21.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z20.h }, p1, [x21]\n" + "st1h { z17.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z19.h }, p1, [x21]\n" + "st1h { z16.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x22, 5f\n" + "4:" // Main row loop: Column loop + "whilelt p0.h, XZR, x22\n" + "ld1h { z17.h }, p0/Z, [x25]\n" + "decw x22\n" + "ld1h { z16.h }, p0/Z, [x24]\n" + "cmp x22, #0x0\n" + "incd x25, ALL, MUL #4\n" + "zip1 z18.h, z17.h, z16.h\n" + "ld1h { z17.h }, p0/Z, [x23]\n" + "incd x24, ALL, MUL #4\n" + "incd x23, ALL, MUL #4\n" + "ld1h { z16.h }, p0/Z, [x19]\n" + "incd x19, ALL, MUL #4\n" + "zip1 z16.h, z17.h, z16.h\n" + "st1h { z18.h }, p1, [x21]\n" + "st1h { z16.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #2\n" + "bge 1b\n" + "cbz %x[height], 12f\n" + "6:" // Main loop skip + "7:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "mov x20, %x[width]\n" + "cnth x19, ALL, MUL #2\n" + "add %x[in], x24, %x[in_stride]\n" + "csel x24, x24, %x[pad_row], GT\n" + "cmp x20, x19\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x2\n" + "blt 9f\n" + "8:" // Tail row loop: Unroll column loop + "ld1h { z18.h }, p1/Z, [x25]\n" + "sub x20, x20, x19\n" + "cmp x20, x19\n" + "ld1h { z16.h }, p1/Z, [x24]\n" + "zip1 z17.h, z18.h, z16.h\n" + "zip2 z19.h, z18.h, z16.h\n" + "ld1h { z18.h }, p1/Z, [x25, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "ld1h { z16.h }, p1/Z, [x24, #1, MUL VL]\n" + "st1h { z17.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "zip1 z17.h, z18.h, z16.h\n" + "st1h { z19.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "addvl x24, x24, #2\n" + "zip2 z16.h, z18.h, z16.h\n" + "st1h { z17.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z16.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "bge 8b\n" + "9:" // Tail row loop: Unroll column loop skip + "cbz x20, 11f\n" + "10:" // Tail row loop: Column loop + "whilelt p0.h, XZR, x20\n" + "ld1h { z17.h }, p0/Z, [x25]\n" + "decw x20\n" + "ld1h { z16.h }, p0/Z, [x24]\n" + "cmp x20, #0x0\n" + "incd x25, ALL, MUL #4\n" + "zip1 z16.h, z17.h, z16.h\n" + "incd x24, ALL, MUL #4\n" + "st1h { z16.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 10b\n" + "11:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #1\n" + "bge 7b\n" + "12:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<1, 2, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL_2x2( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_2x2_fp32bf16.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_2x2_fp32bf16.hpp new file mode 100644 index 0000000000..d8fa686f21 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_1VL_2x2_fp32bf16.hpp @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_1VL_2x2_fp32bf16(bfloat16 *out, const float *in, size_t width, size_t in_stride, size_t height) +{ + float *pad_row = reinterpret_cast<float *>(alloca(width * sizeof(float))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(float)); + } + + size_t out_stride = 1 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p1.b\n" + "blt 6f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "mov x22, %x[width]\n" + "cnth x20, ALL, MUL #2\n" + "add x19, x23, %x[in_stride]\n" + "cmp x22, x20\n" + "add %x[in], x19, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1w { z16.s }, p1/Z, [x25]\n" + ".inst 0x658aa618 // bfcvt z24.h, p1/M, z16.s\n" + "sub x22, x22, x20\n" + "cmp x22, x20\n" + "ld1w { z16.s }, p1/Z, [x23]\n" + ".inst 0x658aa617 // bfcvt z23.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x25, #1, MUL VL]\n" + ".inst 0x658aa616 // bfcvt z22.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x23, #1, MUL VL]\n" + ".inst 0x658aa615 // bfcvt z21.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x25, #2, MUL VL]\n" + ".inst 0x658aa614 // bfcvt z20.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x23, #2, MUL VL]\n" + ".inst 0x658aa613 // bfcvt z19.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x25, #3, MUL VL]\n" + ".inst 0x658aa612 // bfcvt z18.h, p1/M, z16.s\n" + "addvl x25, x25, #4\n" + "ld1w { z16.s }, p1/Z, [x23, #3, MUL VL]\n" + ".inst 0x658aa611 // bfcvt z17.h, p1/M, z16.s\n" + "addvl x23, x23, #4\n" + "ld1w { z16.s }, p1/Z, [x24]\n" + ".inst 0x648aa618 // bfcvtnt z24.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x19]\n" + ".inst 0x648aa617 // bfcvtnt z23.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #1, MUL VL]\n" + ".inst 0x648aa616 // bfcvtnt z22.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x19, #1, MUL VL]\n" + ".inst 0x648aa615 // bfcvtnt z21.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #2, MUL VL]\n" + ".inst 0x648aa614 // bfcvtnt z20.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x19, #2, MUL VL]\n" + ".inst 0x648aa613 // bfcvtnt z19.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + ".inst 0x648aa612 // bfcvtnt z18.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x19, #3, MUL VL]\n" + "st1h { z24.h }, p1, [x21]\n" + "addvl x19, x19, #4\n" + ".inst 0x648aa611 // bfcvtnt z17.h, p1/M, z16.s\n" + "st1h { z23.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z22.h }, p1, [x21]\n" + "st1h { z21.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z20.h }, p1, [x21]\n" + "st1h { z19.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z18.h }, p1, [x21]\n" + "st1h { z17.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x22, 5f\n" + "4:" // Main row loop: Column loop + "whilelt p0.s, XZR, x22\n" + "ld1w { z16.s }, p0/Z, [x25]\n" + ".inst 0x658aa612 // bfcvt z18.h, p1/M, z16.s\n" + "decw x22\n" + "ld1w { z16.s }, p0/Z, [x23]\n" + ".inst 0x658aa611 // bfcvt z17.h, p1/M, z16.s\n" + "cmp x22, #0x0\n" + "addvl x25, x25, #1\n" + "ld1w { z16.s }, p0/Z, [x24]\n" + "addvl x24, x24, #1\n" + "addvl x23, x23, #1\n" + ".inst 0x648aa612 // bfcvtnt z18.h, p1/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x19]\n" + "addvl x19, x19, #1\n" + ".inst 0x648aa611 // bfcvtnt z17.h, p1/M, z16.s\n" + "st1h { z18.h }, p1, [x21]\n" + "st1h { z17.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #2\n" + "bge 1b\n" + "cbz %x[height], 12f\n" + "6:" // Main loop skip + "7:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "mov x20, %x[width]\n" + "cnth x19, ALL, MUL #2\n" + "add %x[in], x24, %x[in_stride]\n" + "csel x24, x24, %x[pad_row], GT\n" + "cmp x20, x19\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x2\n" + "blt 9f\n" + "8:" // Tail row loop: Unroll column loop + "ld1w { z16.s }, p1/Z, [x25]\n" + ".inst 0x658aa614 // bfcvt z20.h, p1/M, z16.s\n" + "sub x20, x20, x19\n" + "cmp x20, x19\n" + "ld1w { z16.s }, p1/Z, [x25, #1, MUL VL]\n" + ".inst 0x658aa613 // bfcvt z19.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x25, #2, MUL VL]\n" + ".inst 0x658aa612 // bfcvt z18.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x25, #3, MUL VL]\n" + ".inst 0x658aa611 // bfcvt z17.h, p1/M, z16.s\n" + "addvl x25, x25, #4\n" + "ld1w { z16.s }, p1/Z, [x24]\n" + ".inst 0x648aa614 // bfcvtnt z20.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #1, MUL VL]\n" + ".inst 0x648aa613 // bfcvtnt z19.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #2, MUL VL]\n" + ".inst 0x648aa612 // bfcvtnt z18.h, p1/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #3, MUL VL]\n" + "st1h { z20.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "addvl x24, x24, #4\n" + "st1h { z19.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + ".inst 0x648aa611 // bfcvtnt z17.h, p1/M, z16.s\n" + "st1h { z18.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z17.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "bge 8b\n" + "9:" // Tail row loop: Unroll column loop skip + "cbz x20, 11f\n" + "10:" // Tail row loop: Column loop + "whilelt p0.s, XZR, x20\n" + "ld1w { z16.s }, p0/Z, [x25]\n" + ".inst 0x658aa611 // bfcvt z17.h, p1/M, z16.s\n" + "decw x20\n" + "ld1w { z16.s }, p0/Z, [x24]\n" + "cmp x20, #0x0\n" + "addvl x25, x25, #1\n" + ".inst 0x648aa611 // bfcvtnt z17.h, p1/M, z16.s\n" + "addvl x24, x24, #1\n" + "st1h { z17.h }, p1, [x21]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 10b\n" + "11:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #1\n" + "bge 7b\n" + "12:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace +template<> +void Transform<1, 2, true, VLType::SME>( + bfloat16 *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_1VL_2x2_fp32bf16( + out, + in + k0 * stride + x0, + (xmax-x0), + stride * sizeof(float), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL.hpp new file mode 100644 index 0000000000..334115907d --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL.hpp @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_2VL(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + size_t out_stride = 2 * height * sme::get_vector_length<uint8_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p2.b\n" + "blt 6f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "mov x22, %x[width]\n" + "cnth x19, ALL, MUL #4\n" + "add x20, x23, %x[in_stride]\n" + "cmp x22, x19\n" + "add %x[in], x20, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "sub x22, x22, x19\n" + "ld1h { z31.h }, p2/Z, [x25]\n" + "cmp x22, x19\n" + "ld1h { z30.h }, p2/Z, [x25, #1, MUL VL]\n" + "ld1h { z29.h }, p2/Z, [x25, #2, MUL VL]\n" + "ld1h { z28.h }, p2/Z, [x25, #3, MUL VL]\n" + "addvl x25, x25, #4\n" + "ld1h { z27.h }, p2/Z, [x24]\n" + "ld1h { z26.h }, p2/Z, [x24, #1, MUL VL]\n" + "ld1h { z25.h }, p2/Z, [x24, #2, MUL VL]\n" + "ld1h { z24.h }, p2/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + "ld1h { z23.h }, p2/Z, [x23]\n" + "ld1h { z22.h }, p2/Z, [x23, #1, MUL VL]\n" + "ld1h { z21.h }, p2/Z, [x23, #2, MUL VL]\n" + "ld1h { z20.h }, p2/Z, [x23, #3, MUL VL]\n" + "addvl x23, x23, #4\n" + "ld1h { z19.h }, p2/Z, [x20]\n" + "ld1h { z18.h }, p2/Z, [x20, #1, MUL VL]\n" + "ld1h { z17.h }, p2/Z, [x20, #2, MUL VL]\n" + "ld1h { z16.h }, p2/Z, [x20, #3, MUL VL]\n" + "st1h { z31.h }, p2, [x21]\n" + "addvl x20, x20, #4\n" + "st1h { z30.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z27.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z26.h }, p2, [x21, #3, MUL VL]\n" + "st1h { z23.h }, p2, [x21, #4, MUL VL]\n" + "st1h { z22.h }, p2, [x21, #5, MUL VL]\n" + "st1h { z19.h }, p2, [x21, #6, MUL VL]\n" + "st1h { z18.h }, p2, [x21, #7, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z29.h }, p2, [x21]\n" + "st1h { z28.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z25.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z24.h }, p2, [x21, #3, MUL VL]\n" + "st1h { z21.h }, p2, [x21, #4, MUL VL]\n" + "st1h { z20.h }, p2, [x21, #5, MUL VL]\n" + "st1h { z17.h }, p2, [x21, #6, MUL VL]\n" + "st1h { z16.h }, p2, [x21, #7, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x22, 5f\n" + "4:" // Main row loop: Column loop + "mov x19, x22\n" + "whilelt p1.h, XZR, x19\n" + "ld1h { z23.h }, p1/Z, [x25]\n" + "dech x19\n" + "dech x22, ALL, MUL #2\n" + "ld1h { z22.h }, p1/Z, [x24]\n" + "whilelt p0.h, XZR, x19\n" + "cmp x22, #0x0\n" + "ld1h { z21.h }, p0/Z, [x25, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "ld1h { z20.h }, p0/Z, [x24, #1, MUL VL]\n" + "addvl x24, x24, #2\n" + "ld1h { z19.h }, p1/Z, [x23]\n" + "ld1h { z18.h }, p0/Z, [x23, #1, MUL VL]\n" + "addvl x23, x23, #2\n" + "ld1h { z17.h }, p1/Z, [x20]\n" + "ld1h { z16.h }, p0/Z, [x20, #1, MUL VL]\n" + "addvl x20, x20, #2\n" + "st1h { z23.h }, p2, [x21]\n" + "st1h { z21.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z22.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z20.h }, p2, [x21, #3, MUL VL]\n" + "st1h { z19.h }, p2, [x21, #4, MUL VL]\n" + "st1h { z18.h }, p2, [x21, #5, MUL VL]\n" + "st1h { z17.h }, p2, [x21, #6, MUL VL]\n" + "st1h { z16.h }, p2, [x21, #7, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #8\n" + "bge 1b\n" + "cbz %x[height], 12f\n" + "6:" // Main loop skip + "7:" // Tail row loop: Head + "mov x20, %x[width]\n" + "cnth x19, ALL, MUL #4\n" + "mov x25, %x[in]\n" + "cmp x20, x19\n" + "add %x[in], x25, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x1\n" + "blt 9f\n" + "8:" // Tail row loop: Unroll column loop + "sub x20, x20, x19\n" + "ld1h { z19.h }, p2/Z, [x25]\n" + "cmp x20, x19\n" + "ld1h { z18.h }, p2/Z, [x25, #1, MUL VL]\n" + "ld1h { z17.h }, p2/Z, [x25, #2, MUL VL]\n" + "ld1h { z16.h }, p2/Z, [x25, #3, MUL VL]\n" + "st1h { z19.h }, p2, [x21]\n" + "addvl x25, x25, #4\n" + "st1h { z18.h }, p2, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z17.h }, p2, [x21]\n" + "st1h { z16.h }, p2, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 8b\n" + "9:" // Tail row loop: Unroll column loop skip + "cbz x20, 11f\n" + "10:" // Tail row loop: Column loop + "mov x19, x20\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z17.h }, p0/Z, [x25]\n" + "dech x19\n" + "dech x20, ALL, MUL #2\n" + "whilelt p0.h, XZR, x19\n" + "cmp x20, #0x0\n" + "ld1h { z16.h }, p0/Z, [x25, #1, MUL VL]\n" + "st1h { z17.h }, p2, [x21]\n" + "addvl x25, x25, #2\n" + "st1h { z16.h }, p2, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 10b\n" + "11:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #2\n" + "bge 7b\n" + "12:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<2, 1, true, VLType::SME>( + float *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(float) / 2, + stride * sizeof(float), + (kmax-k0) + ); +} + +template<> +void Transform<2, 1, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +template<> +void Transform<2, 1, true, VLType::SME>( + __fp16 *out, const __fp16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(__fp16) / 2, + stride * sizeof(__fp16), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp new file mode 100644 index 0000000000..39c49990eb --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_1x4.hpp @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_2VL_1x4(uint8_t *out, const uint8_t *in, size_t width, size_t in_stride, size_t height) +{ + uint8_t *pad_row = reinterpret_cast<uint8_t *>(alloca(width * sizeof(uint8_t))); + + if (height % 4) { + memset(pad_row, 0, width * sizeof(uint8_t)); + } + + size_t out_stride = 2 * roundup<size_t>(height, 4) * sme::get_vector_length<uint32_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p1.b\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "cmp %x[height], #0x3\n" + "add %x[in], x22, %x[in_stride]\n" + "csel x22, x22, %x[pad_row], GT\n" + "csel x23, x23, %x[pad_row], GE\n" + "cmp %x[height], #0x1\n" + "mov x21, %x[width]\n" + "cntb x20\n" + "csel x24, x24, %x[pad_row], GT\n" + "cmp x21, x20\n" + "mov x19, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1b { z17.b }, p1/Z, [x25]\n" + "sub x21, x21, x20\n" + "cmp x21, x20\n" + "ld1b { z18.b }, p1/Z, [x24]\n" + "addvl x25, x25, #1\n" + "addvl x24, x24, #1\n" + "ld1b { z16.b }, p1/Z, [x23]\n" + "zip1 z20.b, z17.b, z16.b\n" + "zip2 z19.b, z17.b, z16.b\n" + "addvl x23, x23, #1\n" + "ld1b { z17.b }, p1/Z, [x22]\n" + "zip1 z16.b, z18.b, z17.b\n" + "zip2 z18.b, z18.b, z17.b\n" + "addvl x22, x22, #1\n" + "zip1 z17.b, z20.b, z16.b\n" + "zip2 z16.b, z20.b, z16.b\n" + "st1b { z17.b }, p1, [x19]\n" + "st1b { z16.b }, p1, [x19, #1, MUL VL]\n" + "add x19, x19, %x[out_stride]\n" + "zip1 z17.b, z19.b, z18.b\n" + "zip2 z16.b, z19.b, z18.b\n" + "st1b { z17.b }, p1, [x19]\n" + "st1b { z16.b }, p1, [x19, #1, MUL VL]\n" + "add x19, x19, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x21, 5f\n" + "4:" // Main row loop: Column loop + "whilelt p0.b, XZR, x21\n" + "ld1b { z18.b }, p0/Z, [x25]\n" + "decw x21, ALL, MUL #2\n" + "ld1b { z17.b }, p0/Z, [x24]\n" + "cmp x21, #0x0\n" + "incd x25, ALL, MUL #4\n" + "ld1b { z16.b }, p0/Z, [x23]\n" + "zip1 z18.b, z18.b, z16.b\n" + "incd x24, ALL, MUL #4\n" + "incd x23, ALL, MUL #4\n" + "ld1b { z16.b }, p0/Z, [x22]\n" + "zip1 z16.b, z17.b, z16.b\n" + "incd x22, ALL, MUL #4\n" + "zip1 z17.b, z18.b, z16.b\n" + "zip2 z16.b, z18.b, z16.b\n" + "st1b { z17.b }, p1, [x19]\n" + "st1b { z16.b }, p1, [x19, #1, MUL VL]\n" + "add x19, x19, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #2\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<2, 4, true, VLType::SME>( + uint8_t *out, const uint8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(uint8_t) / 1, + stride * sizeof(uint8_t), + (kmax-k0) + ); +} + +template<> +void Transform<2, 4, true, VLType::SME>( + int8_t *out, const int8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(int8_t) / 1, + stride * sizeof(int8_t), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_2x2.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_2x2.hpp new file mode 100644 index 0000000000..cfa868226a --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_2x2.hpp @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_2VL_2x2(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + uint16_t *pad_row = reinterpret_cast<uint16_t *>(alloca(width * sizeof(uint16_t))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(uint16_t)); + } + + size_t out_stride = 2 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p1.b\n" + "blt 6f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "mov x22, %x[width]\n" + "cnth x20, ALL, MUL #2\n" + "add x19, x23, %x[in_stride]\n" + "cmp x22, x20\n" + "add %x[in], x19, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1h { z17.h }, p1/Z, [x25]\n" + "sub x22, x22, x20\n" + "cmp x22, x20\n" + "ld1h { z16.h }, p1/Z, [x24]\n" + "zip1 z24.h, z17.h, z16.h\n" + "zip2 z23.h, z17.h, z16.h\n" + "ld1h { z17.h }, p1/Z, [x23]\n" + "ld1h { z16.h }, p1/Z, [x19]\n" + "zip1 z22.h, z17.h, z16.h\n" + "zip2 z21.h, z17.h, z16.h\n" + "ld1h { z17.h }, p1/Z, [x25, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "ld1h { z16.h }, p1/Z, [x24, #1, MUL VL]\n" + "addvl x24, x24, #2\n" + "zip1 z20.h, z17.h, z16.h\n" + "zip2 z19.h, z17.h, z16.h\n" + "ld1h { z18.h }, p1/Z, [x23, #1, MUL VL]\n" + "addvl x23, x23, #2\n" + "ld1h { z16.h }, p1/Z, [x19, #1, MUL VL]\n" + "st1h { z24.h }, p1, [x21]\n" + "addvl x19, x19, #2\n" + "zip1 z17.h, z18.h, z16.h\n" + "st1h { z23.h }, p1, [x21, #1, MUL VL]\n" + "zip2 z16.h, z18.h, z16.h\n" + "st1h { z22.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z21.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z20.h }, p1, [x21]\n" + "st1h { z19.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z17.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z16.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x22, 5f\n" + "4:" // Main row loop: Column loop + "whilelt p0.h, XZR, x22\n" + "ld1h { z17.h }, p0/Z, [x25]\n" + "decw x22, ALL, MUL #2\n" + "ld1h { z16.h }, p0/Z, [x24]\n" + "cmp x22, #0x0\n" + "addvl x25, x25, #1\n" + "zip1 z20.h, z17.h, z16.h\n" + "ld1h { z19.h }, p0/Z, [x23]\n" + "addvl x24, x24, #1\n" + "addvl x23, x23, #1\n" + "zip2 z18.h, z17.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x19]\n" + "addvl x19, x19, #1\n" + "zip1 z17.h, z19.h, z16.h\n" + "zip2 z16.h, z19.h, z16.h\n" + "st1h { z20.h }, p1, [x21]\n" + "st1h { z18.h }, p1, [x21, #1, MUL VL]\n" + "st1h { z17.h }, p1, [x21, #2, MUL VL]\n" + "st1h { z16.h }, p1, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #4\n" + "bge 1b\n" + "cbz %x[height], 12f\n" + "6:" // Main loop skip + "7:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "mov x20, %x[width]\n" + "cnth x19, ALL, MUL #2\n" + "add %x[in], x24, %x[in_stride]\n" + "csel x24, x24, %x[pad_row], GT\n" + "cmp x20, x19\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x2\n" + "blt 9f\n" + "8:" // Tail row loop: Unroll column loop + "ld1h { z18.h }, p1/Z, [x25]\n" + "sub x20, x20, x19\n" + "cmp x20, x19\n" + "ld1h { z16.h }, p1/Z, [x24]\n" + "zip1 z17.h, z18.h, z16.h\n" + "zip2 z19.h, z18.h, z16.h\n" + "ld1h { z18.h }, p1/Z, [x25, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "ld1h { z16.h }, p1/Z, [x24, #1, MUL VL]\n" + "st1h { z17.h }, p1, [x21]\n" + "addvl x24, x24, #2\n" + "zip1 z17.h, z18.h, z16.h\n" + "st1h { z19.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "zip2 z16.h, z18.h, z16.h\n" + "st1h { z17.h }, p1, [x21]\n" + "st1h { z16.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 8b\n" + "9:" // Tail row loop: Unroll column loop skip + "cbz x20, 11f\n" + "10:" // Tail row loop: Column loop + "whilelt p0.h, XZR, x20\n" + "ld1h { z18.h }, p0/Z, [x25]\n" + "decw x20, ALL, MUL #2\n" + "ld1h { z16.h }, p0/Z, [x24]\n" + "cmp x20, #0x0\n" + "addvl x25, x25, #1\n" + "zip1 z17.h, z18.h, z16.h\n" + "addvl x24, x24, #1\n" + "zip2 z16.h, z18.h, z16.h\n" + "st1h { z17.h }, p1, [x21]\n" + "st1h { z16.h }, p1, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 10b\n" + "11:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #2\n" + "bge 7b\n" + "12:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<2, 2, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL_2x2( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_2x2_fp32bf16.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_2x2_fp32bf16.hpp new file mode 100644 index 0000000000..65936d9464 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_2VL_2x2_fp32bf16.hpp @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_2VL_2x2_fp32bf16(bfloat16 *out, const float *in, size_t width, size_t in_stride, size_t height) +{ + float *pad_row = reinterpret_cast<float *>(alloca(width * sizeof(float))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(float)); + } + + size_t out_stride = 2 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p2.b\n" + "blt 6f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "mov x22, %x[width]\n" + "cnth x19, ALL, MUL #2\n" + "add x20, x23, %x[in_stride]\n" + "cmp x22, x19\n" + "add %x[in], x20, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "blt 3f\n" + "2:" // Main row loop: Unroll column loop + "ld1w { z16.s }, p2/Z, [x25]\n" + ".inst 0x658aaa18 // bfcvt z24.h, p2/M, z16.s\n" + "sub x22, x22, x19\n" + "cmp x22, x19\n" + "ld1w { z16.s }, p2/Z, [x25, #1, MUL VL]\n" + ".inst 0x658aaa17 // bfcvt z23.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23]\n" + ".inst 0x658aaa16 // bfcvt z22.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23, #1, MUL VL]\n" + ".inst 0x658aaa15 // bfcvt z21.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x25, #2, MUL VL]\n" + ".inst 0x658aaa14 // bfcvt z20.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x25, #3, MUL VL]\n" + ".inst 0x658aaa13 // bfcvt z19.h, p2/M, z16.s\n" + "addvl x25, x25, #4\n" + "ld1w { z16.s }, p2/Z, [x23, #2, MUL VL]\n" + ".inst 0x658aaa12 // bfcvt z18.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x23, #3, MUL VL]\n" + ".inst 0x658aaa11 // bfcvt z17.h, p2/M, z16.s\n" + "addvl x23, x23, #4\n" + "ld1w { z16.s }, p2/Z, [x24]\n" + ".inst 0x648aaa18 // bfcvtnt z24.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #1, MUL VL]\n" + ".inst 0x648aaa17 // bfcvtnt z23.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20]\n" + ".inst 0x648aaa16 // bfcvtnt z22.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, #1, MUL VL]\n" + ".inst 0x648aaa15 // bfcvtnt z21.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #2, MUL VL]\n" + ".inst 0x648aaa14 // bfcvtnt z20.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + ".inst 0x648aaa13 // bfcvtnt z19.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, #2, MUL VL]\n" + ".inst 0x648aaa12 // bfcvtnt z18.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x20, #3, MUL VL]\n" + "st1h { z24.h }, p2, [x21]\n" + "addvl x20, x20, #4\n" + ".inst 0x648aaa11 // bfcvtnt z17.h, p2/M, z16.s\n" + "st1h { z23.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z22.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z21.h }, p2, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z20.h }, p2, [x21]\n" + "st1h { z19.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z18.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z17.h }, p2, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 2b\n" + "3:" // Main row loop: Unroll column loop skip + "cbz x22, 5f\n" + "4:" // Main row loop: Column loop + "mov x19, x22\n" + "whilelt p1.s, XZR, x19\n" + "ld1w { z16.s }, p1/Z, [x25]\n" + ".inst 0x658aaa14 // bfcvt z20.h, p2/M, z16.s\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z16.s }, p0/Z, [x25, #1, MUL VL]\n" + ".inst 0x658aaa13 // bfcvt z19.h, p2/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x23]\n" + ".inst 0x658aaa12 // bfcvt z18.h, p2/M, z16.s\n" + "decw x22, ALL, MUL #2\n" + "cmp x22, #0x0\n" + "ld1w { z16.s }, p0/Z, [x23, #1, MUL VL]\n" + ".inst 0x658aaa11 // bfcvt z17.h, p2/M, z16.s\n" + "addvl x25, x25, #2\n" + "addvl x23, x23, #2\n" + "ld1w { z16.s }, p1/Z, [x24]\n" + ".inst 0x648aaa14 // bfcvtnt z20.h, p2/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x24, #1, MUL VL]\n" + "addvl x24, x24, #2\n" + ".inst 0x648aaa13 // bfcvtnt z19.h, p2/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x20]\n" + ".inst 0x648aaa12 // bfcvtnt z18.h, p2/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x20, #1, MUL VL]\n" + "addvl x20, x20, #2\n" + ".inst 0x648aaa11 // bfcvtnt z17.h, p2/M, z16.s\n" + "st1h { z20.h }, p2, [x21]\n" + "st1h { z19.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z18.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z17.h }, p2, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 4b\n" + "5:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #4\n" + "bge 1b\n" + "cbz %x[height], 12f\n" + "6:" // Main loop skip + "7:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "mov x20, %x[width]\n" + "cnth x19, ALL, MUL #2\n" + "add %x[in], x24, %x[in_stride]\n" + "csel x24, x24, %x[pad_row], GT\n" + "cmp x20, x19\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x2\n" + "blt 9f\n" + "8:" // Tail row loop: Unroll column loop + "ld1w { z16.s }, p2/Z, [x25]\n" + ".inst 0x658aaa14 // bfcvt z20.h, p2/M, z16.s\n" + "sub x20, x20, x19\n" + "cmp x20, x19\n" + "ld1w { z16.s }, p2/Z, [x25, #1, MUL VL]\n" + ".inst 0x658aaa13 // bfcvt z19.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x25, #2, MUL VL]\n" + ".inst 0x658aaa12 // bfcvt z18.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x25, #3, MUL VL]\n" + ".inst 0x658aaa11 // bfcvt z17.h, p2/M, z16.s\n" + "addvl x25, x25, #4\n" + "ld1w { z16.s }, p2/Z, [x24]\n" + ".inst 0x648aaa14 // bfcvtnt z20.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #1, MUL VL]\n" + ".inst 0x648aaa13 // bfcvtnt z19.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #2, MUL VL]\n" + ".inst 0x648aaa12 // bfcvtnt z18.h, p2/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #3, MUL VL]\n" + "st1h { z20.h }, p2, [x21]\n" + "addvl x24, x24, #4\n" + ".inst 0x648aaa11 // bfcvtnt z17.h, p2/M, z16.s\n" + "st1h { z19.h }, p2, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "st1h { z18.h }, p2, [x21]\n" + "st1h { z17.h }, p2, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bge 8b\n" + "9:" // Tail row loop: Unroll column loop skip + "cbz x20, 11f\n" + "10:" // Tail row loop: Column loop + "mov x19, x20\n" + "whilelt p1.s, XZR, x19\n" + "ld1w { z16.s }, p1/Z, [x25]\n" + ".inst 0x658aaa12 // bfcvt z18.h, p2/M, z16.s\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z16.s }, p0/Z, [x25, #1, MUL VL]\n" + ".inst 0x658aaa11 // bfcvt z17.h, p2/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24]\n" + "decw x20, ALL, MUL #2\n" + "cmp x20, #0x0\n" + ".inst 0x648aaa12 // bfcvtnt z18.h, p2/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x24, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "addvl x24, x24, #2\n" + ".inst 0x648aaa11 // bfcvtnt z17.h, p2/M, z16.s\n" + "st1h { z18.h }, p2, [x21]\n" + "st1h { z17.h }, p2, [x21, #1, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 10b\n" + "11:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #2\n" + "bge 7b\n" + "12:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace +template<> +void Transform<2, 2, true, VLType::SME>( + bfloat16 *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_2VL_2x2_fp32bf16( + out, + in + k0 * stride + x0, + (xmax-x0), + stride * sizeof(float), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL.hpp new file mode 100644 index 0000000000..7b783c3e5d --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL.hpp @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_4VL(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + size_t out_stride = 4 * height * sme::get_vector_length<uint8_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p4.b\n" + "blt 4f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "add %x[in], x22, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "mov x20, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x19, x20\n" + "whilelt p3.h, XZR, x19\n" + "ld1h { z31.h }, p3/Z, [x25]\n" + "dech x19\n" + "whilelt p2.h, XZR, x19\n" + "ld1h { z30.h }, p2/Z, [x25, #1, MUL VL]\n" + "dech x19\n" + "whilelt p1.h, XZR, x19\n" + "ld1h { z29.h }, p1/Z, [x25, #2, MUL VL]\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z28.h }, p0/Z, [x25, #3, MUL VL]\n" + "mov x19, x21\n" + "dech x20, ALL, MUL #4\n" + "ld1h { z27.h }, p3/Z, [x24]\n" + "ld1h { z26.h }, p2/Z, [x24, #1, MUL VL]\n" + "cmp x20, #0x0\n" + "addvl x25, x25, #4\n" + "ld1h { z25.h }, p1/Z, [x24, #2, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "ld1h { z24.h }, p0/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + "ld1h { z23.h }, p3/Z, [x23]\n" + "ld1h { z22.h }, p2/Z, [x23, #1, MUL VL]\n" + "ld1h { z21.h }, p1/Z, [x23, #2, MUL VL]\n" + "ld1h { z20.h }, p0/Z, [x23, #3, MUL VL]\n" + "addvl x23, x23, #4\n" + "ld1h { z19.h }, p3/Z, [x22]\n" + "ld1h { z18.h }, p2/Z, [x22, #1, MUL VL]\n" + "ld1h { z17.h }, p1/Z, [x22, #2, MUL VL]\n" + "ld1h { z16.h }, p0/Z, [x22, #3, MUL VL]\n" + "st1h { z31.h }, p4, [x19]\n" + "addvl x22, x22, #4\n" + "st1h { z30.h }, p4, [x19, #1, MUL VL]\n" + "st1h { z29.h }, p4, [x19, #2, MUL VL]\n" + "st1h { z28.h }, p4, [x19, #3, MUL VL]\n" + "st1h { z27.h }, p4, [x19, #4, MUL VL]\n" + "st1h { z26.h }, p4, [x19, #5, MUL VL]\n" + "st1h { z25.h }, p4, [x19, #6, MUL VL]\n" + "st1h { z24.h }, p4, [x19, #7, MUL VL]\n" + "addvl x19, x19, #16\n" + "st1h { z23.h }, p4, [x19, #-8, MUL VL]\n" + "st1h { z22.h }, p4, [x19, #-7, MUL VL]\n" + "st1h { z21.h }, p4, [x19, #-6, MUL VL]\n" + "st1h { z20.h }, p4, [x19, #-5, MUL VL]\n" + "st1h { z19.h }, p4, [x19, #-4, MUL VL]\n" + "st1h { z18.h }, p4, [x19, #-3, MUL VL]\n" + "st1h { z17.h }, p4, [x19, #-2, MUL VL]\n" + "st1h { z16.h }, p4, [x19, #-1, MUL VL]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #16\n" + "bge 1b\n" + "cbz %x[height], 8f\n" + "4:" // Main loop skip + "5:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add %x[in], x25, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x1\n" + "mov x20, %x[width]\n" + "6:" // Tail row loop: Column loop + "mov x19, x20\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z19.h }, p0/Z, [x25]\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z18.h }, p0/Z, [x25, #1, MUL VL]\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z17.h }, p0/Z, [x25, #2, MUL VL]\n" + "dech x19\n" + "dech x20, ALL, MUL #4\n" + "whilelt p0.h, XZR, x19\n" + "cmp x20, #0x0\n" + "ld1h { z16.h }, p0/Z, [x25, #3, MUL VL]\n" + "st1h { z19.h }, p4, [x21]\n" + "addvl x25, x25, #4\n" + "st1h { z18.h }, p4, [x21, #1, MUL VL]\n" + "st1h { z17.h }, p4, [x21, #2, MUL VL]\n" + "st1h { z16.h }, p4, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 6b\n" + "7:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #4\n" + "bge 5b\n" + "8:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<4, 1, true, VLType::SME>( + float *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(float) / 2, + stride * sizeof(float), + (kmax-k0) + ); +} + +template<> +void Transform<4, 1, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +template<> +void Transform<4, 1, true, VLType::SME>( + __fp16 *out, const __fp16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(__fp16) / 2, + stride * sizeof(__fp16), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp new file mode 100644 index 0000000000..0429bb07fe --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_1x4.hpp @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_4VL_1x4(uint8_t *out, const uint8_t *in, size_t width, size_t in_stride, size_t height) +{ + uint8_t *pad_row = reinterpret_cast<uint8_t *>(alloca(width * sizeof(uint8_t))); + + if (height % 4) { + memset(pad_row, 0, width * sizeof(uint8_t)); + } + + size_t out_stride = 4 * roundup<size_t>(height, 4) * sme::get_vector_length<uint32_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "ptrue p1.b\n" + "1:" // Main row loop: Head + "mov x24, %x[in]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "add x21, x22, %x[in_stride]\n" + "cmp %x[height], #0x3\n" + "add %x[in], x21, %x[in_stride]\n" + "csel x21, x21, %x[pad_row], GT\n" + "csel x22, x22, %x[pad_row], GE\n" + "cmp %x[height], #0x1\n" + "mov x20, %x[out]\n" + "csel x23, x23, %x[pad_row], GT\n" + "sub %x[height], %x[height], #0x4\n" + "mov x19, %x[width]\n" + "2:" // Main row loop: Column loop + "whilelt p0.b, XZR, x19\n" + "ld1b { z17.b }, p0/Z, [x24]\n" + "decw x19, ALL, MUL #4\n" + "ld1b { z19.b }, p0/Z, [x23]\n" + "cmp x19, #0x0\n" + "addvl x24, x24, #1\n" + "ld1b { z16.b }, p0/Z, [x22]\n" + "zip1 z18.b, z17.b, z16.b\n" + "zip2 z20.b, z17.b, z16.b\n" + "addvl x23, x23, #1\n" + "ld1b { z16.b }, p0/Z, [x21]\n" + "zip1 z17.b, z19.b, z16.b\n" + "zip2 z19.b, z19.b, z16.b\n" + "addvl x22, x22, #1\n" + "addvl x21, x21, #1\n" + "zip1 z16.b, z18.b, z17.b\n" + "zip2 z18.b, z18.b, z17.b\n" + "st1b { z16.b }, p1, [x20]\n" + "zip1 z17.b, z20.b, z19.b\n" + "zip2 z16.b, z20.b, z19.b\n" + "st1b { z18.b }, p1, [x20, #1, MUL VL]\n" + "st1b { z17.b }, p1, [x20, #2, MUL VL]\n" + "st1b { z16.b }, p1, [x20, #3, MUL VL]\n" + "add x20, x20, %x[out_stride]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #4\n" + "bge 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<4, 4, true, VLType::SME>( + uint8_t *out, const uint8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(uint8_t) / 1, + stride * sizeof(uint8_t), + (kmax-k0) + ); +} + +template<> +void Transform<4, 4, true, VLType::SME>( + int8_t *out, const int8_t *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL_1x4( + reinterpret_cast<uint8_t *>(out), + reinterpret_cast<const uint8_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(int8_t) / 1, + stride * sizeof(int8_t), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_2x2.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_2x2.hpp new file mode 100644 index 0000000000..d1534db6c6 --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_2x2.hpp @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_4VL_2x2(uint16_t *out, const uint16_t *in, size_t width, size_t in_stride, size_t height) +{ + uint16_t *pad_row = reinterpret_cast<uint16_t *>(alloca(width * sizeof(uint16_t))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(uint16_t)); + } + + size_t out_stride = 4 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p2.b\n" + "blt 4f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "add %x[in], x22, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "mov x20, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x19, x20\n" + "whilelt p1.h, XZR, x19\n" + "ld1h { z19.h }, p1/Z, [x25]\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z18.h }, p0/Z, [x25, #1, MUL VL]\n" + "ld1h { z17.h }, p1/Z, [x24]\n" + "decw x20, ALL, MUL #4\n" + "cmp x20, #0x0\n" + "zip1 z24.h, z19.h, z17.h\n" + "ld1h { z16.h }, p0/Z, [x24, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "addvl x24, x24, #2\n" + "zip2 z23.h, z19.h, z17.h\n" + "ld1h { z17.h }, p1/Z, [x23]\n" + "zip1 z22.h, z18.h, z16.h\n" + "zip2 z21.h, z18.h, z16.h\n" + "ld1h { z20.h }, p0/Z, [x23, #1, MUL VL]\n" + "addvl x23, x23, #2\n" + "ld1h { z16.h }, p1/Z, [x22]\n" + "zip1 z19.h, z17.h, z16.h\n" + "zip2 z18.h, z17.h, z16.h\n" + "ld1h { z16.h }, p0/Z, [x22, #1, MUL VL]\n" + "addvl x22, x22, #2\n" + "zip1 z17.h, z20.h, z16.h\n" + "zip2 z16.h, z20.h, z16.h\n" + "st1h { z24.h }, p2, [x21]\n" + "st1h { z23.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z22.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z21.h }, p2, [x21, #3, MUL VL]\n" + "st1h { z19.h }, p2, [x21, #4, MUL VL]\n" + "st1h { z18.h }, p2, [x21, #5, MUL VL]\n" + "st1h { z17.h }, p2, [x21, #6, MUL VL]\n" + "st1h { z16.h }, p2, [x21, #7, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #8\n" + "bge 1b\n" + "cbz %x[height], 8f\n" + "4:" // Main loop skip + "5:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "add %x[in], x24, %x[in_stride]\n" + "mov x21, %x[out]\n" + "csel x24, x24, %x[pad_row], GT\n" + "sub %x[height], %x[height], #0x2\n" + "mov x20, %x[width]\n" + "6:" // Tail row loop: Column loop + "mov x19, x20\n" + "whilelt p1.h, XZR, x19\n" + "ld1h { z18.h }, p1/Z, [x25]\n" + "dech x19\n" + "whilelt p0.h, XZR, x19\n" + "ld1h { z20.h }, p0/Z, [x25, #1, MUL VL]\n" + "ld1h { z17.h }, p1/Z, [x24]\n" + "decw x20, ALL, MUL #4\n" + "cmp x20, #0x0\n" + "zip1 z19.h, z18.h, z17.h\n" + "ld1h { z16.h }, p0/Z, [x24, #1, MUL VL]\n" + "addvl x25, x25, #2\n" + "addvl x24, x24, #2\n" + "zip2 z18.h, z18.h, z17.h\n" + "zip1 z17.h, z20.h, z16.h\n" + "zip2 z16.h, z20.h, z16.h\n" + "st1h { z19.h }, p2, [x21]\n" + "st1h { z18.h }, p2, [x21, #1, MUL VL]\n" + "st1h { z17.h }, p2, [x21, #2, MUL VL]\n" + "st1h { z16.h }, p2, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 6b\n" + "7:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #4\n" + "bge 5b\n" + "8:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace + +template<> +void Transform<4, 2, true, VLType::SME>( + bfloat16 *out, const bfloat16 *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL_2x2( + reinterpret_cast<uint16_t *>(out), + reinterpret_cast<const uint16_t *>(in + k0 * stride + x0), + (xmax-x0) * sizeof(bfloat16) / 2, + stride * sizeof(bfloat16), + (kmax-k0) + ); +} + +#endif diff --git a/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_2x2_fp32bf16.hpp b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_2x2_fp32bf16.hpp new file mode 100644 index 0000000000..59ac4bf50b --- /dev/null +++ b/src/core/NEON/kernels/arm_gemm/transforms/sme_transpose_interleave_4VL_2x2_fp32bf16.hpp @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2022 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __ARM_FEATURE_SVE + + +namespace { + +void sme_transpose_interleave_4VL_2x2_fp32bf16(bfloat16 *out, const float *in, size_t width, size_t in_stride, size_t height) +{ + float *pad_row = reinterpret_cast<float *>(alloca(width * sizeof(float))); + + if (height % 2) { + memset(pad_row, 0, width * sizeof(float)); + } + + size_t out_stride = 4 * roundup<size_t>(height, 2) * sme::get_vector_length<uint16_t>(); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "cmp %x[height], #0x4\n" + "ptrue p4.b\n" + "blt 4f\n" + "1:" // Main row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "add x23, x24, %x[in_stride]\n" + "add x22, x23, %x[in_stride]\n" + "add %x[in], x22, %x[in_stride]\n" + "mov x21, %x[out]\n" + "sub %x[height], %x[height], #0x4\n" + "mov x20, %x[width]\n" + "2:" // Main row loop: Column loop + "mov x19, x20\n" + "whilelt p3.s, XZR, x19\n" + "ld1w { z16.s }, p3/Z, [x25]\n" + ".inst 0x658ab218 // bfcvt z24.h, p4/M, z16.s\n" + "decw x19\n" + "whilelt p2.s, XZR, x19\n" + "ld1w { z16.s }, p2/Z, [x25, #1, MUL VL]\n" + ".inst 0x658ab217 // bfcvt z23.h, p4/M, z16.s\n" + "decw x19\n" + "whilelt p1.s, XZR, x19\n" + "ld1w { z16.s }, p1/Z, [x25, #2, MUL VL]\n" + ".inst 0x658ab216 // bfcvt z22.h, p4/M, z16.s\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z16.s }, p0/Z, [x25, #3, MUL VL]\n" + ".inst 0x658ab215 // bfcvt z21.h, p4/M, z16.s\n" + "ld1w { z16.s }, p3/Z, [x23]\n" + ".inst 0x658ab214 // bfcvt z20.h, p4/M, z16.s\n" + "decw x20, ALL, MUL #4\n" + "cmp x20, #0x0\n" + "ld1w { z16.s }, p2/Z, [x23, #1, MUL VL]\n" + ".inst 0x658ab213 // bfcvt z19.h, p4/M, z16.s\n" + "addvl x25, x25, #4\n" + "ld1w { z16.s }, p1/Z, [x23, #2, MUL VL]\n" + ".inst 0x658ab212 // bfcvt z18.h, p4/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x23, #3, MUL VL]\n" + ".inst 0x658ab211 // bfcvt z17.h, p4/M, z16.s\n" + "addvl x23, x23, #4\n" + "ld1w { z16.s }, p3/Z, [x24]\n" + ".inst 0x648ab218 // bfcvtnt z24.h, p4/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #1, MUL VL]\n" + ".inst 0x648ab217 // bfcvtnt z23.h, p4/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #2, MUL VL]\n" + ".inst 0x648ab216 // bfcvtnt z22.h, p4/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + ".inst 0x648ab215 // bfcvtnt z21.h, p4/M, z16.s\n" + "ld1w { z16.s }, p3/Z, [x22]\n" + ".inst 0x648ab214 // bfcvtnt z20.h, p4/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x22, #1, MUL VL]\n" + ".inst 0x648ab213 // bfcvtnt z19.h, p4/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x22, #2, MUL VL]\n" + ".inst 0x648ab212 // bfcvtnt z18.h, p4/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x22, #3, MUL VL]\n" + "addvl x22, x22, #4\n" + ".inst 0x648ab211 // bfcvtnt z17.h, p4/M, z16.s\n" + "st1h { z24.h }, p4, [x21]\n" + "st1h { z23.h }, p4, [x21, #1, MUL VL]\n" + "st1h { z22.h }, p4, [x21, #2, MUL VL]\n" + "st1h { z21.h }, p4, [x21, #3, MUL VL]\n" + "st1h { z20.h }, p4, [x21, #4, MUL VL]\n" + "st1h { z19.h }, p4, [x21, #5, MUL VL]\n" + "st1h { z18.h }, p4, [x21, #6, MUL VL]\n" + "st1h { z17.h }, p4, [x21, #7, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 2b\n" + "3:" // Main row loop: Column loop skip + "cmp %x[height], #0x4\n" + "addvl %x[out], %x[out], #8\n" + "bge 1b\n" + "cbz %x[height], 8f\n" + "4:" // Main loop skip + "5:" // Tail row loop: Head + "mov x25, %x[in]\n" + "add x24, x25, %x[in_stride]\n" + "cmp %x[height], #0x1\n" + "add %x[in], x24, %x[in_stride]\n" + "mov x21, %x[out]\n" + "csel x24, x24, %x[pad_row], GT\n" + "sub %x[height], %x[height], #0x2\n" + "mov x20, %x[width]\n" + "6:" // Tail row loop: Column loop + "mov x19, x20\n" + "whilelt p3.s, XZR, x19\n" + "ld1w { z16.s }, p3/Z, [x25]\n" + ".inst 0x658ab214 // bfcvt z20.h, p4/M, z16.s\n" + "decw x19\n" + "whilelt p2.s, XZR, x19\n" + "ld1w { z16.s }, p2/Z, [x25, #1, MUL VL]\n" + ".inst 0x658ab213 // bfcvt z19.h, p4/M, z16.s\n" + "decw x19\n" + "whilelt p1.s, XZR, x19\n" + "ld1w { z16.s }, p1/Z, [x25, #2, MUL VL]\n" + ".inst 0x658ab212 // bfcvt z18.h, p4/M, z16.s\n" + "decw x19\n" + "whilelt p0.s, XZR, x19\n" + "ld1w { z16.s }, p0/Z, [x25, #3, MUL VL]\n" + ".inst 0x658ab211 // bfcvt z17.h, p4/M, z16.s\n" + "ld1w { z16.s }, p3/Z, [x24]\n" + "decw x20, ALL, MUL #4\n" + "cmp x20, #0x0\n" + ".inst 0x648ab214 // bfcvtnt z20.h, p4/M, z16.s\n" + "ld1w { z16.s }, p2/Z, [x24, #1, MUL VL]\n" + "addvl x25, x25, #4\n" + ".inst 0x648ab213 // bfcvtnt z19.h, p4/M, z16.s\n" + "ld1w { z16.s }, p1/Z, [x24, #2, MUL VL]\n" + ".inst 0x648ab212 // bfcvtnt z18.h, p4/M, z16.s\n" + "ld1w { z16.s }, p0/Z, [x24, #3, MUL VL]\n" + "addvl x24, x24, #4\n" + ".inst 0x648ab211 // bfcvtnt z17.h, p4/M, z16.s\n" + "st1h { z20.h }, p4, [x21]\n" + "st1h { z19.h }, p4, [x21, #1, MUL VL]\n" + "st1h { z18.h }, p4, [x21, #2, MUL VL]\n" + "st1h { z17.h }, p4, [x21, #3, MUL VL]\n" + "add x21, x21, %x[out_stride]\n" + "bgt 6b\n" + "7:" // Tail row loop: Column loop skip + "cmp %x[height], #0x1\n" + "addvl %x[out], %x[out], #4\n" + "bge 5b\n" + "8:" // Done + ".inst 0xd503467f // SMSTOP\n" + : [height] "+&r" (height), [in] "+&r" (in), [out] "+&r" (out) + : [in_stride] "r" (in_stride), [out_stride] "r" (out_stride), [pad_row] "r" (pad_row), [width] "r" (width) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // anonymous namespace +template<> +void Transform<4, 2, true, VLType::SME>( + bfloat16 *out, const float *in, int stride, int x0, int xmax, int k0, int kmax) +{ + sme_transpose_interleave_4VL_2x2_fp32bf16( + out, + in + k0 * stride + x0, + (xmax-x0), + stride * sizeof(float), + (kmax-k0) + ); +} + +#endif |