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Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp31
1 files changed, 16 insertions, 15 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp
index 7640fcaa20..cdc70705c5 100644
--- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp
+++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_s8s32_dot_3VLx8/generic.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 Arm Limited.
+ * Copyright (c) 2019-2020 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -51,20 +51,20 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"mov z9.s, #0\n"
"mov z10.s, #0\n"
"mov z11.s, #0\n"
- "mov z12.s, #0\n"
"ld1rqb z0.b, p0/z, [%[a_ptr]]\n"
- "mov z13.s, #0\n"
+ "mov z12.s, #0\n"
"ld1b z4.b, p0/z, [%[b_ptr]]\n"
- "mov z14.s, #0\n"
+ "mov z13.s, #0\n"
"ld1rqb z1.b, p0/z, [%[a_ptr], #0x10]\n"
- "mov z15.s, #0\n"
+ "mov z14.s, #0\n"
"ld1b z5.b, p0/z, [%[b_ptr], #1, MUL VL]\n"
- "mov z16.s, #0\n"
+ "mov z15.s, #0\n"
"ld1rqb z2.b, p0/z, [%[a_ptr], #0x20]\n"
- "mov z17.s, #0\n"
+ "mov z16.s, #0\n"
"add %[a_ptr], %[a_ptr], #0x40\n"
- "mov z18.s, #0\n"
+ "mov z17.s, #0\n"
"addvl %[b_ptr], %[b_ptr], #3\n"
+ "mov z18.s, #0\n"
"mov z19.s, #0\n"
"mov z20.s, #0\n"
"mov z21.s, #0\n"
@@ -208,8 +208,8 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"sdot z9.s, z4.b, z0.b[1]\n"
"sdot z10.s, z4.b, z0.b[2]\n"
"sdot z11.s, z4.b, z0.b[3]\n"
- "sdot z20.s, z4.b, z1.b[0]\n"
"st1w z8.s, p0, [%[c_ptr]]\n"
+ "sdot z20.s, z4.b, z1.b[0]\n"
"sdot z21.s, z4.b, z1.b[1]\n"
"sdot z22.s, z4.b, z1.b[2]\n"
"sdot z23.s, z4.b, z1.b[3]\n"
@@ -217,8 +217,8 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"sdot z13.s, z5.b, z0.b[1]\n"
"sdot z14.s, z5.b, z0.b[2]\n"
"sdot z15.s, z5.b, z0.b[3]\n"
- "sdot z24.s, z5.b, z1.b[0]\n"
"st1w z12.s, p0, [%[c_ptr], #1, MUL VL]\n"
+ "sdot z24.s, z5.b, z1.b[0]\n"
"sdot z25.s, z5.b, z1.b[1]\n"
"sdot z26.s, z5.b, z1.b[2]\n"
"sdot z27.s, z5.b, z1.b[3]\n"
@@ -226,10 +226,11 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"sdot z17.s, z6.b, z0.b[1]\n"
"sdot z18.s, z6.b, z0.b[2]\n"
"sdot z19.s, z6.b, z0.b[3]\n"
- "sdot z28.s, z6.b, z1.b[0]\n"
"st1w z16.s, p0, [%[c_ptr], #2, MUL VL]\n"
+ "sdot z28.s, z6.b, z1.b[0]\n"
"sdot z29.s, z6.b, z1.b[1]\n"
"sdot z30.s, z6.b, z1.b[2]\n"
+ "st1w z9.s, p0, [%[c_ptr], #3, MUL VL]\n"
"sdot z31.s, z6.b, z1.b[3]\n"
"b 4f\n"
"3:\n"
@@ -267,8 +268,8 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"sdot z9.s, z4.b, z2.b[1]\n"
"sdot z10.s, z4.b, z2.b[2]\n"
"sdot z11.s, z4.b, z2.b[3]\n"
- "sdot z20.s, z4.b, z3.b[0]\n"
"st1w z8.s, p0, [%[c_ptr]]\n"
+ "sdot z20.s, z4.b, z3.b[0]\n"
"sdot z21.s, z4.b, z3.b[1]\n"
"sdot z22.s, z4.b, z3.b[2]\n"
"sdot z23.s, z4.b, z3.b[3]\n"
@@ -276,8 +277,8 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"sdot z13.s, z5.b, z2.b[1]\n"
"sdot z14.s, z5.b, z2.b[2]\n"
"sdot z15.s, z5.b, z2.b[3]\n"
- "sdot z24.s, z5.b, z3.b[0]\n"
"st1w z12.s, p0, [%[c_ptr], #1, MUL VL]\n"
+ "sdot z24.s, z5.b, z3.b[0]\n"
"sdot z25.s, z5.b, z3.b[1]\n"
"sdot z26.s, z5.b, z3.b[2]\n"
"sdot z27.s, z5.b, z3.b[3]\n"
@@ -285,13 +286,13 @@ void sve_interleaved_s8s32_dot_3VLx8(const int8_t *Apanel, const int8_t *Bpanel,
"sdot z17.s, z6.b, z2.b[1]\n"
"sdot z18.s, z6.b, z2.b[2]\n"
"sdot z19.s, z6.b, z2.b[3]\n"
- "sdot z28.s, z6.b, z3.b[0]\n"
"st1w z16.s, p0, [%[c_ptr], #2, MUL VL]\n"
+ "sdot z28.s, z6.b, z3.b[0]\n"
"sdot z29.s, z6.b, z3.b[1]\n"
"sdot z30.s, z6.b, z3.b[2]\n"
+ "st1w z9.s, p0, [%[c_ptr], #3, MUL VL]\n"
"sdot z31.s, z6.b, z3.b[3]\n"
"4:\n"
- "st1w z9.s, p0, [%[c_ptr], #3, MUL VL]\n"
"st1w z13.s, p0, [%[c_ptr], #4, MUL VL]\n"
"st1w z17.s, p0, [%[c_ptr], #5, MUL VL]\n"
"st1w z10.s, p0, [%[c_ptr], #6, MUL VL]\n"