diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp | 112 |
1 files changed, 56 insertions, 56 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp index 0006fddb2a..ee9f58f811 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp32_mla_8x3VL/a64fx.cpp @@ -54,31 +54,31 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "2:" // Width loop "ldr x20, [%x[args_ptr], %[offsetof_K]]\n" "mov %x[Apanel], x21\n" + "cmp x20, #0x2\n" "mov z8.b, #0x0\n" "mov z9.b, #0x0\n" - "mov z10.b, #0x0\n" "ld1w { z0.s }, p0/Z, [x22]\n" + "mov z10.b, #0x0\n" "mov z11.b, #0x0\n" - "mov z12.b, #0x0\n" "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n" - "cmp x20, #0x2\n" + "mov z12.b, #0x0\n" "mov z13.b, #0x0\n" + "ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n" "mov z14.b, #0x0\n" "mov z15.b, #0x0\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" "mov z16.b, #0x0\n" - "ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n" "mov z17.b, #0x0\n" + "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" "mov z18.b, #0x0\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" "mov z19.b, #0x0\n" + "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" "mov z20.b, #0x0\n" - "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" "mov z21.b, #0x0\n" + "ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n" "mov z22.b, #0x0\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" "mov z23.b, #0x0\n" "mov z24.b, #0x0\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #12]\n" "mov z25.b, #0x0\n" "mov z26.b, #0x0\n" "mov z27.b, #0x0\n" @@ -92,7 +92,7 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "fmla z9.s, p0/M, z1.s, z3.s\n" "sub x20, x20, #0x2\n" "fmla z10.s, p0/M, z2.s, z3.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #16]\n" "fmla z11.s, p0/M, z0.s, z4.s\n" "fmla z12.s, p0/M, z1.s, z4.s\n" "fmla z13.s, p0/M, z2.s, z4.s\n" @@ -101,63 +101,63 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "fmla z15.s, p0/M, z1.s, z5.s\n" "cmp x20, #0x2\n" "fmla z16.s, p0/M, z2.s, z5.s\n" - "ld1rw { z7.s }, p0/Z, [%x[Apanel], #24]\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel], #24]\n" "fmla z17.s, p0/M, z0.s, z6.s\n" "fmla z18.s, p0/M, z1.s, z6.s\n" "fmla z19.s, p0/M, z2.s, z6.s\n" - "ld1rw { z6.s }, p0/Z, [%x[Apanel], #28]\n" - "fmla z20.s, p0/M, z0.s, z3.s\n" - "fmla z21.s, p0/M, z1.s, z3.s\n" - "fmla z22.s, p0/M, z2.s, z3.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #32]\n" + "ld1rw { z5.s }, p0/Z, [%x[Apanel], #28]\n" + "fmla z20.s, p0/M, z0.s, z7.s\n" + "fmla z21.s, p0/M, z1.s, z7.s\n" + "fmla z22.s, p0/M, z2.s, z7.s\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #32]\n" "fmla z23.s, p0/M, z0.s, z4.s\n" "fmla z24.s, p0/M, z1.s, z4.s\n" "fmla z25.s, p0/M, z2.s, z4.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #36]\n" - "fmla z26.s, p0/M, z0.s, z7.s\n" - "fmla z27.s, p0/M, z1.s, z7.s\n" - "fmla z28.s, p0/M, z2.s, z7.s\n" + "fmla z26.s, p0/M, z0.s, z3.s\n" + "fmla z27.s, p0/M, z1.s, z3.s\n" + "fmla z28.s, p0/M, z2.s, z3.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel], #40]\n" - "fmla z29.s, p0/M, z0.s, z6.s\n" - "ld1w { z7.s }, p0/Z, [x22, #3, MUL VL]\n" - "fmla z30.s, p0/M, z1.s, z6.s\n" - "fmla z31.s, p0/M, z2.s, z6.s\n" - "ld1w { z6.s }, p0/Z, [x22, #4, MUL VL]\n" - "ld1w { z2.s }, p0/Z, [x22, #5, MUL VL]\n" - "addvl x22, x22, #6\n" + "fmla z29.s, p0/M, z0.s, z5.s\n" + "ld1w { z6.s }, p0/Z, [x22, #3, MUL VL]\n" + "fmla z30.s, p0/M, z1.s, z5.s\n" + "fmla z31.s, p0/M, z2.s, z5.s\n" + "ld1w { z2.s }, p0/Z, [x22, #4, MUL VL]\n" + "ld1w { z5.s }, p0/Z, [x22, #5, MUL VL]\n" + "fmla z8.s, p0/M, z6.s, z7.s\n" "ld1rw { z1.s }, p0/Z, [%x[Apanel], #44]\n" - "fmla z8.s, p0/M, z7.s, z5.s\n" - "fmla z11.s, p0/M, z7.s, z4.s\n" - "fmla z9.s, p0/M, z6.s, z5.s\n" - "fmla z12.s, p0/M, z6.s, z4.s\n" - "fmla z10.s, p0/M, z2.s, z5.s\n" - "fmla z13.s, p0/M, z2.s, z4.s\n" - "ld1rw { z5.s }, p0/Z, [%x[Apanel], #48]\n" - "fmla z14.s, p0/M, z7.s, z3.s\n" - "fmla z15.s, p0/M, z6.s, z3.s\n" + "fmla z9.s, p0/M, z2.s, z7.s\n" + "fmla z10.s, p0/M, z5.s, z7.s\n" + "fmla z11.s, p0/M, z6.s, z4.s\n" + "ld1rw { z7.s }, p0/Z, [%x[Apanel], #48]\n" + "fmla z12.s, p0/M, z2.s, z4.s\n" + "fmla z13.s, p0/M, z5.s, z4.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #52]\n" - "fmla z16.s, p0/M, z2.s, z3.s\n" - "fmla z17.s, p0/M, z7.s, z1.s\n" + "fmla z14.s, p0/M, z6.s, z3.s\n" + "fmla z15.s, p0/M, z2.s, z3.s\n" + "addvl x22, x22, #6\n" + "fmla z16.s, p0/M, z5.s, z3.s\n" "ld1rw { z0.s }, p0/Z, [%x[Apanel], #56]\n" - "fmla z18.s, p0/M, z6.s, z1.s\n" - "fmla z19.s, p0/M, z2.s, z1.s\n" + "fmla z17.s, p0/M, z6.s, z1.s\n" + "fmla z18.s, p0/M, z2.s, z1.s\n" + "fmla z19.s, p0/M, z5.s, z1.s\n" "ld1rw { z1.s }, p0/Z, [%x[Apanel], #60]\n" "add %x[Apanel], %x[Apanel], #0x40\n" - "fmla z20.s, p0/M, z7.s, z5.s\n" - "fmla z21.s, p0/M, z6.s, z5.s\n" - "fmla z22.s, p0/M, z2.s, z5.s\n" - "fmla z23.s, p0/M, z7.s, z4.s\n" + "fmla z20.s, p0/M, z6.s, z7.s\n" + "fmla z21.s, p0/M, z2.s, z7.s\n" + "fmla z22.s, p0/M, z5.s, z7.s\n" + "fmla z23.s, p0/M, z6.s, z4.s\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" - "fmla z24.s, p0/M, z6.s, z4.s\n" - "fmla z25.s, p0/M, z2.s, z4.s\n" + "fmla z24.s, p0/M, z2.s, z4.s\n" + "fmla z25.s, p0/M, z5.s, z4.s\n" "ld1rw { z4.s }, p0/Z, [%x[Apanel], #4]\n" - "fmla z26.s, p0/M, z7.s, z0.s\n" - "fmla z27.s, p0/M, z6.s, z0.s\n" - "fmla z28.s, p0/M, z2.s, z0.s\n" - "fmla z29.s, p0/M, z7.s, z1.s\n" + "fmla z26.s, p0/M, z6.s, z0.s\n" + "fmla z27.s, p0/M, z2.s, z0.s\n" + "fmla z28.s, p0/M, z5.s, z0.s\n" + "fmla z29.s, p0/M, z6.s, z1.s\n" "ld1w { z0.s }, p0/Z, [x22]\n" - "fmla z30.s, p0/M, z6.s, z1.s\n" - "fmla z31.s, p0/M, z2.s, z1.s\n" + "fmla z30.s, p0/M, z2.s, z1.s\n" + "fmla z31.s, p0/M, z5.s, z1.s\n" "ld1w { z1.s }, p0/Z, [x22, #1, MUL VL]\n" "ld1w { z2.s }, p0/Z, [x22, #2, MUL VL]\n" "ld1rw { z5.s }, p0/Z, [%x[Apanel], #8]\n" @@ -199,20 +199,19 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n" "ld1w { z4.s }, p0/Z, [x22, #2, MUL VL]\n" "ld1rw { z3.s }, p0/Z, [%x[Apanel]]\n" - "addvl x22, x22, #3\n" + "fmla z8.s, p0/M, z6.s, z3.s\n" "ld1rw { z2.s }, p0/Z, [%x[Apanel], #4]\n" "ld1rw { z1.s }, p0/Z, [%x[Apanel], #8]\n" - "ld1rw { z0.s }, p0/Z, [%x[Apanel], #12]\n" - "fmla z8.s, p0/M, z6.s, z3.s\n" "fmla z9.s, p0/M, z5.s, z3.s\n" + "ld1rw { z0.s }, p0/Z, [%x[Apanel], #12]\n" "fmla z10.s, p0/M, z4.s, z3.s\n" "fmla z11.s, p0/M, z6.s, z2.s\n" - "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" "fmla z12.s, p0/M, z5.s, z2.s\n" "fmla z13.s, p0/M, z4.s, z2.s\n" - "ld1rw { z2.s }, p0/Z, [%x[Apanel], #20]\n" + "ld1rw { z3.s }, p0/Z, [%x[Apanel], #16]\n" "fmla z14.s, p0/M, z6.s, z1.s\n" "fmla z15.s, p0/M, z5.s, z1.s\n" + "ld1rw { z2.s }, p0/Z, [%x[Apanel], #20]\n" "fmla z16.s, p0/M, z4.s, z1.s\n" "fmla z17.s, p0/M, z6.s, z0.s\n" "ld1rw { z1.s }, p0/Z, [%x[Apanel], #24]\n" @@ -221,9 +220,10 @@ void sve_interleaved_fp32_mla_8x3VL_a64fx( "ld1rw { z0.s }, p0/Z, [%x[Apanel], #28]\n" "fmla z20.s, p0/M, z6.s, z3.s\n" "fmla z21.s, p0/M, z5.s, z3.s\n" - "add %x[Apanel], %x[Apanel], #0x20\n" + "addvl x22, x22, #3\n" "fmla z22.s, p0/M, z4.s, z3.s\n" "fmla z23.s, p0/M, z6.s, z2.s\n" + "add %x[Apanel], %x[Apanel], #0x20\n" "fmla z24.s, p0/M, z5.s, z2.s\n" "fmla z25.s, p0/M, z4.s, z2.s\n" "fmla z26.s, p0/M, z6.s, z1.s\n" |