diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp index 3b16c97e2c..09180c8f36 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, 2023 Arm Limited. + * Copyright (c) 2019-2021, 2023-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -54,22 +54,22 @@ void sve_interleaved_fp16_mla_8x3VL( "2:" // Width loop "ldr x20, [%x[args_ptr], %[offsetof_K]]\n" "mov %x[Apanel], x21\n" - "cmp x20, #0x2\n" "mov z8.b, #0x0\n" "mov z9.b, #0x0\n" - "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" "mov z10.b, #0x0\n" - "mov z11.b, #0x0\n" "ld1h { z2.h }, p0/Z, [x22]\n" + "mov z11.b, #0x0\n" "mov z12.b, #0x0\n" - "mov z13.b, #0x0\n" "ld1h { z3.h }, p0/Z, [x22, #1, MUL VL]\n" + "cmp x20, #0x2\n" + "mov z13.b, #0x0\n" "mov z14.b, #0x0\n" "mov z15.b, #0x0\n" - "ld1h { z4.h }, p0/Z, [x22, #2, MUL VL]\n" "mov z16.b, #0x0\n" + "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" "mov z17.b, #0x0\n" "mov z18.b, #0x0\n" + "ld1h { z4.h }, p0/Z, [x22, #2, MUL VL]\n" "mov z19.b, #0x0\n" "mov z20.b, #0x0\n" "mov z21.b, #0x0\n" @@ -147,12 +147,12 @@ void sve_interleaved_fp16_mla_8x3VL( "fmla z31.h, z1.h, z7.h[7]\n" "bge 3b\n" "4:" // main loop skip + "add %x[Apanel], %x[Apanel], #0x10\n" + "addvl x22, x22, #3\n" "fmla z8.h, z2.h, z0.h[0]\n" "fmla z11.h, z2.h, z0.h[1]\n" - "add %x[Apanel], %x[Apanel], #0x10\n" "fmla z14.h, z2.h, z0.h[2]\n" "fmla z17.h, z2.h, z0.h[3]\n" - "addvl x22, x22, #3\n" "fmla z20.h, z2.h, z0.h[4]\n" "fmla z23.h, z2.h, z0.h[5]\n" "fmla z26.h, z2.h, z0.h[6]\n" @@ -176,16 +176,16 @@ void sve_interleaved_fp16_mla_8x3VL( "cbz x20, 5f\n" "ld1rqh { z3.h }, p0/Z, [%x[Apanel]]\n" "ld1h { z2.h }, p0/Z, [x22]\n" - "fmla z8.h, z2.h, z3.h[0]\n" + "add %x[Apanel], %x[Apanel], #0x10\n" "ld1h { z1.h }, p0/Z, [x22, #1, MUL VL]\n" "ld1h { z0.h }, p0/Z, [x22, #2, MUL VL]\n" + "addvl x22, x22, #3\n" + "fmla z8.h, z2.h, z3.h[0]\n" "fmla z11.h, z2.h, z3.h[1]\n" "fmla z14.h, z2.h, z3.h[2]\n" "fmla z17.h, z2.h, z3.h[3]\n" - "add %x[Apanel], %x[Apanel], #0x10\n" "fmla z20.h, z2.h, z3.h[4]\n" "fmla z23.h, z2.h, z3.h[5]\n" - "addvl x22, x22, #3\n" "fmla z26.h, z2.h, z3.h[6]\n" "fmla z29.h, z2.h, z3.h[7]\n" "fmla z9.h, z1.h, z3.h[0]\n" |