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Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_mmla_8x3VL/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_mmla_8x3VL/generic.cpp140
1 files changed, 70 insertions, 70 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_mmla_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_mmla_8x3VL/generic.cpp
index de4f0ad313..fe5382db05 100644
--- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_mmla_8x3VL/generic.cpp
+++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_bf16fp32_mmla_8x3VL/generic.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021 Arm Limited.
+ * Copyright (c) 2019-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -10,16 +10,16 @@
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
#ifdef ARM_COMPUTE_ENABLE_SVE
@@ -33,28 +33,28 @@ void sve_interleaved_bf16fp32_mmla_8x3VL(
float *Cpanel, int ablocks, int bblocks, int K) {
struct KernelArgs {
- size_t bblocks = {};
size_t K = {};
const bfloat16 *Bpanel = {};
+ size_t bblocks = {};
} ka;
- ka.bblocks = bblocks;
ka.K = (K/4) - 1;
ka.Bpanel = Bpanel;
+ ka.bblocks = bblocks;
__asm__ __volatile__(
"ptrue p0.b\n"
"1:" // Height loop
- "ldr x22, [%x[args_ptr], %[offsetof_bblocks]]\n"
+ "ldr x23, [%x[args_ptr], %[offsetof_bblocks]]\n"
+ "ldr x22, [%x[args_ptr], %[offsetof_Bpanel]]\n"
"mov x21, %x[Apanel]\n"
- "ldr x20, [%x[args_ptr], %[offsetof_Bpanel]]\n"
"2:" // Width loop
- "ldr x19, [%x[args_ptr], %[offsetof_K]]\n"
+ "ldr x20, [%x[args_ptr], %[offsetof_K]]\n"
"mov %x[Apanel], x21\n"
- "cmp x19, #0x2\n"
+ "cmp x20, #0x2\n"
"mov z8.b, #0x0\n"
"mov z9.b, #0x0\n"
- "ld1h { z4.h }, p0/Z, [x20]\n"
+ "ld1h { z4.h }, p0/Z, [x22]\n"
"mov z10.b, #0x0\n"
"mov z11.b, #0x0\n"
"ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n"
@@ -63,13 +63,13 @@ void sve_interleaved_bf16fp32_mmla_8x3VL(
"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n"
"mov z14.b, #0x0\n"
"mov z15.b, #0x0\n"
- "ld1h { z5.h }, p0/Z, [x20, #1, MUL VL]\n"
+ "ld1h { z5.h }, p0/Z, [x22, #1, MUL VL]\n"
"mov z16.b, #0x0\n"
"mov z17.b, #0x0\n"
"ld1rqh { z2.h }, p0/Z, [%x[Apanel], #32]\n"
"mov z18.b, #0x0\n"
"mov z19.b, #0x0\n"
- "addvl x20, x20, #2\n"
+ "addvl x22, x22, #2\n"
"mov z20.b, #0x0\n"
"mov z21.b, #0x0\n"
"add %x[Apanel], %x[Apanel], #0x30\n"
@@ -87,143 +87,143 @@ void sve_interleaved_bf16fp32_mmla_8x3VL(
"3:" // main loop head
"ld1rqh { z3.h }, p0/Z, [%x[Apanel]]\n"
".inst 0x6464e408 // bfmmla z8.s, z0.h, z4.h\n"
- ".inst 0x6464e42e // bfmmla z14.s, z1.h, z4.h\n"
".inst 0x6465e40b // bfmmla z11.s, z0.h, z5.h\n"
+ ".inst 0x6464e42e // bfmmla z14.s, z1.h, z4.h\n"
".inst 0x6465e431 // bfmmla z17.s, z1.h, z5.h\n"
- "ld1h { z6.h }, p0/Z, [x20]\n"
+ "ld1h { z6.h }, p0/Z, [x22]\n"
".inst 0x6464e454 // bfmmla z20.s, z2.h, z4.h\n"
".inst 0x6465e457 // bfmmla z23.s, z2.h, z5.h\n"
- "ld1h { z7.h }, p0/Z, [x20, #1, MUL VL]\n"
+ "ld1h { z7.h }, p0/Z, [x22, #1, MUL VL]\n"
".inst 0x6464e47a // bfmmla z26.s, z3.h, z4.h\n"
".inst 0x6465e47d // bfmmla z29.s, z3.h, z5.h\n"
- "ld1h { z4.h }, p0/Z, [x20, #2, MUL VL]\n"
- "ld1h { z5.h }, p0/Z, [x20, #3, MUL VL]\n"
+ "ld1h { z4.h }, p0/Z, [x22, #2, MUL VL]\n"
+ "ld1h { z5.h }, p0/Z, [x22, #3, MUL VL]\n"
".inst 0x6466e409 // bfmmla z9.s, z0.h, z6.h\n"
+ ".inst 0x6467e40c // bfmmla z12.s, z0.h, z7.h\n"
".inst 0x6466e42f // bfmmla z15.s, z1.h, z6.h\n"
+ ".inst 0x6467e432 // bfmmla z18.s, z1.h, z7.h\n"
+ "sub x20, x20, #0x2\n"
".inst 0x6466e455 // bfmmla z21.s, z2.h, z6.h\n"
+ ".inst 0x6467e458 // bfmmla z24.s, z2.h, z7.h\n"
+ "cmp x20, #0x2\n"
".inst 0x6466e47b // bfmmla z27.s, z3.h, z6.h\n"
- "ld1h { z6.h }, p0/Z, [x20, #4, MUL VL]\n"
- ".inst 0x6467e40c // bfmmla z12.s, z0.h, z7.h\n"
+ ".inst 0x6467e47e // bfmmla z30.s, z3.h, z7.h\n"
+ "ld1h { z6.h }, p0/Z, [x22, #4, MUL VL]\n"
".inst 0x6464e40a // bfmmla z10.s, z0.h, z4.h\n"
- "sub x19, x19, #0x2\n"
".inst 0x6465e40d // bfmmla z13.s, z0.h, z5.h\n"
- ".inst 0x6467e432 // bfmmla z18.s, z1.h, z7.h\n"
"ld1rqh { z0.h }, p0/Z, [%x[Apanel], #16]\n"
".inst 0x6464e430 // bfmmla z16.s, z1.h, z4.h\n"
".inst 0x6465e433 // bfmmla z19.s, z1.h, z5.h\n"
"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #32]\n"
- ".inst 0x6467e458 // bfmmla z24.s, z2.h, z7.h\n"
- ".inst 0x6467e47e // bfmmla z30.s, z3.h, z7.h\n"
- "ld1h { z7.h }, p0/Z, [x20, #5, MUL VL]\n"
".inst 0x6464e456 // bfmmla z22.s, z2.h, z4.h\n"
".inst 0x6465e459 // bfmmla z25.s, z2.h, z5.h\n"
- "ld1rqh { z2.h }, p0/Z, [%x[Apanel], #48]\n"
+ "ld1h { z7.h }, p0/Z, [x22, #5, MUL VL]\n"
".inst 0x6464e47c // bfmmla z28.s, z3.h, z4.h\n"
".inst 0x6465e47f // bfmmla z31.s, z3.h, z5.h\n"
+ "ld1rqh { z2.h }, p0/Z, [%x[Apanel], #48]\n"
"ld1rqh { z3.h }, p0/Z, [%x[Apanel], #64]\n"
- "ld1h { z4.h }, p0/Z, [x20, #6, MUL VL]\n"
- "ld1h { z5.h }, p0/Z, [x20, #7, MUL VL]\n"
- "addvl x20, x20, #16\n"
+ "ld1h { z4.h }, p0/Z, [x22, #6, MUL VL]\n"
".inst 0x6466e408 // bfmmla z8.s, z0.h, z6.h\n"
- ".inst 0x6466e42e // bfmmla z14.s, z1.h, z6.h\n"
- "cmp x19, #0x2\n"
+ "ld1h { z5.h }, p0/Z, [x22, #7, MUL VL]\n"
+ "addvl x22, x22, #16\n"
".inst 0x6467e40b // bfmmla z11.s, z0.h, z7.h\n"
+ ".inst 0x6466e42e // bfmmla z14.s, z1.h, z6.h\n"
".inst 0x6467e431 // bfmmla z17.s, z1.h, z7.h\n"
".inst 0x6466e454 // bfmmla z20.s, z2.h, z6.h\n"
".inst 0x6467e457 // bfmmla z23.s, z2.h, z7.h\n"
".inst 0x6466e47a // bfmmla z26.s, z3.h, z6.h\n"
".inst 0x6467e47d // bfmmla z29.s, z3.h, z7.h\n"
- "ld1h { z6.h }, p0/Z, [x20, #-8, MUL VL]\n"
- "ld1h { z7.h }, p0/Z, [x20, #-7, MUL VL]\n"
+ "ld1h { z6.h }, p0/Z, [x22, #-8, MUL VL]\n"
+ "ld1h { z7.h }, p0/Z, [x22, #-7, MUL VL]\n"
".inst 0x6464e409 // bfmmla z9.s, z0.h, z4.h\n"
+ ".inst 0x6465e40c // bfmmla z12.s, z0.h, z5.h\n"
".inst 0x6464e42f // bfmmla z15.s, z1.h, z4.h\n"
+ ".inst 0x6465e432 // bfmmla z18.s, z1.h, z5.h\n"
".inst 0x6464e455 // bfmmla z21.s, z2.h, z4.h\n"
+ ".inst 0x6465e458 // bfmmla z24.s, z2.h, z5.h\n"
".inst 0x6464e47b // bfmmla z27.s, z3.h, z4.h\n"
- "ld1h { z4.h }, p0/Z, [x20, #-6, MUL VL]\n"
- ".inst 0x6465e40c // bfmmla z12.s, z0.h, z5.h\n"
+ ".inst 0x6465e47e // bfmmla z30.s, z3.h, z5.h\n"
+ "ld1h { z4.h }, p0/Z, [x22, #-6, MUL VL]\n"
".inst 0x6466e40a // bfmmla z10.s, z0.h, z6.h\n"
".inst 0x6467e40d // bfmmla z13.s, z0.h, z7.h\n"
- ".inst 0x6465e432 // bfmmla z18.s, z1.h, z5.h\n"
"ld1rqh { z0.h }, p0/Z, [%x[Apanel], #80]\n"
".inst 0x6466e430 // bfmmla z16.s, z1.h, z6.h\n"
".inst 0x6467e433 // bfmmla z19.s, z1.h, z7.h\n"
"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #96]\n"
- ".inst 0x6465e458 // bfmmla z24.s, z2.h, z5.h\n"
- ".inst 0x6465e47e // bfmmla z30.s, z3.h, z5.h\n"
- "ld1h { z5.h }, p0/Z, [x20, #-5, MUL VL]\n"
".inst 0x6466e456 // bfmmla z22.s, z2.h, z6.h\n"
".inst 0x6467e459 // bfmmla z25.s, z2.h, z7.h\n"
- "ld1rqh { z2.h }, p0/Z, [%x[Apanel], #112]\n"
+ "ld1h { z5.h }, p0/Z, [x22, #-5, MUL VL]\n"
".inst 0x6466e47c // bfmmla z28.s, z3.h, z6.h\n"
".inst 0x6467e47f // bfmmla z31.s, z3.h, z7.h\n"
+ "ld1rqh { z2.h }, p0/Z, [%x[Apanel], #112]\n"
"add %x[Apanel], %x[Apanel], #0x80\n"
- "addvl x20, x20, #-4\n"
+ "addvl x22, x22, #-4\n"
"bge 3b\n"
"4:" // main loop skip
"ld1rqh { z3.h }, p0/Z, [%x[Apanel]]\n"
".inst 0x6464e408 // bfmmla z8.s, z0.h, z4.h\n"
- ".inst 0x6464e42e // bfmmla z14.s, z1.h, z4.h\n"
".inst 0x6465e40b // bfmmla z11.s, z0.h, z5.h\n"
+ ".inst 0x6464e42e // bfmmla z14.s, z1.h, z4.h\n"
".inst 0x6465e431 // bfmmla z17.s, z1.h, z5.h\n"
- "ld1h { z6.h }, p0/Z, [x20]\n"
+ "ld1h { z6.h }, p0/Z, [x22]\n"
".inst 0x6464e454 // bfmmla z20.s, z2.h, z4.h\n"
".inst 0x6465e457 // bfmmla z23.s, z2.h, z5.h\n"
- "ld1h { z7.h }, p0/Z, [x20, #1, MUL VL]\n"
+ "ld1h { z7.h }, p0/Z, [x22, #1, MUL VL]\n"
".inst 0x6464e47a // bfmmla z26.s, z3.h, z4.h\n"
".inst 0x6465e47d // bfmmla z29.s, z3.h, z5.h\n"
- "ld1h { z4.h }, p0/Z, [x20, #2, MUL VL]\n"
- "ld1h { z5.h }, p0/Z, [x20, #3, MUL VL]\n"
+ "ld1h { z4.h }, p0/Z, [x22, #2, MUL VL]\n"
+ "ld1h { z5.h }, p0/Z, [x22, #3, MUL VL]\n"
".inst 0x6466e409 // bfmmla z9.s, z0.h, z6.h\n"
+ ".inst 0x6467e40c // bfmmla z12.s, z0.h, z7.h\n"
".inst 0x6466e42f // bfmmla z15.s, z1.h, z6.h\n"
+ ".inst 0x6467e432 // bfmmla z18.s, z1.h, z7.h\n"
+ "add %x[Apanel], %x[Apanel], #0x10\n"
".inst 0x6466e455 // bfmmla z21.s, z2.h, z6.h\n"
+ ".inst 0x6467e458 // bfmmla z24.s, z2.h, z7.h\n"
+ "addvl x22, x22, #4\n"
".inst 0x6466e47b // bfmmla z27.s, z3.h, z6.h\n"
- "add %x[Apanel], %x[Apanel], #0x10\n"
- ".inst 0x6467e40c // bfmmla z12.s, z0.h, z7.h\n"
+ ".inst 0x6467e47e // bfmmla z30.s, z3.h, z7.h\n"
".inst 0x6464e40a // bfmmla z10.s, z0.h, z4.h\n"
- "addvl x20, x20, #4\n"
".inst 0x6465e40d // bfmmla z13.s, z0.h, z5.h\n"
- ".inst 0x6467e432 // bfmmla z18.s, z1.h, z7.h\n"
".inst 0x6464e430 // bfmmla z16.s, z1.h, z4.h\n"
".inst 0x6465e433 // bfmmla z19.s, z1.h, z5.h\n"
- ".inst 0x6467e458 // bfmmla z24.s, z2.h, z7.h\n"
- ".inst 0x6467e47e // bfmmla z30.s, z3.h, z7.h\n"
".inst 0x6464e456 // bfmmla z22.s, z2.h, z4.h\n"
".inst 0x6465e459 // bfmmla z25.s, z2.h, z5.h\n"
".inst 0x6464e47c // bfmmla z28.s, z3.h, z4.h\n"
".inst 0x6465e47f // bfmmla z31.s, z3.h, z5.h\n"
- "cbz x19, 5f\n"
- "ld1h { z6.h }, p0/Z, [x20]\n"
+ "cbz x20, 5f\n"
+ "ld1h { z6.h }, p0/Z, [x22]\n"
"ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n"
".inst 0x6466e408 // bfmmla z8.s, z0.h, z6.h\n"
"ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n"
- "ld1h { z7.h }, p0/Z, [x20, #1, MUL VL]\n"
- ".inst 0x6466e42e // bfmmla z14.s, z1.h, z6.h\n"
+ "ld1h { z7.h }, p0/Z, [x22, #1, MUL VL]\n"
+ ".inst 0x6467e40b // bfmmla z11.s, z0.h, z7.h\n"
"ld1rqh { z2.h }, p0/Z, [%x[Apanel], #32]\n"
"ld1rqh { z3.h }, p0/Z, [%x[Apanel], #48]\n"
- ".inst 0x6467e40b // bfmmla z11.s, z0.h, z7.h\n"
+ ".inst 0x6466e42e // bfmmla z14.s, z1.h, z6.h\n"
".inst 0x6467e431 // bfmmla z17.s, z1.h, z7.h\n"
".inst 0x6466e454 // bfmmla z20.s, z2.h, z6.h\n"
- "ld1h { z4.h }, p0/Z, [x20, #2, MUL VL]\n"
+ "ld1h { z4.h }, p0/Z, [x22, #2, MUL VL]\n"
".inst 0x6467e457 // bfmmla z23.s, z2.h, z7.h\n"
".inst 0x6466e47a // bfmmla z26.s, z3.h, z6.h\n"
- "ld1h { z5.h }, p0/Z, [x20, #3, MUL VL]\n"
+ "ld1h { z5.h }, p0/Z, [x22, #3, MUL VL]\n"
".inst 0x6467e47d // bfmmla z29.s, z3.h, z7.h\n"
- "ld1h { z6.h }, p0/Z, [x20, #4, MUL VL]\n"
- "ld1h { z7.h }, p0/Z, [x20, #5, MUL VL]\n"
+ "ld1h { z6.h }, p0/Z, [x22, #4, MUL VL]\n"
+ "ld1h { z7.h }, p0/Z, [x22, #5, MUL VL]\n"
".inst 0x6464e409 // bfmmla z9.s, z0.h, z4.h\n"
+ ".inst 0x6465e40c // bfmmla z12.s, z0.h, z5.h\n"
+ "addvl x22, x22, #6\n"
".inst 0x6464e42f // bfmmla z15.s, z1.h, z4.h\n"
+ ".inst 0x6465e432 // bfmmla z18.s, z1.h, z5.h\n"
"add %x[Apanel], %x[Apanel], #0x40\n"
".inst 0x6464e455 // bfmmla z21.s, z2.h, z4.h\n"
+ ".inst 0x6465e458 // bfmmla z24.s, z2.h, z5.h\n"
".inst 0x6464e47b // bfmmla z27.s, z3.h, z4.h\n"
- "addvl x20, x20, #6\n"
- ".inst 0x6465e40c // bfmmla z12.s, z0.h, z5.h\n"
+ ".inst 0x6465e47e // bfmmla z30.s, z3.h, z5.h\n"
".inst 0x6466e40a // bfmmla z10.s, z0.h, z6.h\n"
".inst 0x6467e40d // bfmmla z13.s, z0.h, z7.h\n"
- ".inst 0x6465e432 // bfmmla z18.s, z1.h, z5.h\n"
".inst 0x6466e430 // bfmmla z16.s, z1.h, z6.h\n"
".inst 0x6467e433 // bfmmla z19.s, z1.h, z7.h\n"
- ".inst 0x6465e458 // bfmmla z24.s, z2.h, z5.h\n"
- ".inst 0x6465e47e // bfmmla z30.s, z3.h, z5.h\n"
".inst 0x6466e456 // bfmmla z22.s, z2.h, z6.h\n"
".inst 0x6467e459 // bfmmla z25.s, z2.h, z7.h\n"
".inst 0x6466e47c // bfmmla z28.s, z3.h, z6.h\n"
@@ -243,7 +243,7 @@ void sve_interleaved_bf16fp32_mmla_8x3VL(
"uzp2 z14.d, z14.d, z17.d\n"
"st1w { z9.s }, p0, [%x[Cpanel], #4, MUL VL]\n"
"uzp1 z17.d, z15.d, z18.d\n"
- "subs x22, x22, #0x1\n"
+ "subs x23, x23, #0x1\n"
"st1w { z10.s }, p0, [%x[Cpanel], #5, MUL VL]\n"
"uzp2 z15.d, z15.d, z18.d\n"
"uzp1 z18.d, z16.d, z19.d\n"
@@ -285,7 +285,7 @@ void sve_interleaved_bf16fp32_mmla_8x3VL(
"bne 1b\n"
: [Apanel] "+&r" (Apanel), [Cpanel] "+&r" (Cpanel), [ablocks] "+&r" (ablocks)
: [args_ptr] "r" (&ka), [offsetof_Bpanel] "I" (offsetof(KernelArgs, Bpanel)), [offsetof_K] "I" (offsetof(KernelArgs, K)), [offsetof_bblocks] "I" (offsetof(KernelArgs, bblocks))
- : "cc", "memory", "p0", "x19", "x20", "x21", "x22", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"
+ : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31"
);
}
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-20 09:51:17 +0000