diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/generic.cpp | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/generic.cpp index 1e9a3f119e..4a0b31daff 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_ffinterleaved_fp32_mla_8x3VL/generic.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Arm Limited. + * Copyright (c) 2022-2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -10,16 +10,16 @@ * sell copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. */ #ifdef ARM_COMPUTE_ENABLE_SVE @@ -52,29 +52,29 @@ void sve_ffinterleaved_fp32_mla_8x3VL( __asm__ __volatile__( "ptrue p0.b\n" "1:" // Height loop - "ldr x25, [%x[args_ptr], %[offsetof_Bpanel]]\n" - "ldr x24, [%x[args_ptr], %[offsetof_N]]\n" - "str x25, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" - "mov x23, %x[Apanel]\n" + "ldr x26, [%x[args_ptr], %[offsetof_Bpanel]]\n" + "ldr x25, [%x[args_ptr], %[offsetof_N]]\n" + "str x26, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" + "mov x24, %x[Apanel]\n" "2:" // Width loop - "ldr x25, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" - "ldr x19, [%x[args_ptr], %[offsetof_B_stride]]\n" - "cntw x22, ALL, MUL #2\n" - "add x21, x25, x19, LSL #2\n" - "add x20, x21, x19, LSL #2\n" - "add x19, x20, x19, LSL #2\n" - "cmp x24, x22\n" - "str x19, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" - "mov %x[Apanel], x23\n" + "ldr x26, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" + "ldr x20, [%x[args_ptr], %[offsetof_B_stride]]\n" + "cntw x23, ALL, MUL #2\n" + "add x22, x26, x20, LSL #2\n" + "add x21, x22, x20, LSL #2\n" + "add x20, x21, x20, LSL #2\n" + "cmp x25, x23\n" + "str x20, [%x[args_ptr], %[offsetof_cur_B_ptr]]\n" + "mov %x[Apanel], x24\n" "bgt 3f\n" - "decw x22\n" - "cmp x24, x22\n" - "mov x20, x25\n" + "decw x23\n" + "cmp x25, x23\n" + "mov x21, x26\n" "bgt 3f\n" - "mov x21, x25\n" + "mov x22, x26\n" "3:" // B setup done - "ldr x19, [%x[args_ptr], %[offsetof_K]]\n" - "cmp x19, #0x2\n" + "ldr x20, [%x[args_ptr], %[offsetof_K]]\n" + "cmp x20, #0x2\n" "mov z8.b, #0x0\n" "mov z9.b, #0x0\n" "mov z10.b, #0x0\n" @@ -84,13 +84,13 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "ld1rqw { z1.s }, p0/Z, [%x[Apanel], #16]\n" "mov z13.b, #0x0\n" "mov z14.b, #0x0\n" - "ld1w { z4.s }, p0/Z, [x25]\n" + "ld1w { z4.s }, p0/Z, [x26]\n" "mov z15.b, #0x0\n" "mov z16.b, #0x0\n" - "ld1w { z5.s }, p0/Z, [x21]\n" + "ld1w { z5.s }, p0/Z, [x22]\n" "mov z17.b, #0x0\n" "mov z18.b, #0x0\n" - "ld1w { z6.s }, p0/Z, [x20]\n" + "ld1w { z6.s }, p0/Z, [x21]\n" "mov z19.b, #0x0\n" "mov z20.b, #0x0\n" "mov z21.b, #0x0\n" @@ -114,25 +114,25 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "ld1rqw { z3.s }, p0/Z, [%x[Apanel], #48]\n" "fmla z20.s, z4.s, z1.s[0]\n" "fmla z23.s, z4.s, z1.s[1]\n" - "sub x19, x19, #0x2\n" + "sub x20, x20, #0x2\n" "fmla z26.s, z4.s, z1.s[2]\n" "fmla z29.s, z4.s, z1.s[3]\n" - "ld1w { z4.s }, p0/Z, [x25, #1, MUL VL]\n" + "ld1w { z4.s }, p0/Z, [x26, #1, MUL VL]\n" "fmla z9.s, z5.s, z0.s[0]\n" "fmla z12.s, z5.s, z0.s[1]\n" - "addvl x25, x25, #2\n" + "addvl x26, x26, #2\n" "fmla z15.s, z5.s, z0.s[2]\n" "fmla z18.s, z5.s, z0.s[3]\n" - "cmp x19, #0x2\n" + "cmp x20, #0x2\n" "fmla z21.s, z5.s, z1.s[0]\n" "fmla z24.s, z5.s, z1.s[1]\n" "add %x[Apanel], %x[Apanel], #0x40\n" "fmla z27.s, z5.s, z1.s[2]\n" "fmla z30.s, z5.s, z1.s[3]\n" - "ld1w { z5.s }, p0/Z, [x21, #1, MUL VL]\n" + "ld1w { z5.s }, p0/Z, [x22, #1, MUL VL]\n" "fmla z10.s, z6.s, z0.s[0]\n" "fmla z13.s, z6.s, z0.s[1]\n" - "addvl x21, x21, #2\n" + "addvl x22, x22, #2\n" "fmla z16.s, z6.s, z0.s[2]\n" "fmla z19.s, z6.s, z0.s[3]\n" "ld1rqw { z0.s }, p0/Z, [%x[Apanel]]\n" @@ -140,8 +140,8 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "fmla z25.s, z6.s, z1.s[1]\n" "fmla z28.s, z6.s, z1.s[2]\n" "fmla z31.s, z6.s, z1.s[3]\n" - "ld1w { z6.s }, p0/Z, [x20, #1, MUL VL]\n" - "addvl x20, x20, #2\n" + "ld1w { z6.s }, p0/Z, [x21, #1, MUL VL]\n" + "addvl x21, x21, #2\n" "fmla z8.s, z4.s, z2.s[0]\n" "fmla z11.s, z4.s, z2.s[1]\n" "fmla z14.s, z4.s, z2.s[2]\n" @@ -151,7 +151,7 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "fmla z23.s, z4.s, z3.s[1]\n" "fmla z26.s, z4.s, z3.s[2]\n" "fmla z29.s, z4.s, z3.s[3]\n" - "ld1w { z4.s }, p0/Z, [x25]\n" + "ld1w { z4.s }, p0/Z, [x26]\n" "fmla z9.s, z5.s, z2.s[0]\n" "fmla z12.s, z5.s, z2.s[1]\n" "fmla z15.s, z5.s, z2.s[2]\n" @@ -160,7 +160,7 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "fmla z24.s, z5.s, z3.s[1]\n" "fmla z27.s, z5.s, z3.s[2]\n" "fmla z30.s, z5.s, z3.s[3]\n" - "ld1w { z5.s }, p0/Z, [x21]\n" + "ld1w { z5.s }, p0/Z, [x22]\n" "fmla z10.s, z6.s, z2.s[0]\n" "fmla z13.s, z6.s, z2.s[1]\n" "fmla z16.s, z6.s, z2.s[2]\n" @@ -169,7 +169,7 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "fmla z25.s, z6.s, z3.s[1]\n" "fmla z28.s, z6.s, z3.s[2]\n" "fmla z31.s, z6.s, z3.s[3]\n" - "ld1w { z6.s }, p0/Z, [x20]\n" + "ld1w { z6.s }, p0/Z, [x21]\n" "bge 4b\n" "5:" // main loop skip "fmla z8.s, z4.s, z0.s[0]\n" @@ -177,13 +177,13 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "add %x[Apanel], %x[Apanel], #0x20\n" "fmla z14.s, z4.s, z0.s[2]\n" "fmla z17.s, z4.s, z0.s[3]\n" - "addvl x25, x25, #1\n" + "addvl x26, x26, #1\n" "fmla z20.s, z4.s, z1.s[0]\n" "fmla z23.s, z4.s, z1.s[1]\n" - "addvl x21, x21, #1\n" + "addvl x22, x22, #1\n" "fmla z26.s, z4.s, z1.s[2]\n" "fmla z29.s, z4.s, z1.s[3]\n" - "addvl x20, x20, #1\n" + "addvl x21, x21, #1\n" "fmla z9.s, z5.s, z0.s[0]\n" "fmla z12.s, z5.s, z0.s[1]\n" "fmla z15.s, z5.s, z0.s[2]\n" @@ -200,14 +200,14 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "fmla z25.s, z6.s, z1.s[1]\n" "fmla z28.s, z6.s, z1.s[2]\n" "fmla z31.s, z6.s, z1.s[3]\n" - "cbz x19, 6f\n" + "cbz x20, 6f\n" "ld1rqw { z0.s }, p0/Z, [%x[Apanel]]\n" "ld1rqw { z1.s }, p0/Z, [%x[Apanel], #16]\n" "add %x[Apanel], %x[Apanel], #0x20\n" - "ld1w { z7.s }, p0/Z, [x25]\n" - "ld1w { z4.s }, p0/Z, [x21]\n" + "ld1w { z7.s }, p0/Z, [x26]\n" + "ld1w { z4.s }, p0/Z, [x22]\n" "fmla z8.s, z7.s, z0.s[0]\n" - "ld1w { z5.s }, p0/Z, [x20]\n" + "ld1w { z5.s }, p0/Z, [x21]\n" "fmla z11.s, z7.s, z0.s[1]\n" "fmla z14.s, z7.s, z0.s[2]\n" "fmla z17.s, z7.s, z0.s[3]\n" @@ -232,9 +232,9 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "fmla z28.s, z5.s, z1.s[2]\n" "fmla z31.s, z5.s, z1.s[3]\n" "6:" // multiply loop done - "decw x24, ALL, MUL #3\n" + "decw x25, ALL, MUL #3\n" "st1w { z8.s }, p0, [%x[Cpanel]]\n" - "cmp x24, XZR\n" + "cmp x25, XZR\n" "st1w { z9.s }, p0, [%x[Cpanel], #1, MUL VL]\n" "st1w { z10.s }, p0, [%x[Cpanel], #2, MUL VL]\n" "st1w { z11.s }, p0, [%x[Cpanel], #3, MUL VL]\n" @@ -265,7 +265,7 @@ void sve_ffinterleaved_fp32_mla_8x3VL( "bne 1b\n" : [Apanel] "+&r" (Apanel), [Cpanel] "+&r" (Cpanel), [ablocks] "+&r" (ablocks) : [args_ptr] "r" (&ka), [offsetof_B_stride] "I" (offsetof(KernelArgs, B_stride)), [offsetof_Bpanel] "I" (offsetof(KernelArgs, Bpanel)), [offsetof_K] "I" (offsetof(KernelArgs, K)), [offsetof_N] "I" (offsetof(KernelArgs, N)), [offsetof_cur_B_ptr] "I" (offsetof(KernelArgs, cur_B_ptr)) - : "cc", "memory", "p0", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + : "cc", "memory", "p0", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" ); } |