diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst/generic.cpp | 316 |
1 files changed, 157 insertions, 159 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst/generic.cpp index 1676119bc1..c2bec4cdab 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst/generic.cpp @@ -22,12 +22,13 @@ * SOFTWARE. */ -#if defined(__aarch64__) #include "arm_gemm.hpp" #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace depthwise { @@ -41,7 +42,7 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( ) { __asm__ __volatile__( - "lsr x12, %x[n_channels], #0x2\n" + "lsr x9, %x[n_channels], #0x2\n" "add x20, %x[qp], %[offsetof_Requantize32_minval]\n" "ld1r { v8.4s }, [x20]\n" "add x20, %x[qp], %[offsetof_Requantize32_maxval]\n" @@ -59,7 +60,7 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "add x20, %x[qp], %[offsetof_Requantize32_per_layer_right_shift]\n" "ld1r { v1.4s }, [x20]\n" "mov x11, #0x0\n" - "cbz x12, 6f\n" + "cbz x9, 6f\n" "1:" // Channel loop "movi v23.4s, #0x0\n" "cbz %x[bias], 2f\n" @@ -67,34 +68,34 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "ldr q23, [%x[bias], x20]\n" "2:" // Channel loop: Load bias: Done "ldr s0, [%x[params]], #0x4\n" - "mov x21, %x[inptrs]\n" - "ldp x10, x9, [x21], #0x10\n" - "subs x20, %x[n_points], #0x1\n" - "ldr s14, [x10, x11]\n" - "ldr s15, [x9, x11]\n" + "mov x25, %x[inptrs]\n" + "ldp x21, x20, [x25], #0x10\n" + "subs x24, %x[n_points], #0x1\n" + "ldr s14, [x21, x11]\n" + "ldr s15, [x20, x11]\n" "mov v24.16b, v23.16b\n" "mov v25.16b, v23.16b\n" - "ldp x28, x27, [x21], #0x10\n" - "ldr s16, [x28, x11]\n" + "ldp x21, x20, [x25], #0x10\n" + "ldr s16, [x21, x11]\n" "mov v26.16b, v23.16b\n" "mov v27.16b, v23.16b\n" - "ldr s17, [x27, x11]\n" - "ldp x26, x25, [x21], #0x10\n" + "ldr s17, [x20, x11]\n" + "ldp x21, x20, [x25], #0x10\n" "mov v28.16b, v23.16b\n" "mov v29.16b, v23.16b\n" - "ldr s18, [x26, x11]\n" - "ldr s19, [x25, x11]\n" + "ldr s18, [x21, x11]\n" + "ldr s19, [x20, x11]\n" "mov v30.16b, v23.16b\n" "mov v31.16b, v23.16b\n" - "ldp x24, x23, [x21], #0x10\n" - "ldr s20, [x24, x11]\n" + "ldp x21, x20, [x25], #0x10\n" + "ldr s20, [x21, x11]\n" "ssubl v0.8h, v0.8b, v5.8b\n" "usubl v14.8h, v14.8b, v6.8b\n" - "ldr s21, [x23, x11]\n" - "ldr x22, [x21], #0x8\n" + "ldr s21, [x20, x11]\n" + "ldr x20, [x25], #0x8\n" "usubl v15.8h, v15.8b, v6.8b\n" "usubl v16.8h, v16.8b, v6.8b\n" - "ldr s22, [x22, x11]\n" + "ldr s22, [x20, x11]\n" "usubl v17.8h, v17.8b, v6.8b\n" "usubl v18.8h, v18.8b, v6.8b\n" "usubl v19.8h, v19.8b, v6.8b\n" @@ -103,35 +104,35 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "usubl v22.8h, v22.8b, v6.8b\n" "ble 4f\n" "3:" // Channel loop: Planar loop - "ldp x10, x9, [x21], #0x10\n" - "ldp x28, x27, [x21], #0x10\n" + "ldp x23, x22, [x25], #0x10\n" + "ldp x21, x20, [x25], #0x10\n" "smlal v23.4s, v14.4h, v0.4h\n" "smlal v24.4s, v15.4h, v0.4h\n" - "ldr s14, [x10, x11]\n" - "ldr s15, [x9, x11]\n" + "ldr s14, [x23, x11]\n" + "ldr s15, [x22, x11]\n" "smlal v25.4s, v16.4h, v0.4h\n" "smlal v26.4s, v17.4h, v0.4h\n" - "ldr s16, [x28, x11]\n" - "ldr s17, [x27, x11]\n" + "ldr s16, [x21, x11]\n" + "ldr s17, [x20, x11]\n" "smlal v27.4s, v18.4h, v0.4h\n" "smlal v28.4s, v19.4h, v0.4h\n" - "ldp x26, x25, [x21], #0x10\n" - "ldr s18, [x26, x11]\n" + "ldp x21, x20, [x25], #0x10\n" + "ldr s18, [x21, x11]\n" "smlal v29.4s, v20.4h, v0.4h\n" "smlal v30.4s, v21.4h, v0.4h\n" - "ldr s19, [x25, x11]\n" - "ldp x24, x23, [x21], #0x10\n" + "ldr s19, [x20, x11]\n" + "ldp x21, x20, [x25], #0x10\n" "smlal v31.4s, v22.4h, v0.4h\n" - "subs x20, x20, #0x1\n" + "subs x24, x24, #0x1\n" "ldr s0, [%x[params]], #0x4\n" - "ldr s20, [x24, x11]\n" + "ldr s20, [x21, x11]\n" "ssubl v0.8h, v0.8b, v5.8b\n" "usubl v14.8h, v14.8b, v6.8b\n" - "ldr s21, [x23, x11]\n" - "ldr x22, [x21], #0x8\n" + "ldr s21, [x20, x11]\n" + "ldr x20, [x25], #0x8\n" "usubl v15.8h, v15.8b, v6.8b\n" "usubl v16.8h, v16.8b, v6.8b\n" - "ldr s22, [x22, x11]\n" + "ldr s22, [x20, x11]\n" "usubl v17.8h, v17.8b, v6.8b\n" "usubl v18.8h, v18.8b, v6.8b\n" "usubl v19.8h, v19.8b, v6.8b\n" @@ -167,45 +168,45 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "sqrdmulh v24.4s, v24.4s, v2.4s\n" "sqrdmulh v25.4s, v25.4s, v2.4s\n" "ldr x20, [%x[outptrs], #0x40]\n" - "and v21.16b, v23.16b, v1.16b\n" - "and v20.16b, v24.16b, v1.16b\n" - "and v19.16b, v25.16b, v1.16b\n" + "and v18.16b, v23.16b, v1.16b\n" + "and v17.16b, v24.16b, v1.16b\n" + "and v16.16b, v25.16b, v1.16b\n" "sshl v26.4s, v26.4s, v3.4s\n" "sshl v27.4s, v27.4s, v3.4s\n" "sshl v28.4s, v28.4s, v3.4s\n" "sshl v29.4s, v29.4s, v3.4s\n" "sshl v30.4s, v30.4s, v3.4s\n" "sshl v31.4s, v31.4s, v3.4s\n" - "sshr v21.4s, v21.4s, #0x1f\n" - "sshr v20.4s, v20.4s, #0x1f\n" - "sshr v19.4s, v19.4s, #0x1f\n" + "sshr v18.4s, v18.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "sshr v16.4s, v16.4s, #0x1f\n" "sqrdmulh v26.4s, v26.4s, v2.4s\n" "sqrdmulh v27.4s, v27.4s, v2.4s\n" "sqrdmulh v28.4s, v28.4s, v2.4s\n" "sqrdmulh v29.4s, v29.4s, v2.4s\n" "sqrdmulh v30.4s, v30.4s, v2.4s\n" "sqrdmulh v31.4s, v31.4s, v2.4s\n" - "sqadd v23.4s, v23.4s, v21.4s\n" - "sqadd v24.4s, v24.4s, v20.4s\n" - "sqadd v25.4s, v25.4s, v19.4s\n" - "and v18.16b, v26.16b, v1.16b\n" - "and v17.16b, v27.16b, v1.16b\n" - "and v16.16b, v28.16b, v1.16b\n" - "and v21.16b, v29.16b, v1.16b\n" - "and v20.16b, v30.16b, v1.16b\n" - "and v19.16b, v31.16b, v1.16b\n" - "sshr v18.4s, v18.4s, #0x1f\n" - "sshr v17.4s, v17.4s, #0x1f\n" - "sshr v16.4s, v16.4s, #0x1f\n" + "sqadd v23.4s, v23.4s, v18.4s\n" + "sqadd v24.4s, v24.4s, v17.4s\n" + "sqadd v25.4s, v25.4s, v16.4s\n" + "and v21.16b, v26.16b, v1.16b\n" + "and v20.16b, v27.16b, v1.16b\n" + "and v19.16b, v28.16b, v1.16b\n" + "and v18.16b, v29.16b, v1.16b\n" + "and v17.16b, v30.16b, v1.16b\n" + "and v16.16b, v31.16b, v1.16b\n" "sshr v21.4s, v21.4s, #0x1f\n" "sshr v20.4s, v20.4s, #0x1f\n" "sshr v19.4s, v19.4s, #0x1f\n" - "sqadd v26.4s, v26.4s, v18.4s\n" - "sqadd v27.4s, v27.4s, v17.4s\n" - "sqadd v28.4s, v28.4s, v16.4s\n" - "sqadd v29.4s, v29.4s, v21.4s\n" - "sqadd v30.4s, v30.4s, v20.4s\n" - "sqadd v31.4s, v31.4s, v19.4s\n" + "sshr v18.4s, v18.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "sqadd v26.4s, v26.4s, v21.4s\n" + "sqadd v27.4s, v27.4s, v20.4s\n" + "sqadd v28.4s, v28.4s, v19.4s\n" + "sqadd v29.4s, v29.4s, v18.4s\n" + "sqadd v30.4s, v30.4s, v17.4s\n" + "sqadd v31.4s, v31.4s, v16.4s\n" "srshl v23.4s, v23.4s, v1.4s\n" "srshl v24.4s, v24.4s, v1.4s\n" "srshl v25.4s, v25.4s, v1.4s\n" @@ -270,7 +271,7 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "str s30, [x21, x11]\n" "str s31, [x20, x11]\n" "add x11, x11, #0x4\n" - "cmp x11, x12, LSL #2\n" + "cmp x11, x9, LSL #2\n" "blt 1b\n" "6:" // Oddments "tst %x[n_channels], #0x3\n" @@ -288,61 +289,61 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "8:" // Oddments: Load bias: Bit 1: End "9:" // Oddments: Load bias: Done "ldr s0, [%x[params]], #0x4\n" - "mov x21, %x[inptrs]\n" - "ldp x10, x9, [x21], #0x10\n" + "mov x10, %x[inptrs]\n" + "ldp x9, x28, [x10], #0x10\n" "mov v24.16b, v23.16b\n" - "ldp x28, x27, [x21], #0x10\n" - "ldp x26, x25, [x21], #0x10\n" + "ldp x27, x26, [x10], #0x10\n" + "ldp x25, x24, [x10], #0x10\n" "mov v25.16b, v23.16b\n" "mov v26.16b, v23.16b\n" - "ldp x24, x23, [x21], #0x10\n" - "ldr x22, [x21], #0x8\n" + "ldp x23, x22, [x10], #0x10\n" + "ldr x21, [x10], #0x8\n" "mov v27.16b, v23.16b\n" "mov v28.16b, v23.16b\n" "mov v29.16b, v23.16b\n" "mov v30.16b, v23.16b\n" - "add x10, x10, x11\n" "add x9, x9, x11\n" + "add x28, x28, x11\n" "mov v31.16b, v23.16b\n" "ssubl v0.8h, v0.8b, v5.8b\n" - "add x28, x28, x11\n" "add x27, x27, x11\n" "add x26, x26, x11\n" "add x25, x25, x11\n" "add x24, x24, x11\n" "add x23, x23, x11\n" "add x22, x22, x11\n" + "add x21, x21, x11\n" "tbz %x[n_channels], #1, 10f\n" - "ldr h14, [x10], #0x2\n" - "ldr h15, [x9], #0x2\n" - "ldr h16, [x28], #0x2\n" - "ldr h17, [x27], #0x2\n" - "ldr h18, [x26], #0x2\n" - "ldr h19, [x25], #0x2\n" - "ldr h20, [x24], #0x2\n" - "ldr h21, [x23], #0x2\n" - "ldr h22, [x22], #0x2\n" + "ldr h14, [x9], #0x2\n" + "ldr h15, [x28], #0x2\n" + "ldr h16, [x27], #0x2\n" + "ldr h17, [x26], #0x2\n" + "ldr h18, [x25], #0x2\n" + "ldr h19, [x24], #0x2\n" + "ldr h20, [x23], #0x2\n" + "ldr h21, [x22], #0x2\n" + "ldr h22, [x21], #0x2\n" "tbz %x[n_channels], #0, 11f\n" - "ld1 { v14.b }[2], [x10], #0x1\n" - "ld1 { v15.b }[2], [x9], #0x1\n" - "ld1 { v16.b }[2], [x28], #0x1\n" - "ld1 { v17.b }[2], [x27], #0x1\n" - "ld1 { v18.b }[2], [x26], #0x1\n" - "ld1 { v19.b }[2], [x25], #0x1\n" - "ld1 { v20.b }[2], [x24], #0x1\n" - "ld1 { v21.b }[2], [x23], #0x1\n" - "ld1 { v22.b }[2], [x22], #0x1\n" + "ld1 { v14.b }[2], [x9], #0x1\n" + "ld1 { v15.b }[2], [x28], #0x1\n" + "ld1 { v16.b }[2], [x27], #0x1\n" + "ld1 { v17.b }[2], [x26], #0x1\n" + "ld1 { v18.b }[2], [x25], #0x1\n" + "ld1 { v19.b }[2], [x24], #0x1\n" + "ld1 { v20.b }[2], [x23], #0x1\n" + "ld1 { v21.b }[2], [x22], #0x1\n" + "ld1 { v22.b }[2], [x21], #0x1\n" "b 11f\n" "10:" // Oddments: Load: Bit 1: Unset - "ldr b14, [x10], #0x1\n" - "ldr b15, [x9], #0x1\n" - "ldr b16, [x28], #0x1\n" - "ldr b17, [x27], #0x1\n" - "ldr b18, [x26], #0x1\n" - "ldr b19, [x25], #0x1\n" - "ldr b20, [x24], #0x1\n" - "ldr b21, [x23], #0x1\n" - "ldr b22, [x22], #0x1\n" + "ldr b14, [x9], #0x1\n" + "ldr b15, [x28], #0x1\n" + "ldr b16, [x27], #0x1\n" + "ldr b17, [x26], #0x1\n" + "ldr b18, [x25], #0x1\n" + "ldr b19, [x24], #0x1\n" + "ldr b20, [x23], #0x1\n" + "ldr b21, [x22], #0x1\n" + "ldr b22, [x21], #0x1\n" "11:" // Oddments: Load: Bit 1: End "subs x20, %x[n_points], #0x1\n" "usubl v14.8h, v14.8b, v6.8b\n" @@ -356,62 +357,62 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "usubl v22.8h, v22.8b, v6.8b\n" "ble 15f\n" "12:" // Oddments: Planar loop - "ldp x10, x9, [x21], #0x10\n" - "ldp x28, x27, [x21], #0x10\n" + "ldp x9, x28, [x10], #0x10\n" + "ldp x27, x26, [x10], #0x10\n" "smlal v23.4s, v14.4h, v0.4h\n" "smlal v24.4s, v15.4h, v0.4h\n" - "ldp x26, x25, [x21], #0x10\n" - "ldp x24, x23, [x21], #0x10\n" + "ldp x25, x24, [x10], #0x10\n" + "ldp x23, x22, [x10], #0x10\n" "smlal v25.4s, v16.4h, v0.4h\n" "smlal v26.4s, v17.4h, v0.4h\n" "smlal v27.4s, v18.4h, v0.4h\n" "smlal v28.4s, v19.4h, v0.4h\n" - "ldr x22, [x21], #0x8\n" - "add x10, x10, x11\n" + "ldr x21, [x10], #0x8\n" + "add x9, x9, x11\n" "smlal v29.4s, v20.4h, v0.4h\n" "smlal v30.4s, v21.4h, v0.4h\n" - "add x9, x9, x11\n" "add x28, x28, x11\n" + "add x27, x27, x11\n" "smlal v31.4s, v22.4h, v0.4h\n" "ldr s0, [%x[params]], #0x4\n" "ssubl v0.8h, v0.8b, v5.8b\n" - "add x27, x27, x11\n" "add x26, x26, x11\n" "add x25, x25, x11\n" "add x24, x24, x11\n" "add x23, x23, x11\n" "add x22, x22, x11\n" + "add x21, x21, x11\n" "tbz %x[n_channels], #1, 13f\n" - "ldr h14, [x10], #0x2\n" - "ldr h15, [x9], #0x2\n" - "ldr h16, [x28], #0x2\n" - "ldr h17, [x27], #0x2\n" - "ldr h18, [x26], #0x2\n" - "ldr h19, [x25], #0x2\n" - "ldr h20, [x24], #0x2\n" - "ldr h21, [x23], #0x2\n" - "ldr h22, [x22], #0x2\n" + "ldr h14, [x9], #0x2\n" + "ldr h15, [x28], #0x2\n" + "ldr h16, [x27], #0x2\n" + "ldr h17, [x26], #0x2\n" + "ldr h18, [x25], #0x2\n" + "ldr h19, [x24], #0x2\n" + "ldr h20, [x23], #0x2\n" + "ldr h21, [x22], #0x2\n" + "ldr h22, [x21], #0x2\n" "tbz %x[n_channels], #0, 14f\n" - "ld1 { v14.b }[2], [x10], #0x1\n" - "ld1 { v15.b }[2], [x9], #0x1\n" - "ld1 { v16.b }[2], [x28], #0x1\n" - "ld1 { v17.b }[2], [x27], #0x1\n" - "ld1 { v18.b }[2], [x26], #0x1\n" - "ld1 { v19.b }[2], [x25], #0x1\n" - "ld1 { v20.b }[2], [x24], #0x1\n" - "ld1 { v21.b }[2], [x23], #0x1\n" - "ld1 { v22.b }[2], [x22], #0x1\n" + "ld1 { v14.b }[2], [x9], #0x1\n" + "ld1 { v15.b }[2], [x28], #0x1\n" + "ld1 { v16.b }[2], [x27], #0x1\n" + "ld1 { v17.b }[2], [x26], #0x1\n" + "ld1 { v18.b }[2], [x25], #0x1\n" + "ld1 { v19.b }[2], [x24], #0x1\n" + "ld1 { v20.b }[2], [x23], #0x1\n" + "ld1 { v21.b }[2], [x22], #0x1\n" + "ld1 { v22.b }[2], [x21], #0x1\n" "b 14f\n" "13:" // Oddments: Planar loop: Load: Bit 1: Unset - "ldr b14, [x10], #0x1\n" - "ldr b15, [x9], #0x1\n" - "ldr b16, [x28], #0x1\n" - "ldr b17, [x27], #0x1\n" - "ldr b18, [x26], #0x1\n" - "ldr b19, [x25], #0x1\n" - "ldr b20, [x24], #0x1\n" - "ldr b21, [x23], #0x1\n" - "ldr b22, [x22], #0x1\n" + "ldr b14, [x9], #0x1\n" + "ldr b15, [x28], #0x1\n" + "ldr b16, [x27], #0x1\n" + "ldr b17, [x26], #0x1\n" + "ldr b18, [x25], #0x1\n" + "ldr b19, [x24], #0x1\n" + "ldr b20, [x23], #0x1\n" + "ldr b21, [x22], #0x1\n" + "ldr b22, [x21], #0x1\n" "14:" // Oddments: Planar loop: Load: Bit 1: End "subs x20, x20, #0x1\n" "usubl v14.8h, v14.8b, v6.8b\n" @@ -457,9 +458,7 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "cbz %x[rq_left_shift_ptr], 19f\n" "ld1 { v3.s }[0], [x20], #0x4\n" "19:" // Oddments: Load quantisation parameters: Bit 1: Unset: Bit 0: Load left shift: Done - "20:" // Oddments: Load quantisation parameters: Bit 1: End - "21:" // Oddments: Load quantisation parameters: Done "sshl v23.4s, v23.4s, v3.4s\n" "sshl v24.4s, v24.4s, v3.4s\n" @@ -473,11 +472,11 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "sqrdmulh v25.4s, v25.4s, v2.4s\n" "ldr x20, [%x[outptrs], #0x40]\n" "add x28, x28, x11\n" - "and v21.16b, v23.16b, v1.16b\n" - "and v20.16b, v24.16b, v1.16b\n" + "and v18.16b, v23.16b, v1.16b\n" + "and v17.16b, v24.16b, v1.16b\n" "add x27, x27, x11\n" "add x26, x26, x11\n" - "and v19.16b, v25.16b, v1.16b\n" + "and v16.16b, v25.16b, v1.16b\n" "sshl v26.4s, v26.4s, v3.4s\n" "add x25, x25, x11\n" "add x24, x24, x11\n" @@ -490,36 +489,36 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "add x21, x21, x11\n" "add x20, x20, x11\n" "sshl v31.4s, v31.4s, v3.4s\n" - "sshr v21.4s, v21.4s, #0x1f\n" - "sshr v20.4s, v20.4s, #0x1f\n" - "sshr v19.4s, v19.4s, #0x1f\n" + "sshr v18.4s, v18.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "sshr v16.4s, v16.4s, #0x1f\n" "sqrdmulh v26.4s, v26.4s, v2.4s\n" "sqrdmulh v27.4s, v27.4s, v2.4s\n" "sqrdmulh v28.4s, v28.4s, v2.4s\n" "sqrdmulh v29.4s, v29.4s, v2.4s\n" "sqrdmulh v30.4s, v30.4s, v2.4s\n" "sqrdmulh v31.4s, v31.4s, v2.4s\n" - "sqadd v23.4s, v23.4s, v21.4s\n" - "sqadd v24.4s, v24.4s, v20.4s\n" - "sqadd v25.4s, v25.4s, v19.4s\n" - "and v18.16b, v26.16b, v1.16b\n" - "and v17.16b, v27.16b, v1.16b\n" - "and v16.16b, v28.16b, v1.16b\n" - "and v21.16b, v29.16b, v1.16b\n" - "and v20.16b, v30.16b, v1.16b\n" - "and v19.16b, v31.16b, v1.16b\n" - "sshr v18.4s, v18.4s, #0x1f\n" - "sshr v17.4s, v17.4s, #0x1f\n" - "sshr v16.4s, v16.4s, #0x1f\n" + "sqadd v23.4s, v23.4s, v18.4s\n" + "sqadd v24.4s, v24.4s, v17.4s\n" + "sqadd v25.4s, v25.4s, v16.4s\n" + "and v21.16b, v26.16b, v1.16b\n" + "and v20.16b, v27.16b, v1.16b\n" + "and v19.16b, v28.16b, v1.16b\n" + "and v18.16b, v29.16b, v1.16b\n" + "and v17.16b, v30.16b, v1.16b\n" + "and v16.16b, v31.16b, v1.16b\n" "sshr v21.4s, v21.4s, #0x1f\n" "sshr v20.4s, v20.4s, #0x1f\n" "sshr v19.4s, v19.4s, #0x1f\n" - "sqadd v26.4s, v26.4s, v18.4s\n" - "sqadd v27.4s, v27.4s, v17.4s\n" - "sqadd v28.4s, v28.4s, v16.4s\n" - "sqadd v29.4s, v29.4s, v21.4s\n" - "sqadd v30.4s, v30.4s, v20.4s\n" - "sqadd v31.4s, v31.4s, v19.4s\n" + "sshr v18.4s, v18.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "sqadd v26.4s, v26.4s, v21.4s\n" + "sqadd v27.4s, v27.4s, v20.4s\n" + "sqadd v28.4s, v28.4s, v19.4s\n" + "sqadd v29.4s, v29.4s, v18.4s\n" + "sqadd v30.4s, v30.4s, v17.4s\n" + "sqadd v31.4s, v31.4s, v16.4s\n" "srshl v23.4s, v23.4s, v1.4s\n" "srshl v24.4s, v24.4s, v1.4s\n" "srshl v25.4s, v25.4s, v1.4s\n" @@ -606,15 +605,14 @@ void a64_u8s8u8q_nhwc_generic_output9_mla_depthfirst_impl( "st1 { v30.b }[0], [x21], #0x1\n" "st1 { v31.b }[0], [x20], #0x1\n" "23:" // Oddments: Store: Bit 1: End - "24:" // End - : [params] "+&r" (params) : [bias] "r" (qp.bias), [inptrs] "r" (inptrs), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [offsetof_Requantize32_a_offset] "I" (offsetof(arm_gemm::Requantize32, a_offset)), [offsetof_Requantize32_b_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [offsetof_Requantize32_c_offset] "I" (offsetof(arm_gemm::Requantize32, c_offset)), [offsetof_Requantize32_maxval] "I" (offsetof(arm_gemm::Requantize32, maxval)), [offsetof_Requantize32_minval] "I" (offsetof(arm_gemm::Requantize32, minval)), [offsetof_Requantize32_per_layer_left_shift] "I" (offsetof(arm_gemm::Requantize32, per_layer_left_shift)), [offsetof_Requantize32_per_layer_mul] "I" (offsetof(arm_gemm::Requantize32, per_layer_mul)), [offsetof_Requantize32_per_layer_right_shift] "I" (offsetof(arm_gemm::Requantize32, per_layer_right_shift)), [outptrs] "r" (outptrs), [qp] "r" (&qp), [rq_left_shift_ptr] "r" (qp.per_channel_left_shifts), [rq_mul_ptr] "r" (qp.per_channel_muls), [rq_right_shift_ptr] "r" (qp.per_channel_right_shifts) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace depthwise } // namespace arm_conv -#endif // defined(__aarch64__) + +#endif // defined(__aarch64__) |