diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp index 49f69c4204..42ff502b0f 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst/generic.cpp @@ -267,7 +267,7 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "ldr q19, [x12, #0x10]\n" "smlal2 v18.4s, v24.8h, v7.8h\n" "smlal v11.4s, v24.4h, v1.4h\n" - "sqdmulh v15.4s, v15.4s, v22.4s\n" + "sqrdmulh v15.4s, v15.4s, v22.4s\n" "ldr q30, [x11, #0x10]\n" "smlal2 v10.4s, v24.8h, v1.8h\n" "ldr d24, [x22, x15]\n" @@ -283,7 +283,7 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "add x17, x17, #0x48\n" "smlal v13.4s, v28.4h, v7.4h\n" "smlal2 v17.4s, v28.8h, v7.8h\n" - "sqdmulh v18.4s, v18.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" "subs x16, x16, #0x1\n" "smlal2 v10.4s, v25.8h, v6.8h\n" "ldr d25, [x20, x15]\n" @@ -299,7 +299,7 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "ushll v29.8h, v29.8b, #0x0\n" "smlal2 v10.4s, v27.8h, v7.8h\n" "smlal2 v9.4s, v26.8h, v7.8h\n" - "sqdmulh v13.4s, v13.4s, v22.4s\n" + "sqrdmulh v13.4s, v13.4s, v22.4s\n" "add x15, x15, #0x8\n" "smlal v11.4s, v24.4h, v5.4h\n" "smlal v23.4s, v25.4h, v6.4h\n" @@ -307,17 +307,17 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "add x11, x11, #0x20\n" "smlal2 v10.4s, v24.8h, v5.8h\n" "smlal2 v9.4s, v25.8h, v6.8h\n" - "sqdmulh v17.4s, v17.4s, v19.4s\n" + "sqrdmulh v17.4s, v17.4s, v19.4s\n" "smlal v11.4s, v25.4h, v8.4h\n" "smlal v23.4s, v29.4h, v8.4h\n" - "sqdmulh v11.4s, v11.4s, v22.4s\n" + "sqrdmulh v11.4s, v11.4s, v22.4s\n" "smlal2 v10.4s, v25.8h, v8.8h\n" "smlal2 v9.4s, v29.8h, v8.8h\n" - "sqdmulh v23.4s, v23.4s, v22.4s\n" + "sqrdmulh v23.4s, v23.4s, v22.4s\n" "and v22.16b, v11.16b, v31.16b\n" - "sqdmulh v10.4s, v10.4s, v19.4s\n" + "sqrdmulh v10.4s, v10.4s, v19.4s\n" "and v20.16b, v23.16b, v31.16b\n" - "sqdmulh v9.4s, v9.4s, v19.4s\n" + "sqrdmulh v9.4s, v9.4s, v19.4s\n" "and v19.16b, v18.16b, v30.16b\n" "sshr v1.4s, v1.4s, #0x1f\n" "and v27.16b, v17.16b, v30.16b\n" @@ -519,7 +519,7 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "ldr q19, [x12, #0x10]\n" "smlal2 v18.4s, v24.8h, v7.8h\n" "smlal v11.4s, v24.4h, v1.4h\n" - "sqdmulh v15.4s, v15.4s, v22.4s\n" + "sqrdmulh v15.4s, v15.4s, v22.4s\n" "ldr q30, [x11, #0x10]\n" "smlal2 v10.4s, v24.8h, v1.8h\n" "ldr d24, [x22, x15]\n" @@ -535,7 +535,7 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "tst x8, #0x7\n" "smlal v13.4s, v28.4h, v7.4h\n" "smlal2 v17.4s, v28.8h, v7.8h\n" - "sqdmulh v18.4s, v18.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" "add x12, x12, #0x20\n" "smlal2 v10.4s, v25.8h, v6.8h\n" "ldr d25, [x20, x15]\n" @@ -551,24 +551,24 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "ushll v29.8h, v29.8b, #0x0\n" "smlal2 v10.4s, v27.8h, v7.8h\n" "smlal2 v9.4s, v26.8h, v7.8h\n" - "sqdmulh v13.4s, v13.4s, v22.4s\n" + "sqrdmulh v13.4s, v13.4s, v22.4s\n" "add x15, x15, #0x8\n" "smlal v11.4s, v24.4h, v5.4h\n" "smlal v23.4s, v25.4h, v6.4h\n" "and v1.16b, v13.16b, v31.16b\n" "smlal2 v10.4s, v24.8h, v5.8h\n" "smlal2 v9.4s, v25.8h, v6.8h\n" - "sqdmulh v17.4s, v17.4s, v19.4s\n" + "sqrdmulh v17.4s, v17.4s, v19.4s\n" "smlal v11.4s, v25.4h, v8.4h\n" "smlal v23.4s, v29.4h, v8.4h\n" - "sqdmulh v11.4s, v11.4s, v22.4s\n" + "sqrdmulh v11.4s, v11.4s, v22.4s\n" "smlal2 v10.4s, v25.8h, v8.8h\n" "smlal2 v9.4s, v29.8h, v8.8h\n" - "sqdmulh v23.4s, v23.4s, v22.4s\n" + "sqrdmulh v23.4s, v23.4s, v22.4s\n" "and v22.16b, v11.16b, v31.16b\n" - "sqdmulh v10.4s, v10.4s, v19.4s\n" + "sqrdmulh v10.4s, v10.4s, v19.4s\n" "and v20.16b, v23.16b, v31.16b\n" - "sqdmulh v9.4s, v9.4s, v19.4s\n" + "sqrdmulh v9.4s, v9.4s, v19.4s\n" "and v19.16b, v18.16b, v30.16b\n" "sshr v1.4s, v1.4s, #0x1f\n" "and v27.16b, v17.16b, v30.16b\n" @@ -1272,22 +1272,22 @@ void a64_u8qa_nhwc_3x3_s2_output2x2_mla_depthfirst_impl( "ld1 { v22.s }[0], [x12]\n" "ld1 { v31.s }[0], [x11]\n" "83:" // Oddments: Load requant params: Bit 2: End - "sqdmulh v15.4s, v15.4s, v22.4s\n" - "sqdmulh v13.4s, v13.4s, v22.4s\n" + "sqrdmulh v15.4s, v15.4s, v22.4s\n" + "sqrdmulh v13.4s, v13.4s, v22.4s\n" "add x10, x10, x14\n" "add x9, x9, x14\n" - "sqdmulh v11.4s, v11.4s, v22.4s\n" - "sqdmulh v23.4s, v23.4s, v22.4s\n" + "sqrdmulh v11.4s, v11.4s, v22.4s\n" + "sqrdmulh v23.4s, v23.4s, v22.4s\n" "add x28, x28, x14\n" "add x27, x27, x14\n" "and v4.16b, v15.16b, v31.16b\n" - "sqdmulh v18.4s, v18.4s, v19.4s\n" + "sqrdmulh v18.4s, v18.4s, v19.4s\n" "and v1.16b, v13.16b, v31.16b\n" - "sqdmulh v17.4s, v17.4s, v19.4s\n" + "sqrdmulh v17.4s, v17.4s, v19.4s\n" "and v22.16b, v11.16b, v31.16b\n" - "sqdmulh v10.4s, v10.4s, v19.4s\n" + "sqrdmulh v10.4s, v10.4s, v19.4s\n" "and v20.16b, v23.16b, v31.16b\n" - "sqdmulh v9.4s, v9.4s, v19.4s\n" + "sqrdmulh v9.4s, v9.4s, v19.4s\n" "sshr v4.4s, v4.4s, #0x1f\n" "and v19.16b, v18.16b, v30.16b\n" "sshr v1.4s, v1.4s, #0x1f\n" |