diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp | 414 |
1 files changed, 207 insertions, 207 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp index be3c8cf9f8..59eb11649b 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp @@ -49,21 +49,21 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "lsr x10, %x[n_output_channels], #0x2\n" "add x20, %x[qp], %[offsetof_Requantize32_minval]\n" "ld1r { v15.4s }, [x20]\n" - "add x21, %x[qp], %[offsetof_Requantize32_maxval]\n" + "add x20, %x[qp], %[offsetof_Requantize32_maxval]\n" + "ld1r { v14.4s }, [x20]\n" "add x20, %x[qp], %[offsetof_Requantize32_a_offset]\n" - "ld1r { v14.4s }, [x21]\n" "ld1r { v13.16b }, [x20]\n" - "add x21, %x[qp], %[offsetof_Requantize32_b_offset]\n" + "add x20, %x[qp], %[offsetof_Requantize32_b_offset]\n" + "ld1r { v12.16b }, [x20]\n" "add x20, %x[qp], %[offsetof_Requantize32_c_offset]\n" - "ld1r { v12.16b }, [x21]\n" "ld1r { v11.4s }, [x20]\n" - "add x21, %x[qp], %[offsetof_Requantize32_per_layer_left_shift]\n" + "add x20, %x[qp], %[offsetof_Requantize32_per_layer_left_shift]\n" + "ld1r { v10.4s }, [x20]\n" "add x20, %x[qp], %[offsetof_Requantize32_per_layer_mul]\n" - "ld1r { v10.4s }, [x21]\n" "ld1r { v9.4s }, [x20]\n" "add x20, %x[qp], %[offsetof_Requantize32_per_layer_right_shift]\n" - "mov x9, #0x0\n" "ld1r { v8.4s }, [x20]\n" + "mov x9, #0x0\n" "cbz x10, 9f\n" "1:" // Output channel loop "movi v31.4s, #0x0\n" @@ -96,20 +96,20 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "3:" // Output channel loop: Load quantization parameters: Done "ldr s5, [%x[weights]], #0x4\n" "mov x22, %x[inptrs]\n" - "lsr x23, %x[kernel_points], #0x1\n" "ldp x21, x20, [x22], #0x10\n" + "lsr x23, %x[kernel_points], #0x1\n" "ldr d0, [x21, #0x0]\n" "ldr d4, [x20, #0x0]\n" - "ssubl v5.8h, v5.8b, v12.8b\n" "ssubl v0.8h, v0.8b, v13.8b\n" "ssubl v4.8h, v4.8b, v13.8b\n" + "ssubl v5.8h, v5.8b, v12.8b\n" "cbz x23, 7f\n" "ldr s7, [%x[weights]], #0x4\n" "ldp x21, x20, [x22], #0x10\n" "subs x23, x23, #0x1\n" + "ssubl v7.8h, v7.8b, v12.8b\n" "ldr d3, [x21, #0x0]\n" "ldr d6, [x20, #0x0]\n" - "ssubl v7.8h, v7.8b, v12.8b\n" "ssubl v3.8h, v3.8b, v13.8b\n" "ssubl v6.8h, v6.8b, v13.8b\n" "beq 5f\n" @@ -125,13 +125,13 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smlal v22.4s, v5.4h, v0.h[6]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" "ldr d0, [x21, #0x0]\n" + "ssubl v0.8h, v0.8b, v13.8b\n" "smlal v24.4s, v5.4h, v4.h[0]\n" "smlal v25.4s, v5.4h, v4.h[1]\n" "smlal v26.4s, v5.4h, v4.h[2]\n" "smlal v27.4s, v5.4h, v4.h[3]\n" "smlal v28.4s, v5.4h, v4.h[4]\n" "smlal v29.4s, v5.4h, v4.h[5]\n" - "ssubl v0.8h, v0.8b, v13.8b\n" "smlal v30.4s, v5.4h, v4.h[6]\n" "smlal v31.4s, v5.4h, v4.h[7]\n" "ldr d4, [x20, #0x0]\n" @@ -139,22 +139,22 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "ldp x21, x20, [x22], #0x10\n" "smlal v16.4s, v7.4h, v3.h[0]\n" "smlal v17.4s, v7.4h, v3.h[1]\n" + "ssubl v4.8h, v4.8b, v13.8b\n" "smlal v18.4s, v7.4h, v3.h[2]\n" "smlal v19.4s, v7.4h, v3.h[3]\n" + "ssubl v5.8h, v5.8b, v12.8b\n" "smlal v20.4s, v7.4h, v3.h[4]\n" "smlal v21.4s, v7.4h, v3.h[5]\n" - "ssubl v4.8h, v4.8b, v13.8b\n" "smlal v22.4s, v7.4h, v3.h[6]\n" "smlal v23.4s, v7.4h, v3.h[7]\n" "ldr d3, [x21, #0x0]\n" - "ssubl v5.8h, v5.8b, v12.8b\n" + "ssubl v3.8h, v3.8b, v13.8b\n" "smlal v24.4s, v7.4h, v6.h[0]\n" "smlal v25.4s, v7.4h, v6.h[1]\n" "smlal v26.4s, v7.4h, v6.h[2]\n" "smlal v27.4s, v7.4h, v6.h[3]\n" "smlal v28.4s, v7.4h, v6.h[4]\n" "smlal v29.4s, v7.4h, v6.h[5]\n" - "ssubl v3.8h, v3.8b, v13.8b\n" "smlal v30.4s, v7.4h, v6.h[6]\n" "smlal v31.4s, v7.4h, v6.h[7]\n" "ldr d6, [x20, #0x0]\n" @@ -172,54 +172,54 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smlal v19.4s, v5.4h, v0.h[3]\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" - "smlal v20.4s, v5.4h, v0.h[4]\n" - "smlal v21.4s, v5.4h, v0.h[5]\n" + "smlal v16.4s, v7.4h, v3.h[0]\n" + "smlal v17.4s, v7.4h, v3.h[1]\n" + "sshl v16.4s, v16.4s, v10.4s\n" "ldr x23, [%x[outptrs], #0x20]\n" + "smlal v18.4s, v7.4h, v3.h[2]\n" + "smlal v19.4s, v7.4h, v3.h[3]\n" + "sshl v17.4s, v17.4s, v10.4s\n" "ldr x22, [%x[outptrs], #0x28]\n" + "smlal v20.4s, v5.4h, v0.h[4]\n" + "smlal v21.4s, v5.4h, v0.h[5]\n" + "sshl v18.4s, v18.4s, v10.4s\n" + "ldr x21, [%x[outptrs], #0x30]\n" "smlal v22.4s, v5.4h, v0.h[6]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" - "ldr x21, [%x[outptrs], #0x30]\n" + "sshl v19.4s, v19.4s, v10.4s\n" "ldr x20, [%x[outptrs], #0x38]\n" - "smlal v16.4s, v7.4h, v3.h[0]\n" - "smlal v17.4s, v7.4h, v3.h[1]\n" - "smlal v18.4s, v7.4h, v3.h[2]\n" - "smlal v19.4s, v7.4h, v3.h[3]\n" "smlal v24.4s, v5.4h, v4.h[0]\n" "smlal v25.4s, v5.4h, v4.h[1]\n" + "sqrdmulh v16.4s, v16.4s, v9.4s\n" "smlal v20.4s, v7.4h, v3.h[4]\n" "smlal v21.4s, v7.4h, v3.h[5]\n" - "sshl v16.4s, v16.4s, v10.4s\n" - "sshl v17.4s, v17.4s, v10.4s\n" + "sqrdmulh v17.4s, v17.4s, v9.4s\n" "smlal v22.4s, v7.4h, v3.h[6]\n" "smlal v23.4s, v7.4h, v3.h[7]\n" - "sshl v18.4s, v18.4s, v10.4s\n" - "sshl v19.4s, v19.4s, v10.4s\n" - "smlal v26.4s, v5.4h, v4.h[2]\n" + "sqrdmulh v18.4s, v18.4s, v9.4s\n" "smlal v24.4s, v7.4h, v6.h[0]\n" "smlal v25.4s, v7.4h, v6.h[1]\n" - "sqrdmulh v16.4s, v16.4s, v9.4s\n" - "sqrdmulh v17.4s, v17.4s, v9.4s\n" + "sqrdmulh v19.4s, v19.4s, v9.4s\n" + "smlal v26.4s, v5.4h, v4.h[2]\n" "smlal v27.4s, v5.4h, v4.h[3]\n" + "and v3.16b, v16.16b, v8.16b\n" "smlal v28.4s, v5.4h, v4.h[4]\n" - "sqrdmulh v18.4s, v18.4s, v9.4s\n" - "sqrdmulh v19.4s, v19.4s, v9.4s\n" "smlal v29.4s, v5.4h, v4.h[5]\n" + "and v2.16b, v17.16b, v8.16b\n" "smlal v30.4s, v5.4h, v4.h[6]\n" "smlal v31.4s, v5.4h, v4.h[7]\n" - "and v3.16b, v16.16b, v8.16b\n" - "and v2.16b, v17.16b, v8.16b\n" - "sshl v20.4s, v20.4s, v10.4s\n" - "smlal v26.4s, v7.4h, v6.h[2]\n" "and v1.16b, v18.16b, v8.16b\n" "and v0.16b, v19.16b, v8.16b\n" - "smlal v27.4s, v7.4h, v6.h[3]\n" + "sshl v20.4s, v20.4s, v10.4s\n" + "smlal v26.4s, v7.4h, v6.h[2]\n" "sshl v21.4s, v21.4s, v10.4s\n" "sshl v22.4s, v22.4s, v10.4s\n" - "smlal v28.4s, v7.4h, v6.h[4]\n" + "smlal v27.4s, v7.4h, v6.h[3]\n" "sshl v23.4s, v23.4s, v10.4s\n" "sshl v24.4s, v24.4s, v10.4s\n" - "smlal v29.4s, v7.4h, v6.h[5]\n" + "smlal v28.4s, v7.4h, v6.h[4]\n" "sshl v25.4s, v25.4s, v10.4s\n" + "smlal v29.4s, v7.4h, v6.h[5]\n" "smlal v30.4s, v7.4h, v6.h[6]\n" "smlal v31.4s, v7.4h, v6.h[7]\n" "sshr v3.4s, v3.4s, #0x1f\n" @@ -357,49 +357,49 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smax v30.4s, v30.4s, v15.4s\n" "smax v31.4s, v31.4s, v15.4s\n" "uzp1 v16.16b, v16.16b, v16.16b\n" + "str s16, [x27, x9]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "uzp1 v17.16b, v17.16b, v17.16b\n" "uzp1 v18.16b, v18.16b, v18.16b\n" + "str s17, [x26, x9]\n" + "ldr x26, [%x[outptrs], #0x48]\n" "uzp1 v19.16b, v19.16b, v19.16b\n" "uzp1 v20.16b, v20.16b, v20.16b\n" + "str s18, [x25, x9]\n" + "ldr x25, [%x[outptrs], #0x50]\n" "uzp1 v21.16b, v21.16b, v21.16b\n" "uzp1 v22.16b, v22.16b, v22.16b\n" + "str s19, [x24, x9]\n" + "ldr x24, [%x[outptrs], #0x58]\n" "uzp1 v23.16b, v23.16b, v23.16b\n" - "str s16, [x27, x9]\n" - "ldr x27, [%x[outptrs], #0x40]\n" "uzp1 v24.16b, v24.16b, v24.16b\n" + "str s20, [x23, x9]\n" + "ldr x23, [%x[outptrs], #0x60]\n" "uzp1 v25.16b, v25.16b, v25.16b\n" - "str s17, [x26, x9]\n" - "ldr x26, [%x[outptrs], #0x48]\n" "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s21, [x22, x9]\n" + "ldr x22, [%x[outptrs], #0x68]\n" "uzp1 v27.16b, v27.16b, v27.16b\n" - "str s18, [x25, x9]\n" - "ldr x25, [%x[outptrs], #0x50]\n" "uzp1 v28.16b, v28.16b, v28.16b\n" + "str s22, [x21, x9]\n" + "ldr x21, [%x[outptrs], #0x70]\n" "uzp1 v29.16b, v29.16b, v29.16b\n" - "str s19, [x24, x9]\n" - "ldr x24, [%x[outptrs], #0x58]\n" "uzp1 v30.16b, v30.16b, v30.16b\n" + "str s23, [x20, x9]\n" + "ldr x20, [%x[outptrs], #0x78]\n" "uzp1 v31.16b, v31.16b, v31.16b\n" - "str s20, [x23, x9]\n" - "ldr x23, [%x[outptrs], #0x60]\n" - "str s21, [x22, x9]\n" - "ldr x22, [%x[outptrs], #0x68]\n" "uzp1 v24.16b, v24.16b, v24.16b\n" + "str s24, [x27, x9]\n" "uzp1 v25.16b, v25.16b, v25.16b\n" - "str s22, [x21, x9]\n" - "ldr x21, [%x[outptrs], #0x70]\n" "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s25, [x26, x9]\n" "uzp1 v27.16b, v27.16b, v27.16b\n" - "str s23, [x20, x9]\n" - "ldr x20, [%x[outptrs], #0x78]\n" "uzp1 v28.16b, v28.16b, v28.16b\n" + "str s26, [x25, x9]\n" "uzp1 v29.16b, v29.16b, v29.16b\n" "uzp1 v30.16b, v30.16b, v30.16b\n" - "uzp1 v31.16b, v31.16b, v31.16b\n" - "str s24, [x27, x9]\n" - "str s25, [x26, x9]\n" - "str s26, [x25, x9]\n" "str s27, [x24, x9]\n" + "uzp1 v31.16b, v31.16b, v31.16b\n" "str s28, [x23, x9]\n" "str s29, [x22, x9]\n" "str s30, [x21, x9]\n" @@ -421,70 +421,70 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smlal v22.4s, v5.4h, v0.h[6]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" "ldr d0, [x20, #0x0]\n" - "ldr x22, [%x[outptrs], #0x28]\n" + "ssubl v0.8h, v0.8b, v13.8b\n" "smlal v24.4s, v5.4h, v4.h[0]\n" "smlal v25.4s, v5.4h, v4.h[1]\n" + "ldr x22, [%x[outptrs], #0x28]\n" "ldr x21, [%x[outptrs], #0x30]\n" - "ldr x20, [%x[outptrs], #0x38]\n" "smlal v26.4s, v5.4h, v4.h[2]\n" "smlal v27.4s, v5.4h, v4.h[3]\n" + "ldr x20, [%x[outptrs], #0x38]\n" "smlal v28.4s, v5.4h, v4.h[4]\n" "smlal v29.4s, v5.4h, v4.h[5]\n" - "ssubl v0.8h, v0.8b, v13.8b\n" "smlal v30.4s, v5.4h, v4.h[6]\n" "smlal v31.4s, v5.4h, v4.h[7]\n" "ldr s5, [%x[weights]], #0x4\n" "ldr d4, [x28, #0x0]\n" "smlal v16.4s, v7.4h, v3.h[0]\n" "smlal v17.4s, v7.4h, v3.h[1]\n" + "ssubl v5.8h, v5.8b, v12.8b\n" "smlal v18.4s, v7.4h, v3.h[2]\n" "smlal v19.4s, v7.4h, v3.h[3]\n" - "ssubl v5.8h, v5.8b, v12.8b\n" - "smlal v20.4s, v7.4h, v3.h[4]\n" - "smlal v21.4s, v7.4h, v3.h[5]\n" "ssubl v4.8h, v4.8b, v13.8b\n" - "smlal v22.4s, v7.4h, v3.h[6]\n" - "smlal v23.4s, v7.4h, v3.h[7]\n" "smlal v16.4s, v5.4h, v0.h[0]\n" "smlal v17.4s, v5.4h, v0.h[1]\n" + "sshl v16.4s, v16.4s, v10.4s\n" "smlal v18.4s, v5.4h, v0.h[2]\n" "smlal v19.4s, v5.4h, v0.h[3]\n" + "sshl v17.4s, v17.4s, v10.4s\n" + "smlal v20.4s, v7.4h, v3.h[4]\n" + "smlal v21.4s, v7.4h, v3.h[5]\n" + "sshl v18.4s, v18.4s, v10.4s\n" + "smlal v22.4s, v7.4h, v3.h[6]\n" + "smlal v23.4s, v7.4h, v3.h[7]\n" + "sshl v19.4s, v19.4s, v10.4s\n" "smlal v24.4s, v7.4h, v6.h[0]\n" "smlal v25.4s, v7.4h, v6.h[1]\n" + "sqrdmulh v16.4s, v16.4s, v9.4s\n" "smlal v20.4s, v5.4h, v0.h[4]\n" "smlal v21.4s, v5.4h, v0.h[5]\n" - "sshl v16.4s, v16.4s, v10.4s\n" - "sshl v17.4s, v17.4s, v10.4s\n" + "sqrdmulh v17.4s, v17.4s, v9.4s\n" "smlal v22.4s, v5.4h, v0.h[6]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" - "sshl v18.4s, v18.4s, v10.4s\n" - "sshl v19.4s, v19.4s, v10.4s\n" - "smlal v26.4s, v7.4h, v6.h[2]\n" + "sqrdmulh v18.4s, v18.4s, v9.4s\n" "smlal v24.4s, v5.4h, v4.h[0]\n" "smlal v25.4s, v5.4h, v4.h[1]\n" - "sqrdmulh v16.4s, v16.4s, v9.4s\n" - "sqrdmulh v17.4s, v17.4s, v9.4s\n" + "sqrdmulh v19.4s, v19.4s, v9.4s\n" + "smlal v26.4s, v7.4h, v6.h[2]\n" "smlal v27.4s, v7.4h, v6.h[3]\n" + "and v3.16b, v16.16b, v8.16b\n" "smlal v28.4s, v7.4h, v6.h[4]\n" - "sqrdmulh v18.4s, v18.4s, v9.4s\n" - "sqrdmulh v19.4s, v19.4s, v9.4s\n" "smlal v29.4s, v7.4h, v6.h[5]\n" + "and v2.16b, v17.16b, v8.16b\n" "smlal v30.4s, v7.4h, v6.h[6]\n" "smlal v31.4s, v7.4h, v6.h[7]\n" - "and v3.16b, v16.16b, v8.16b\n" - "and v2.16b, v17.16b, v8.16b\n" - "sshl v20.4s, v20.4s, v10.4s\n" - "smlal v26.4s, v5.4h, v4.h[2]\n" "and v1.16b, v18.16b, v8.16b\n" "and v0.16b, v19.16b, v8.16b\n" - "smlal v27.4s, v5.4h, v4.h[3]\n" + "sshl v20.4s, v20.4s, v10.4s\n" + "smlal v26.4s, v5.4h, v4.h[2]\n" "sshl v21.4s, v21.4s, v10.4s\n" "sshl v22.4s, v22.4s, v10.4s\n" - "smlal v28.4s, v5.4h, v4.h[4]\n" + "smlal v27.4s, v5.4h, v4.h[3]\n" "sshl v23.4s, v23.4s, v10.4s\n" "sshl v24.4s, v24.4s, v10.4s\n" - "smlal v29.4s, v5.4h, v4.h[5]\n" + "smlal v28.4s, v5.4h, v4.h[4]\n" "sshl v25.4s, v25.4s, v10.4s\n" + "smlal v29.4s, v5.4h, v4.h[5]\n" "smlal v30.4s, v5.4h, v4.h[6]\n" "smlal v31.4s, v5.4h, v4.h[7]\n" "sshr v3.4s, v3.4s, #0x1f\n" @@ -622,49 +622,49 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smax v30.4s, v30.4s, v15.4s\n" "smax v31.4s, v31.4s, v15.4s\n" "uzp1 v16.16b, v16.16b, v16.16b\n" + "str s16, [x27, x9]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "uzp1 v17.16b, v17.16b, v17.16b\n" "uzp1 v18.16b, v18.16b, v18.16b\n" + "str s17, [x26, x9]\n" + "ldr x26, [%x[outptrs], #0x48]\n" "uzp1 v19.16b, v19.16b, v19.16b\n" "uzp1 v20.16b, v20.16b, v20.16b\n" + "str s18, [x25, x9]\n" + "ldr x25, [%x[outptrs], #0x50]\n" "uzp1 v21.16b, v21.16b, v21.16b\n" "uzp1 v22.16b, v22.16b, v22.16b\n" + "str s19, [x24, x9]\n" + "ldr x24, [%x[outptrs], #0x58]\n" "uzp1 v23.16b, v23.16b, v23.16b\n" - "str s16, [x27, x9]\n" - "ldr x27, [%x[outptrs], #0x40]\n" "uzp1 v24.16b, v24.16b, v24.16b\n" + "str s20, [x23, x9]\n" + "ldr x23, [%x[outptrs], #0x60]\n" "uzp1 v25.16b, v25.16b, v25.16b\n" - "str s17, [x26, x9]\n" - "ldr x26, [%x[outptrs], #0x48]\n" "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s21, [x22, x9]\n" + "ldr x22, [%x[outptrs], #0x68]\n" "uzp1 v27.16b, v27.16b, v27.16b\n" - "str s18, [x25, x9]\n" - "ldr x25, [%x[outptrs], #0x50]\n" "uzp1 v28.16b, v28.16b, v28.16b\n" + "str s22, [x21, x9]\n" + "ldr x21, [%x[outptrs], #0x70]\n" "uzp1 v29.16b, v29.16b, v29.16b\n" - "str s19, [x24, x9]\n" - "ldr x24, [%x[outptrs], #0x58]\n" "uzp1 v30.16b, v30.16b, v30.16b\n" + "str s23, [x20, x9]\n" + "ldr x20, [%x[outptrs], #0x78]\n" "uzp1 v31.16b, v31.16b, v31.16b\n" - "str s20, [x23, x9]\n" - "ldr x23, [%x[outptrs], #0x60]\n" - "str s21, [x22, x9]\n" - "ldr x22, [%x[outptrs], #0x68]\n" "uzp1 v24.16b, v24.16b, v24.16b\n" + "str s24, [x27, x9]\n" "uzp1 v25.16b, v25.16b, v25.16b\n" - "str s22, [x21, x9]\n" - "ldr x21, [%x[outptrs], #0x70]\n" "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s25, [x26, x9]\n" "uzp1 v27.16b, v27.16b, v27.16b\n" - "str s23, [x20, x9]\n" - "ldr x20, [%x[outptrs], #0x78]\n" "uzp1 v28.16b, v28.16b, v28.16b\n" + "str s26, [x25, x9]\n" "uzp1 v29.16b, v29.16b, v29.16b\n" "uzp1 v30.16b, v30.16b, v30.16b\n" - "uzp1 v31.16b, v31.16b, v31.16b\n" - "str s24, [x27, x9]\n" - "str s25, [x26, x9]\n" - "str s26, [x25, x9]\n" "str s27, [x24, x9]\n" + "uzp1 v31.16b, v31.16b, v31.16b\n" "str s28, [x23, x9]\n" "str s29, [x22, x9]\n" "str s30, [x21, x9]\n" @@ -673,45 +673,45 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "7:" // Output channel loop: Single kernel point "smlal v16.4s, v5.4h, v0.h[0]\n" "smlal v17.4s, v5.4h, v0.h[1]\n" + "sshl v16.4s, v16.4s, v10.4s\n" "ldr x27, [%x[outptrs], #0x0]\n" - "ldr x26, [%x[outptrs], #0x8]\n" "smlal v18.4s, v5.4h, v0.h[2]\n" "smlal v19.4s, v5.4h, v0.h[3]\n" - "ldr x25, [%x[outptrs], #0x10]\n" - "ldr x24, [%x[outptrs], #0x18]\n" + "sshl v17.4s, v17.4s, v10.4s\n" + "ldr x26, [%x[outptrs], #0x8]\n" + "sshl v18.4s, v18.4s, v10.4s\n" + "sshl v19.4s, v19.4s, v10.4s\n" "smlal v20.4s, v5.4h, v0.h[4]\n" + "ldr x25, [%x[outptrs], #0x10]\n" "smlal v21.4s, v5.4h, v0.h[5]\n" - "ldr x23, [%x[outptrs], #0x20]\n" - "ldr x22, [%x[outptrs], #0x28]\n" "smlal v22.4s, v5.4h, v0.h[6]\n" + "sqrdmulh v16.4s, v16.4s, v9.4s\n" + "ldr x24, [%x[outptrs], #0x18]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" - "ldr x21, [%x[outptrs], #0x30]\n" - "ldr x20, [%x[outptrs], #0x38]\n" - "sshl v16.4s, v16.4s, v10.4s\n" - "sshl v17.4s, v17.4s, v10.4s\n" "smlal v24.4s, v5.4h, v4.h[0]\n" - "sshl v18.4s, v18.4s, v10.4s\n" - "sshl v19.4s, v19.4s, v10.4s\n" - "smlal v25.4s, v5.4h, v4.h[1]\n" - "sshl v20.4s, v20.4s, v10.4s\n" - "sshl v21.4s, v21.4s, v10.4s\n" - "smlal v26.4s, v5.4h, v4.h[2]\n" - "sqrdmulh v16.4s, v16.4s, v9.4s\n" "sqrdmulh v17.4s, v17.4s, v9.4s\n" - "smlal v27.4s, v5.4h, v4.h[3]\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "smlal v25.4s, v5.4h, v4.h[1]\n" "sqrdmulh v18.4s, v18.4s, v9.4s\n" + "smlal v26.4s, v5.4h, v4.h[2]\n" + "ldr x22, [%x[outptrs], #0x28]\n" "sqrdmulh v19.4s, v19.4s, v9.4s\n" - "smlal v28.4s, v5.4h, v4.h[4]\n" - "sshl v22.4s, v22.4s, v10.4s\n" - "sshl v23.4s, v23.4s, v10.4s\n" - "smlal v29.4s, v5.4h, v4.h[5]\n" "and v3.16b, v16.16b, v8.16b\n" + "smlal v27.4s, v5.4h, v4.h[3]\n" + "ldr x21, [%x[outptrs], #0x30]\n" "and v2.16b, v17.16b, v8.16b\n" - "smlal v30.4s, v5.4h, v4.h[6]\n" "and v1.16b, v18.16b, v8.16b\n" + "smlal v28.4s, v5.4h, v4.h[4]\n" + "ldr x20, [%x[outptrs], #0x38]\n" "and v0.16b, v19.16b, v8.16b\n" - "smlal v31.4s, v5.4h, v4.h[7]\n" + "sshl v20.4s, v20.4s, v10.4s\n" + "smlal v29.4s, v5.4h, v4.h[5]\n" + "sshl v21.4s, v21.4s, v10.4s\n" + "sshl v22.4s, v22.4s, v10.4s\n" + "smlal v30.4s, v5.4h, v4.h[6]\n" + "sshl v23.4s, v23.4s, v10.4s\n" "sshl v24.4s, v24.4s, v10.4s\n" + "smlal v31.4s, v5.4h, v4.h[7]\n" "sshl v25.4s, v25.4s, v10.4s\n" "sshr v3.4s, v3.4s, #0x1f\n" "sshr v2.4s, v2.4s, #0x1f\n" @@ -848,49 +848,49 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smax v30.4s, v30.4s, v15.4s\n" "smax v31.4s, v31.4s, v15.4s\n" "uzp1 v16.16b, v16.16b, v16.16b\n" + "str s16, [x27, x9]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "uzp1 v17.16b, v17.16b, v17.16b\n" "uzp1 v18.16b, v18.16b, v18.16b\n" + "str s17, [x26, x9]\n" + "ldr x26, [%x[outptrs], #0x48]\n" "uzp1 v19.16b, v19.16b, v19.16b\n" "uzp1 v20.16b, v20.16b, v20.16b\n" + "str s18, [x25, x9]\n" + "ldr x25, [%x[outptrs], #0x50]\n" "uzp1 v21.16b, v21.16b, v21.16b\n" "uzp1 v22.16b, v22.16b, v22.16b\n" + "str s19, [x24, x9]\n" + "ldr x24, [%x[outptrs], #0x58]\n" "uzp1 v23.16b, v23.16b, v23.16b\n" - "str s16, [x27, x9]\n" - "ldr x27, [%x[outptrs], #0x40]\n" "uzp1 v24.16b, v24.16b, v24.16b\n" + "str s20, [x23, x9]\n" + "ldr x23, [%x[outptrs], #0x60]\n" "uzp1 v25.16b, v25.16b, v25.16b\n" - "str s17, [x26, x9]\n" - "ldr x26, [%x[outptrs], #0x48]\n" "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s21, [x22, x9]\n" + "ldr x22, [%x[outptrs], #0x68]\n" "uzp1 v27.16b, v27.16b, v27.16b\n" - "str s18, [x25, x9]\n" - "ldr x25, [%x[outptrs], #0x50]\n" "uzp1 v28.16b, v28.16b, v28.16b\n" + "str s22, [x21, x9]\n" + "ldr x21, [%x[outptrs], #0x70]\n" "uzp1 v29.16b, v29.16b, v29.16b\n" - "str s19, [x24, x9]\n" - "ldr x24, [%x[outptrs], #0x58]\n" "uzp1 v30.16b, v30.16b, v30.16b\n" + "str s23, [x20, x9]\n" + "ldr x20, [%x[outptrs], #0x78]\n" "uzp1 v31.16b, v31.16b, v31.16b\n" - "str s20, [x23, x9]\n" - "ldr x23, [%x[outptrs], #0x60]\n" - "str s21, [x22, x9]\n" - "ldr x22, [%x[outptrs], #0x68]\n" "uzp1 v24.16b, v24.16b, v24.16b\n" + "str s24, [x27, x9]\n" "uzp1 v25.16b, v25.16b, v25.16b\n" - "str s22, [x21, x9]\n" - "ldr x21, [%x[outptrs], #0x70]\n" "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s25, [x26, x9]\n" "uzp1 v27.16b, v27.16b, v27.16b\n" - "str s23, [x20, x9]\n" - "ldr x20, [%x[outptrs], #0x78]\n" "uzp1 v28.16b, v28.16b, v28.16b\n" + "str s26, [x25, x9]\n" "uzp1 v29.16b, v29.16b, v29.16b\n" "uzp1 v30.16b, v30.16b, v30.16b\n" - "uzp1 v31.16b, v31.16b, v31.16b\n" - "str s24, [x27, x9]\n" - "str s25, [x26, x9]\n" - "str s26, [x25, x9]\n" "str s27, [x24, x9]\n" + "uzp1 v31.16b, v31.16b, v31.16b\n" "str s28, [x23, x9]\n" "str s29, [x22, x9]\n" "str s30, [x21, x9]\n" @@ -965,20 +965,20 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "18:" // Output channel oddments: Load quantization parameters: Done "ldr s5, [%x[weights]], #0x4\n" "mov x22, %x[inptrs]\n" - "lsr x23, %x[kernel_points], #0x1\n" "ldp x21, x20, [x22], #0x10\n" + "lsr x23, %x[kernel_points], #0x1\n" "ldr d0, [x21, #0x0]\n" "ldr d4, [x20, #0x0]\n" - "ssubl v5.8h, v5.8b, v12.8b\n" "ssubl v0.8h, v0.8b, v13.8b\n" "ssubl v4.8h, v4.8b, v13.8b\n" + "ssubl v5.8h, v5.8b, v12.8b\n" "cbz x23, 22f\n" "ldr s7, [%x[weights]], #0x4\n" "ldp x21, x20, [x22], #0x10\n" "subs x23, x23, #0x1\n" + "ssubl v7.8h, v7.8b, v12.8b\n" "ldr d3, [x21, #0x0]\n" "ldr d6, [x20, #0x0]\n" - "ssubl v7.8h, v7.8b, v12.8b\n" "ssubl v3.8h, v3.8b, v13.8b\n" "ssubl v6.8h, v6.8b, v13.8b\n" "beq 20f\n" @@ -994,13 +994,13 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smlal v22.4s, v5.4h, v0.h[6]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" "ldr d0, [x21, #0x0]\n" + "ssubl v0.8h, v0.8b, v13.8b\n" "smlal v24.4s, v5.4h, v4.h[0]\n" "smlal v25.4s, v5.4h, v4.h[1]\n" "smlal v26.4s, v5.4h, v4.h[2]\n" "smlal v27.4s, v5.4h, v4.h[3]\n" "smlal v28.4s, v5.4h, v4.h[4]\n" "smlal v29.4s, v5.4h, v4.h[5]\n" - "ssubl v0.8h, v0.8b, v13.8b\n" "smlal v30.4s, v5.4h, v4.h[6]\n" "smlal v31.4s, v5.4h, v4.h[7]\n" "ldr d4, [x20, #0x0]\n" @@ -1008,22 +1008,22 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "ldp x21, x20, [x22], #0x10\n" "smlal v16.4s, v7.4h, v3.h[0]\n" "smlal v17.4s, v7.4h, v3.h[1]\n" + "ssubl v4.8h, v4.8b, v13.8b\n" "smlal v18.4s, v7.4h, v3.h[2]\n" "smlal v19.4s, v7.4h, v3.h[3]\n" + "ssubl v5.8h, v5.8b, v12.8b\n" "smlal v20.4s, v7.4h, v3.h[4]\n" "smlal v21.4s, v7.4h, v3.h[5]\n" - "ssubl v4.8h, v4.8b, v13.8b\n" "smlal v22.4s, v7.4h, v3.h[6]\n" "smlal v23.4s, v7.4h, v3.h[7]\n" "ldr d3, [x21, #0x0]\n" - "ssubl v5.8h, v5.8b, v12.8b\n" + "ssubl v3.8h, v3.8b, v13.8b\n" "smlal v24.4s, v7.4h, v6.h[0]\n" "smlal v25.4s, v7.4h, v6.h[1]\n" "smlal v26.4s, v7.4h, v6.h[2]\n" "smlal v27.4s, v7.4h, v6.h[3]\n" "smlal v28.4s, v7.4h, v6.h[4]\n" "smlal v29.4s, v7.4h, v6.h[5]\n" - "ssubl v3.8h, v3.8b, v13.8b\n" "smlal v30.4s, v7.4h, v6.h[6]\n" "smlal v31.4s, v7.4h, v6.h[7]\n" "ldr d6, [x20, #0x0]\n" @@ -1077,27 +1077,27 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "smlal v22.4s, v5.4h, v0.h[6]\n" "smlal v23.4s, v5.4h, v0.h[7]\n" "ldr d2, [x21, #0x0]\n" + "ssubl v2.8h, v2.8b, v13.8b\n" "smlal v24.4s, v5.4h, v4.h[0]\n" "smlal v25.4s, v5.4h, v4.h[1]\n" "smlal v26.4s, v5.4h, v4.h[2]\n" "smlal v27.4s, v5.4h, v4.h[3]\n" "smlal v28.4s, v5.4h, v4.h[4]\n" "smlal v29.4s, v5.4h, v4.h[5]\n" - "ssubl v2.8h, v2.8b, v13.8b\n" "smlal v30.4s, v5.4h, v4.h[6]\n" "smlal v31.4s, v5.4h, v4.h[7]\n" "ldr d1, [x20, #0x0]\n" "ldr s0, [%x[weights]], #0x4\n" "smlal v16.4s, v7.4h, v3.h[0]\n" "smlal v17.4s, v7.4h, v3.h[1]\n" + "ssubl v1.8h, v1.8b, v13.8b\n" "smlal v18.4s, v7.4h, v3.h[2]\n" "smlal v19.4s, v7.4h, v3.h[3]\n" + "ssubl v0.8h, v0.8b, v12.8b\n" "smlal v20.4s, v7.4h, v3.h[4]\n" "smlal v21.4s, v7.4h, v3.h[5]\n" - "ssubl v1.8h, v1.8b, v13.8b\n" "smlal v22.4s, v7.4h, v3.h[6]\n" "smlal v23.4s, v7.4h, v3.h[7]\n" - "ssubl v0.8h, v0.8b, v12.8b\n" "smlal v24.4s, v7.4h, v6.h[0]\n" "smlal v25.4s, v7.4h, v6.h[1]\n" "smlal v26.4s, v7.4h, v6.h[2]\n" @@ -1145,18 +1145,18 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "sshl v17.4s, v17.4s, v10.4s\n" "sshl v18.4s, v18.4s, v10.4s\n" "sshl v19.4s, v19.4s, v10.4s\n" - "sshl v20.4s, v20.4s, v10.4s\n" - "sshl v21.4s, v21.4s, v10.4s\n" "sqrdmulh v16.4s, v16.4s, v9.4s\n" "sqrdmulh v17.4s, v17.4s, v9.4s\n" "sqrdmulh v18.4s, v18.4s, v9.4s\n" "sqrdmulh v19.4s, v19.4s, v9.4s\n" - "sshl v22.4s, v22.4s, v10.4s\n" - "sshl v23.4s, v23.4s, v10.4s\n" "and v3.16b, v16.16b, v8.16b\n" "and v2.16b, v17.16b, v8.16b\n" "and v1.16b, v18.16b, v8.16b\n" "and v0.16b, v19.16b, v8.16b\n" + "sshl v20.4s, v20.4s, v10.4s\n" + "sshl v21.4s, v21.4s, v10.4s\n" + "sshl v22.4s, v22.4s, v10.4s\n" + "sshl v23.4s, v23.4s, v10.4s\n" "sshl v24.4s, v24.4s, v10.4s\n" "sshl v25.4s, v25.4s, v10.4s\n" "sshr v3.4s, v3.4s, #0x1f\n" @@ -1320,47 +1320,47 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "tbz %x[n_output_channels], #1, 24f\n" "ldr x27, [%x[outptrs], #0x0]\n" "ldr x26, [%x[outptrs], #0x8]\n" + "add x27, x27, x9\n" + "add x26, x26, x9\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" + "add x25, x25, x9\n" + "add x24, x24, x9\n" "ldr x23, [%x[outptrs], #0x20]\n" "ldr x22, [%x[outptrs], #0x28]\n" + "add x23, x23, x9\n" + "add x22, x22, x9\n" "ldr x21, [%x[outptrs], #0x30]\n" "ldr x20, [%x[outptrs], #0x38]\n" - "add x27, x27, x9\n" - "add x26, x26, x9\n" - "add x25, x25, x9\n" - "add x24, x24, x9\n" + "add x21, x21, x9\n" + "add x20, x20, x9\n" "st1 { v16.h }[0], [x27]\n" "ldr x27, [%x[outptrs], #0x40]\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "add x27, x27, x9\n" "st1 { v17.h }[0], [x26]\n" "ldr x26, [%x[outptrs], #0x48]\n" - "add x21, x21, x9\n" - "add x20, x20, x9\n" + "add x26, x26, x9\n" "st1 { v18.h }[0], [x25]\n" "ldr x25, [%x[outptrs], #0x50]\n" + "add x25, x25, x9\n" "st1 { v19.h }[0], [x24]\n" "ldr x24, [%x[outptrs], #0x58]\n" - "add x27, x27, x9\n" + "add x24, x24, x9\n" "st1 { v20.h }[0], [x23]\n" "ldr x23, [%x[outptrs], #0x60]\n" - "add x26, x26, x9\n" + "add x23, x23, x9\n" "st1 { v21.h }[0], [x22]\n" "ldr x22, [%x[outptrs], #0x68]\n" - "add x25, x25, x9\n" + "add x22, x22, x9\n" "st1 { v22.h }[0], [x21]\n" "ldr x21, [%x[outptrs], #0x70]\n" - "add x24, x24, x9\n" + "add x21, x21, x9\n" "st1 { v23.h }[0], [x20]\n" "ldr x20, [%x[outptrs], #0x78]\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" - "st1 { v24.h }[0], [x27]\n" - "add x21, x21, x9\n" - "st1 { v25.h }[0], [x26]\n" "add x20, x20, x9\n" "add x9, x9, #0x2\n" + "st1 { v24.h }[0], [x27]\n" + "st1 { v25.h }[0], [x26]\n" "st1 { v26.h }[0], [x25]\n" "st1 { v27.h }[0], [x24]\n" "st1 { v28.h }[0], [x23]\n" @@ -1370,46 +1370,46 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "tbz %x[n_output_channels], #0, 25f\n" "ldr x27, [%x[outptrs], #0x0]\n" "ldr x26, [%x[outptrs], #0x8]\n" + "add x27, x27, x9\n" + "add x26, x26, x9\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" + "add x25, x25, x9\n" + "add x24, x24, x9\n" "ldr x23, [%x[outptrs], #0x20]\n" "ldr x22, [%x[outptrs], #0x28]\n" + "add x23, x23, x9\n" + "add x22, x22, x9\n" "ldr x21, [%x[outptrs], #0x30]\n" "ldr x20, [%x[outptrs], #0x38]\n" - "add x27, x27, x9\n" - "add x26, x26, x9\n" - "add x25, x25, x9\n" - "add x24, x24, x9\n" + "add x21, x21, x9\n" + "add x20, x20, x9\n" "st1 { v16.b }[2], [x27]\n" "ldr x27, [%x[outptrs], #0x40]\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "add x27, x27, x9\n" "st1 { v17.b }[2], [x26]\n" "ldr x26, [%x[outptrs], #0x48]\n" - "add x21, x21, x9\n" - "add x20, x20, x9\n" + "add x26, x26, x9\n" "st1 { v18.b }[2], [x25]\n" "ldr x25, [%x[outptrs], #0x50]\n" + "add x25, x25, x9\n" "st1 { v19.b }[2], [x24]\n" "ldr x24, [%x[outptrs], #0x58]\n" - "add x27, x27, x9\n" + "add x24, x24, x9\n" "st1 { v20.b }[2], [x23]\n" "ldr x23, [%x[outptrs], #0x60]\n" - "add x26, x26, x9\n" + "add x23, x23, x9\n" "st1 { v21.b }[2], [x22]\n" "ldr x22, [%x[outptrs], #0x68]\n" - "add x25, x25, x9\n" + "add x22, x22, x9\n" "st1 { v22.b }[2], [x21]\n" "ldr x21, [%x[outptrs], #0x70]\n" - "add x24, x24, x9\n" + "add x21, x21, x9\n" "st1 { v23.b }[2], [x20]\n" "ldr x20, [%x[outptrs], #0x78]\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "add x20, x20, x9\n" "st1 { v24.b }[2], [x27]\n" - "add x21, x21, x9\n" "st1 { v25.b }[2], [x26]\n" - "add x20, x20, x9\n" "st1 { v26.b }[2], [x25]\n" "st1 { v27.b }[2], [x24]\n" "st1 { v28.b }[2], [x23]\n" @@ -1420,46 +1420,46 @@ void a64_s8q_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_imp "24:" // Output channel oddments: Done: Store: Bit 1: Unset "ldr x27, [%x[outptrs], #0x0]\n" "ldr x26, [%x[outptrs], #0x8]\n" + "add x27, x27, x9\n" + "add x26, x26, x9\n" "ldr x25, [%x[outptrs], #0x10]\n" "ldr x24, [%x[outptrs], #0x18]\n" + "add x25, x25, x9\n" + "add x24, x24, x9\n" "ldr x23, [%x[outptrs], #0x20]\n" "ldr x22, [%x[outptrs], #0x28]\n" + "add x23, x23, x9\n" + "add x22, x22, x9\n" "ldr x21, [%x[outptrs], #0x30]\n" "ldr x20, [%x[outptrs], #0x38]\n" - "add x27, x27, x9\n" - "add x26, x26, x9\n" - "add x25, x25, x9\n" - "add x24, x24, x9\n" + "add x21, x21, x9\n" + "add x20, x20, x9\n" "st1 { v16.b }[0], [x27]\n" "ldr x27, [%x[outptrs], #0x40]\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "add x27, x27, x9\n" "st1 { v17.b }[0], [x26]\n" "ldr x26, [%x[outptrs], #0x48]\n" - "add x21, x21, x9\n" - "add x20, x20, x9\n" + "add x26, x26, x9\n" "st1 { v18.b }[0], [x25]\n" "ldr x25, [%x[outptrs], #0x50]\n" + "add x25, x25, x9\n" "st1 { v19.b }[0], [x24]\n" "ldr x24, [%x[outptrs], #0x58]\n" - "add x27, x27, x9\n" + "add x24, x24, x9\n" "st1 { v20.b }[0], [x23]\n" "ldr x23, [%x[outptrs], #0x60]\n" - "add x26, x26, x9\n" + "add x23, x23, x9\n" "st1 { v21.b }[0], [x22]\n" "ldr x22, [%x[outptrs], #0x68]\n" - "add x25, x25, x9\n" + "add x22, x22, x9\n" "st1 { v22.b }[0], [x21]\n" "ldr x21, [%x[outptrs], #0x70]\n" - "add x24, x24, x9\n" + "add x21, x21, x9\n" "st1 { v23.b }[0], [x20]\n" "ldr x20, [%x[outptrs], #0x78]\n" - "add x23, x23, x9\n" - "add x22, x22, x9\n" + "add x20, x20, x9\n" "st1 { v24.b }[0], [x27]\n" - "add x21, x21, x9\n" "st1 { v25.b }[0], [x26]\n" - "add x20, x20, x9\n" "st1 { v26.b }[0], [x25]\n" "st1 { v27.b }[0], [x24]\n" "st1 { v28.b }[0], [x23]\n" |