diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_3x3_s2_with_multiplier_output2x4_dot_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_3x3_s2_with_multiplier_output2x4_dot_depthfirst/generic.cpp | 527 |
1 files changed, 527 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_3x3_s2_with_multiplier_output2x4_dot_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_3x3_s2_with_multiplier_output2x4_dot_depthfirst/generic.cpp new file mode 100644 index 0000000000..2fb6d3538f --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_s8q_packed_to_nhwc_3x3_s2_with_multiplier_output2x4_dot_depthfirst/generic.cpp @@ -0,0 +1,527 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +#include "arm_gemm.hpp" +#include <cstddef> +#include <cstdint> + +namespace arm_conv { +namespace depthwise { + +void a64_s8q_packed_to_nhwc_3x3_s2_with_multiplier_output2x4_dot_depthfirst_impl( + const int8_t *const *const inptrs, + int8_t *const *const outptrs, + const void *params, + unsigned int n_output_channels, + const arm_gemm::Requantize32& qp +) +{ + __asm__ __volatile__( + "movi v5.16b, #0x1\n" + "ldr x22, [%x[inptrs], #0x0]\n" + "add SP, SP, #-0x80\n" + "ushr v5.4s, v5.4s, #0x8\n" + "ldr x20, [%x[inptrs], #0x8]\n" + "add x21, %x[qp], %[offsetof_Requantize32_b_offset]\n" + "movi v26.4s, #0x0\n" + "ldr x19, [%x[inptrs], #0x10]\n" + "mov x11, #0x0\n" + "movi v1.4s, #0x0\n" + "ld1 { v15.16b }, [x22]\n" + "mov x10, #0x0\n" + "movi v22.4s, #0x0\n" + "ld1 { v29.16b }, [x20]\n" + "add x9, %x[qp], %[offsetof_Requantize32_c_offset]\n" + "movi v25.4s, #0x0\n" + "ld1 { v0.16b }, [x19]\n" + "add x28, %x[qp], %[offsetof_Requantize32_minval]\n" + "movi v13.4s, #0x0\n" + "ldr x20, [%x[inptrs], #0x18]\n" + "add x27, %x[qp], %[offsetof_Requantize32_maxval]\n" + "mov v20.16b, v15.16b\n" + "ldr x19, [%x[inptrs], #0x20]\n" + "cmp %x[n_channels], #0x4\n" + "ext v20.16b, v20.16b, v20.16b, #0x2\n" + "ld1r { v4.4s }, [x21]\n" + "mov v17.16b, v15.16b\n" + "ld1 { v2.16b }, [x20]\n" + "ext v17.16b, v17.16b, v17.16b, #0x4\n" + "ld1 { v7.16b }, [x19]\n" + "mov v23.16b, v15.16b\n" + "ldp x26, x25, [%x[outptrs], #0x0]\n" + "ext v23.16b, v23.16b, v23.16b, #0x6\n" + "ldp x24, x23, [%x[outptrs], #0x10]\n" + "mov v18.16b, v29.16b\n" + "ldp x22, x21, [%x[outptrs], #0x20]\n" + "zip1 v15.4s, v15.4s, v17.4s\n" + "ldp x20, x19, [%x[outptrs], #0x30]\n" + "ext v18.16b, v18.16b, v18.16b, #0x2\n" + "ld1r { v14.4s }, [x9]\n" + "zip1 v20.4s, v20.4s, v23.4s\n" + "ld1r { v27.4s }, [x28]\n" + "zip1 v15.4s, v15.4s, v20.4s\n" + "ld1r { v23.4s }, [x27]\n" + "mov v17.16b, v29.16b\n" + "ldr q6, [%x[params], #0x0]\n" + "ext v17.16b, v17.16b, v17.16b, #0x4\n" + "ldr q8, [%x[params], #0x10]\n" + "mov v11.16b, v29.16b\n" + "ldr q9, [%x[params], #0x20]\n" + "ext v11.16b, v11.16b, v11.16b, #0x6\n" + "ldr q10, [%x[params], #0x30]\n" + "add %x[params], %x[params], #0x40\n" + "zip1 v29.4s, v29.4s, v17.4s\n" + "mov v12.16b, v0.16b\n" + "ext v12.16b, v12.16b, v12.16b, #0x2\n" + "zip1 v18.4s, v18.4s, v11.4s\n" + "zip1 v29.4s, v29.4s, v18.4s\n" + "mov v17.16b, v0.16b\n" + "ext v17.16b, v17.16b, v17.16b, #0x4\n" + "mov v11.16b, v0.16b\n" + "ext v11.16b, v11.16b, v11.16b, #0x6\n" + "mov v18.16b, v2.16b\n" + "zip1 v0.4s, v0.4s, v17.4s\n" + "ext v18.16b, v18.16b, v18.16b, #0x2\n" + "zip1 v12.4s, v12.4s, v11.4s\n" + "zip1 v0.4s, v0.4s, v12.4s\n" + "mov v17.16b, v2.16b\n" + "ext v17.16b, v17.16b, v17.16b, #0x4\n" + "mov v19.16b, v2.16b\n" + "ext v19.16b, v19.16b, v19.16b, #0x6\n" + "mov v28.16b, v7.16b\n" + "zip1 v2.4s, v2.4s, v17.4s\n" + "ext v28.16b, v28.16b, v28.16b, #0x2\n" + "zip1 v18.4s, v18.4s, v19.4s\n" + "zip1 v2.4s, v2.4s, v18.4s\n" + "mov v18.16b, v7.16b\n" + "ext v18.16b, v18.16b, v18.16b, #0x4\n" + "mov v21.16b, v7.16b\n" + "ext v21.16b, v21.16b, v21.16b, #0x6\n" + "movi v30.4s, #0x0\n" + "zip1 v7.4s, v7.4s, v18.4s\n" + "movi v3.4s, #0x0\n" + "zip1 v28.4s, v28.4s, v21.4s\n" + "zip1 v7.4s, v7.4s, v28.4s\n" + "movi v12.4s, #0x0\n" + "movi v11.4s, #0x0\n" + "movi v19.4s, #0x0\n" + "movi v21.4s, #0x0\n" + "movi v17.4s, #0x0\n" + "movi v16.4s, #0x0\n" + "movi v28.4s, #0x0\n" + "movi v18.4s, #0x0\n" + "movi v20.4s, #0x0\n" + "movi v24.4s, #0x0\n" + "movi v31.4s, #0x0\n" + ".inst 0x4f8fe0ba // sdot v26.4s, v5.16b, v15.4b[0]\n" + ".inst 0x4fafe0a1 // sdot v1.4s, v5.16b, v15.4b[1]\n" + ".inst 0x4f8fe8b6 // sdot v22.4s, v5.16b, v15.4b[2]\n" + ".inst 0x4fafe8b9 // sdot v25.4s, v5.16b, v15.4b[3]\n" + ".inst 0x4f9de0ad // sdot v13.4s, v5.16b, v29.4b[0]\n" + ".inst 0x4fbde0be // sdot v30.4s, v5.16b, v29.4b[1]\n" + ".inst 0x4f9de8a3 // sdot v3.4s, v5.16b, v29.4b[2]\n" + ".inst 0x4fbde8ac // sdot v12.4s, v5.16b, v29.4b[3]\n" + ".inst 0x4f80e0ab // sdot v11.4s, v5.16b, v0.4b[0]\n" + ".inst 0x4fa0e0b3 // sdot v19.4s, v5.16b, v0.4b[1]\n" + ".inst 0x4f80e8b5 // sdot v21.4s, v5.16b, v0.4b[2]\n" + ".inst 0x4fa0e8b1 // sdot v17.4s, v5.16b, v0.4b[3]\n" + ".inst 0x4f82e0b0 // sdot v16.4s, v5.16b, v2.4b[0]\n" + ".inst 0x4fa2e0bc // sdot v28.4s, v5.16b, v2.4b[1]\n" + ".inst 0x4f82e8b2 // sdot v18.4s, v5.16b, v2.4b[2]\n" + ".inst 0x4fa2e8b4 // sdot v20.4s, v5.16b, v2.4b[3]\n" + ".inst 0x4f87e0b8 // sdot v24.4s, v5.16b, v7.4b[0]\n" + ".inst 0x4fa7e0bf // sdot v31.4s, v5.16b, v7.4b[1]\n" + "mov v26.16b, v26.16b\n" + "mov v1.16b, v1.16b\n" + "mov v22.16b, v22.16b\n" + "mov v25.16b, v25.16b\n" + "add v26.4s, v26.4s, v13.4s\n" + "movi v13.4s, #0x0\n" + ".inst 0x4f87e8ad // sdot v13.4s, v5.16b, v7.4b[2]\n" + "add v1.4s, v1.4s, v30.4s\n" + "movi v30.4s, #0x0\n" + ".inst 0x4fa7e8be // sdot v30.4s, v5.16b, v7.4b[3]\n" + "add v22.4s, v22.4s, v3.4s\n" + "add v25.4s, v25.4s, v12.4s\n" + "add v26.4s, v26.4s, v11.4s\n" + "add v1.4s, v1.4s, v19.4s\n" + "add v22.4s, v22.4s, v21.4s\n" + "add v25.4s, v25.4s, v17.4s\n" + "mov v11.16b, v11.16b\n" + "mov v3.16b, v19.16b\n" + "mov v19.16b, v21.16b\n" + "mov v21.16b, v17.16b\n" + "add v11.4s, v11.4s, v16.4s\n" + "add v3.4s, v3.4s, v28.4s\n" + "add v19.4s, v19.4s, v18.4s\n" + "add v21.4s, v21.4s, v20.4s\n" + "add v11.4s, v11.4s, v24.4s\n" + "add v3.4s, v3.4s, v31.4s\n" + "add v19.4s, v19.4s, v13.4s\n" + "add v21.4s, v21.4s, v30.4s\n" + "neg v4.4s, v4.4s\n" + "mul v26.4s, v26.4s, v4.4s\n" + "str q26, [SP, #0x0]\n" + "mul v1.4s, v1.4s, v4.4s\n" + "mul v22.4s, v22.4s, v4.4s\n" + "str q1, [SP, #0x10]\n" + "mul v25.4s, v25.4s, v4.4s\n" + "mul v11.4s, v11.4s, v4.4s\n" + "str q22, [SP, #0x20]\n" + "mul v3.4s, v3.4s, v4.4s\n" + "str q25, [SP, #0x30]\n" + "mul v19.4s, v19.4s, v4.4s\n" + "mul v21.4s, v21.4s, v4.4s\n" + "str q11, [SP, #0x40]\n" + "add v26.4s, v26.4s, v6.4s\n" + "str q3, [SP, #0x50]\n" + "add v1.4s, v1.4s, v6.4s\n" + "str q19, [SP, #0x60]\n" + "add v22.4s, v22.4s, v6.4s\n" + "add v25.4s, v25.4s, v6.4s\n" + "str q21, [SP, #0x70]\n" + "add v11.4s, v11.4s, v6.4s\n" + "add v3.4s, v3.4s, v6.4s\n" + "add v19.4s, v19.4s, v6.4s\n" + "add v21.4s, v21.4s, v6.4s\n" + "ble 2f\n" + "1:" // Loop + ".inst 0x4f8fe11a // sdot v26.4s, v8.16b, v15.4b[0]\n" + "ldr q20, [%x[params], #0x0]\n" + "add x11, x11, #0x10\n" + ".inst 0x4fafe101 // sdot v1.4s, v8.16b, v15.4b[1]\n" + "ldr q4, [%x[params], #0x10]\n" + "sub %x[n_channels], %x[n_channels], #0x4\n" + ".inst 0x4f8fe916 // sdot v22.4s, v8.16b, v15.4b[2]\n" + "ldr q6, [%x[params], #0x20]\n" + "cmp %x[n_channels], #0x4\n" + ".inst 0x4fafe919 // sdot v25.4s, v8.16b, v15.4b[3]\n" + ".inst 0x4f80e10b // sdot v11.4s, v8.16b, v0.4b[0]\n" + ".inst 0x4fa0e103 // sdot v3.4s, v8.16b, v0.4b[1]\n" + ".inst 0x4f80e913 // sdot v19.4s, v8.16b, v0.4b[2]\n" + ".inst 0x4fa0e915 // sdot v21.4s, v8.16b, v0.4b[3]\n" + "ldr q8, [%x[params], #0x30]\n" + ".inst 0x4f9de13a // sdot v26.4s, v9.16b, v29.4b[0]\n" + ".inst 0x4fbde121 // sdot v1.4s, v9.16b, v29.4b[1]\n" + ".inst 0x4f9de936 // sdot v22.4s, v9.16b, v29.4b[2]\n" + ".inst 0x4fbde939 // sdot v25.4s, v9.16b, v29.4b[3]\n" + ".inst 0x4f82e12b // sdot v11.4s, v9.16b, v2.4b[0]\n" + ".inst 0x4fa2e123 // sdot v3.4s, v9.16b, v2.4b[1]\n" + ".inst 0x4f82e933 // sdot v19.4s, v9.16b, v2.4b[2]\n" + ".inst 0x4fa2e935 // sdot v21.4s, v9.16b, v2.4b[3]\n" + "ldr q9, [%x[params], #0x40]\n" + ".inst 0x4f80e15a // sdot v26.4s, v10.16b, v0.4b[0]\n" + ".inst 0x4fa0e141 // sdot v1.4s, v10.16b, v0.4b[1]\n" + ".inst 0x4f80e956 // sdot v22.4s, v10.16b, v0.4b[2]\n" + ".inst 0x4fa0e959 // sdot v25.4s, v10.16b, v0.4b[3]\n" + ".inst 0x4f87e14b // sdot v11.4s, v10.16b, v7.4b[0]\n" + ".inst 0x4fa7e143 // sdot v3.4s, v10.16b, v7.4b[1]\n" + ".inst 0x4f87e953 // sdot v19.4s, v10.16b, v7.4b[2]\n" + ".inst 0x4fa7e955 // sdot v21.4s, v10.16b, v7.4b[3]\n" + "ldr q10, [%x[params], #0x50]\n" + "add %x[params], %x[params], #0x60\n" + "sqrdmulh v26.4s, v26.4s, v20.4s\n" + "sqrdmulh v1.4s, v1.4s, v20.4s\n" + "sqrdmulh v22.4s, v22.4s, v20.4s\n" + "sqrdmulh v25.4s, v25.4s, v20.4s\n" + "sqrdmulh v11.4s, v11.4s, v20.4s\n" + "and v30.16b, v26.16b, v4.16b\n" + "and v17.16b, v1.16b, v4.16b\n" + "and v16.16b, v22.16b, v4.16b\n" + "sshr v30.4s, v30.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "sqadd v26.4s, v26.4s, v30.4s\n" + "sqadd v1.4s, v1.4s, v17.4s\n" + "sqadd v22.4s, v22.4s, v16.4s\n" + "and v16.16b, v25.16b, v4.16b\n" + "srshl v26.4s, v26.4s, v4.4s\n" + "srshl v1.4s, v1.4s, v4.4s\n" + "srshl v22.4s, v22.4s, v4.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "add v26.4s, v26.4s, v14.4s\n" + "add v1.4s, v1.4s, v14.4s\n" + "add v22.4s, v22.4s, v14.4s\n" + "smin v26.4s, v26.4s, v23.4s\n" + "smin v1.4s, v1.4s, v23.4s\n" + "smin v22.4s, v22.4s, v23.4s\n" + "smax v26.4s, v26.4s, v27.4s\n" + "smax v1.4s, v1.4s, v27.4s\n" + "smax v22.4s, v22.4s, v27.4s\n" + "uzp1 v26.16b, v26.16b, v26.16b\n" + "uzp1 v1.16b, v1.16b, v1.16b\n" + "uzp1 v26.16b, v26.16b, v26.16b\n" + "str s26, [x26, x10]\n" + "uzp1 v1.16b, v1.16b, v1.16b\n" + "uzp1 v22.16b, v22.16b, v22.16b\n" + "ldr q26, [SP, #0x0]\n" + "sqadd v25.4s, v25.4s, v16.4s\n" + "str s1, [x25, x10]\n" + "uzp1 v22.16b, v22.16b, v22.16b\n" + "ldr q1, [SP, #0x10]\n" + "and v16.16b, v11.16b, v4.16b\n" + "str s22, [x24, x10]\n" + "sqrdmulh v3.4s, v3.4s, v20.4s\n" + "ldr q22, [SP, #0x20]\n" + "srshl v25.4s, v25.4s, v4.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "sqrdmulh v19.4s, v19.4s, v20.4s\n" + "and v17.16b, v3.16b, v4.16b\n" + "add v25.4s, v25.4s, v14.4s\n" + "sqadd v11.4s, v11.4s, v16.4s\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "smin v25.4s, v25.4s, v23.4s\n" + "and v16.16b, v19.16b, v4.16b\n" + "srshl v11.4s, v11.4s, v4.4s\n" + "smax v25.4s, v25.4s, v27.4s\n" + "sqadd v3.4s, v3.4s, v17.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "uzp1 v25.16b, v25.16b, v25.16b\n" + "add v11.4s, v11.4s, v14.4s\n" + "uzp1 v25.16b, v25.16b, v25.16b\n" + "str s25, [x23, x10]\n" + "smin v11.4s, v11.4s, v23.4s\n" + "srshl v3.4s, v3.4s, v4.4s\n" + "ldr q25, [SP, #0x30]\n" + "sqadd v19.4s, v19.4s, v16.4s\n" + "sqrdmulh v21.4s, v21.4s, v20.4s\n" + "smax v11.4s, v11.4s, v27.4s\n" + "add v3.4s, v3.4s, v14.4s\n" + "srshl v19.4s, v19.4s, v4.4s\n" + "uzp1 v11.16b, v11.16b, v11.16b\n" + "smin v3.4s, v3.4s, v23.4s\n" + "uzp1 v11.16b, v11.16b, v11.16b\n" + "str s11, [x22, x10]\n" + "smax v3.4s, v3.4s, v27.4s\n" + "add v19.4s, v19.4s, v14.4s\n" + "ldr q11, [SP, #0x40]\n" + "and v16.16b, v21.16b, v4.16b\n" + "add v26.4s, v26.4s, v6.4s\n" + "uzp1 v3.16b, v3.16b, v3.16b\n" + "smin v19.4s, v19.4s, v23.4s\n" + "uzp1 v3.16b, v3.16b, v3.16b\n" + "str s3, [x21, x10]\n" + "smax v19.4s, v19.4s, v27.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "ldr q3, [SP, #0x50]\n" + "add v1.4s, v1.4s, v6.4s\n" + "add v22.4s, v22.4s, v6.4s\n" + "uzp1 v19.16b, v19.16b, v19.16b\n" + "sqadd v21.4s, v21.4s, v16.4s\n" + "uzp1 v19.16b, v19.16b, v19.16b\n" + "str s19, [x20, x10]\n" + "add v25.4s, v25.4s, v6.4s\n" + "add v11.4s, v11.4s, v6.4s\n" + "ldr q19, [SP, #0x60]\n" + "srshl v21.4s, v21.4s, v4.4s\n" + "add v3.4s, v3.4s, v6.4s\n" + "add v21.4s, v21.4s, v14.4s\n" + "add v19.4s, v19.4s, v6.4s\n" + "smin v21.4s, v21.4s, v23.4s\n" + "smax v21.4s, v21.4s, v27.4s\n" + "uzp1 v21.16b, v21.16b, v21.16b\n" + "uzp1 v21.16b, v21.16b, v21.16b\n" + "str s21, [x19, x10]\n" + "add x10, x10, #0x4\n" + "ldr q21, [SP, #0x70]\n" + "add v21.4s, v21.4s, v6.4s\n" + "bgt 1b\n" + "2:" // Tail + ".inst 0x4f8fe11a // sdot v26.4s, v8.16b, v15.4b[0]\n" + "ldr q20, [%x[params], #0x0]\n" + "add x26, x26, x10\n" + ".inst 0x4fafe101 // sdot v1.4s, v8.16b, v15.4b[1]\n" + "ldr q4, [%x[params], #0x10]\n" + "add x25, x25, x10\n" + ".inst 0x4f8fe916 // sdot v22.4s, v8.16b, v15.4b[2]\n" + "add x24, x24, x10\n" + ".inst 0x4fafe919 // sdot v25.4s, v8.16b, v15.4b[3]\n" + "add x23, x23, x10\n" + ".inst 0x4f80e10b // sdot v11.4s, v8.16b, v0.4b[0]\n" + "add x22, x22, x10\n" + ".inst 0x4fa0e103 // sdot v3.4s, v8.16b, v0.4b[1]\n" + "add x21, x21, x10\n" + ".inst 0x4f80e913 // sdot v19.4s, v8.16b, v0.4b[2]\n" + "add x20, x20, x10\n" + ".inst 0x4fa0e915 // sdot v21.4s, v8.16b, v0.4b[3]\n" + "add x19, x19, x10\n" + ".inst 0x4f9de13a // sdot v26.4s, v9.16b, v29.4b[0]\n" + "cmp %x[n_channels], #0x4\n" + ".inst 0x4fbde121 // sdot v1.4s, v9.16b, v29.4b[1]\n" + "add %x[params], %x[params], #0x20\n" + ".inst 0x4f9de936 // sdot v22.4s, v9.16b, v29.4b[2]\n" + ".inst 0x4fbde939 // sdot v25.4s, v9.16b, v29.4b[3]\n" + ".inst 0x4f82e12b // sdot v11.4s, v9.16b, v2.4b[0]\n" + ".inst 0x4fa2e123 // sdot v3.4s, v9.16b, v2.4b[1]\n" + ".inst 0x4f82e933 // sdot v19.4s, v9.16b, v2.4b[2]\n" + ".inst 0x4fa2e935 // sdot v21.4s, v9.16b, v2.4b[3]\n" + ".inst 0x4f80e15a // sdot v26.4s, v10.16b, v0.4b[0]\n" + ".inst 0x4fa0e141 // sdot v1.4s, v10.16b, v0.4b[1]\n" + ".inst 0x4f80e956 // sdot v22.4s, v10.16b, v0.4b[2]\n" + ".inst 0x4fa0e959 // sdot v25.4s, v10.16b, v0.4b[3]\n" + ".inst 0x4f87e14b // sdot v11.4s, v10.16b, v7.4b[0]\n" + ".inst 0x4fa7e143 // sdot v3.4s, v10.16b, v7.4b[1]\n" + ".inst 0x4f87e953 // sdot v19.4s, v10.16b, v7.4b[2]\n" + ".inst 0x4fa7e955 // sdot v21.4s, v10.16b, v7.4b[3]\n" + "sqrdmulh v26.4s, v26.4s, v20.4s\n" + "sqrdmulh v1.4s, v1.4s, v20.4s\n" + "sqrdmulh v22.4s, v22.4s, v20.4s\n" + "sqrdmulh v25.4s, v25.4s, v20.4s\n" + "and v30.16b, v26.16b, v4.16b\n" + "and v17.16b, v1.16b, v4.16b\n" + "and v16.16b, v22.16b, v4.16b\n" + "sshr v30.4s, v30.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "sqadd v26.4s, v26.4s, v30.4s\n" + "sqadd v1.4s, v1.4s, v17.4s\n" + "sqadd v22.4s, v22.4s, v16.4s\n" + "and v16.16b, v25.16b, v4.16b\n" + "srshl v26.4s, v26.4s, v4.4s\n" + "srshl v1.4s, v1.4s, v4.4s\n" + "srshl v22.4s, v22.4s, v4.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "add v26.4s, v26.4s, v14.4s\n" + "add v1.4s, v1.4s, v14.4s\n" + "add v22.4s, v22.4s, v14.4s\n" + "smin v26.4s, v26.4s, v23.4s\n" + "smin v1.4s, v1.4s, v23.4s\n" + "smin v22.4s, v22.4s, v23.4s\n" + "smax v26.4s, v26.4s, v27.4s\n" + "smax v1.4s, v1.4s, v27.4s\n" + "smax v22.4s, v22.4s, v27.4s\n" + "uzp1 v26.16b, v26.16b, v26.16b\n" + "uzp1 v1.16b, v1.16b, v1.16b\n" + "uzp1 v26.16b, v26.16b, v26.16b\n" + "uzp1 v1.16b, v1.16b, v1.16b\n" + "uzp1 v22.16b, v22.16b, v22.16b\n" + "sqadd v25.4s, v25.4s, v16.4s\n" + "uzp1 v22.16b, v22.16b, v22.16b\n" + "sqrdmulh v11.4s, v11.4s, v20.4s\n" + "sqrdmulh v3.4s, v3.4s, v20.4s\n" + "srshl v25.4s, v25.4s, v4.4s\n" + "sqrdmulh v19.4s, v19.4s, v20.4s\n" + "and v16.16b, v11.16b, v4.16b\n" + "and v17.16b, v3.16b, v4.16b\n" + "add v25.4s, v25.4s, v14.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "sshr v17.4s, v17.4s, #0x1f\n" + "smin v25.4s, v25.4s, v23.4s\n" + "sqadd v11.4s, v11.4s, v16.4s\n" + "sqadd v3.4s, v3.4s, v17.4s\n" + "smax v25.4s, v25.4s, v27.4s\n" + "and v16.16b, v19.16b, v4.16b\n" + "srshl v11.4s, v11.4s, v4.4s\n" + "uzp1 v25.16b, v25.16b, v25.16b\n" + "srshl v3.4s, v3.4s, v4.4s\n" + "uzp1 v25.16b, v25.16b, v25.16b\n" + "add v11.4s, v11.4s, v14.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "add v3.4s, v3.4s, v14.4s\n" + "smin v11.4s, v11.4s, v23.4s\n" + "sqadd v19.4s, v19.4s, v16.4s\n" + "smin v3.4s, v3.4s, v23.4s\n" + "smax v11.4s, v11.4s, v27.4s\n" + "sqrdmulh v21.4s, v21.4s, v20.4s\n" + "smax v3.4s, v3.4s, v27.4s\n" + "uzp1 v11.16b, v11.16b, v11.16b\n" + "srshl v19.4s, v19.4s, v4.4s\n" + "uzp1 v11.16b, v11.16b, v11.16b\n" + "uzp1 v3.16b, v3.16b, v3.16b\n" + "and v16.16b, v21.16b, v4.16b\n" + "uzp1 v3.16b, v3.16b, v3.16b\n" + "add v19.4s, v19.4s, v14.4s\n" + "sshr v16.4s, v16.4s, #0x1f\n" + "smin v19.4s, v19.4s, v23.4s\n" + "sqadd v21.4s, v21.4s, v16.4s\n" + "smax v19.4s, v19.4s, v27.4s\n" + "srshl v21.4s, v21.4s, v4.4s\n" + "uzp1 v19.16b, v19.16b, v19.16b\n" + "uzp1 v19.16b, v19.16b, v19.16b\n" + "add v21.4s, v21.4s, v14.4s\n" + "smin v21.4s, v21.4s, v23.4s\n" + "smax v21.4s, v21.4s, v27.4s\n" + "uzp1 v21.16b, v21.16b, v21.16b\n" + "uzp1 v21.16b, v21.16b, v21.16b\n" + "blt 3f\n" + "str s26, [x26, #0x0]\n" + "str s1, [x25, #0x0]\n" + "str s22, [x24, #0x0]\n" + "str s25, [x23, #0x0]\n" + "str s11, [x22, #0x0]\n" + "str s3, [x21, #0x0]\n" + "str s19, [x20, #0x0]\n" + "str s21, [x19, #0x0]\n" + "b 4f\n" + "3:" // Tail: Oddments + "st1 { v26.b }[0], [x26], #0x1\n" + "subs %x[n_channels], %x[n_channels], #0x1\n" + "st1 { v1.b }[0], [x25], #0x1\n" + "st1 { v22.b }[0], [x24], #0x1\n" + "st1 { v25.b }[0], [x23], #0x1\n" + "st1 { v11.b }[0], [x22], #0x1\n" + "st1 { v3.b }[0], [x21], #0x1\n" + "st1 { v19.b }[0], [x20], #0x1\n" + "st1 { v21.b }[0], [x19], #0x1\n" + "beq 4f\n" + "st1 { v26.b }[1], [x26], #0x1\n" + "subs %x[n_channels], %x[n_channels], #0x1\n" + "st1 { v1.b }[1], [x25], #0x1\n" + "st1 { v22.b }[1], [x24], #0x1\n" + "st1 { v25.b }[1], [x23], #0x1\n" + "st1 { v11.b }[1], [x22], #0x1\n" + "st1 { v3.b }[1], [x21], #0x1\n" + "st1 { v19.b }[1], [x20], #0x1\n" + "st1 { v21.b }[1], [x19], #0x1\n" + "beq 4f\n" + "st1 { v26.b }[2], [x26], #0x1\n" + "subs %x[n_channels], %x[n_channels], #0x1\n" + "st1 { v1.b }[2], [x25], #0x1\n" + "st1 { v22.b }[2], [x24], #0x1\n" + "st1 { v25.b }[2], [x23], #0x1\n" + "st1 { v11.b }[2], [x22], #0x1\n" + "st1 { v3.b }[2], [x21], #0x1\n" + "st1 { v19.b }[2], [x20], #0x1\n" + "st1 { v21.b }[2], [x19], #0x1\n" + "beq 4f\n" + "st1 { v26.b }[3], [x26], #0x1\n" + "subs %x[n_channels], %x[n_channels], #0x1\n" + "st1 { v1.b }[3], [x25], #0x1\n" + "st1 { v22.b }[3], [x24], #0x1\n" + "st1 { v25.b }[3], [x23], #0x1\n" + "st1 { v11.b }[3], [x22], #0x1\n" + "st1 { v3.b }[3], [x21], #0x1\n" + "st1 { v19.b }[3], [x20], #0x1\n" + "st1 { v21.b }[3], [x19], #0x1\n" + "4:" // Tail: End + "add SP, SP, #0x80\n" + : [n_channels] "+&r" (n_output_channels), [params] "+&r" (params) + : [inptrs] "r" (inptrs), [offsetof_Requantize32_b_offset] "I" (offsetof(arm_gemm::Requantize32, b_offset)), [offsetof_Requantize32_c_offset] "I" (offsetof(arm_gemm::Requantize32, c_offset)), [offsetof_Requantize32_maxval] "I" (offsetof(arm_gemm::Requantize32, maxval)), [offsetof_Requantize32_minval] "I" (offsetof(arm_gemm::Requantize32, minval)), [outptrs] "r" (outptrs), [qp] "r" (&qp) + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + ); +} + +} // namespace depthwise +} // namespace arm_conv |