diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp | 1196 |
1 files changed, 598 insertions, 598 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp index c28f29c4f9..cc18dd4bb4 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst/generic.cpp @@ -22,10 +22,11 @@ * SOFTWARE. */ -#if defined(__aarch64__) #include <cstddef> #include <cstdint> +#if defined(__aarch64__) + namespace arm_conv { namespace depthwise { @@ -43,10 +44,10 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im const float minmax_vals[2] = { activation_min, activation_max }; __asm__ __volatile__( - "ld1r { v11.4s }, [%x[minmax_vals]]\n" + "ld1r { v12.4s }, [%x[minmax_vals]]\n" "lsr x11, %x[n_output_channels], #0x2\n" "add x20, %x[minmax_vals], #0x4\n" - "ld1r { v10.4s }, [x20]\n" + "ld1r { v11.4s }, [x20]\n" "mov x10, #0x0\n" "cbz x11, 8f\n" "1:" // Output channel loop @@ -55,16 +56,16 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "lsl x20, x10, #0x2\n" "ldr q31, [%x[bias], x20]\n" "2:" // Output channel loop: Load bias: Done - "ldr q9, [%x[weights], #0x0]\n" - "mov x20, %x[inptrs]\n" - "ldp x23, x9, [x20], #0x10\n" - "lsr x21, %x[kernel_points], #0x1\n" - "ldr q8, [x23, #0x0]\n" - "ldr q7, [x23, #0x10]\n" + "ldr q10, [%x[weights], #0x0]\n" + "mov x22, %x[inptrs]\n" + "ldp x21, x20, [x22], #0x10\n" + "lsr x23, %x[kernel_points], #0x1\n" + "ldr q3, [x21, #0x0]\n" + "ldr q2, [x21, #0x10]\n" "mov v16.16b, v31.16b\n" "mov v17.16b, v31.16b\n" - "ldr q6, [x9, #0x0]\n" - "ldr q5, [x9, #0x10]\n" + "ldr q1, [x20, #0x0]\n" + "ldr q0, [x20, #0x10]\n" "mov v18.16b, v31.16b\n" "mov v19.16b, v31.16b\n" "mov v20.16b, v31.16b\n" @@ -80,368 +81,368 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "mov v29.16b, v31.16b\n" "mov v30.16b, v31.16b\n" "mov v31.16b, v31.16b\n" - "cbz x21, 6f\n" - "ldr q4, [%x[weights], #0x0]\n" - "ldp x23, x9, [x20], #0x10\n" - "subs x21, x21, #0x1\n" + "cbz x23, 6f\n" + "ldr q9, [%x[weights], #0x0]\n" + "ldp x21, x20, [x22], #0x10\n" + "subs x23, x23, #0x1\n" "add %x[weights], %x[weights], #0x10\n" - "ldr q3, [x23, #0x0]\n" - "ldr q2, [x23, #0x10]\n" - "ldr q1, [x9, #0x0]\n" - "ldr q0, [x9, #0x10]\n" + "ldr q8, [x21, #0x0]\n" + "ldr q7, [x21, #0x10]\n" + "ldr q6, [x20, #0x0]\n" + "ldr q5, [x20, #0x10]\n" "beq 4f\n" "3:" // Output channel loop: Kernel loop - "ldp x23, x9, [x20], #0x10\n" + "ldp x21, x20, [x22], #0x10\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "subs x23, x23, #0x1\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "ldr q3, [x21, #0x0]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "ldr q2, [x21, #0x10]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "ldr q1, [x20, #0x0]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" + "ldr q0, [x20, #0x10]\n" + "ldr q10, [%x[weights], #0x0]\n" + "ldp x21, x20, [x22], #0x10\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" - "subs x21, x21, #0x1\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr q8, [x23, #0x0]\n" + "ldr q8, [x21, #0x0]\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" - "ldr q7, [x23, #0x10]\n" + "ldr q7, [x21, #0x10]\n" "fmla v24.4s, v9.4s, v6.s[0]\n" "fmla v25.4s, v9.4s, v6.s[1]\n" "fmla v26.4s, v9.4s, v6.s[2]\n" "fmla v27.4s, v9.4s, v6.s[3]\n" - "ldr q6, [x9, #0x0]\n" + "ldr q6, [x20, #0x0]\n" "fmla v28.4s, v9.4s, v5.s[0]\n" "fmla v29.4s, v9.4s, v5.s[1]\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" - "ldr q5, [x9, #0x10]\n" - "ldr q9, [%x[weights], #0x0]\n" - "ldp x23, x9, [x20], #0x10\n" - "fmla v16.4s, v4.4s, v3.s[0]\n" - "fmla v17.4s, v4.4s, v3.s[1]\n" - "fmla v18.4s, v4.4s, v3.s[2]\n" - "fmla v19.4s, v4.4s, v3.s[3]\n" - "ldr q3, [x23, #0x0]\n" - "fmla v20.4s, v4.4s, v2.s[0]\n" - "fmla v21.4s, v4.4s, v2.s[1]\n" - "fmla v22.4s, v4.4s, v2.s[2]\n" - "fmla v23.4s, v4.4s, v2.s[3]\n" - "ldr q2, [x23, #0x10]\n" - "fmla v24.4s, v4.4s, v1.s[0]\n" - "fmla v25.4s, v4.4s, v1.s[1]\n" - "fmla v26.4s, v4.4s, v1.s[2]\n" - "fmla v27.4s, v4.4s, v1.s[3]\n" - "ldr q1, [x9, #0x0]\n" - "fmla v28.4s, v4.4s, v0.s[0]\n" - "fmla v29.4s, v4.4s, v0.s[1]\n" - "fmla v30.4s, v4.4s, v0.s[2]\n" - "fmla v31.4s, v4.4s, v0.s[3]\n" - "ldr q0, [x9, #0x10]\n" - "ldr q4, [%x[weights], #0x10]\n" + "ldr q5, [x20, #0x10]\n" + "ldr q9, [%x[weights], #0x10]\n" "add %x[weights], %x[weights], #0x20\n" "bgt 3b\n" "4:" // Output channel loop: Kernel loop tail "tbnz %x[kernel_points], #0, 5f\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "lsl x28, x10, #0x2\n" + "ldr x27, [%x[outptrs], #0x0]\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "ldr x26, [%x[outptrs], #0x8]\n" + "ldr x25, [%x[outptrs], #0x10]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "ldr x21, [%x[outptrs], #0x30]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "ldr x20, [%x[outptrs], #0x38]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" - "lsl x28, x10, #0x2\n" - "ldr x20, [%x[outptrs], #0x0]\n" + "fmin v16.4s, v16.4s, v11.4s\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr x21, [%x[outptrs], #0x8]\n" - "ldr x22, [%x[outptrs], #0x10]\n" + "fmin v17.4s, v17.4s, v11.4s\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" - "ldr x23, [%x[outptrs], #0x18]\n" - "ldr x24, [%x[outptrs], #0x20]\n" + "fmin v18.4s, v18.4s, v11.4s\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" - "ldr x25, [%x[outptrs], #0x28]\n" - "ldr x26, [%x[outptrs], #0x30]\n" + "fmin v19.4s, v19.4s, v11.4s\n" "fmla v24.4s, v9.4s, v6.s[0]\n" "fmla v25.4s, v9.4s, v6.s[1]\n" - "ldr x27, [%x[outptrs], #0x38]\n" + "fmin v20.4s, v20.4s, v11.4s\n" "fmla v26.4s, v9.4s, v6.s[2]\n" "fmla v27.4s, v9.4s, v6.s[3]\n" + "fmin v21.4s, v21.4s, v11.4s\n" "fmla v28.4s, v9.4s, v5.s[0]\n" "fmla v29.4s, v9.4s, v5.s[1]\n" + "fmin v22.4s, v22.4s, v11.4s\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" - "fmla v16.4s, v4.4s, v3.s[0]\n" - "fmla v17.4s, v4.4s, v3.s[1]\n" - "fmin v16.4s, v16.4s, v10.4s\n" - "fmla v18.4s, v4.4s, v3.s[2]\n" - "fmla v19.4s, v4.4s, v3.s[3]\n" - "fmin v17.4s, v17.4s, v10.4s\n" - "fmla v20.4s, v4.4s, v2.s[0]\n" - "fmla v21.4s, v4.4s, v2.s[1]\n" - "fmin v18.4s, v18.4s, v10.4s\n" - "fmla v22.4s, v4.4s, v2.s[2]\n" - "fmla v23.4s, v4.4s, v2.s[3]\n" - "fmin v19.4s, v19.4s, v10.4s\n" - "fmla v24.4s, v4.4s, v1.s[0]\n" - "fmla v25.4s, v4.4s, v1.s[1]\n" - "fmin v20.4s, v20.4s, v10.4s\n" - "fmla v26.4s, v4.4s, v1.s[2]\n" - "fmla v27.4s, v4.4s, v1.s[3]\n" - "fmin v21.4s, v21.4s, v10.4s\n" - "fmla v28.4s, v4.4s, v0.s[0]\n" - "fmla v29.4s, v4.4s, v0.s[1]\n" - "fmin v22.4s, v22.4s, v10.4s\n" - "fmla v30.4s, v4.4s, v0.s[2]\n" - "fmla v31.4s, v4.4s, v0.s[3]\n" - "fmin v23.4s, v23.4s, v10.4s\n" - "fmax v16.4s, v16.4s, v11.4s\n" - "fmax v17.4s, v17.4s, v11.4s\n" - "str q16, [x20, x28]\n" - "ldr x20, [%x[outptrs], #0x40]\n" - "fmax v18.4s, v18.4s, v11.4s\n" - "fmax v19.4s, v19.4s, v11.4s\n" - "str q17, [x21, x28]\n" - "ldr x21, [%x[outptrs], #0x48]\n" - "fmax v20.4s, v20.4s, v11.4s\n" - "fmax v21.4s, v21.4s, v11.4s\n" - "str q18, [x22, x28]\n" - "ldr x22, [%x[outptrs], #0x50]\n" - "fmax v22.4s, v22.4s, v11.4s\n" - "fmax v23.4s, v23.4s, v11.4s\n" - "str q19, [x23, x28]\n" - "ldr x23, [%x[outptrs], #0x58]\n" - "fmin v24.4s, v24.4s, v10.4s\n" - "fmin v25.4s, v25.4s, v10.4s\n" - "str q20, [x24, x28]\n" - "ldr x24, [%x[outptrs], #0x60]\n" - "fmin v26.4s, v26.4s, v10.4s\n" - "fmin v27.4s, v27.4s, v10.4s\n" - "str q21, [x25, x28]\n" - "ldr x25, [%x[outptrs], #0x68]\n" - "fmin v28.4s, v28.4s, v10.4s\n" - "fmin v29.4s, v29.4s, v10.4s\n" - "str q22, [x26, x28]\n" - "ldr x26, [%x[outptrs], #0x70]\n" - "fmin v30.4s, v30.4s, v10.4s\n" - "fmin v31.4s, v31.4s, v10.4s\n" - "str q23, [x27, x28]\n" - "ldr x27, [%x[outptrs], #0x78]\n" - "fmax v24.4s, v24.4s, v11.4s\n" - "fmax v25.4s, v25.4s, v11.4s\n" - "str q24, [x20, x28]\n" - "fmax v26.4s, v26.4s, v11.4s\n" - "fmax v27.4s, v27.4s, v11.4s\n" - "str q25, [x21, x28]\n" - "fmax v28.4s, v28.4s, v11.4s\n" - "fmax v29.4s, v29.4s, v11.4s\n" - "str q26, [x22, x28]\n" - "fmax v30.4s, v30.4s, v11.4s\n" - "fmax v31.4s, v31.4s, v11.4s\n" - "str q27, [x23, x28]\n" - "str q28, [x24, x28]\n" - "str q29, [x25, x28]\n" - "str q30, [x26, x28]\n" - "str q31, [x27, x28]\n" + "fmin v23.4s, v23.4s, v11.4s\n" + "fmax v16.4s, v16.4s, v12.4s\n" + "fmax v17.4s, v17.4s, v12.4s\n" + "str q16, [x27, x28]\n" + "ldr x27, [%x[outptrs], #0x40]\n" + "fmax v18.4s, v18.4s, v12.4s\n" + "fmax v19.4s, v19.4s, v12.4s\n" + "str q17, [x26, x28]\n" + "ldr x26, [%x[outptrs], #0x48]\n" + "fmax v20.4s, v20.4s, v12.4s\n" + "fmax v21.4s, v21.4s, v12.4s\n" + "str q18, [x25, x28]\n" + "ldr x25, [%x[outptrs], #0x50]\n" + "fmax v22.4s, v22.4s, v12.4s\n" + "fmax v23.4s, v23.4s, v12.4s\n" + "str q19, [x24, x28]\n" + "ldr x24, [%x[outptrs], #0x58]\n" + "fmin v24.4s, v24.4s, v11.4s\n" + "fmin v25.4s, v25.4s, v11.4s\n" + "str q20, [x23, x28]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "fmin v26.4s, v26.4s, v11.4s\n" + "fmin v27.4s, v27.4s, v11.4s\n" + "str q21, [x22, x28]\n" + "ldr x22, [%x[outptrs], #0x68]\n" + "fmin v28.4s, v28.4s, v11.4s\n" + "fmin v29.4s, v29.4s, v11.4s\n" + "str q22, [x21, x28]\n" + "ldr x21, [%x[outptrs], #0x70]\n" + "fmin v30.4s, v30.4s, v11.4s\n" + "fmin v31.4s, v31.4s, v11.4s\n" + "str q23, [x20, x28]\n" + "ldr x20, [%x[outptrs], #0x78]\n" + "fmax v24.4s, v24.4s, v12.4s\n" + "fmax v25.4s, v25.4s, v12.4s\n" + "str q24, [x27, x28]\n" + "fmax v26.4s, v26.4s, v12.4s\n" + "fmax v27.4s, v27.4s, v12.4s\n" + "str q25, [x26, x28]\n" + "fmax v28.4s, v28.4s, v12.4s\n" + "fmax v29.4s, v29.4s, v12.4s\n" + "str q26, [x25, x28]\n" + "fmax v30.4s, v30.4s, v12.4s\n" + "fmax v31.4s, v31.4s, v12.4s\n" + "str q27, [x24, x28]\n" + "str q28, [x23, x28]\n" + "str q29, [x22, x28]\n" + "str q30, [x21, x28]\n" + "str q31, [x20, x28]\n" "b 7f\n" "5:" // Output channel loop: Odd tail - "fmla v16.4s, v9.4s, v8.s[0]\n" - "fmla v17.4s, v9.4s, v8.s[1]\n" - "ldp x23, x9, [x20], #0x10\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "ldp x20, x9, [x22], #0x10\n" "lsl x28, x10, #0x2\n" - "fmla v18.4s, v9.4s, v8.s[2]\n" - "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr q8, [x23, #0x0]\n" - "ldr x20, [%x[outptrs], #0x0]\n" - "fmla v20.4s, v9.4s, v7.s[0]\n" - "fmla v21.4s, v9.4s, v7.s[1]\n" - "ldr x21, [%x[outptrs], #0x8]\n" - "ldr x22, [%x[outptrs], #0x10]\n" - "fmla v22.4s, v9.4s, v7.s[2]\n" - "fmla v23.4s, v9.4s, v7.s[3]\n" - "ldr q7, [x23, #0x10]\n" - "ldr x23, [%x[outptrs], #0x18]\n" - "fmla v24.4s, v9.4s, v6.s[0]\n" - "fmla v25.4s, v9.4s, v6.s[1]\n" - "ldr x24, [%x[outptrs], #0x20]\n" - "ldr x25, [%x[outptrs], #0x28]\n" - "fmla v26.4s, v9.4s, v6.s[2]\n" - "fmla v27.4s, v9.4s, v6.s[3]\n" - "ldr q6, [x9, #0x0]\n" - "ldr x26, [%x[outptrs], #0x30]\n" - "fmla v28.4s, v9.4s, v5.s[0]\n" - "fmla v29.4s, v9.4s, v5.s[1]\n" - "ldr x27, [%x[outptrs], #0x38]\n" - "fmla v30.4s, v9.4s, v5.s[2]\n" - "fmla v31.4s, v9.4s, v5.s[3]\n" - "ldr q9, [%x[weights], #0x0]\n" - "ldr q5, [x9, #0x10]\n" - "fmla v16.4s, v4.4s, v3.s[0]\n" - "fmla v17.4s, v4.4s, v3.s[1]\n" - "add %x[weights], %x[weights], #0x10\n" - "fmla v18.4s, v4.4s, v3.s[2]\n" - "fmla v19.4s, v4.4s, v3.s[3]\n" - "fmla v20.4s, v4.4s, v2.s[0]\n" - "fmla v21.4s, v4.4s, v2.s[1]\n" - "fmla v22.4s, v4.4s, v2.s[2]\n" - "fmla v23.4s, v4.4s, v2.s[3]\n" - "fmla v24.4s, v4.4s, v1.s[0]\n" - "fmla v25.4s, v4.4s, v1.s[1]\n" - "fmla v26.4s, v4.4s, v1.s[2]\n" - "fmla v27.4s, v4.4s, v1.s[3]\n" - "fmla v28.4s, v4.4s, v0.s[0]\n" - "fmla v29.4s, v4.4s, v0.s[1]\n" - "fmla v30.4s, v4.4s, v0.s[2]\n" - "fmla v31.4s, v4.4s, v0.s[3]\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "ldr q4, [x20, #0x0]\n" + "ldr x27, [%x[outptrs], #0x0]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "ldr x26, [%x[outptrs], #0x8]\n" + "ldr x25, [%x[outptrs], #0x10]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "ldr q3, [x20, #0x10]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "ldr q2, [x9, #0x0]\n" + "ldr x21, [%x[outptrs], #0x30]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "ldr x20, [%x[outptrs], #0x38]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" + "ldr q1, [%x[weights], #0x0]\n" + "ldr q0, [x9, #0x10]\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" - "fmin v16.4s, v16.4s, v10.4s\n" + "add %x[weights], %x[weights], #0x10\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "fmin v17.4s, v17.4s, v10.4s\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" - "fmin v18.4s, v18.4s, v10.4s\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" - "fmin v19.4s, v19.4s, v10.4s\n" "fmla v24.4s, v9.4s, v6.s[0]\n" "fmla v25.4s, v9.4s, v6.s[1]\n" - "fmin v20.4s, v20.4s, v10.4s\n" "fmla v26.4s, v9.4s, v6.s[2]\n" "fmla v27.4s, v9.4s, v6.s[3]\n" - "fmin v21.4s, v21.4s, v10.4s\n" "fmla v28.4s, v9.4s, v5.s[0]\n" "fmla v29.4s, v9.4s, v5.s[1]\n" - "fmin v22.4s, v22.4s, v10.4s\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" - "fmin v23.4s, v23.4s, v10.4s\n" - "fmax v16.4s, v16.4s, v11.4s\n" - "fmax v17.4s, v17.4s, v11.4s\n" - "str q16, [x20, x28]\n" - "ldr x20, [%x[outptrs], #0x40]\n" - "fmax v18.4s, v18.4s, v11.4s\n" - "fmax v19.4s, v19.4s, v11.4s\n" - "str q17, [x21, x28]\n" - "ldr x21, [%x[outptrs], #0x48]\n" - "fmax v20.4s, v20.4s, v11.4s\n" - "fmax v21.4s, v21.4s, v11.4s\n" - "str q18, [x22, x28]\n" - "ldr x22, [%x[outptrs], #0x50]\n" - "fmax v22.4s, v22.4s, v11.4s\n" - "fmax v23.4s, v23.4s, v11.4s\n" - "str q19, [x23, x28]\n" - "ldr x23, [%x[outptrs], #0x58]\n" - "fmin v24.4s, v24.4s, v10.4s\n" - "fmin v25.4s, v25.4s, v10.4s\n" - "str q20, [x24, x28]\n" - "ldr x24, [%x[outptrs], #0x60]\n" - "fmin v26.4s, v26.4s, v10.4s\n" - "fmin v27.4s, v27.4s, v10.4s\n" - "str q21, [x25, x28]\n" - "ldr x25, [%x[outptrs], #0x68]\n" - "fmin v28.4s, v28.4s, v10.4s\n" - "fmin v29.4s, v29.4s, v10.4s\n" - "str q22, [x26, x28]\n" - "ldr x26, [%x[outptrs], #0x70]\n" - "fmin v30.4s, v30.4s, v10.4s\n" - "fmin v31.4s, v31.4s, v10.4s\n" - "str q23, [x27, x28]\n" - "ldr x27, [%x[outptrs], #0x78]\n" - "fmax v24.4s, v24.4s, v11.4s\n" - "fmax v25.4s, v25.4s, v11.4s\n" - "str q24, [x20, x28]\n" - "fmax v26.4s, v26.4s, v11.4s\n" - "fmax v27.4s, v27.4s, v11.4s\n" - "str q25, [x21, x28]\n" - "fmax v28.4s, v28.4s, v11.4s\n" - "fmax v29.4s, v29.4s, v11.4s\n" - "str q26, [x22, x28]\n" - "fmax v30.4s, v30.4s, v11.4s\n" - "fmax v31.4s, v31.4s, v11.4s\n" - "str q27, [x23, x28]\n" - "str q28, [x24, x28]\n" - "str q29, [x25, x28]\n" - "str q30, [x26, x28]\n" - "str q31, [x27, x28]\n" + "fmla v16.4s, v1.4s, v4.s[0]\n" + "fmla v17.4s, v1.4s, v4.s[1]\n" + "fmin v16.4s, v16.4s, v11.4s\n" + "fmla v18.4s, v1.4s, v4.s[2]\n" + "fmla v19.4s, v1.4s, v4.s[3]\n" + "fmin v17.4s, v17.4s, v11.4s\n" + "fmla v20.4s, v1.4s, v3.s[0]\n" + "fmla v21.4s, v1.4s, v3.s[1]\n" + "fmin v18.4s, v18.4s, v11.4s\n" + "fmla v22.4s, v1.4s, v3.s[2]\n" + "fmla v23.4s, v1.4s, v3.s[3]\n" + "fmin v19.4s, v19.4s, v11.4s\n" + "fmla v24.4s, v1.4s, v2.s[0]\n" + "fmla v25.4s, v1.4s, v2.s[1]\n" + "fmin v20.4s, v20.4s, v11.4s\n" + "fmla v26.4s, v1.4s, v2.s[2]\n" + "fmla v27.4s, v1.4s, v2.s[3]\n" + "fmin v21.4s, v21.4s, v11.4s\n" + "fmla v28.4s, v1.4s, v0.s[0]\n" + "fmla v29.4s, v1.4s, v0.s[1]\n" + "fmin v22.4s, v22.4s, v11.4s\n" + "fmla v30.4s, v1.4s, v0.s[2]\n" + "fmla v31.4s, v1.4s, v0.s[3]\n" + "fmin v23.4s, v23.4s, v11.4s\n" + "fmax v16.4s, v16.4s, v12.4s\n" + "fmax v17.4s, v17.4s, v12.4s\n" + "str q16, [x27, x28]\n" + "ldr x27, [%x[outptrs], #0x40]\n" + "fmax v18.4s, v18.4s, v12.4s\n" + "fmax v19.4s, v19.4s, v12.4s\n" + "str q17, [x26, x28]\n" + "ldr x26, [%x[outptrs], #0x48]\n" + "fmax v20.4s, v20.4s, v12.4s\n" + "fmax v21.4s, v21.4s, v12.4s\n" + "str q18, [x25, x28]\n" + "ldr x25, [%x[outptrs], #0x50]\n" + "fmax v22.4s, v22.4s, v12.4s\n" + "fmax v23.4s, v23.4s, v12.4s\n" + "str q19, [x24, x28]\n" + "ldr x24, [%x[outptrs], #0x58]\n" + "fmin v24.4s, v24.4s, v11.4s\n" + "fmin v25.4s, v25.4s, v11.4s\n" + "str q20, [x23, x28]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "fmin v26.4s, v26.4s, v11.4s\n" + "fmin v27.4s, v27.4s, v11.4s\n" + "str q21, [x22, x28]\n" + "ldr x22, [%x[outptrs], #0x68]\n" + "fmin v28.4s, v28.4s, v11.4s\n" + "fmin v29.4s, v29.4s, v11.4s\n" + "str q22, [x21, x28]\n" + "ldr x21, [%x[outptrs], #0x70]\n" + "fmin v30.4s, v30.4s, v11.4s\n" + "fmin v31.4s, v31.4s, v11.4s\n" + "str q23, [x20, x28]\n" + "ldr x20, [%x[outptrs], #0x78]\n" + "fmax v24.4s, v24.4s, v12.4s\n" + "fmax v25.4s, v25.4s, v12.4s\n" + "str q24, [x27, x28]\n" + "fmax v26.4s, v26.4s, v12.4s\n" + "fmax v27.4s, v27.4s, v12.4s\n" + "str q25, [x26, x28]\n" + "fmax v28.4s, v28.4s, v12.4s\n" + "fmax v29.4s, v29.4s, v12.4s\n" + "str q26, [x25, x28]\n" + "fmax v30.4s, v30.4s, v12.4s\n" + "fmax v31.4s, v31.4s, v12.4s\n" + "str q27, [x24, x28]\n" + "str q28, [x23, x28]\n" + "str q29, [x22, x28]\n" + "str q30, [x21, x28]\n" + "str q31, [x20, x28]\n" "b 7f\n" "6:" // Output channel loop: Single kernel point - "fmla v16.4s, v9.4s, v8.s[0]\n" - "fmla v17.4s, v9.4s, v8.s[1]\n" - "fmin v16.4s, v16.4s, v10.4s\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "fmin v16.4s, v16.4s, v11.4s\n" "lsl x28, x10, #0x2\n" - "fmla v18.4s, v9.4s, v8.s[2]\n" - "fmla v19.4s, v9.4s, v8.s[3]\n" - "fmin v17.4s, v17.4s, v10.4s\n" - "ldr x20, [%x[outptrs], #0x0]\n" - "fmla v20.4s, v9.4s, v7.s[0]\n" - "fmla v21.4s, v9.4s, v7.s[1]\n" - "fmin v18.4s, v18.4s, v10.4s\n" - "ldr x21, [%x[outptrs], #0x8]\n" - "fmla v22.4s, v9.4s, v7.s[2]\n" - "fmla v23.4s, v9.4s, v7.s[3]\n" - "fmin v19.4s, v19.4s, v10.4s\n" - "ldr x22, [%x[outptrs], #0x10]\n" - "fmla v24.4s, v9.4s, v6.s[0]\n" - "fmla v25.4s, v9.4s, v6.s[1]\n" - "fmin v20.4s, v20.4s, v10.4s\n" - "ldr x23, [%x[outptrs], #0x18]\n" - "fmla v26.4s, v9.4s, v6.s[2]\n" - "fmla v27.4s, v9.4s, v6.s[3]\n" - "fmin v21.4s, v21.4s, v10.4s\n" - "ldr x24, [%x[outptrs], #0x20]\n" - "fmla v28.4s, v9.4s, v5.s[0]\n" - "fmla v29.4s, v9.4s, v5.s[1]\n" - "fmin v22.4s, v22.4s, v10.4s\n" - "ldr x25, [%x[outptrs], #0x28]\n" - "fmla v30.4s, v9.4s, v5.s[2]\n" - "fmla v31.4s, v9.4s, v5.s[3]\n" - "fmin v23.4s, v23.4s, v10.4s\n" - "ldr x26, [%x[outptrs], #0x30]\n" - "ldr x27, [%x[outptrs], #0x38]\n" - "fmax v16.4s, v16.4s, v11.4s\n" - "fmax v17.4s, v17.4s, v11.4s\n" - "str q16, [x20, x28]\n" - "fmax v18.4s, v18.4s, v11.4s\n" - "fmax v19.4s, v19.4s, v11.4s\n" - "str q17, [x21, x28]\n" - "ldr x20, [%x[outptrs], #0x40]\n" - "fmax v20.4s, v20.4s, v11.4s\n" - "fmax v21.4s, v21.4s, v11.4s\n" - "str q18, [x22, x28]\n" - "ldr x21, [%x[outptrs], #0x48]\n" - "fmax v22.4s, v22.4s, v11.4s\n" - "fmax v23.4s, v23.4s, v11.4s\n" - "str q19, [x23, x28]\n" - "ldr x22, [%x[outptrs], #0x50]\n" - "fmin v24.4s, v24.4s, v10.4s\n" - "fmin v25.4s, v25.4s, v10.4s\n" - "str q20, [x24, x28]\n" - "ldr x23, [%x[outptrs], #0x58]\n" - "fmin v26.4s, v26.4s, v10.4s\n" - "fmin v27.4s, v27.4s, v10.4s\n" - "str q21, [x25, x28]\n" - "ldr x24, [%x[outptrs], #0x60]\n" - "fmin v28.4s, v28.4s, v10.4s\n" - "fmin v29.4s, v29.4s, v10.4s\n" - "str q22, [x26, x28]\n" - "ldr x25, [%x[outptrs], #0x68]\n" - "fmin v30.4s, v30.4s, v10.4s\n" - "fmin v31.4s, v31.4s, v10.4s\n" - "str q23, [x27, x28]\n" - "ldr x26, [%x[outptrs], #0x70]\n" - "ldr x27, [%x[outptrs], #0x78]\n" - "fmax v24.4s, v24.4s, v11.4s\n" - "fmax v25.4s, v25.4s, v11.4s\n" - "str q24, [x20, x28]\n" - "fmax v26.4s, v26.4s, v11.4s\n" - "fmax v27.4s, v27.4s, v11.4s\n" - "str q25, [x21, x28]\n" - "fmax v28.4s, v28.4s, v11.4s\n" - "fmax v29.4s, v29.4s, v11.4s\n" - "str q26, [x22, x28]\n" - "fmax v30.4s, v30.4s, v11.4s\n" - "fmax v31.4s, v31.4s, v11.4s\n" - "str q27, [x23, x28]\n" - "str q28, [x24, x28]\n" - "str q29, [x25, x28]\n" - "str q30, [x26, x28]\n" - "str q31, [x27, x28]\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "fmin v17.4s, v17.4s, v11.4s\n" + "ldr x27, [%x[outptrs], #0x0]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "fmin v18.4s, v18.4s, v11.4s\n" + "ldr x26, [%x[outptrs], #0x8]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "fmin v19.4s, v19.4s, v11.4s\n" + "ldr x25, [%x[outptrs], #0x10]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "fmin v20.4s, v20.4s, v11.4s\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "fmin v21.4s, v21.4s, v11.4s\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmin v22.4s, v22.4s, v11.4s\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" + "fmin v23.4s, v23.4s, v11.4s\n" + "ldr x21, [%x[outptrs], #0x30]\n" + "ldr x20, [%x[outptrs], #0x38]\n" + "fmax v16.4s, v16.4s, v12.4s\n" + "fmax v17.4s, v17.4s, v12.4s\n" + "str q16, [x27, x28]\n" + "fmax v18.4s, v18.4s, v12.4s\n" + "fmax v19.4s, v19.4s, v12.4s\n" + "str q17, [x26, x28]\n" + "ldr x27, [%x[outptrs], #0x40]\n" + "fmax v20.4s, v20.4s, v12.4s\n" + "fmax v21.4s, v21.4s, v12.4s\n" + "str q18, [x25, x28]\n" + "ldr x26, [%x[outptrs], #0x48]\n" + "fmax v22.4s, v22.4s, v12.4s\n" + "fmax v23.4s, v23.4s, v12.4s\n" + "str q19, [x24, x28]\n" + "ldr x25, [%x[outptrs], #0x50]\n" + "fmin v24.4s, v24.4s, v11.4s\n" + "fmin v25.4s, v25.4s, v11.4s\n" + "str q20, [x23, x28]\n" + "ldr x24, [%x[outptrs], #0x58]\n" + "fmin v26.4s, v26.4s, v11.4s\n" + "fmin v27.4s, v27.4s, v11.4s\n" + "str q21, [x22, x28]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "fmin v28.4s, v28.4s, v11.4s\n" + "fmin v29.4s, v29.4s, v11.4s\n" + "str q22, [x21, x28]\n" + "ldr x22, [%x[outptrs], #0x68]\n" + "fmin v30.4s, v30.4s, v11.4s\n" + "fmin v31.4s, v31.4s, v11.4s\n" + "str q23, [x20, x28]\n" + "ldr x21, [%x[outptrs], #0x70]\n" + "ldr x20, [%x[outptrs], #0x78]\n" + "fmax v24.4s, v24.4s, v12.4s\n" + "fmax v25.4s, v25.4s, v12.4s\n" + "str q24, [x27, x28]\n" + "fmax v26.4s, v26.4s, v12.4s\n" + "fmax v27.4s, v27.4s, v12.4s\n" + "str q25, [x26, x28]\n" + "fmax v28.4s, v28.4s, v12.4s\n" + "fmax v29.4s, v29.4s, v12.4s\n" + "str q26, [x25, x28]\n" + "fmax v30.4s, v30.4s, v12.4s\n" + "fmax v31.4s, v31.4s, v12.4s\n" + "str q27, [x24, x28]\n" + "str q28, [x23, x28]\n" + "str q29, [x22, x28]\n" + "str q30, [x21, x28]\n" + "str q31, [x20, x28]\n" "7:" // Output channel loop: Done "add x10, x10, #0x4\n" "cmp x10, x11, LSL #2\n" @@ -461,16 +462,16 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "ld1 { v31.s }[0], [x20]\n" "10:" // Output channel oddments: Load bias: Bit 1: End "11:" // Output channel oddments: Load bias: Done - "ldr q9, [%x[weights], #0x0]\n" - "mov x20, %x[inptrs]\n" - "ldp x23, x9, [x20], #0x10\n" - "lsr x21, %x[kernel_points], #0x1\n" - "ldr q8, [x23, #0x0]\n" - "ldr q7, [x23, #0x10]\n" + "ldr q10, [%x[weights], #0x0]\n" + "mov x22, %x[inptrs]\n" + "ldp x21, x20, [x22], #0x10\n" + "lsr x23, %x[kernel_points], #0x1\n" + "ldr q3, [x21, #0x0]\n" + "ldr q2, [x21, #0x10]\n" "mov v16.16b, v31.16b\n" "mov v17.16b, v31.16b\n" - "ldr q6, [x9, #0x0]\n" - "ldr q5, [x9, #0x10]\n" + "ldr q1, [x20, #0x0]\n" + "ldr q0, [x20, #0x10]\n" "mov v18.16b, v31.16b\n" "mov v19.16b, v31.16b\n" "mov v20.16b, v31.16b\n" @@ -486,66 +487,82 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "mov v29.16b, v31.16b\n" "mov v30.16b, v31.16b\n" "mov v31.16b, v31.16b\n" - "cbz x21, 15f\n" - "ldr q4, [%x[weights], #0x0]\n" - "ldp x23, x9, [x20], #0x10\n" - "subs x21, x21, #0x1\n" + "cbz x23, 15f\n" + "ldr q9, [%x[weights], #0x0]\n" + "ldp x21, x20, [x22], #0x10\n" + "subs x23, x23, #0x1\n" "add %x[weights], %x[weights], #0x10\n" - "ldr q3, [x23, #0x0]\n" - "ldr q2, [x23, #0x10]\n" - "ldr q1, [x9, #0x0]\n" - "ldr q0, [x9, #0x10]\n" + "ldr q8, [x21, #0x0]\n" + "ldr q7, [x21, #0x10]\n" + "ldr q6, [x20, #0x0]\n" + "ldr q5, [x20, #0x10]\n" "beq 13f\n" "12:" // Output channel oddments: Kernel loop - "ldp x23, x9, [x20], #0x10\n" + "ldp x21, x20, [x22], #0x10\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "subs x23, x23, #0x1\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "ldr q3, [x21, #0x0]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "ldr q2, [x21, #0x10]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "ldr q1, [x20, #0x0]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" + "ldr q0, [x20, #0x10]\n" + "ldr q10, [%x[weights], #0x0]\n" + "ldp x21, x20, [x22], #0x10\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" - "subs x21, x21, #0x1\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr q8, [x23, #0x0]\n" + "ldr q8, [x21, #0x0]\n" "fmla v20.4s, v9.4s, v7.s[0]\n" "fmla v21.4s, v9.4s, v7.s[1]\n" "fmla v22.4s, v9.4s, v7.s[2]\n" "fmla v23.4s, v9.4s, v7.s[3]\n" - "ldr q7, [x23, #0x10]\n" + "ldr q7, [x21, #0x10]\n" "fmla v24.4s, v9.4s, v6.s[0]\n" "fmla v25.4s, v9.4s, v6.s[1]\n" "fmla v26.4s, v9.4s, v6.s[2]\n" "fmla v27.4s, v9.4s, v6.s[3]\n" - "ldr q6, [x9, #0x0]\n" + "ldr q6, [x20, #0x0]\n" "fmla v28.4s, v9.4s, v5.s[0]\n" "fmla v29.4s, v9.4s, v5.s[1]\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" - "ldr q5, [x9, #0x10]\n" - "ldr q9, [%x[weights], #0x0]\n" - "ldp x23, x9, [x20], #0x10\n" - "fmla v16.4s, v4.4s, v3.s[0]\n" - "fmla v17.4s, v4.4s, v3.s[1]\n" - "fmla v18.4s, v4.4s, v3.s[2]\n" - "fmla v19.4s, v4.4s, v3.s[3]\n" - "ldr q3, [x23, #0x0]\n" - "fmla v20.4s, v4.4s, v2.s[0]\n" - "fmla v21.4s, v4.4s, v2.s[1]\n" - "fmla v22.4s, v4.4s, v2.s[2]\n" - "fmla v23.4s, v4.4s, v2.s[3]\n" - "ldr q2, [x23, #0x10]\n" - "fmla v24.4s, v4.4s, v1.s[0]\n" - "fmla v25.4s, v4.4s, v1.s[1]\n" - "fmla v26.4s, v4.4s, v1.s[2]\n" - "fmla v27.4s, v4.4s, v1.s[3]\n" - "ldr q1, [x9, #0x0]\n" - "fmla v28.4s, v4.4s, v0.s[0]\n" - "fmla v29.4s, v4.4s, v0.s[1]\n" - "fmla v30.4s, v4.4s, v0.s[2]\n" - "fmla v31.4s, v4.4s, v0.s[3]\n" - "ldr q0, [x9, #0x10]\n" - "ldr q4, [%x[weights], #0x10]\n" + "ldr q5, [x20, #0x10]\n" + "ldr q9, [%x[weights], #0x10]\n" "add %x[weights], %x[weights], #0x20\n" "bgt 12b\n" "13:" // Output channel oddments: Kernel loop tail "tbnz %x[kernel_points], #0, 14f\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" "fmla v18.4s, v9.4s, v8.s[2]\n" @@ -562,65 +579,33 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "fmla v29.4s, v9.4s, v5.s[1]\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" - "fmla v16.4s, v4.4s, v3.s[0]\n" - "fmla v17.4s, v4.4s, v3.s[1]\n" - "fmla v18.4s, v4.4s, v3.s[2]\n" - "fmla v19.4s, v4.4s, v3.s[3]\n" - "fmla v20.4s, v4.4s, v2.s[0]\n" - "fmla v21.4s, v4.4s, v2.s[1]\n" - "fmla v22.4s, v4.4s, v2.s[2]\n" - "fmla v23.4s, v4.4s, v2.s[3]\n" - "fmla v24.4s, v4.4s, v1.s[0]\n" - "fmla v25.4s, v4.4s, v1.s[1]\n" - "fmla v26.4s, v4.4s, v1.s[2]\n" - "fmla v27.4s, v4.4s, v1.s[3]\n" - "fmla v28.4s, v4.4s, v0.s[0]\n" - "fmla v29.4s, v4.4s, v0.s[1]\n" - "fmla v30.4s, v4.4s, v0.s[2]\n" - "fmla v31.4s, v4.4s, v0.s[3]\n" "b 16f\n" "14:" // Output channel oddments: Odd tail + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "ldp x21, x20, [x22], #0x10\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "ldr q4, [x21, #0x0]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "ldr q3, [x21, #0x10]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "ldr q2, [x20, #0x0]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" + "ldr q1, [x20, #0x10]\n" + "ldr q0, [%x[weights], #0x0]\n" "fmla v16.4s, v9.4s, v8.s[0]\n" "fmla v17.4s, v9.4s, v8.s[1]\n" - "ldp x23, x9, [x20], #0x10\n" - "fmla v18.4s, v9.4s, v8.s[2]\n" - "fmla v19.4s, v9.4s, v8.s[3]\n" - "ldr q8, [x23, #0x0]\n" - "fmla v20.4s, v9.4s, v7.s[0]\n" - "fmla v21.4s, v9.4s, v7.s[1]\n" - "fmla v22.4s, v9.4s, v7.s[2]\n" - "fmla v23.4s, v9.4s, v7.s[3]\n" - "ldr q7, [x23, #0x10]\n" - "fmla v24.4s, v9.4s, v6.s[0]\n" - "fmla v25.4s, v9.4s, v6.s[1]\n" - "fmla v26.4s, v9.4s, v6.s[2]\n" - "fmla v27.4s, v9.4s, v6.s[3]\n" - "ldr q6, [x9, #0x0]\n" - "fmla v28.4s, v9.4s, v5.s[0]\n" - "fmla v29.4s, v9.4s, v5.s[1]\n" - "fmla v30.4s, v9.4s, v5.s[2]\n" - "fmla v31.4s, v9.4s, v5.s[3]\n" - "ldr q5, [x9, #0x10]\n" - "ldr q9, [%x[weights], #0x0]\n" - "fmla v16.4s, v4.4s, v3.s[0]\n" - "fmla v17.4s, v4.4s, v3.s[1]\n" "add %x[weights], %x[weights], #0x10\n" - "fmla v18.4s, v4.4s, v3.s[2]\n" - "fmla v19.4s, v4.4s, v3.s[3]\n" - "fmla v20.4s, v4.4s, v2.s[0]\n" - "fmla v21.4s, v4.4s, v2.s[1]\n" - "fmla v22.4s, v4.4s, v2.s[2]\n" - "fmla v23.4s, v4.4s, v2.s[3]\n" - "fmla v24.4s, v4.4s, v1.s[0]\n" - "fmla v25.4s, v4.4s, v1.s[1]\n" - "fmla v26.4s, v4.4s, v1.s[2]\n" - "fmla v27.4s, v4.4s, v1.s[3]\n" - "fmla v28.4s, v4.4s, v0.s[0]\n" - "fmla v29.4s, v4.4s, v0.s[1]\n" - "fmla v30.4s, v4.4s, v0.s[2]\n" - "fmla v31.4s, v4.4s, v0.s[3]\n" - "fmla v16.4s, v9.4s, v8.s[0]\n" - "fmla v17.4s, v9.4s, v8.s[1]\n" "fmla v18.4s, v9.4s, v8.s[2]\n" "fmla v19.4s, v9.4s, v8.s[3]\n" "fmla v20.4s, v9.4s, v7.s[0]\n" @@ -635,216 +620,231 @@ void a64_fp32_packed_to_nhwc_generic_with_multiplier_output2x8_mla_depthfirst_im "fmla v29.4s, v9.4s, v5.s[1]\n" "fmla v30.4s, v9.4s, v5.s[2]\n" "fmla v31.4s, v9.4s, v5.s[3]\n" + "fmla v16.4s, v0.4s, v4.s[0]\n" + "fmla v17.4s, v0.4s, v4.s[1]\n" + "fmla v18.4s, v0.4s, v4.s[2]\n" + "fmla v19.4s, v0.4s, v4.s[3]\n" + "fmla v20.4s, v0.4s, v3.s[0]\n" + "fmla v21.4s, v0.4s, v3.s[1]\n" + "fmla v22.4s, v0.4s, v3.s[2]\n" + "fmla v23.4s, v0.4s, v3.s[3]\n" + "fmla v24.4s, v0.4s, v2.s[0]\n" + "fmla v25.4s, v0.4s, v2.s[1]\n" + "fmla v26.4s, v0.4s, v2.s[2]\n" + "fmla v27.4s, v0.4s, v2.s[3]\n" + "fmla v28.4s, v0.4s, v1.s[0]\n" + "fmla v29.4s, v0.4s, v1.s[1]\n" + "fmla v30.4s, v0.4s, v1.s[2]\n" + "fmla v31.4s, v0.4s, v1.s[3]\n" "b 16f\n" "15:" // Output channel oddments: Single kernel point - "fmla v16.4s, v9.4s, v8.s[0]\n" - "fmla v17.4s, v9.4s, v8.s[1]\n" - "fmla v18.4s, v9.4s, v8.s[2]\n" - "fmla v19.4s, v9.4s, v8.s[3]\n" - "fmla v20.4s, v9.4s, v7.s[0]\n" - "fmla v21.4s, v9.4s, v7.s[1]\n" - "fmla v22.4s, v9.4s, v7.s[2]\n" - "fmla v23.4s, v9.4s, v7.s[3]\n" - "fmla v24.4s, v9.4s, v6.s[0]\n" - "fmla v25.4s, v9.4s, v6.s[1]\n" - "fmla v26.4s, v9.4s, v6.s[2]\n" - "fmla v27.4s, v9.4s, v6.s[3]\n" - "fmla v28.4s, v9.4s, v5.s[0]\n" - "fmla v29.4s, v9.4s, v5.s[1]\n" - "fmla v30.4s, v9.4s, v5.s[2]\n" - "fmla v31.4s, v9.4s, v5.s[3]\n" + "fmla v16.4s, v10.4s, v3.s[0]\n" + "fmla v17.4s, v10.4s, v3.s[1]\n" + "fmla v18.4s, v10.4s, v3.s[2]\n" + "fmla v19.4s, v10.4s, v3.s[3]\n" + "fmla v20.4s, v10.4s, v2.s[0]\n" + "fmla v21.4s, v10.4s, v2.s[1]\n" + "fmla v22.4s, v10.4s, v2.s[2]\n" + "fmla v23.4s, v10.4s, v2.s[3]\n" + "fmla v24.4s, v10.4s, v1.s[0]\n" + "fmla v25.4s, v10.4s, v1.s[1]\n" + "fmla v26.4s, v10.4s, v1.s[2]\n" + "fmla v27.4s, v10.4s, v1.s[3]\n" + "fmla v28.4s, v10.4s, v0.s[0]\n" + "fmla v29.4s, v10.4s, v0.s[1]\n" + "fmla v30.4s, v10.4s, v0.s[2]\n" + "fmla v31.4s, v10.4s, v0.s[3]\n" "16:" // Output channel oddments: Done - "fmin v16.4s, v16.4s, v10.4s\n" - "fmin v17.4s, v17.4s, v10.4s\n" - "fmin v18.4s, v18.4s, v10.4s\n" - "fmin v19.4s, v19.4s, v10.4s\n" - "fmin v20.4s, v20.4s, v10.4s\n" - "fmin v21.4s, v21.4s, v10.4s\n" - "fmin v22.4s, v22.4s, v10.4s\n" - "fmin v23.4s, v23.4s, v10.4s\n" - "fmin v24.4s, v24.4s, v10.4s\n" - "fmin v25.4s, v25.4s, v10.4s\n" - "fmin v26.4s, v26.4s, v10.4s\n" - "fmin v27.4s, v27.4s, v10.4s\n" - "fmin v28.4s, v28.4s, v10.4s\n" - "fmin v29.4s, v29.4s, v10.4s\n" - "fmin v30.4s, v30.4s, v10.4s\n" - "fmin v31.4s, v31.4s, v10.4s\n" - "fmax v16.4s, v16.4s, v11.4s\n" - "fmax v17.4s, v17.4s, v11.4s\n" - "fmax v18.4s, v18.4s, v11.4s\n" - "fmax v19.4s, v19.4s, v11.4s\n" - "fmax v20.4s, v20.4s, v11.4s\n" - "fmax v21.4s, v21.4s, v11.4s\n" - "fmax v22.4s, v22.4s, v11.4s\n" - "fmax v23.4s, v23.4s, v11.4s\n" - "fmax v24.4s, v24.4s, v11.4s\n" - "fmax v25.4s, v25.4s, v11.4s\n" - "fmax v26.4s, v26.4s, v11.4s\n" - "fmax v27.4s, v27.4s, v11.4s\n" - "fmax v28.4s, v28.4s, v11.4s\n" - "fmax v29.4s, v29.4s, v11.4s\n" - "fmax v30.4s, v30.4s, v11.4s\n" - "fmax v31.4s, v31.4s, v11.4s\n" + "fmin v16.4s, v16.4s, v11.4s\n" + "fmin v17.4s, v17.4s, v11.4s\n" + "fmin v18.4s, v18.4s, v11.4s\n" + "fmin v19.4s, v19.4s, v11.4s\n" + "fmin v20.4s, v20.4s, v11.4s\n" + "fmin v21.4s, v21.4s, v11.4s\n" + "fmin v22.4s, v22.4s, v11.4s\n" + "fmin v23.4s, v23.4s, v11.4s\n" + "fmin v24.4s, v24.4s, v11.4s\n" + "fmin v25.4s, v25.4s, v11.4s\n" + "fmin v26.4s, v26.4s, v11.4s\n" + "fmin v27.4s, v27.4s, v11.4s\n" + "fmin v28.4s, v28.4s, v11.4s\n" + "fmin v29.4s, v29.4s, v11.4s\n" + "fmin v30.4s, v30.4s, v11.4s\n" + "fmin v31.4s, v31.4s, v11.4s\n" + "fmax v16.4s, v16.4s, v12.4s\n" + "fmax v17.4s, v17.4s, v12.4s\n" + "fmax v18.4s, v18.4s, v12.4s\n" + "fmax v19.4s, v19.4s, v12.4s\n" + "fmax v20.4s, v20.4s, v12.4s\n" + "fmax v21.4s, v21.4s, v12.4s\n" + "fmax v22.4s, v22.4s, v12.4s\n" + "fmax v23.4s, v23.4s, v12.4s\n" + "fmax v24.4s, v24.4s, v12.4s\n" + "fmax v25.4s, v25.4s, v12.4s\n" + "fmax v26.4s, v26.4s, v12.4s\n" + "fmax v27.4s, v27.4s, v12.4s\n" + "fmax v28.4s, v28.4s, v12.4s\n" + "fmax v29.4s, v29.4s, v12.4s\n" + "fmax v30.4s, v30.4s, v12.4s\n" + "fmax v31.4s, v31.4s, v12.4s\n" "tbz %x[n_output_channels], #1, 17f\n" - "ldr x20, [%x[outptrs], #0x0]\n" - "ldr x21, [%x[outptrs], #0x8]\n" - "add x20, x20, x10, LSL #2\n" - "add x21, x21, x10, LSL #2\n" - "ldr x22, [%x[outptrs], #0x10]\n" - "ldr x23, [%x[outptrs], #0x18]\n" - "add x22, x22, x10, LSL #2\n" - "add x23, x23, x10, LSL #2\n" - "ldr x24, [%x[outptrs], #0x20]\n" - "ldr x25, [%x[outptrs], #0x28]\n" - "add x24, x24, x10, LSL #2\n" - "add x25, x25, x10, LSL #2\n" - "ldr x26, [%x[outptrs], #0x30]\n" - "ldr x27, [%x[outptrs], #0x38]\n" - "add x26, x26, x10, LSL #2\n" + "ldr x27, [%x[outptrs], #0x0]\n" + "ldr x26, [%x[outptrs], #0x8]\n" "add x27, x27, x10, LSL #2\n" - "st1 { v16.d }[0], [x20]\n" - "ldr x20, [%x[outptrs], #0x40]\n" - "add x20, x20, x10, LSL #2\n" - "st1 { v17.d }[0], [x21]\n" - "ldr x21, [%x[outptrs], #0x48]\n" - "add x21, x21, x10, LSL #2\n" - "st1 { v18.d }[0], [x22]\n" - "ldr x22, [%x[outptrs], #0x50]\n" - "add x22, x22, x10, LSL #2\n" - "st1 { v19.d }[0], [x23]\n" - "ldr x23, [%x[outptrs], #0x58]\n" - "add x23, x23, x10, LSL #2\n" - "st1 { v20.d }[0], [x24]\n" - "ldr x24, [%x[outptrs], #0x60]\n" - "add x24, x24, x10, LSL #2\n" - "st1 { v21.d }[0], [x25]\n" - "ldr x25, [%x[outptrs], #0x68]\n" - "add x25, x25, x10, LSL #2\n" - "st1 { v22.d }[0], [x26]\n" - "ldr x26, [%x[outptrs], #0x70]\n" "add x26, x26, x10, LSL #2\n" - "st1 { v23.d }[0], [x27]\n" - "ldr x27, [%x[outptrs], #0x78]\n" + "ldr x25, [%x[outptrs], #0x10]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "add x25, x25, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" + "ldr x21, [%x[outptrs], #0x30]\n" + "ldr x20, [%x[outptrs], #0x38]\n" + "add x21, x21, x10, LSL #2\n" + "add x20, x20, x10, LSL #2\n" + "st1 { v16.d }[0], [x27]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "add x27, x27, x10, LSL #2\n" + "st1 { v17.d }[0], [x26]\n" + "ldr x26, [%x[outptrs], #0x48]\n" + "add x26, x26, x10, LSL #2\n" + "st1 { v18.d }[0], [x25]\n" + "ldr x25, [%x[outptrs], #0x50]\n" + "add x25, x25, x10, LSL #2\n" + "st1 { v19.d }[0], [x24]\n" + "ldr x24, [%x[outptrs], #0x58]\n" + "add x24, x24, x10, LSL #2\n" + "st1 { v20.d }[0], [x23]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "add x23, x23, x10, LSL #2\n" + "st1 { v21.d }[0], [x22]\n" + "ldr x22, [%x[outptrs], #0x68]\n" + "add x22, x22, x10, LSL #2\n" + "st1 { v22.d }[0], [x21]\n" + "ldr x21, [%x[outptrs], #0x70]\n" + "add x21, x21, x10, LSL #2\n" + "st1 { v23.d }[0], [x20]\n" + "ldr x20, [%x[outptrs], #0x78]\n" + "add x20, x20, x10, LSL #2\n" "add x10, x10, #0x2\n" - "st1 { v24.d }[0], [x20]\n" - "st1 { v25.d }[0], [x21]\n" - "st1 { v26.d }[0], [x22]\n" - "st1 { v27.d }[0], [x23]\n" - "st1 { v28.d }[0], [x24]\n" - "st1 { v29.d }[0], [x25]\n" - "st1 { v30.d }[0], [x26]\n" - "st1 { v31.d }[0], [x27]\n" + "st1 { v24.d }[0], [x27]\n" + "st1 { v25.d }[0], [x26]\n" + "st1 { v26.d }[0], [x25]\n" + "st1 { v27.d }[0], [x24]\n" + "st1 { v28.d }[0], [x23]\n" + "st1 { v29.d }[0], [x22]\n" + "st1 { v30.d }[0], [x21]\n" + "st1 { v31.d }[0], [x20]\n" "tbz %x[n_output_channels], #0, 18f\n" - "ldr x20, [%x[outptrs], #0x0]\n" - "ldr x21, [%x[outptrs], #0x8]\n" - "add x20, x20, x10, LSL #2\n" - "add x21, x21, x10, LSL #2\n" - "ldr x22, [%x[outptrs], #0x10]\n" - "ldr x23, [%x[outptrs], #0x18]\n" - "add x22, x22, x10, LSL #2\n" - "add x23, x23, x10, LSL #2\n" - "ldr x24, [%x[outptrs], #0x20]\n" - "ldr x25, [%x[outptrs], #0x28]\n" - "add x24, x24, x10, LSL #2\n" - "add x25, x25, x10, LSL #2\n" - "ldr x26, [%x[outptrs], #0x30]\n" - "ldr x27, [%x[outptrs], #0x38]\n" - "add x26, x26, x10, LSL #2\n" + "ldr x27, [%x[outptrs], #0x0]\n" + "ldr x26, [%x[outptrs], #0x8]\n" "add x27, x27, x10, LSL #2\n" - "st1 { v16.s }[2], [x20]\n" - "ldr x20, [%x[outptrs], #0x40]\n" - "add x20, x20, x10, LSL #2\n" - "st1 { v17.s }[2], [x21]\n" - "ldr x21, [%x[outptrs], #0x48]\n" - "add x21, x21, x10, LSL #2\n" - "st1 { v18.s }[2], [x22]\n" - "ldr x22, [%x[outptrs], #0x50]\n" - "add x22, x22, x10, LSL #2\n" - "st1 { v19.s }[2], [x23]\n" - "ldr x23, [%x[outptrs], #0x58]\n" - "add x23, x23, x10, LSL #2\n" - "st1 { v20.s }[2], [x24]\n" - "ldr x24, [%x[outptrs], #0x60]\n" - "add x24, x24, x10, LSL #2\n" - "st1 { v21.s }[2], [x25]\n" - "ldr x25, [%x[outptrs], #0x68]\n" - "add x25, x25, x10, LSL #2\n" - "st1 { v22.s }[2], [x26]\n" - "ldr x26, [%x[outptrs], #0x70]\n" "add x26, x26, x10, LSL #2\n" - "st1 { v23.s }[2], [x27]\n" - "ldr x27, [%x[outptrs], #0x78]\n" + "ldr x25, [%x[outptrs], #0x10]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "add x25, x25, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" + "ldr x21, [%x[outptrs], #0x30]\n" + "ldr x20, [%x[outptrs], #0x38]\n" + "add x21, x21, x10, LSL #2\n" + "add x20, x20, x10, LSL #2\n" + "st1 { v16.s }[2], [x27]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "add x27, x27, x10, LSL #2\n" - "st1 { v24.s }[2], [x20]\n" - "st1 { v25.s }[2], [x21]\n" - "st1 { v26.s }[2], [x22]\n" - "st1 { v27.s }[2], [x23]\n" - "st1 { v28.s }[2], [x24]\n" - "st1 { v29.s }[2], [x25]\n" - "st1 { v30.s }[2], [x26]\n" - "st1 { v31.s }[2], [x27]\n" + "st1 { v17.s }[2], [x26]\n" + "ldr x26, [%x[outptrs], #0x48]\n" + "add x26, x26, x10, LSL #2\n" + "st1 { v18.s }[2], [x25]\n" + "ldr x25, [%x[outptrs], #0x50]\n" + "add x25, x25, x10, LSL #2\n" + "st1 { v19.s }[2], [x24]\n" + "ldr x24, [%x[outptrs], #0x58]\n" + "add x24, x24, x10, LSL #2\n" + "st1 { v20.s }[2], [x23]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "add x23, x23, x10, LSL #2\n" + "st1 { v21.s }[2], [x22]\n" + "ldr x22, [%x[outptrs], #0x68]\n" + "add x22, x22, x10, LSL #2\n" + "st1 { v22.s }[2], [x21]\n" + "ldr x21, [%x[outptrs], #0x70]\n" + "add x21, x21, x10, LSL #2\n" + "st1 { v23.s }[2], [x20]\n" + "ldr x20, [%x[outptrs], #0x78]\n" + "add x20, x20, x10, LSL #2\n" + "st1 { v24.s }[2], [x27]\n" + "st1 { v25.s }[2], [x26]\n" + "st1 { v26.s }[2], [x25]\n" + "st1 { v27.s }[2], [x24]\n" + "st1 { v28.s }[2], [x23]\n" + "st1 { v29.s }[2], [x22]\n" + "st1 { v30.s }[2], [x21]\n" + "st1 { v31.s }[2], [x20]\n" "b 18f\n" "17:" // Output channel oddments: Done: Store: Bit 1: Unset - "ldr x20, [%x[outptrs], #0x0]\n" - "ldr x21, [%x[outptrs], #0x8]\n" - "add x20, x20, x10, LSL #2\n" - "add x21, x21, x10, LSL #2\n" - "ldr x22, [%x[outptrs], #0x10]\n" - "ldr x23, [%x[outptrs], #0x18]\n" - "add x22, x22, x10, LSL #2\n" - "add x23, x23, x10, LSL #2\n" - "ldr x24, [%x[outptrs], #0x20]\n" - "ldr x25, [%x[outptrs], #0x28]\n" - "add x24, x24, x10, LSL #2\n" - "add x25, x25, x10, LSL #2\n" - "ldr x26, [%x[outptrs], #0x30]\n" - "ldr x27, [%x[outptrs], #0x38]\n" - "add x26, x26, x10, LSL #2\n" + "ldr x27, [%x[outptrs], #0x0]\n" + "ldr x26, [%x[outptrs], #0x8]\n" "add x27, x27, x10, LSL #2\n" - "st1 { v16.s }[0], [x20]\n" - "ldr x20, [%x[outptrs], #0x40]\n" - "add x20, x20, x10, LSL #2\n" - "st1 { v17.s }[0], [x21]\n" - "ldr x21, [%x[outptrs], #0x48]\n" - "add x21, x21, x10, LSL #2\n" - "st1 { v18.s }[0], [x22]\n" - "ldr x22, [%x[outptrs], #0x50]\n" - "add x22, x22, x10, LSL #2\n" - "st1 { v19.s }[0], [x23]\n" - "ldr x23, [%x[outptrs], #0x58]\n" - "add x23, x23, x10, LSL #2\n" - "st1 { v20.s }[0], [x24]\n" - "ldr x24, [%x[outptrs], #0x60]\n" - "add x24, x24, x10, LSL #2\n" - "st1 { v21.s }[0], [x25]\n" - "ldr x25, [%x[outptrs], #0x68]\n" - "add x25, x25, x10, LSL #2\n" - "st1 { v22.s }[0], [x26]\n" - "ldr x26, [%x[outptrs], #0x70]\n" "add x26, x26, x10, LSL #2\n" - "st1 { v23.s }[0], [x27]\n" - "ldr x27, [%x[outptrs], #0x78]\n" + "ldr x25, [%x[outptrs], #0x10]\n" + "ldr x24, [%x[outptrs], #0x18]\n" + "add x25, x25, x10, LSL #2\n" + "add x24, x24, x10, LSL #2\n" + "ldr x23, [%x[outptrs], #0x20]\n" + "ldr x22, [%x[outptrs], #0x28]\n" + "add x23, x23, x10, LSL #2\n" + "add x22, x22, x10, LSL #2\n" + "ldr x21, [%x[outptrs], #0x30]\n" + "ldr x20, [%x[outptrs], #0x38]\n" + "add x21, x21, x10, LSL #2\n" + "add x20, x20, x10, LSL #2\n" + "st1 { v16.s }[0], [x27]\n" + "ldr x27, [%x[outptrs], #0x40]\n" "add x27, x27, x10, LSL #2\n" - "st1 { v24.s }[0], [x20]\n" - "st1 { v25.s }[0], [x21]\n" - "st1 { v26.s }[0], [x22]\n" - "st1 { v27.s }[0], [x23]\n" - "st1 { v28.s }[0], [x24]\n" - "st1 { v29.s }[0], [x25]\n" - "st1 { v30.s }[0], [x26]\n" - "st1 { v31.s }[0], [x27]\n" + "st1 { v17.s }[0], [x26]\n" + "ldr x26, [%x[outptrs], #0x48]\n" + "add x26, x26, x10, LSL #2\n" + "st1 { v18.s }[0], [x25]\n" + "ldr x25, [%x[outptrs], #0x50]\n" + "add x25, x25, x10, LSL #2\n" + "st1 { v19.s }[0], [x24]\n" + "ldr x24, [%x[outptrs], #0x58]\n" + "add x24, x24, x10, LSL #2\n" + "st1 { v20.s }[0], [x23]\n" + "ldr x23, [%x[outptrs], #0x60]\n" + "add x23, x23, x10, LSL #2\n" + "st1 { v21.s }[0], [x22]\n" + "ldr x22, [%x[outptrs], #0x68]\n" + "add x22, x22, x10, LSL #2\n" + "st1 { v22.s }[0], [x21]\n" + "ldr x21, [%x[outptrs], #0x70]\n" + "add x21, x21, x10, LSL #2\n" + "st1 { v23.s }[0], [x20]\n" + "ldr x20, [%x[outptrs], #0x78]\n" + "add x20, x20, x10, LSL #2\n" + "st1 { v24.s }[0], [x27]\n" + "st1 { v25.s }[0], [x26]\n" + "st1 { v26.s }[0], [x25]\n" + "st1 { v27.s }[0], [x24]\n" + "st1 { v28.s }[0], [x23]\n" + "st1 { v29.s }[0], [x22]\n" + "st1 { v30.s }[0], [x21]\n" + "st1 { v31.s }[0], [x20]\n" "18:" // Output channel oddments: Done: Store: Bit 1: End - "19:" // Done - : [weights] "+&r" (weights) : [bias] "r" (bias), [inptrs] "r" (inptrs), [kernel_points] "r" ((uint64_t) kernel_points), [minmax_vals] "r" (minmax_vals), [n_output_channels] "r" ((uint64_t) n_output_channels), [outptrs] "r" (outptrs) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } } // namespace depthwise } // namespace arm_conv -#endif // defined(__aarch64__) + +#endif // defined(__aarch64__) |