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Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp376
1 files changed, 376 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp
new file mode 100644
index 0000000000..a2f577784f
--- /dev/null
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_generic_output9_mla_depthfirst/generic.cpp
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2021, 2023 Arm Limited.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <cstddef>
+#include <cstdint>
+
+#if defined(__aarch64__)
+
+namespace arm_conv {
+namespace depthwise {
+
+void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl(
+ const float *const *const inptrs,
+ float *const *const outptrs,
+ const void *params,
+ const void *bias,
+ const unsigned int n_points,
+ const unsigned int n_channels,
+ const float activation_min,
+ const float activation_max
+)
+{
+ const float minmax_vals[2] = { activation_min, activation_max };
+
+ __asm__ __volatile__(
+ "ld1r { v2.4s }, [%x[minmax_vals]]\n"
+ "lsr x9, %x[n_channels], #0x2\n"
+ "add x20, %x[minmax_vals], #0x4\n"
+ "ld1r { v1.4s }, [x20]\n"
+ "mov x11, #0x0\n"
+ "cbz x9, 5f\n"
+ "1:" // Channel loop
+ "movi v23.16b, #0x0\n"
+ "cbz %x[bias], 2f\n"
+ "ldr q23, [%x[bias], x11]\n"
+ "2:" // Channel loop: Load bias: Done
+ "ldr q0, [%x[params], #0x0]\n"
+ "mov x26, %x[inptrs]\n"
+ "ldp x21, x20, [x26], #0x10\n"
+ "subs x25, %x[n_points], #0x1\n"
+ "ldr q14, [x21, x11]\n"
+ "ldr q15, [x20, x11]\n"
+ "mov v24.16b, v23.16b\n"
+ "mov v25.16b, v23.16b\n"
+ "ldp x21, x20, [x26], #0x10\n"
+ "ldr q16, [x21, x11]\n"
+ "mov v26.16b, v23.16b\n"
+ "mov v27.16b, v23.16b\n"
+ "ldr q17, [x20, x11]\n"
+ "ldp x21, x20, [x26], #0x10\n"
+ "mov v28.16b, v23.16b\n"
+ "mov v29.16b, v23.16b\n"
+ "ldr q18, [x21, x11]\n"
+ "ldr q19, [x20, x11]\n"
+ "mov v30.16b, v23.16b\n"
+ "mov v31.16b, v23.16b\n"
+ "ldp x21, x20, [x26], #0x10\n"
+ "ldr q20, [x21, x11]\n"
+ "add %x[params], %x[params], #0x10\n"
+ "ldr q21, [x20, x11]\n"
+ "ldr x20, [x26], #0x8\n"
+ "ldr q22, [x20, x11]\n"
+ "ble 4f\n"
+ "3:" // Channel loop: Planar loop
+ "ldp x20, x24, [x26], #0x10\n"
+ "ldp x23, x22, [x26], #0x10\n"
+ "subs x25, x25, #0x1\n"
+ "fmla v23.4s, v14.4s, v0.4s\n"
+ "ldr q14, [x20, x11]\n"
+ "ldp x21, x20, [x26], #0x10\n"
+ "fmla v24.4s, v15.4s, v0.4s\n"
+ "fmla v25.4s, v16.4s, v0.4s\n"
+ "ldr q15, [x24, x11]\n"
+ "ldr q16, [x23, x11]\n"
+ "fmla v26.4s, v17.4s, v0.4s\n"
+ "fmla v27.4s, v18.4s, v0.4s\n"
+ "ldr q17, [x22, x11]\n"
+ "ldr q18, [x21, x11]\n"
+ "fmla v28.4s, v19.4s, v0.4s\n"
+ "fmla v29.4s, v20.4s, v0.4s\n"
+ "ldr q19, [x20, x11]\n"
+ "ldp x21, x20, [x26], #0x10\n"
+ "fmla v30.4s, v21.4s, v0.4s\n"
+ "fmla v31.4s, v22.4s, v0.4s\n"
+ "ldr q0, [%x[params], #0x0]\n"
+ "ldr q20, [x21, x11]\n"
+ "add %x[params], %x[params], #0x10\n"
+ "ldr q21, [x20, x11]\n"
+ "ldr x20, [x26], #0x8\n"
+ "ldr q22, [x20, x11]\n"
+ "bgt 3b\n"
+ "4:" // Channel loop: Planar tail
+ "fmla v23.4s, v14.4s, v0.4s\n"
+ "fmla v24.4s, v15.4s, v0.4s\n"
+ "fmax v23.4s, v23.4s, v2.4s\n"
+ "ldp x28, x27, [%x[outptrs], #0x0]\n"
+ "fmla v25.4s, v16.4s, v0.4s\n"
+ "fmla v26.4s, v17.4s, v0.4s\n"
+ "fmax v24.4s, v24.4s, v2.4s\n"
+ "ldp x26, x25, [%x[outptrs], #0x10]\n"
+ "fmla v27.4s, v18.4s, v0.4s\n"
+ "fmla v28.4s, v19.4s, v0.4s\n"
+ "fmax v25.4s, v25.4s, v2.4s\n"
+ "ldp x24, x23, [%x[outptrs], #0x20]\n"
+ "fmla v29.4s, v20.4s, v0.4s\n"
+ "fmla v30.4s, v21.4s, v0.4s\n"
+ "fmax v26.4s, v26.4s, v2.4s\n"
+ "ldp x22, x21, [%x[outptrs], #0x30]\n"
+ "fmla v31.4s, v22.4s, v0.4s\n"
+ "fmax v27.4s, v27.4s, v2.4s\n"
+ "ldr x20, [%x[outptrs], #0x40]\n"
+ "fmax v28.4s, v28.4s, v2.4s\n"
+ "fmax v29.4s, v29.4s, v2.4s\n"
+ "fmax v30.4s, v30.4s, v2.4s\n"
+ "fmax v31.4s, v31.4s, v2.4s\n"
+ "fmin v23.4s, v23.4s, v1.4s\n"
+ "fmin v24.4s, v24.4s, v1.4s\n"
+ "str q23, [x28, x11]\n"
+ "fmin v25.4s, v25.4s, v1.4s\n"
+ "fmin v26.4s, v26.4s, v1.4s\n"
+ "str q24, [x27, x11]\n"
+ "fmin v27.4s, v27.4s, v1.4s\n"
+ "fmin v28.4s, v28.4s, v1.4s\n"
+ "str q25, [x26, x11]\n"
+ "fmin v29.4s, v29.4s, v1.4s\n"
+ "fmin v30.4s, v30.4s, v1.4s\n"
+ "str q26, [x25, x11]\n"
+ "fmin v31.4s, v31.4s, v1.4s\n"
+ "str q27, [x24, x11]\n"
+ "str q28, [x23, x11]\n"
+ "str q29, [x22, x11]\n"
+ "str q30, [x21, x11]\n"
+ "str q31, [x20, x11]\n"
+ "add x11, x11, #0x10\n"
+ "cmp x11, x9, LSL #4\n"
+ "blt 1b\n"
+ "5:" // Oddments
+ "tst %x[n_channels], #0x3\n"
+ "beq 17f\n"
+ "movi v23.16b, #0x0\n"
+ "cbz %x[bias], 8f\n"
+ "add x20, %x[bias], x11\n"
+ "tbz %x[n_channels], #1, 6f\n"
+ "ld1 { v23.d }[0], [x20], #0x8\n"
+ "tbz %x[n_channels], #0, 7f\n"
+ "ld1 { v23.s }[2], [x20], #0x4\n"
+ "b 7f\n"
+ "6:" // Oddments: Load bias: Bit 1: Unset
+ "ld1 { v23.s }[0], [x20], #0x4\n"
+ "7:" // Oddments: Load bias: Bit 1: End
+ "8:" // Oddments: Load bias: Done
+ "ldr q0, [%x[params], #0x0]\n"
+ "mov x10, %x[inptrs]\n"
+ "ldp x9, x28, [x10], #0x10\n"
+ "mov v24.16b, v23.16b\n"
+ "ldp x27, x26, [x10], #0x10\n"
+ "ldp x25, x24, [x10], #0x10\n"
+ "mov v25.16b, v23.16b\n"
+ "mov v26.16b, v23.16b\n"
+ "ldp x23, x22, [x10], #0x10\n"
+ "ldr x21, [x10], #0x8\n"
+ "mov v27.16b, v23.16b\n"
+ "mov v28.16b, v23.16b\n"
+ "mov v29.16b, v23.16b\n"
+ "mov v30.16b, v23.16b\n"
+ "add x9, x9, x11\n"
+ "add x28, x28, x11\n"
+ "mov v31.16b, v23.16b\n"
+ "add x27, x27, x11\n"
+ "add x26, x26, x11\n"
+ "add x25, x25, x11\n"
+ "add x24, x24, x11\n"
+ "add x23, x23, x11\n"
+ "add x22, x22, x11\n"
+ "add x21, x21, x11\n"
+ "add %x[params], %x[params], #0x10\n"
+ "tbz %x[n_channels], #1, 9f\n"
+ "ldr d14, [x9], #0x8\n"
+ "ldr d15, [x28], #0x8\n"
+ "ldr d16, [x27], #0x8\n"
+ "ldr d17, [x26], #0x8\n"
+ "ldr d18, [x25], #0x8\n"
+ "ldr d19, [x24], #0x8\n"
+ "ldr d20, [x23], #0x8\n"
+ "ldr d21, [x22], #0x8\n"
+ "ldr d22, [x21], #0x8\n"
+ "tbz %x[n_channels], #0, 10f\n"
+ "ld1 { v14.s }[2], [x9], #0x4\n"
+ "ld1 { v15.s }[2], [x28], #0x4\n"
+ "ld1 { v16.s }[2], [x27], #0x4\n"
+ "ld1 { v17.s }[2], [x26], #0x4\n"
+ "ld1 { v18.s }[2], [x25], #0x4\n"
+ "ld1 { v19.s }[2], [x24], #0x4\n"
+ "ld1 { v20.s }[2], [x23], #0x4\n"
+ "ld1 { v21.s }[2], [x22], #0x4\n"
+ "ld1 { v22.s }[2], [x21], #0x4\n"
+ "b 10f\n"
+ "9:" // Oddments: Load: Bit 1: Unset
+ "ldr s14, [x9], #0x4\n"
+ "ldr s15, [x28], #0x4\n"
+ "ldr s16, [x27], #0x4\n"
+ "ldr s17, [x26], #0x4\n"
+ "ldr s18, [x25], #0x4\n"
+ "ldr s19, [x24], #0x4\n"
+ "ldr s20, [x23], #0x4\n"
+ "ldr s21, [x22], #0x4\n"
+ "ldr s22, [x21], #0x4\n"
+ "10:" // Oddments: Load: Bit 1: End
+ "subs x20, %x[n_points], #0x1\n"
+ "ble 14f\n"
+ "11:" // Oddments: Planar loop
+ "ldp x9, x28, [x10], #0x10\n"
+ "ldp x27, x26, [x10], #0x10\n"
+ "fmla v23.4s, v14.4s, v0.4s\n"
+ "fmla v24.4s, v15.4s, v0.4s\n"
+ "ldp x25, x24, [x10], #0x10\n"
+ "ldp x23, x22, [x10], #0x10\n"
+ "fmla v25.4s, v16.4s, v0.4s\n"
+ "fmla v26.4s, v17.4s, v0.4s\n"
+ "ldr x21, [x10], #0x8\n"
+ "fmla v27.4s, v18.4s, v0.4s\n"
+ "fmla v28.4s, v19.4s, v0.4s\n"
+ "add x9, x9, x11\n"
+ "fmla v29.4s, v20.4s, v0.4s\n"
+ "fmla v30.4s, v21.4s, v0.4s\n"
+ "add x28, x28, x11\n"
+ "add x27, x27, x11\n"
+ "fmla v31.4s, v22.4s, v0.4s\n"
+ "ldr q0, [%x[params], #0x0]\n"
+ "add x26, x26, x11\n"
+ "add x25, x25, x11\n"
+ "add x24, x24, x11\n"
+ "add x23, x23, x11\n"
+ "add x22, x22, x11\n"
+ "add x21, x21, x11\n"
+ "add %x[params], %x[params], #0x10\n"
+ "tbz %x[n_channels], #1, 12f\n"
+ "ldr d14, [x9], #0x8\n"
+ "ldr d15, [x28], #0x8\n"
+ "ldr d16, [x27], #0x8\n"
+ "ldr d17, [x26], #0x8\n"
+ "ldr d18, [x25], #0x8\n"
+ "ldr d19, [x24], #0x8\n"
+ "ldr d20, [x23], #0x8\n"
+ "ldr d21, [x22], #0x8\n"
+ "ldr d22, [x21], #0x8\n"
+ "tbz %x[n_channels], #0, 13f\n"
+ "ld1 { v14.s }[2], [x9], #0x4\n"
+ "ld1 { v15.s }[2], [x28], #0x4\n"
+ "ld1 { v16.s }[2], [x27], #0x4\n"
+ "ld1 { v17.s }[2], [x26], #0x4\n"
+ "ld1 { v18.s }[2], [x25], #0x4\n"
+ "ld1 { v19.s }[2], [x24], #0x4\n"
+ "ld1 { v20.s }[2], [x23], #0x4\n"
+ "ld1 { v21.s }[2], [x22], #0x4\n"
+ "ld1 { v22.s }[2], [x21], #0x4\n"
+ "b 13f\n"
+ "12:" // Oddments: Planar loop: Load: Bit 1: Unset
+ "ldr s14, [x9], #0x4\n"
+ "ldr s15, [x28], #0x4\n"
+ "ldr s16, [x27], #0x4\n"
+ "ldr s17, [x26], #0x4\n"
+ "ldr s18, [x25], #0x4\n"
+ "ldr s19, [x24], #0x4\n"
+ "ldr s20, [x23], #0x4\n"
+ "ldr s21, [x22], #0x4\n"
+ "ldr s22, [x21], #0x4\n"
+ "13:" // Oddments: Planar loop: Load: Bit 1: End
+ "subs x20, x20, #0x1\n"
+ "bgt 11b\n"
+ "14:" // Oddments: Planar tail
+ "fmla v23.4s, v14.4s, v0.4s\n"
+ "fmla v24.4s, v15.4s, v0.4s\n"
+ "fmax v23.4s, v23.4s, v2.4s\n"
+ "ldp x28, x27, [%x[outptrs], #0x0]\n"
+ "fmla v25.4s, v16.4s, v0.4s\n"
+ "fmla v26.4s, v17.4s, v0.4s\n"
+ "fmax v24.4s, v24.4s, v2.4s\n"
+ "ldp x26, x25, [%x[outptrs], #0x10]\n"
+ "fmla v27.4s, v18.4s, v0.4s\n"
+ "fmla v28.4s, v19.4s, v0.4s\n"
+ "fmax v25.4s, v25.4s, v2.4s\n"
+ "ldp x24, x23, [%x[outptrs], #0x20]\n"
+ "fmla v29.4s, v20.4s, v0.4s\n"
+ "fmla v30.4s, v21.4s, v0.4s\n"
+ "fmax v26.4s, v26.4s, v2.4s\n"
+ "ldp x22, x21, [%x[outptrs], #0x30]\n"
+ "fmla v31.4s, v22.4s, v0.4s\n"
+ "fmax v27.4s, v27.4s, v2.4s\n"
+ "ldr x20, [%x[outptrs], #0x40]\n"
+ "add x28, x28, x11\n"
+ "fmax v28.4s, v28.4s, v2.4s\n"
+ "fmax v29.4s, v29.4s, v2.4s\n"
+ "add x27, x27, x11\n"
+ "add x26, x26, x11\n"
+ "fmax v30.4s, v30.4s, v2.4s\n"
+ "fmax v31.4s, v31.4s, v2.4s\n"
+ "add x25, x25, x11\n"
+ "add x24, x24, x11\n"
+ "fmin v23.4s, v23.4s, v1.4s\n"
+ "fmin v24.4s, v24.4s, v1.4s\n"
+ "add x23, x23, x11\n"
+ "add x22, x22, x11\n"
+ "fmin v25.4s, v25.4s, v1.4s\n"
+ "fmin v26.4s, v26.4s, v1.4s\n"
+ "add x21, x21, x11\n"
+ "add x20, x20, x11\n"
+ "fmin v27.4s, v27.4s, v1.4s\n"
+ "fmin v28.4s, v28.4s, v1.4s\n"
+ "fmin v29.4s, v29.4s, v1.4s\n"
+ "fmin v30.4s, v30.4s, v1.4s\n"
+ "fmin v31.4s, v31.4s, v1.4s\n"
+ "tbz %x[n_channels], #1, 15f\n"
+ "st1 { v23.d }[0], [x28], #0x8\n"
+ "st1 { v24.d }[0], [x27], #0x8\n"
+ "st1 { v25.d }[0], [x26], #0x8\n"
+ "st1 { v26.d }[0], [x25], #0x8\n"
+ "st1 { v27.d }[0], [x24], #0x8\n"
+ "st1 { v28.d }[0], [x23], #0x8\n"
+ "st1 { v29.d }[0], [x22], #0x8\n"
+ "st1 { v30.d }[0], [x21], #0x8\n"
+ "st1 { v31.d }[0], [x20], #0x8\n"
+ "tbz %x[n_channels], #0, 16f\n"
+ "st1 { v23.s }[2], [x28], #0x4\n"
+ "st1 { v24.s }[2], [x27], #0x4\n"
+ "st1 { v25.s }[2], [x26], #0x4\n"
+ "st1 { v26.s }[2], [x25], #0x4\n"
+ "st1 { v27.s }[2], [x24], #0x4\n"
+ "st1 { v28.s }[2], [x23], #0x4\n"
+ "st1 { v29.s }[2], [x22], #0x4\n"
+ "st1 { v30.s }[2], [x21], #0x4\n"
+ "st1 { v31.s }[2], [x20], #0x4\n"
+ "b 16f\n"
+ "15:" // Oddments: Store: Bit 1: Unset
+ "st1 { v23.s }[0], [x28], #0x4\n"
+ "st1 { v24.s }[0], [x27], #0x4\n"
+ "st1 { v25.s }[0], [x26], #0x4\n"
+ "st1 { v26.s }[0], [x25], #0x4\n"
+ "st1 { v27.s }[0], [x24], #0x4\n"
+ "st1 { v28.s }[0], [x23], #0x4\n"
+ "st1 { v29.s }[0], [x22], #0x4\n"
+ "st1 { v30.s }[0], [x21], #0x4\n"
+ "st1 { v31.s }[0], [x20], #0x4\n"
+ "16:" // Oddments: Store: Bit 1: End
+ "17:" // End
+ : [params] "+&r" (params)
+ : [bias] "r" (bias), [inptrs] "r" (inptrs), [minmax_vals] "r" (minmax_vals), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [outptrs] "r" (outptrs)
+ : "cc", "memory", "v0", "v1", "v2", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ );
+}
+
+} // namespace depthwise
+} // namespace arm_conv
+
+#endif // defined(__aarch64__)
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-03 17:03:27 +0000