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Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp466
1 files changed, 233 insertions, 233 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp
index f65633002e..24fe255dfb 100644
--- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp
@@ -25,7 +25,7 @@
#include <cstddef>
#include <cstdint>
-#if __aarch64__
+#if defined(__aarch64__)
namespace arm_conv {
namespace depthwise {
@@ -88,258 +88,258 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl(
__asm__ __volatile__(
"ldr x21, [%x[params_struct], %[offsetof_args_outptrs]]\n"
- "mov x26, #0x10\n" // cntb _, ALL, #1
- "lsr x25, %x[n_channels], #0x2\n"
- "ldr x24, [%x[params_struct], %[offsetof_args_params]]\n"
+ "mov x25, #0x10\n" // cntb _, ALL, #1
+ "lsr x24, %x[n_channels], #0x2\n"
+ "ldr x23, [%x[params_struct], %[offsetof_args_params]]\n"
"add x20, %x[params_struct], %[offsetof_args_min]\n"
- "ld1r { v19.4s }, [x20]\n"
+ "ld1r { v26.4s }, [x20]\n"
"add x20, %x[params_struct], %[offsetof_args_max]\n"
- "ld1r { v18.4s }, [x20]\n"
+ "ld1r { v27.4s }, [x20]\n"
"add x13, %x[params_struct], %[offsetof_Args_inptrs]\n"
"ldp x12, x11, [x21, #0x0]\n"
"ldp x10, x9, [x21, #0x10]\n"
"mov x28, #0x0\n"
- "sub x23, XZR, x26\n"
- "cbz x25, 3f\n"
- "ldr q17, [x24, #0x0]\n"
- "ldr q0, [x24, #0x10]\n"
- "cmp x26, x25, LSL #4\n"
- "ldr q1, [x24, #0x20]\n"
- "ldr q2, [x24, #0x30]\n"
- "ldr q3, [x24, #0x40]\n"
- "ldr q4, [x24, #0x50]\n"
- "ldr q5, [x24, #0x60]\n"
- "ldr q6, [x24, #0x70]\n"
- "ldr q7, [x24, #0x80]\n"
- "ldr q8, [x24, #0x90]\n"
- "add x24, x24, #0xa0\n"
- "ldp x22, x20, [x13, #0x0]\n"
- "ldr q9, [x22, x28]\n"
+ "sub x22, XZR, x25\n"
+ "cbz x24, 3f\n"
+ "ldr q31, [x23, #0x0]\n"
+ "ldr q0, [x23, #0x10]\n"
+ "cmp x25, x24, LSL #4\n"
+ "ldr q1, [x23, #0x20]\n"
+ "ldr q2, [x23, #0x30]\n"
+ "ldr q3, [x23, #0x40]\n"
+ "ldr q4, [x23, #0x50]\n"
+ "ldr q5, [x23, #0x60]\n"
+ "ldr q6, [x23, #0x70]\n"
+ "ldr q7, [x23, #0x80]\n"
+ "ldr q8, [x23, #0x90]\n"
+ "add x23, x23, #0xa0\n"
+ "ldp x21, x20, [x13, #0x0]\n"
+ "ldr q9, [x21, x28]\n"
"ldr q10, [x20, x28]\n"
"ldp x21, x20, [x13, #0x10]\n"
"ldr q11, [x21, x28]\n"
"ldr q12, [x20, x28]\n"
- "ldp x22, x21, [x13, #0x20]\n"
- "ldr q13, [x22, x28]\n"
- "ldr q14, [x21, x28]\n"
+ "ldp x21, x20, [x13, #0x20]\n"
+ "ldr q13, [x21, x28]\n"
+ "ldr q14, [x20, x28]\n"
"ldp x21, x20, [x13, #0x30]\n"
"ldr q15, [x21, x28]\n"
"ldr q16, [x20, x28]\n"
"bge 2f\n"
"1:" // Channel loop
- "mov v28.16b, v17.16b\n fmla v28.4s, v8.4s, v9.4s\n"
- "mov v29.16b, v17.16b\n fmla v29.4s, v6.4s, v9.4s\n"
- "ldr x22, [x13, #0x40]\n"
+ "mov v24.16b, v31.16b\n fmla v24.4s, v8.4s, v9.4s\n"
+ "mov v23.16b, v31.16b\n fmla v23.4s, v6.4s, v9.4s\n"
+ "ldr x21, [x13, #0x40]\n"
"ldr x20, [x13, #0x48]\n"
- "fmla v28.4s, v0.4s, v10.4s\n"
- "fmla v29.4s, v1.4s, v12.4s\n"
- "ldr q12, [x20, x28]\n"
- "ldr x21, [x13, #0x50]\n"
- "fmla v28.4s, v1.4s, v11.4s\n"
- "ldr q11, [x22, x28]\n"
- "fmla v29.4s, v2.4s, v13.4s\n"
- "ldr q13, [x21, x28]\n"
- "fmla v28.4s, v3.4s, v14.4s\n"
- "fmla v29.4s, v0.4s, v16.4s\n"
+ "fmla v24.4s, v0.4s, v10.4s\n"
+ "fmla v23.4s, v1.4s, v12.4s\n"
+ "ldr q20, [x20, x28]\n"
+ "ldr x20, [x13, #0x50]\n"
+ "fmla v24.4s, v1.4s, v11.4s\n"
+ "ldr q19, [x21, x28]\n"
+ "fmla v23.4s, v2.4s, v13.4s\n"
+ "ldr q18, [x20, x28]\n"
+ "fmla v24.4s, v3.4s, v14.4s\n"
+ "fmla v23.4s, v0.4s, v16.4s\n"
"ldr x20, [x13, #0x58]\n"
- "ldr q14, [x20, x28]\n"
- "fmla v28.4s, v4.4s, v15.4s\n"
- "fmla v29.4s, v4.4s, v11.4s\n"
- "ldr x20, [x13, #0x78]\n"
- "ldr x22, [x13, #0x60]\n"
- "ldr q15, [x22, x28]\n"
- "fmla v28.4s, v2.4s, v16.4s\n"
- "fmla v29.4s, v5.4s, v12.4s\n"
- "ldr x22, [x13, #0x80]\n"
- "ldr q12, [x22, x28]\n"
- "mov v30.16b, v17.16b\n fmla v30.4s, v2.4s, v9.4s\n"
- "mov v31.16b, v17.16b\n fmla v31.4s, v0.4s, v9.4s\n"
- "ldr q17, [x24, #0x0]\n"
- "fmla v28.4s, v5.4s, v13.4s\n"
- "fmla v29.4s, v3.4s, v13.4s\n"
- "ldr q13, [x20, x28]\n"
- "ldr x21, [x13, #0x68]\n"
- "ldr q11, [x21, x28]\n"
- "fmla v30.4s, v3.4s, v14.4s\n"
- "fmla v31.4s, v4.4s, v13.4s\n"
- "ldr x20, [x13, #0x88]\n"
- "ldr q14, [x20, x28]\n"
- "fmla v30.4s, v0.4s, v15.4s\n"
- "ldr q0, [x24, #0x10]\n"
- "fmla v31.4s, v1.4s, v12.4s\n"
- "ldr x21, [x13, #0x70]\n"
+ "ldr q17, [x20, x28]\n"
+ "fmla v24.4s, v4.4s, v15.4s\n"
+ "fmla v23.4s, v4.4s, v19.4s\n"
+ "ldr x21, [x13, #0x78]\n"
+ "ldr x20, [x13, #0x60]\n"
+ "ldr q22, [x20, x28]\n"
+ "fmla v24.4s, v2.4s, v16.4s\n"
+ "fmla v23.4s, v5.4s, v20.4s\n"
+ "ldr x20, [x13, #0x80]\n"
+ "ldr q21, [x20, x28]\n"
+ "mov v20.16b, v31.16b\n fmla v20.4s, v2.4s, v9.4s\n"
+ "mov v19.16b, v31.16b\n fmla v19.4s, v0.4s, v9.4s\n"
+ "ldr q31, [x23, #0x0]\n"
+ "fmla v24.4s, v5.4s, v18.4s\n"
+ "fmla v23.4s, v3.4s, v18.4s\n"
"ldr q16, [x21, x28]\n"
- "fmla v30.4s, v4.4s, v11.4s\n"
- "fmla v31.4s, v5.4s, v14.4s\n"
- "ldr q4, [x24, #0x50]\n"
+ "ldr x20, [x13, #0x68]\n"
+ "ldr q18, [x20, x28]\n"
+ "fmla v20.4s, v3.4s, v17.4s\n"
+ "fmla v19.4s, v4.4s, v16.4s\n"
+ "ldr x20, [x13, #0x88]\n"
+ "ldr q16, [x20, x28]\n"
+ "fmla v20.4s, v0.4s, v22.4s\n"
+ "ldr q0, [x23, #0x10]\n"
+ "fmla v19.4s, v1.4s, v21.4s\n"
+ "ldr x20, [x13, #0x70]\n"
+ "ldr q17, [x20, x28]\n"
+ "fmla v20.4s, v4.4s, v18.4s\n"
+ "fmla v19.4s, v5.4s, v16.4s\n"
+ "ldr q4, [x23, #0x50]\n"
"ldr x20, [x13, #0x98]\n"
- "fmla v28.4s, v6.4s, v15.4s\n"
- "fmla v30.4s, v1.4s, v16.4s\n"
- "ldr q11, [x20, x28]\n"
- "ldr q1, [x24, #0x20]\n"
- "fmla v31.4s, v2.4s, v11.4s\n"
- "fmla v28.4s, v7.4s, v16.4s\n"
- "ldr q2, [x24, #0x30]\n"
- "ldr x21, [x13, #0x90]\n"
- "fmla v29.4s, v7.4s, v12.4s\n"
- "fmla v29.4s, v8.4s, v11.4s\n"
- "ldr q15, [x21, x28]\n"
- "ldr x21, [x13, #0xa8]\n"
- "fmla v30.4s, v6.4s, v15.4s\n"
- "fmax v28.4s, v28.4s, v19.4s\n"
- "ldr q16, [x21, x28]\n"
- "ldr x22, [x13, #0xa0]\n"
- "fmla v31.4s, v3.4s, v16.4s\n"
- "fmax v29.4s, v29.4s, v19.4s\n"
- "ldr q13, [x22, x28]\n"
- "ldr q3, [x24, #0x40]\n"
- "fmla v30.4s, v7.4s, v13.4s\n"
- "fmla v30.4s, v5.4s, v16.4s\n"
- "ldr q5, [x24, #0x60]\n"
- "ldr x21, [x13, #0xb0]\n"
- "add x23, x23, #0x10\n"
- "fmin v28.4s, v28.4s, v18.4s\n"
- "ldr q14, [x21, x28]\n"
+ "fmla v24.4s, v6.4s, v22.4s\n"
+ "fmla v20.4s, v1.4s, v17.4s\n"
+ "ldr q16, [x20, x28]\n"
+ "ldr q1, [x23, #0x20]\n"
+ "fmla v19.4s, v2.4s, v16.4s\n"
+ "fmla v24.4s, v7.4s, v17.4s\n"
+ "ldr q2, [x23, #0x30]\n"
+ "ldr x20, [x13, #0x90]\n"
+ "fmla v23.4s, v7.4s, v21.4s\n"
+ "fmla v23.4s, v8.4s, v16.4s\n"
+ "ldr q16, [x20, x28]\n"
+ "ldr x20, [x13, #0xa8]\n"
+ "fmla v20.4s, v6.4s, v16.4s\n"
+ "fmax v24.4s, v24.4s, v26.4s\n"
+ "ldr q17, [x20, x28]\n"
+ "ldr x20, [x13, #0xa0]\n"
+ "fmla v19.4s, v3.4s, v17.4s\n"
+ "fmax v23.4s, v23.4s, v26.4s\n"
+ "ldr q16, [x20, x28]\n"
+ "ldr q3, [x23, #0x40]\n"
+ "fmla v20.4s, v7.4s, v16.4s\n"
+ "fmla v20.4s, v5.4s, v17.4s\n"
+ "ldr q5, [x23, #0x60]\n"
+ "ldr x20, [x13, #0xb0]\n"
+ "add x22, x22, #0x10\n"
+ "fmin v24.4s, v24.4s, v27.4s\n"
+ "ldr q16, [x20, x28]\n"
"ldr x20, [x13, #0xb8]\n"
- "fmla v31.4s, v7.4s, v14.4s\n"
- "fmin v29.4s, v29.4s, v18.4s\n"
- "ldr q15, [x20, x28]\n"
- "ldr q7, [x24, #0x80]\n"
- "fmla v31.4s, v6.4s, v15.4s\n"
- "fmla v30.4s, v8.4s, v15.4s\n"
- "ldr q6, [x24, #0x70]\n"
- "ldr x22, [x13, #0xc0]\n"
- "fmax v30.4s, v30.4s, v19.4s\n"
- "fmin v30.4s, v30.4s, v18.4s\n"
- "ldr q11, [x22, x28]\n"
- "fmla v31.4s, v8.4s, v11.4s\n"
- "ldr q8, [x24, #0x90]\n"
- "fmax v31.4s, v31.4s, v19.4s\n"
- "ldp x22, x20, [x13, #0x0]\n"
- "ldr q9, [x22, x26]\n"
- "fmin v31.4s, v31.4s, v18.4s\n"
+ "fmla v19.4s, v7.4s, v16.4s\n"
+ "fmin v23.4s, v23.4s, v27.4s\n"
+ "ldr q16, [x20, x28]\n"
+ "ldr q7, [x23, #0x80]\n"
+ "fmla v19.4s, v6.4s, v16.4s\n"
+ "fmla v20.4s, v8.4s, v16.4s\n"
+ "ldr q6, [x23, #0x70]\n"
+ "ldr x20, [x13, #0xc0]\n"
+ "fmax v20.4s, v20.4s, v26.4s\n"
+ "fmin v20.4s, v20.4s, v27.4s\n"
+ "ldr q16, [x20, x28]\n"
+ "fmla v19.4s, v8.4s, v16.4s\n"
+ "ldr q8, [x23, #0x90]\n"
+ "fmax v19.4s, v19.4s, v26.4s\n"
+ "ldp x21, x20, [x13, #0x0]\n"
+ "ldr q9, [x21, x25]\n"
+ "fmin v19.4s, v19.4s, v27.4s\n"
"add x28, x28, #0x10\n"
- "ldr q10, [x20, x26]\n"
+ "ldr q10, [x20, x25]\n"
"ldp x21, x20, [x13, #0x10]\n"
- "str q28, [x12, x23]\n"
- "add x24, x24, #0xa0\n"
- "ldr q11, [x21, x26]\n"
- "ldr q12, [x20, x26]\n"
- "str q29, [x11, x23]\n"
- "ldp x22, x21, [x13, #0x20]\n"
- "ldr q13, [x22, x26]\n"
- "str q30, [x10, x23]\n"
- "ldr q14, [x21, x26]\n"
+ "str q24, [x12, x22]\n"
+ "add x23, x23, #0xa0\n"
+ "ldr q11, [x21, x25]\n"
+ "ldr q12, [x20, x25]\n"
+ "str q23, [x11, x22]\n"
+ "ldp x21, x20, [x13, #0x20]\n"
+ "ldr q13, [x21, x25]\n"
+ "str q20, [x10, x22]\n"
+ "ldr q14, [x20, x25]\n"
"ldp x21, x20, [x13, #0x30]\n"
- "str q31, [x9, x23]\n"
- "ldr q15, [x21, x26]\n"
- "ldr q16, [x20, x26]\n"
- "add x26, x26, #0x10\n"
- "cmp x26, x25, LSL #4\n"
+ "str q19, [x9, x22]\n"
+ "ldr q15, [x21, x25]\n"
+ "ldr q16, [x20, x25]\n"
+ "add x25, x25, #0x10\n"
+ "cmp x25, x24, LSL #4\n"
"blt 1b\n"
"2:" // Channel tail
- "mov v28.16b, v17.16b\n fmla v28.4s, v8.4s, v9.4s\n"
- "mov v29.16b, v17.16b\n fmla v29.4s, v6.4s, v9.4s\n"
- "ldr x22, [x13, #0x40]\n"
+ "mov v25.16b, v31.16b\n fmla v25.4s, v8.4s, v9.4s\n"
+ "mov v24.16b, v31.16b\n fmla v24.4s, v6.4s, v9.4s\n"
+ "ldr x21, [x13, #0x40]\n"
"ldr x20, [x13, #0x48]\n"
- "fmla v28.4s, v0.4s, v10.4s\n"
- "fmla v29.4s, v1.4s, v12.4s\n"
- "ldr q12, [x20, x28]\n"
- "ldr x21, [x13, #0x50]\n"
- "fmla v28.4s, v1.4s, v11.4s\n"
- "ldr q11, [x22, x28]\n"
- "fmla v29.4s, v2.4s, v13.4s\n"
- "ldr q13, [x21, x28]\n"
- "fmla v28.4s, v3.4s, v14.4s\n"
- "fmla v29.4s, v0.4s, v16.4s\n"
+ "fmla v25.4s, v0.4s, v10.4s\n"
+ "fmla v24.4s, v1.4s, v12.4s\n"
+ "ldr q20, [x20, x28]\n"
+ "ldr x20, [x13, #0x50]\n"
+ "fmla v25.4s, v1.4s, v11.4s\n"
+ "ldr q18, [x21, x28]\n"
+ "fmla v24.4s, v2.4s, v13.4s\n"
+ "ldr q19, [x20, x28]\n"
+ "fmla v25.4s, v3.4s, v14.4s\n"
+ "fmla v24.4s, v0.4s, v16.4s\n"
"ldr x20, [x13, #0x58]\n"
- "ldr q14, [x20, x28]\n"
- "fmla v28.4s, v4.4s, v15.4s\n"
- "fmla v29.4s, v4.4s, v11.4s\n"
- "ldr x20, [x13, #0x78]\n"
- "ldr x22, [x13, #0x60]\n"
- "ldr q15, [x22, x28]\n"
- "fmla v28.4s, v2.4s, v16.4s\n"
- "fmla v29.4s, v5.4s, v12.4s\n"
- "ldr x22, [x13, #0x80]\n"
- "ldr q12, [x22, x28]\n"
- "mov v30.16b, v17.16b\n fmla v30.4s, v2.4s, v9.4s\n"
- "mov v31.16b, v17.16b\n fmla v31.4s, v0.4s, v9.4s\n"
- "ldr x21, [x13, #0x68]\n"
- "ldr q11, [x21, x28]\n"
- "fmla v28.4s, v5.4s, v13.4s\n"
- "fmla v29.4s, v3.4s, v13.4s\n"
- "ldr q13, [x20, x28]\n"
- "fmla v30.4s, v3.4s, v14.4s\n"
- "fmla v31.4s, v4.4s, v13.4s\n"
- "ldr x20, [x13, #0x88]\n"
- "ldr q14, [x20, x28]\n"
- "fmla v30.4s, v0.4s, v15.4s\n"
- "fmla v31.4s, v1.4s, v12.4s\n"
- "ldr x21, [x13, #0x70]\n"
+ "ldr q17, [x20, x28]\n"
+ "fmla v25.4s, v4.4s, v15.4s\n"
+ "fmla v24.4s, v4.4s, v18.4s\n"
+ "ldr x21, [x13, #0x78]\n"
+ "ldr x20, [x13, #0x60]\n"
+ "ldr q23, [x20, x28]\n"
+ "fmla v25.4s, v2.4s, v16.4s\n"
+ "fmla v24.4s, v5.4s, v20.4s\n"
+ "ldr x20, [x13, #0x80]\n"
+ "ldr q22, [x20, x28]\n"
+ "mov v21.16b, v31.16b\n fmla v21.4s, v2.4s, v9.4s\n"
+ "mov v20.16b, v31.16b\n fmla v20.4s, v0.4s, v9.4s\n"
+ "ldr x20, [x13, #0x68]\n"
+ "ldr q18, [x20, x28]\n"
+ "fmla v25.4s, v5.4s, v19.4s\n"
+ "fmla v24.4s, v3.4s, v19.4s\n"
"ldr q16, [x21, x28]\n"
+ "fmla v21.4s, v3.4s, v17.4s\n"
+ "fmla v20.4s, v4.4s, v16.4s\n"
+ "ldr x20, [x13, #0x88]\n"
+ "ldr q16, [x20, x28]\n"
+ "fmla v21.4s, v0.4s, v23.4s\n"
+ "fmla v20.4s, v1.4s, v22.4s\n"
+ "ldr x20, [x13, #0x70]\n"
+ "ldr q17, [x20, x28]\n"
"ldr x20, [x13, #0x98]\n"
- "fmla v30.4s, v4.4s, v11.4s\n"
- "ldr q11, [x20, x28]\n"
- "fmla v31.4s, v5.4s, v14.4s\n"
- "fmla v28.4s, v6.4s, v15.4s\n"
- "ldr x21, [x13, #0x90]\n"
- "ldr q15, [x21, x28]\n"
- "fmla v30.4s, v1.4s, v16.4s\n"
- "ldr x21, [x13, #0xa8]\n"
- "fmla v31.4s, v2.4s, v11.4s\n"
- "fmla v28.4s, v7.4s, v16.4s\n"
- "ldr q16, [x21, x28]\n"
- "ldr x22, [x13, #0xa0]\n"
- "ldr q13, [x22, x28]\n"
- "fmla v30.4s, v6.4s, v15.4s\n"
- "fmla v31.4s, v3.4s, v16.4s\n"
- "ldr x21, [x13, #0xb0]\n"
- "ldr q14, [x21, x28]\n"
- "fmla v30.4s, v7.4s, v13.4s\n"
- "fmla v31.4s, v7.4s, v14.4s\n"
+ "fmla v21.4s, v4.4s, v18.4s\n"
+ "ldr q19, [x20, x28]\n"
+ "fmla v20.4s, v5.4s, v16.4s\n"
+ "fmla v25.4s, v6.4s, v23.4s\n"
+ "ldr x20, [x13, #0x90]\n"
+ "ldr q16, [x20, x28]\n"
+ "fmla v21.4s, v1.4s, v17.4s\n"
+ "ldr x20, [x13, #0xa8]\n"
+ "fmla v20.4s, v2.4s, v19.4s\n"
+ "fmla v25.4s, v7.4s, v17.4s\n"
+ "ldr q18, [x20, x28]\n"
+ "ldr x20, [x13, #0xa0]\n"
+ "ldr q17, [x20, x28]\n"
+ "fmla v21.4s, v6.4s, v16.4s\n"
+ "fmla v20.4s, v3.4s, v18.4s\n"
+ "ldr x20, [x13, #0xb0]\n"
+ "ldr q16, [x20, x28]\n"
+ "fmla v21.4s, v7.4s, v17.4s\n"
+ "fmla v20.4s, v7.4s, v16.4s\n"
"ldr x20, [x13, #0xb8]\n"
- "ldr q15, [x20, x28]\n"
- "fmla v29.4s, v7.4s, v12.4s\n"
- "fmla v30.4s, v5.4s, v16.4s\n"
- "ldr x22, [x13, #0xc0]\n"
- "fmla v31.4s, v6.4s, v15.4s\n"
- "fmla v29.4s, v8.4s, v11.4s\n"
- "ldr q11, [x22, x28]\n"
- "fmla v30.4s, v8.4s, v15.4s\n"
- "fmla v31.4s, v8.4s, v11.4s\n"
- "fmax v28.4s, v28.4s, v19.4s\n"
- "add x23, x23, #0x10\n"
- "fmax v29.4s, v29.4s, v19.4s\n"
- "fmax v30.4s, v30.4s, v19.4s\n"
+ "ldr q17, [x20, x28]\n"
+ "fmla v24.4s, v7.4s, v22.4s\n"
+ "fmla v21.4s, v5.4s, v18.4s\n"
+ "ldr x20, [x13, #0xc0]\n"
+ "fmla v20.4s, v6.4s, v17.4s\n"
+ "fmla v24.4s, v8.4s, v19.4s\n"
+ "ldr q16, [x20, x28]\n"
+ "fmla v21.4s, v8.4s, v17.4s\n"
+ "fmla v20.4s, v8.4s, v16.4s\n"
+ "fmax v25.4s, v25.4s, v26.4s\n"
+ "add x22, x22, #0x10\n"
+ "fmax v24.4s, v24.4s, v26.4s\n"
+ "fmax v21.4s, v21.4s, v26.4s\n"
"add x28, x28, #0x10\n"
- "fmax v31.4s, v31.4s, v19.4s\n"
- "fmin v28.4s, v28.4s, v18.4s\n"
- "str q28, [x12, x23]\n"
- "fmin v29.4s, v29.4s, v18.4s\n"
- "fmin v30.4s, v30.4s, v18.4s\n"
- "str q29, [x11, x23]\n"
- "fmin v31.4s, v31.4s, v18.4s\n"
- "str q30, [x10, x23]\n"
- "str q31, [x9, x23]\n"
+ "fmax v20.4s, v20.4s, v26.4s\n"
+ "fmin v25.4s, v25.4s, v27.4s\n"
+ "str q25, [x12, x22]\n"
+ "fmin v24.4s, v24.4s, v27.4s\n"
+ "fmin v21.4s, v21.4s, v27.4s\n"
+ "str q24, [x11, x22]\n"
+ "fmin v20.4s, v20.4s, v27.4s\n"
+ "str q21, [x10, x22]\n"
+ "str q20, [x9, x22]\n"
"3:" // Oddments
"tst %x[n_channels], #0x3\n"
"beq 42f\n"
- "ldr q17, [x24, #0x0]\n"
- "ldr q0, [x24, #0x10]\n"
- "mov x23, x28\n"
- "add x12, x12, x23\n"
- "ldr q1, [x24, #0x20]\n"
- "ldr q2, [x24, #0x30]\n"
- "add x11, x11, x23\n"
- "add x10, x10, x23\n"
- "ldr q3, [x24, #0x40]\n"
- "ldr q4, [x24, #0x50]\n"
- "add x9, x9, x23\n"
- "ldr q5, [x24, #0x60]\n"
- "ldr q6, [x24, #0x70]\n"
- "ldr q7, [x24, #0x80]\n"
- "ldr q8, [x24, #0x90]\n"
+ "ldr q31, [x23, #0x0]\n"
+ "ldr q0, [x23, #0x10]\n"
+ "mov x20, x28\n"
+ "add x12, x12, x20\n"
+ "ldr q1, [x23, #0x20]\n"
+ "ldr q2, [x23, #0x30]\n"
+ "add x11, x11, x20\n"
+ "add x10, x10, x20\n"
+ "ldr q3, [x23, #0x40]\n"
+ "ldr q4, [x23, #0x50]\n"
+ "add x9, x9, x20\n"
+ "ldr q5, [x23, #0x60]\n"
+ "ldr q6, [x23, #0x70]\n"
+ "ldr q7, [x23, #0x80]\n"
+ "ldr q8, [x23, #0x90]\n"
"ldr x27, [x13, #0x0]\n"
"ldr x26, [x13, #0x8]\n"
"add x27, x27, x28\n"
@@ -385,18 +385,18 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl(
"ld1 { v15.s }[0], [x21], #0x4\n"
"ld1 { v16.s }[0], [x20], #0x4\n"
"5:" // Oddments: Load inputs (2, 2), (0, 0), (0, 1), (0, 3), (0, 4), (1, 0), (1, 1), (0, 2): Bit 1: End
- "mov v28.16b, v17.16b\n fmla v28.4s, v8.4s, v9.4s\n"
+ "mov v28.16b, v31.16b\n fmla v28.4s, v8.4s, v9.4s\n"
"fmla v28.4s, v0.4s, v10.4s\n"
"ldr x20, [x13, #0x40]\n"
"add x20, x20, x28\n"
- "mov v29.16b, v17.16b\n fmla v29.4s, v6.4s, v9.4s\n"
+ "mov v29.16b, v31.16b\n fmla v29.4s, v6.4s, v9.4s\n"
"fmla v28.4s, v1.4s, v11.4s\n"
"fmla v29.4s, v1.4s, v12.4s\n"
"fmla v28.4s, v3.4s, v14.4s\n"
"fmla v29.4s, v2.4s, v13.4s\n"
"fmla v28.4s, v4.4s, v15.4s\n"
- "mov v30.16b, v17.16b\n fmla v30.4s, v2.4s, v9.4s\n"
- "mov v31.16b, v17.16b\n fmla v31.4s, v0.4s, v9.4s\n"
+ "mov v30.16b, v31.16b\n fmla v30.4s, v2.4s, v9.4s\n"
+ "fmla v31.4s, v0.4s, v9.4s\n"
"fmla v28.4s, v2.4s, v16.4s\n"
"fmla v29.4s, v0.4s, v16.4s\n"
"tbz %x[n_channels], #1, 6f\n"
@@ -591,14 +591,14 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl(
"ld1 { v11.s }[0], [x20], #0x4\n"
"39:" // Oddments: Load input (4, 4): Bit 1: End
"fmla v31.4s, v8.4s, v11.4s\n"
- "fmax v28.4s, v28.4s, v19.4s\n"
- "fmax v29.4s, v29.4s, v19.4s\n"
- "fmax v30.4s, v30.4s, v19.4s\n"
- "fmax v31.4s, v31.4s, v19.4s\n"
- "fmin v28.4s, v28.4s, v18.4s\n"
- "fmin v29.4s, v29.4s, v18.4s\n"
- "fmin v30.4s, v30.4s, v18.4s\n"
- "fmin v31.4s, v31.4s, v18.4s\n"
+ "fmax v28.4s, v28.4s, v26.4s\n"
+ "fmax v29.4s, v29.4s, v26.4s\n"
+ "fmax v30.4s, v30.4s, v26.4s\n"
+ "fmax v31.4s, v31.4s, v26.4s\n"
+ "fmin v28.4s, v28.4s, v27.4s\n"
+ "fmin v29.4s, v29.4s, v27.4s\n"
+ "fmin v30.4s, v30.4s, v27.4s\n"
+ "fmin v31.4s, v31.4s, v27.4s\n"
"tbz %x[n_channels], #1, 40f\n"
"st1 { v28.d }[0], [x12], #0x8\n"
"st1 { v29.d }[0], [x11], #0x8\n"
@@ -619,11 +619,11 @@ void a64_fp32_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl(
"42:" // End
:
: [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (&params_struct)
- : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+ : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
);
}
} // namespace depthwise
} // namespace arm_conv
-#endif // __aarch64__
+#endif // defined(__aarch64__)
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-10 18:21:39 +0000