diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst')
2 files changed, 563 insertions, 561 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp index f4027df375..a85e44360e 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2023 Arm Limited. + * Copyright (c) 2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -87,198 +87,198 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( ); __asm__ __volatile__( - "mov x23, #0x0\n" "mov x22, #0x0\n" + "mov x21, #0x0\n" "1:" // Tile loop - "str x23, [%x[params_struct], %[offsetof_args_tile_i]]\n" - "mov x27, #0x2\n" + "str x22, [%x[params_struct], %[offsetof_args_tile_i]]\n" "mov x26, #0x2\n" - "str x22, [%x[params_struct], %[offsetof_args_tile_j]]\n" - "ldr x25, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" - "ldr x24, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" - "mul x21, x23, x25\n" // offset = tile_i * ld_input_row - "ldr x15, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" - "ldr x14, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" - "mul x20, x23, x24\n" // offset = tile_i * ld_output_row - "mov x23, #0x10\n" // cntb _, ALL, #1 - "madd x21, x22, x15, x21\n" // offset += tile_j * ld_input_col - "ldr x13, [%x[params_struct], %[offsetof_args_inptr]]\n" - "lsl x15, x15, #0x1\n" - "ldr x12, [%x[params_struct], %[offsetof_args_outptr]]\n" - "madd x20, x22, x14, x20\n" // offset += tile_j * ld_output_col - "lsr x22, %x[n_channels], #0x3\n" - "add x11, x15, x15\n" - "ldr x10, [%x[params_struct], %[offsetof_args_params]]\n" - "mul x21, x21, x27\n" // offset *= kernel_stride * output_size - "add x13, x13, x21, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) - "add x9, x13, x25, LSL #1\n" - "mul x20, x20, x26\n" // offset *= output_tile_size - "add x28, x9, x25, LSL #1\n" - "add x12, x12, x20, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) + "mov x25, #0x2\n" + "str x21, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x24, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" + "ldr x23, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" + "mul x20, x22, x24\n" // offset = tile_i * ld_input_row + "ldr x14, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" + "ldr x13, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" + "mul x19, x22, x23\n" // offset = tile_i * ld_output_row + "mov x22, #0x10\n" // cntb _, ALL, #1 + "madd x20, x21, x14, x20\n" // offset += tile_j * ld_input_col + "ldr x12, [%x[params_struct], %[offsetof_args_inptr]]\n" + "lsl x14, x14, #0x1\n" + "ldr x11, [%x[params_struct], %[offsetof_args_outptr]]\n" + "madd x19, x21, x13, x19\n" // offset += tile_j * ld_output_col + "lsr x21, %x[n_channels], #0x3\n" + "add x10, x14, x14\n" + "ldr x9, [%x[params_struct], %[offsetof_args_params]]\n" + "mul x20, x20, x26\n" // offset *= kernel_stride * output_size + "add x12, x12, x20, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) + "add x28, x12, x24, LSL #1\n" + "mul x19, x19, x25\n" // offset *= output_tile_size + "add x27, x28, x24, LSL #1\n" + "add x11, x11, x19, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) "add x20, %x[params_struct], %[offsetof_args_min]\n" + "add x19, %x[params_struct], %[offsetof_args_max]\n" "ld1r { v18.8h }, [x20]\n" - "add x20, %x[params_struct], %[offsetof_args_max]\n" - "ld1r { v17.8h }, [x20]\n" - "add x27, x28, x25, LSL #1\n" - "add x26, x11, x15\n" - "add x25, x12, x24, LSL #1\n" - "lsl x14, x14, #0x1\n" - "mov x21, #0x0\n" - "sub x20, XZR, x23\n" - "cbz x22, 4f\n" - "ldr q16, [x10, #0x0]\n" - "ldr q0, [x10, #0x10]\n" - "cmp x23, x22, LSL #4\n" - "ldr q1, [x10, #0x20]\n" - "ldr q2, [x10, #0x30]\n" - "ldr q3, [x10, #0x40]\n" - "ldr q4, [x10, #0x50]\n" - "ldr q5, [x10, #0x60]\n" - "ldr q6, [x10, #0x70]\n" - "ldr q7, [x10, #0x80]\n" - "ldr q8, [x10, #0x90]\n" - "add x10, x10, #0xa0\n" - "ldr q9, [x9, x15]\n" - "ld1 { v10.8h }, [x13]\n" - "ldr q11, [x13, x26]\n" - "ldr q12, [x9, x11]\n" - "ldr q13, [x28, x15]\n" + "ld1r { v17.8h }, [x19]\n" + "add x26, x27, x24, LSL #1\n" + "add x25, x10, x14\n" + "add x24, x11, x23, LSL #1\n" + "lsl x13, x13, #0x1\n" + "mov x20, #0x0\n" + "sub x19, XZR, x22\n" + "cbz x21, 4f\n" + "ldr q16, [x9, #0x0]\n" + "cmp x22, x21, LSL #4\n" + "ldr q0, [x9, #0x10]\n" + "ldr q1, [x9, #0x20]\n" + "ldr q2, [x9, #0x30]\n" + "ldr q3, [x9, #0x40]\n" + "ldr q4, [x9, #0x50]\n" + "ldr q5, [x9, #0x60]\n" + "ldr q6, [x9, #0x70]\n" + "ldr q7, [x9, #0x80]\n" + "ldr q8, [x9, #0x90]\n" + "ldr q9, [x28, x14]\n" + "add x9, x9, #0xa0\n" + "ld1 { v10.8h }, [x12]\n" + "ldr q11, [x12, x25]\n" + "ldr q12, [x28, x10]\n" + "ldr q13, [x27, x14]\n" "bge 3f\n" "2:" // Tile loop: Channel loop "mov v28.16b, v16.16b\n fmla v28.8h, v4.8h, v9.8h\n" "mov v29.16b, v16.16b\n fmla v29.8h, v3.8h, v9.8h\n" - "add x23, x23, #0x10\n" - "cmp x23, x22, LSL #4\n" + "add x22, x22, #0x10\n" + "cmp x22, x21, LSL #4\n" "mov v30.16b, v16.16b\n fmla v30.8h, v1.8h, v9.8h\n" "mov v31.16b, v16.16b\n fmla v31.8h, v0.8h, v9.8h\n" - "ld1 { v9.8h }, [x27]\n" - "ldr q16, [x10, #0x0]\n" + "ld1 { v9.8h }, [x26]\n" + "add x19, x19, #0x10\n" "fmla v28.8h, v0.8h, v10.8h\n" - "ldr q10, [x28, x11]\n" "fmla v29.8h, v2.8h, v11.8h\n" - "ldr q11, [x27, x26]\n" + "ldr q11, [x26, x25]\n" + "ldr q10, [x27, x10]\n" "fmla v30.8h, v2.8h, v12.8h\n" "fmla v31.8h, v1.8h, v12.8h\n" "add x20, x20, #0x10\n" - "add x21, x21, #0x10\n" + "ldr q16, [x9, #0x0]\n" "fmla v28.8h, v5.8h, v12.8h\n" "fmla v29.8h, v4.8h, v12.8h\n" - "ldr q12, [x13, x15]\n" + "ldr q12, [x12, x14]\n" "fmla v30.8h, v6.8h, v9.8h\n" - "ldr q9, [x13, x11]\n" "fmla v31.8h, v3.8h, v13.8h\n" - "add x13, x13, #0x10\n" + "ldr q9, [x12, x10]\n" + "add x12, x12, #0x10\n" "fmla v28.8h, v7.8h, v13.8h\n" "fmla v29.8h, v6.8h, v13.8h\n" "fmla v30.8h, v4.8h, v13.8h\n" "fmla v31.8h, v8.8h, v11.8h\n" - "ld1 { v11.8h }, [x9]\n" + "ld1 { v11.8h }, [x28]\n" "fmla v28.8h, v1.8h, v12.8h\n" "fmla v29.8h, v0.8h, v12.8h\n" - "ldr q12, [x9, x26]\n" - "add x9, x9, #0x10\n" + "ldr q12, [x28, x25]\n" + "add x28, x28, #0x10\n" "fmla v30.8h, v5.8h, v10.8h\n" "fmla v31.8h, v4.8h, v10.8h\n" - "ldr q4, [x10, #0x50]\n" + "ldr q4, [x9, #0x50]\n" "fmla v28.8h, v2.8h, v9.8h\n" "fmla v29.8h, v1.8h, v9.8h\n" - "ld1 { v9.8h }, [x28]\n" - "ldr q1, [x10, #0x20]\n" + "ld1 { v9.8h }, [x27]\n" + "ldr q1, [x9, #0x20]\n" "fmla v30.8h, v0.8h, v11.8h\n" - "ldr q0, [x10, #0x10]\n" "fmla v31.8h, v2.8h, v12.8h\n" - "ldr q2, [x10, #0x30]\n" + "ldr q0, [x9, #0x10]\n" + "ldr q2, [x9, #0x30]\n" "fmla v28.8h, v8.8h, v10.8h\n" "fmla v29.8h, v7.8h, v10.8h\n" - "ldr q10, [x28, x26]\n" - "add x28, x28, #0x10\n" - "ldr q13, [x28, x15]\n" + "ldr q10, [x27, x25]\n" + "add x27, x27, #0x10\n" "fmla v30.8h, v3.8h, v9.8h\n" "fmla v31.8h, v5.8h, v10.8h\n" + "ldr q13, [x27, x14]\n" "fmla v28.8h, v3.8h, v11.8h\n" - "ldr q11, [x27, x15]\n" - "ldr q3, [x10, #0x40]\n" + "ldr q11, [x26, x14]\n" "fmla v29.8h, v5.8h, v12.8h\n" - "ldr q12, [x27, x11]\n" - "ldr q5, [x10, #0x60]\n" + "ldr q12, [x26, x10]\n" "fmla v30.8h, v7.8h, v11.8h\n" "fmla v31.8h, v6.8h, v11.8h\n" - "ldr q11, [x13, x26]\n" + "add x26, x26, #0x10\n" + "ldr q11, [x12, x25]\n" "fmla v28.8h, v6.8h, v9.8h\n" - "ldr q9, [x9, x15]\n" "fmla v29.8h, v8.8h, v10.8h\n" - "ld1 { v10.8h }, [x13]\n" - "ldr q6, [x10, #0x70]\n" + "fmax v28.8h, v28.8h, v18.8h\n" + "ldr q9, [x28, x14]\n" "fmla v30.8h, v8.8h, v12.8h\n" "fmla v31.8h, v7.8h, v12.8h\n" - "ldr q12, [x9, x11]\n" - "ldr q7, [x10, #0x80]\n" - "fmax v28.8h, v28.8h, v18.8h\n" "fmax v29.8h, v29.8h, v18.8h\n" - "ldr q8, [x10, #0x90]\n" + "ld1 { v10.8h }, [x12]\n" "fmax v30.8h, v30.8h, v18.8h\n" "fmax v31.8h, v31.8h, v18.8h\n" - "add x27, x27, #0x10\n" + "ldr q12, [x28, x10]\n" + "ldr q3, [x9, #0x40]\n" "fmin v28.8h, v28.8h, v17.8h\n" "fmin v29.8h, v29.8h, v17.8h\n" - "st1 { v28.8h }, [x12]\n" - "add x10, x10, #0xa0\n" + "st1 { v28.8h }, [x11]\n" + "ldr q5, [x9, #0x60]\n" "fmin v30.8h, v30.8h, v17.8h\n" "fmin v31.8h, v31.8h, v17.8h\n" - "str q29, [x12, x14]\n" - "add x12, x12, #0x10\n" - "st1 { v30.8h }, [x25]\n" - "str q31, [x25, x14]\n" - "add x25, x25, #0x10\n" + "str q29, [x11, x13]\n" + "add x11, x11, #0x10\n" + "st1 { v30.8h }, [x24]\n" + "ldr q6, [x9, #0x70]\n" + "ldr q7, [x9, #0x80]\n" + "str q31, [x24, x13]\n" + "add x24, x24, #0x10\n" + "ldr q8, [x9, #0x90]\n" + "add x9, x9, #0xa0\n" "blt 2b\n" "3:" // Tile loop: Channel tail "mov v28.16b, v16.16b\n fmla v28.8h, v4.8h, v9.8h\n" "mov v29.16b, v16.16b\n fmla v29.8h, v3.8h, v9.8h\n" "mov v30.16b, v16.16b\n fmla v30.8h, v1.8h, v9.8h\n" "mov v31.16b, v16.16b\n fmla v31.8h, v0.8h, v9.8h\n" - "ld1 { v9.8h }, [x27]\n" + "ld1 { v9.8h }, [x26]\n" "fmla v28.8h, v0.8h, v10.8h\n" - "ldr q10, [x28, x11]\n" "fmla v29.8h, v2.8h, v11.8h\n" - "ldr q11, [x27, x26]\n" + "ldr q11, [x26, x25]\n" + "ldr q10, [x27, x10]\n" "fmla v30.8h, v2.8h, v12.8h\n" "fmla v31.8h, v1.8h, v12.8h\n" "fmla v28.8h, v5.8h, v12.8h\n" "fmla v29.8h, v4.8h, v12.8h\n" - "ldr q12, [x13, x15]\n" + "ldr q12, [x12, x14]\n" "fmla v30.8h, v6.8h, v9.8h\n" - "ldr q9, [x13, x11]\n" "fmla v31.8h, v3.8h, v13.8h\n" - "add x13, x13, #0x10\n" + "ldr q9, [x12, x10]\n" + "add x12, x12, #0x10\n" "fmla v28.8h, v7.8h, v13.8h\n" "fmla v29.8h, v6.8h, v13.8h\n" "fmla v30.8h, v4.8h, v13.8h\n" "fmla v31.8h, v8.8h, v11.8h\n" - "ld1 { v11.8h }, [x9]\n" + "ld1 { v11.8h }, [x28]\n" "fmla v28.8h, v1.8h, v12.8h\n" "fmla v29.8h, v0.8h, v12.8h\n" - "ldr q12, [x9, x26]\n" - "add x9, x9, #0x10\n" + "ldr q12, [x28, x25]\n" + "add x28, x28, #0x10\n" "fmla v30.8h, v5.8h, v10.8h\n" "fmla v31.8h, v4.8h, v10.8h\n" "fmla v28.8h, v2.8h, v9.8h\n" "fmla v29.8h, v1.8h, v9.8h\n" - "ld1 { v9.8h }, [x28]\n" + "ld1 { v9.8h }, [x27]\n" "fmla v30.8h, v0.8h, v11.8h\n" "fmla v31.8h, v2.8h, v12.8h\n" "fmla v28.8h, v8.8h, v10.8h\n" "fmla v29.8h, v7.8h, v10.8h\n" - "ldr q10, [x28, x26]\n" - "add x28, x28, #0x10\n" + "ldr q10, [x27, x25]\n" + "add x27, x27, #0x10\n" "fmla v30.8h, v3.8h, v9.8h\n" "fmla v31.8h, v5.8h, v10.8h\n" "fmla v28.8h, v3.8h, v11.8h\n" - "ldr q11, [x27, x15]\n" + "ldr q11, [x26, x14]\n" "fmla v29.8h, v5.8h, v12.8h\n" - "ldr q12, [x27, x11]\n" + "ldr q12, [x26, x10]\n" "fmla v30.8h, v7.8h, v11.8h\n" "fmla v31.8h, v6.8h, v11.8h\n" - "add x27, x27, #0x10\n" + "add x26, x26, #0x10\n" "fmla v28.8h, v6.8h, v9.8h\n" "fmla v29.8h, v8.8h, v10.8h\n" "fmax v28.8h, v28.8h, v18.8h\n" @@ -289,83 +289,83 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( "fmax v31.8h, v31.8h, v18.8h\n" "fmin v28.8h, v28.8h, v17.8h\n" "fmin v29.8h, v29.8h, v17.8h\n" - "st1 { v28.8h }, [x12]\n" + "st1 { v28.8h }, [x11]\n" "fmin v30.8h, v30.8h, v17.8h\n" "fmin v31.8h, v31.8h, v17.8h\n" - "str q29, [x12, x14]\n" - "add x12, x12, #0x10\n" - "st1 { v30.8h }, [x25]\n" - "str q31, [x25, x14]\n" - "add x25, x25, #0x10\n" + "str q29, [x11, x13]\n" + "add x11, x11, #0x10\n" + "st1 { v30.8h }, [x24]\n" + "str q31, [x24, x13]\n" + "add x24, x24, #0x10\n" "4:" // Tile loop: Oddments "tst %x[n_channels], #0x7\n" "beq 57f\n" - "ldr q16, [x10, #0x0]\n" - "ldr q0, [x10, #0x10]\n" - "add x24, x9, x15\n" - "add x23, x13, XZR\n" - "ldr q1, [x10, #0x20]\n" - "ldr q2, [x10, #0x30]\n" - "add x22, x13, x26\n" - "add x21, x9, x11\n" - "ldr q3, [x10, #0x40]\n" - "ldr q4, [x10, #0x50]\n" - "add x20, x28, x15\n" - "ldr q5, [x10, #0x60]\n" - "ldr q6, [x10, #0x70]\n" - "ldr q7, [x10, #0x80]\n" - "ldr q8, [x10, #0x90]\n" + "ldr q16, [x9, #0x0]\n" + "ldr q0, [x9, #0x10]\n" + "ldr q1, [x9, #0x20]\n" + "ldr q2, [x9, #0x30]\n" + "add x23, x28, x14\n" + "add x22, x12, XZR\n" + "ldr q3, [x9, #0x40]\n" + "ldr q4, [x9, #0x50]\n" + "add x21, x12, x25\n" + "add x20, x28, x10\n" + "ldr q5, [x9, #0x60]\n" + "ldr q6, [x9, #0x70]\n" + "add x19, x27, x14\n" + "ldr q7, [x9, #0x80]\n" + "ldr q8, [x9, #0x90]\n" "tbz %x[n_channels], #2, 6f\n" - "ldr d9, [x24], #0x8\n" - "ldr d10, [x23], #0x8\n" - "ldr d11, [x22], #0x8\n" - "ldr d12, [x21], #0x8\n" - "ldr d13, [x20], #0x8\n" + "ldr d9, [x23], #0x8\n" + "ldr d10, [x22], #0x8\n" + "ldr d11, [x21], #0x8\n" + "ldr d12, [x20], #0x8\n" + "ldr d13, [x19], #0x8\n" "tbz %x[n_channels], #1, 5f\n" - "ld1 { v9.s }[2], [x24], #0x4\n" - "ld1 { v10.s }[2], [x23], #0x4\n" - "ld1 { v11.s }[2], [x22], #0x4\n" - "ld1 { v12.s }[2], [x21], #0x4\n" - "ld1 { v13.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x23], #0x4\n" + "ld1 { v10.s }[2], [x22], #0x4\n" + "ld1 { v11.s }[2], [x21], #0x4\n" + "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v13.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 8f\n" - "ld1 { v9.h }[6], [x24]\n" - "ld1 { v10.h }[6], [x23]\n" - "ld1 { v11.h }[6], [x22]\n" - "ld1 { v12.h }[6], [x21]\n" - "ld1 { v13.h }[6], [x20]\n" + "ld1 { v9.h }[6], [x23]\n" + "ld1 { v10.h }[6], [x22]\n" + "ld1 { v11.h }[6], [x21]\n" + "ld1 { v12.h }[6], [x20]\n" + "ld1 { v13.h }[6], [x19]\n" "b 8f\n" "5:" // Tile loop: Oddments: Load inputs: (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 8f\n" - "ld1 { v9.h }[4], [x24]\n" - "ld1 { v10.h }[4], [x23]\n" - "ld1 { v11.h }[4], [x22]\n" - "ld1 { v12.h }[4], [x21]\n" - "ld1 { v13.h }[4], [x20]\n" + "ld1 { v9.h }[4], [x23]\n" + "ld1 { v10.h }[4], [x22]\n" + "ld1 { v11.h }[4], [x21]\n" + "ld1 { v12.h }[4], [x20]\n" + "ld1 { v13.h }[4], [x19]\n" "b 8f\n" "6:" // Tile loop: Oddments: Load inputs: (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: Unset "tbz %x[n_channels], #1, 7f\n" - "ldr s9, [x24], #0x4\n" - "ldr s10, [x23], #0x4\n" - "ldr s11, [x22], #0x4\n" - "ldr s12, [x21], #0x4\n" - "ldr s13, [x20], #0x4\n" + "ldr s9, [x23], #0x4\n" + "ldr s10, [x22], #0x4\n" + "ldr s11, [x21], #0x4\n" + "ldr s12, [x20], #0x4\n" + "ldr s13, [x19], #0x4\n" "tbz %x[n_channels], #0, 8f\n" - "ld1 { v9.h }[2], [x24]\n" - "ld1 { v10.h }[2], [x23]\n" - "ld1 { v11.h }[2], [x22]\n" - "ld1 { v12.h }[2], [x21]\n" - "ld1 { v13.h }[2], [x20]\n" + "ld1 { v9.h }[2], [x23]\n" + "ld1 { v10.h }[2], [x22]\n" + "ld1 { v11.h }[2], [x21]\n" + "ld1 { v12.h }[2], [x20]\n" + "ld1 { v13.h }[2], [x19]\n" "b 8f\n" "7:" // Tile loop: Oddments: Load inputs: (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: Unset: Bit 1: Unset - "ldr h9, [x24, #0x0]\n" - "ldr h10, [x23, #0x0]\n" - "ldr h11, [x22, #0x0]\n" - "ldr h12, [x21, #0x0]\n" - "ldr h13, [x20, #0x0]\n" + "ldr h9, [x23, #0x0]\n" + "ldr h10, [x22, #0x0]\n" + "ldr h11, [x21, #0x0]\n" + "ldr h12, [x20, #0x0]\n" + "ldr h13, [x19, #0x0]\n" "8:" // Tile loop: Oddments: Load inputs: (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: End "mov v28.16b, v16.16b\n fmla v28.8h, v4.8h, v9.8h\n" "mov v29.16b, v16.16b\n fmla v29.8h, v3.8h, v9.8h\n" - "add x20, x27, XZR\n" + "add x19, x26, XZR\n" "mov v30.16b, v16.16b\n fmla v30.8h, v1.8h, v9.8h\n" "mov v31.16b, v16.16b\n fmla v31.8h, v0.8h, v9.8h\n" "fmla v28.8h, v0.8h, v10.8h\n" @@ -375,258 +375,258 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( "fmla v30.8h, v2.8h, v12.8h\n" "fmla v31.8h, v1.8h, v12.8h\n" "tbz %x[n_channels], #2, 10f\n" - "ldr d9, [x20], #0x8\n" + "ldr d9, [x19], #0x8\n" "tbz %x[n_channels], #1, 9f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 12f\n" - "ld1 { v9.h }[6], [x20]\n" + "ld1 { v9.h }[6], [x19]\n" "b 12f\n" "9:" // Tile loop: Oddments: Load inputs: (3, 0): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 12f\n" - "ld1 { v9.h }[4], [x20]\n" + "ld1 { v9.h }[4], [x19]\n" "b 12f\n" "10:" // Tile loop: Oddments: Load inputs: (3, 0): Bit 2: Unset "tbz %x[n_channels], #1, 11f\n" - "ldr s9, [x20], #0x4\n" + "ldr s9, [x19], #0x4\n" "tbz %x[n_channels], #0, 12f\n" - "ld1 { v9.h }[2], [x20]\n" + "ld1 { v9.h }[2], [x19]\n" "b 12f\n" "11:" // Tile loop: Oddments: Load inputs: (3, 0): Bit 2: Unset: Bit 1: Unset - "ldr h9, [x20, #0x0]\n" + "ldr h9, [x19, #0x0]\n" "12:" // Tile loop: Oddments: Load inputs: (3, 0): Bit 2: End "fmla v30.8h, v6.8h, v9.8h\n" "fmla v28.8h, v7.8h, v13.8h\n" - "add x20, x27, x26\n" + "add x19, x26, x25\n" "fmla v29.8h, v6.8h, v13.8h\n" "fmla v30.8h, v4.8h, v13.8h\n" "fmla v31.8h, v3.8h, v13.8h\n" "tbz %x[n_channels], #2, 14f\n" - "ldr d11, [x20], #0x8\n" + "ldr d11, [x19], #0x8\n" "tbz %x[n_channels], #1, 13f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 16f\n" - "ld1 { v11.h }[6], [x20]\n" + "ld1 { v11.h }[6], [x19]\n" "b 16f\n" "13:" // Tile loop: Oddments: Load inputs: (3, 3): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 16f\n" - "ld1 { v11.h }[4], [x20]\n" + "ld1 { v11.h }[4], [x19]\n" "b 16f\n" "14:" // Tile loop: Oddments: Load inputs: (3, 3): Bit 2: Unset "tbz %x[n_channels], #1, 15f\n" - "ldr s11, [x20], #0x4\n" + "ldr s11, [x19], #0x4\n" "tbz %x[n_channels], #0, 16f\n" - "ld1 { v11.h }[2], [x20]\n" + "ld1 { v11.h }[2], [x19]\n" "b 16f\n" "15:" // Tile loop: Oddments: Load inputs: (3, 3): Bit 2: Unset: Bit 1: Unset - "ldr h11, [x20, #0x0]\n" + "ldr h11, [x19, #0x0]\n" "16:" // Tile loop: Oddments: Load inputs: (3, 3): Bit 2: End "fmla v31.8h, v8.8h, v11.8h\n" - "add x20, x13, x15\n" + "add x19, x12, x14\n" "tbz %x[n_channels], #2, 18f\n" - "ldr d12, [x20], #0x8\n" + "ldr d12, [x19], #0x8\n" "tbz %x[n_channels], #1, 17f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 20f\n" - "ld1 { v12.h }[6], [x20]\n" + "ld1 { v12.h }[6], [x19]\n" "b 20f\n" "17:" // Tile loop: Oddments: Load inputs: (0, 1): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 20f\n" - "ld1 { v12.h }[4], [x20]\n" + "ld1 { v12.h }[4], [x19]\n" "b 20f\n" "18:" // Tile loop: Oddments: Load inputs: (0, 1): Bit 2: Unset "tbz %x[n_channels], #1, 19f\n" - "ldr s12, [x20], #0x4\n" + "ldr s12, [x19], #0x4\n" "tbz %x[n_channels], #0, 20f\n" - "ld1 { v12.h }[2], [x20]\n" + "ld1 { v12.h }[2], [x19]\n" "b 20f\n" "19:" // Tile loop: Oddments: Load inputs: (0, 1): Bit 2: Unset: Bit 1: Unset - "ldr h12, [x20, #0x0]\n" + "ldr h12, [x19, #0x0]\n" "20:" // Tile loop: Oddments: Load inputs: (0, 1): Bit 2: End "fmla v28.8h, v1.8h, v12.8h\n" "fmla v29.8h, v0.8h, v12.8h\n" - "add x20, x13, x11\n" + "add x19, x12, x10\n" "tbz %x[n_channels], #2, 22f\n" - "ldr d9, [x20], #0x8\n" + "ldr d9, [x19], #0x8\n" "tbz %x[n_channels], #1, 21f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 24f\n" - "ld1 { v9.h }[6], [x20]\n" + "ld1 { v9.h }[6], [x19]\n" "b 24f\n" "21:" // Tile loop: Oddments: Load inputs: (0, 2): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 24f\n" - "ld1 { v9.h }[4], [x20]\n" + "ld1 { v9.h }[4], [x19]\n" "b 24f\n" "22:" // Tile loop: Oddments: Load inputs: (0, 2): Bit 2: Unset "tbz %x[n_channels], #1, 23f\n" - "ldr s9, [x20], #0x4\n" + "ldr s9, [x19], #0x4\n" "tbz %x[n_channels], #0, 24f\n" - "ld1 { v9.h }[2], [x20]\n" + "ld1 { v9.h }[2], [x19]\n" "b 24f\n" "23:" // Tile loop: Oddments: Load inputs: (0, 2): Bit 2: Unset: Bit 1: Unset - "ldr h9, [x20, #0x0]\n" + "ldr h9, [x19, #0x0]\n" "24:" // Tile loop: Oddments: Load inputs: (0, 2): Bit 2: End "fmla v28.8h, v2.8h, v9.8h\n" "fmla v29.8h, v1.8h, v9.8h\n" - "add x20, x28, x11\n" + "add x19, x27, x10\n" "tbz %x[n_channels], #2, 26f\n" - "ldr d10, [x20], #0x8\n" + "ldr d10, [x19], #0x8\n" "tbz %x[n_channels], #1, 25f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 28f\n" - "ld1 { v10.h }[6], [x20]\n" + "ld1 { v10.h }[6], [x19]\n" "b 28f\n" "25:" // Tile loop: Oddments: Load inputs: (2, 2): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 28f\n" - "ld1 { v10.h }[4], [x20]\n" + "ld1 { v10.h }[4], [x19]\n" "b 28f\n" "26:" // Tile loop: Oddments: Load inputs: (2, 2): Bit 2: Unset "tbz %x[n_channels], #1, 27f\n" - "ldr s10, [x20], #0x4\n" + "ldr s10, [x19], #0x4\n" "tbz %x[n_channels], #0, 28f\n" - "ld1 { v10.h }[2], [x20]\n" + "ld1 { v10.h }[2], [x19]\n" "b 28f\n" "27:" // Tile loop: Oddments: Load inputs: (2, 2): Bit 2: Unset: Bit 1: Unset - "ldr h10, [x20, #0x0]\n" + "ldr h10, [x19, #0x0]\n" "28:" // Tile loop: Oddments: Load inputs: (2, 2): Bit 2: End "fmla v28.8h, v8.8h, v10.8h\n" "fmla v29.8h, v7.8h, v10.8h\n" - "add x20, x9, XZR\n" + "add x19, x28, XZR\n" "fmla v30.8h, v5.8h, v10.8h\n" "fmla v31.8h, v4.8h, v10.8h\n" "tbz %x[n_channels], #2, 30f\n" - "ldr d11, [x20], #0x8\n" + "ldr d11, [x19], #0x8\n" "tbz %x[n_channels], #1, 29f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 32f\n" - "ld1 { v11.h }[6], [x20]\n" + "ld1 { v11.h }[6], [x19]\n" "b 32f\n" "29:" // Tile loop: Oddments: Load inputs: (1, 0): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 32f\n" - "ld1 { v11.h }[4], [x20]\n" + "ld1 { v11.h }[4], [x19]\n" "b 32f\n" "30:" // Tile loop: Oddments: Load inputs: (1, 0): Bit 2: Unset "tbz %x[n_channels], #1, 31f\n" - "ldr s11, [x20], #0x4\n" + "ldr s11, [x19], #0x4\n" "tbz %x[n_channels], #0, 32f\n" - "ld1 { v11.h }[2], [x20]\n" + "ld1 { v11.h }[2], [x19]\n" "b 32f\n" "31:" // Tile loop: Oddments: Load inputs: (1, 0): Bit 2: Unset: Bit 1: Unset - "ldr h11, [x20, #0x0]\n" + "ldr h11, [x19, #0x0]\n" "32:" // Tile loop: Oddments: Load inputs: (1, 0): Bit 2: End "fmla v28.8h, v3.8h, v11.8h\n" "fmla v30.8h, v0.8h, v11.8h\n" - "add x20, x9, x26\n" + "add x19, x28, x25\n" "tbz %x[n_channels], #2, 34f\n" - "ldr d12, [x20], #0x8\n" + "ldr d12, [x19], #0x8\n" "tbz %x[n_channels], #1, 33f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 36f\n" - "ld1 { v12.h }[6], [x20]\n" + "ld1 { v12.h }[6], [x19]\n" "b 36f\n" "33:" // Tile loop: Oddments: Load inputs: (1, 3): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 36f\n" - "ld1 { v12.h }[4], [x20]\n" + "ld1 { v12.h }[4], [x19]\n" "b 36f\n" "34:" // Tile loop: Oddments: Load inputs: (1, 3): Bit 2: Unset "tbz %x[n_channels], #1, 35f\n" - "ldr s12, [x20], #0x4\n" + "ldr s12, [x19], #0x4\n" "tbz %x[n_channels], #0, 36f\n" - "ld1 { v12.h }[2], [x20]\n" + "ld1 { v12.h }[2], [x19]\n" "b 36f\n" "35:" // Tile loop: Oddments: Load inputs: (1, 3): Bit 2: Unset: Bit 1: Unset - "ldr h12, [x20, #0x0]\n" + "ldr h12, [x19, #0x0]\n" "36:" // Tile loop: Oddments: Load inputs: (1, 3): Bit 2: End "fmla v29.8h, v5.8h, v12.8h\n" "fmla v31.8h, v2.8h, v12.8h\n" - "add x20, x28, XZR\n" + "add x19, x27, XZR\n" "tbz %x[n_channels], #2, 38f\n" - "ldr d9, [x20], #0x8\n" + "ldr d9, [x19], #0x8\n" "tbz %x[n_channels], #1, 37f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 40f\n" - "ld1 { v9.h }[6], [x20]\n" + "ld1 { v9.h }[6], [x19]\n" "b 40f\n" "37:" // Tile loop: Oddments: Load inputs: (2, 0): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 40f\n" - "ld1 { v9.h }[4], [x20]\n" + "ld1 { v9.h }[4], [x19]\n" "b 40f\n" "38:" // Tile loop: Oddments: Load inputs: (2, 0): Bit 2: Unset "tbz %x[n_channels], #1, 39f\n" - "ldr s9, [x20], #0x4\n" + "ldr s9, [x19], #0x4\n" "tbz %x[n_channels], #0, 40f\n" - "ld1 { v9.h }[2], [x20]\n" + "ld1 { v9.h }[2], [x19]\n" "b 40f\n" "39:" // Tile loop: Oddments: Load inputs: (2, 0): Bit 2: Unset: Bit 1: Unset - "ldr h9, [x20, #0x0]\n" + "ldr h9, [x19, #0x0]\n" "40:" // Tile loop: Oddments: Load inputs: (2, 0): Bit 2: End "fmla v28.8h, v6.8h, v9.8h\n" "fmla v30.8h, v3.8h, v9.8h\n" - "add x20, x28, x26\n" + "add x19, x27, x25\n" "tbz %x[n_channels], #2, 42f\n" - "ldr d10, [x20], #0x8\n" + "ldr d10, [x19], #0x8\n" "tbz %x[n_channels], #1, 41f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 44f\n" - "ld1 { v10.h }[6], [x20]\n" + "ld1 { v10.h }[6], [x19]\n" "b 44f\n" "41:" // Tile loop: Oddments: Load inputs: (2, 3): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 44f\n" - "ld1 { v10.h }[4], [x20]\n" + "ld1 { v10.h }[4], [x19]\n" "b 44f\n" "42:" // Tile loop: Oddments: Load inputs: (2, 3): Bit 2: Unset "tbz %x[n_channels], #1, 43f\n" - "ldr s10, [x20], #0x4\n" + "ldr s10, [x19], #0x4\n" "tbz %x[n_channels], #0, 44f\n" - "ld1 { v10.h }[2], [x20]\n" + "ld1 { v10.h }[2], [x19]\n" "b 44f\n" "43:" // Tile loop: Oddments: Load inputs: (2, 3): Bit 2: Unset: Bit 1: Unset - "ldr h10, [x20, #0x0]\n" + "ldr h10, [x19, #0x0]\n" "44:" // Tile loop: Oddments: Load inputs: (2, 3): Bit 2: End "fmla v29.8h, v8.8h, v10.8h\n" "fmla v31.8h, v5.8h, v10.8h\n" - "add x20, x27, x15\n" + "add x19, x26, x14\n" "tbz %x[n_channels], #2, 46f\n" - "ldr d11, [x20], #0x8\n" + "ldr d11, [x19], #0x8\n" "tbz %x[n_channels], #1, 45f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 48f\n" - "ld1 { v11.h }[6], [x20]\n" + "ld1 { v11.h }[6], [x19]\n" "b 48f\n" "45:" // Tile loop: Oddments: Load inputs: (3, 1): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 48f\n" - "ld1 { v11.h }[4], [x20]\n" + "ld1 { v11.h }[4], [x19]\n" "b 48f\n" "46:" // Tile loop: Oddments: Load inputs: (3, 1): Bit 2: Unset "tbz %x[n_channels], #1, 47f\n" - "ldr s11, [x20], #0x4\n" + "ldr s11, [x19], #0x4\n" "tbz %x[n_channels], #0, 48f\n" - "ld1 { v11.h }[2], [x20]\n" + "ld1 { v11.h }[2], [x19]\n" "b 48f\n" "47:" // Tile loop: Oddments: Load inputs: (3, 1): Bit 2: Unset: Bit 1: Unset - "ldr h11, [x20, #0x0]\n" + "ldr h11, [x19, #0x0]\n" "48:" // Tile loop: Oddments: Load inputs: (3, 1): Bit 2: End "fmla v30.8h, v7.8h, v11.8h\n" "fmla v31.8h, v6.8h, v11.8h\n" - "add x20, x27, x11\n" + "add x19, x26, x10\n" "tbz %x[n_channels], #2, 50f\n" - "ldr d12, [x20], #0x8\n" + "ldr d12, [x19], #0x8\n" "tbz %x[n_channels], #1, 49f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 52f\n" - "ld1 { v12.h }[6], [x20]\n" + "ld1 { v12.h }[6], [x19]\n" "b 52f\n" "49:" // Tile loop: Oddments: Load inputs: (3, 2): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 52f\n" - "ld1 { v12.h }[4], [x20]\n" + "ld1 { v12.h }[4], [x19]\n" "b 52f\n" "50:" // Tile loop: Oddments: Load inputs: (3, 2): Bit 2: Unset "tbz %x[n_channels], #1, 51f\n" - "ldr s12, [x20], #0x4\n" + "ldr s12, [x19], #0x4\n" "tbz %x[n_channels], #0, 52f\n" - "ld1 { v12.h }[2], [x20]\n" + "ld1 { v12.h }[2], [x19]\n" "b 52f\n" "51:" // Tile loop: Oddments: Load inputs: (3, 2): Bit 2: Unset: Bit 1: Unset - "ldr h12, [x20, #0x0]\n" + "ldr h12, [x19, #0x0]\n" "52:" // Tile loop: Oddments: Load inputs: (3, 2): Bit 2: End "fmla v30.8h, v8.8h, v12.8h\n" "fmla v31.8h, v7.8h, v12.8h\n" @@ -639,82 +639,82 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( "fmin v30.8h, v30.8h, v17.8h\n" "fmin v31.8h, v31.8h, v17.8h\n" "tbz %x[n_channels], #2, 54f\n" - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.d }[0], [x21], x14\n" - "st1 { v30.d }[0], [x20], x14\n" - "add x12, x12, #0x8\n" - "add x25, x25, #0x8\n" - "st1 { v29.d }[0], [x21]\n" - "st1 { v31.d }[0], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.d }[0], [x20], x13\n" + "add x11, x11, #0x8\n" + "add x24, x24, #0x8\n" + "st1 { v30.d }[0], [x19], x13\n" + "st1 { v29.d }[0], [x20]\n" + "st1 { v31.d }[0], [x19]\n" "tbz %x[n_channels], #1, 53f\n" - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.s }[2], [x21], x14\n" - "st1 { v30.s }[2], [x20], x14\n" - "add x12, x12, #0x4\n" - "add x25, x25, #0x4\n" - "st1 { v29.s }[2], [x21]\n" - "st1 { v31.s }[2], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.s }[2], [x20], x13\n" + "add x11, x11, #0x4\n" + "add x24, x24, #0x4\n" + "st1 { v30.s }[2], [x19], x13\n" + "st1 { v29.s }[2], [x20]\n" + "st1 { v31.s }[2], [x19]\n" "tbz %x[n_channels], #0, 56f\n" - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.h }[6], [x21], x14\n" - "st1 { v30.h }[6], [x20], x14\n" - "st1 { v29.h }[6], [x21]\n" - "st1 { v31.h }[6], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.h }[6], [x20], x13\n" + "st1 { v30.h }[6], [x19], x13\n" + "st1 { v29.h }[6], [x20]\n" + "st1 { v31.h }[6], [x19]\n" "b 56f\n" "53:" // Tile loop: Oddments: Store: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 56f\n" - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.h }[4], [x21], x14\n" - "st1 { v30.h }[4], [x20], x14\n" - "st1 { v29.h }[4], [x21]\n" - "st1 { v31.h }[4], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.h }[4], [x20], x13\n" + "st1 { v30.h }[4], [x19], x13\n" + "st1 { v29.h }[4], [x20]\n" + "st1 { v31.h }[4], [x19]\n" "b 56f\n" "54:" // Tile loop: Oddments: Store: Bit 2: Unset "tbz %x[n_channels], #1, 55f\n" - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.s }[0], [x21], x14\n" - "st1 { v30.s }[0], [x20], x14\n" - "add x12, x12, #0x4\n" - "add x25, x25, #0x4\n" - "st1 { v29.s }[0], [x21]\n" - "st1 { v31.s }[0], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.s }[0], [x20], x13\n" + "st1 { v30.s }[0], [x19], x13\n" + "add x11, x11, #0x4\n" + "add x24, x24, #0x4\n" + "st1 { v29.s }[0], [x20]\n" + "st1 { v31.s }[0], [x19]\n" "tbz %x[n_channels], #0, 56f\n" - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.h }[2], [x21], x14\n" - "st1 { v30.h }[2], [x20], x14\n" - "st1 { v29.h }[2], [x21]\n" - "st1 { v31.h }[2], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.h }[2], [x20], x13\n" + "st1 { v30.h }[2], [x19], x13\n" + "st1 { v29.h }[2], [x20]\n" + "st1 { v31.h }[2], [x19]\n" "b 56f\n" "55:" // Tile loop: Oddments: Store: Bit 2: Unset: Bit 1: Unset - "mov x21, x12\n" - "mov x20, x25\n" - "st1 { v28.h }[0], [x21], x14\n" - "st1 { v30.h }[0], [x20], x14\n" - "st1 { v29.h }[0], [x21]\n" - "st1 { v31.h }[0], [x20]\n" + "mov x20, x11\n" + "mov x19, x24\n" + "st1 { v28.h }[0], [x20], x13\n" + "st1 { v30.h }[0], [x19], x13\n" + "st1 { v29.h }[0], [x20]\n" + "st1 { v31.h }[0], [x19]\n" "56:" // Tile loop: Oddments: Store: Bit 2: End "57:" // Tile loop: End - "ldr x22, [%x[params_struct], %[offsetof_args_tile_j]]\n" - "ldr x23, [%x[params_struct], %[offsetof_args_tile_i]]\n" - "add x22, x22, #0x1\n" - "add x21, x23, #0x1\n" - "ldr x20, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" - "cmp x22, x20\n" - "ldr x20, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" - "csel x23, x23, x21, LT\n" - "csel x22, x22, XZR, LT\n" - "cmp x23, x20\n" + "ldr x21, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x22, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "add x21, x21, #0x1\n" + "add x20, x22, #0x1\n" + "ldr x19, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "cmp x21, x19\n" + "ldr x19, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" + "csel x22, x22, x20, LT\n" + "csel x21, x21, XZR, LT\n" + "cmp x22, x19\n" "blt 1b\n" : : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v16", "v17", "v18", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v16", "v17", "v18", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp index bea4715313..a0a44997d1 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, 2023 Arm Limited. + * Copyright (c) 2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -83,18 +83,21 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "lsr x15, %x[n_channels], #0x3\n" "ldr x14, [%x[params_struct], %[offsetof_args_params]]\n" "add x20, %x[params_struct], %[offsetof_args_min]\n" + "add x19, %x[params_struct], %[offsetof_args_max]\n" + "ldp x13, x12, [x21, #0x0]\n" + "ldp x11, x10, [x21, #0x10]\n" + "add x9, %x[params_struct], %[offsetof_Args_inptrs]\n" "ld1r { v18.8h }, [x20]\n" - "add x20, %x[params_struct], %[offsetof_args_max]\n" - "ld1r { v17.8h }, [x20]\n" - "add x13, %x[params_struct], %[offsetof_Args_inptrs]\n" - "ldp x12, x11, [x21, #0x0]\n" - "ldp x10, x9, [x21, #0x10]\n" + "ld1r { v17.8h }, [x19]\n" "mov x28, #0x0\n" "sub x27, XZR, x16\n" "cbz x15, 3f\n" + "ldp x26, x25, [x9, #0x0]\n" + "ldp x24, x23, [x9, #0x10]\n" + "ldr x22, [x9, #0x20]\n" + "cmp x16, x15, LSL #4\n" "ldr q16, [x14, #0x0]\n" "ldr q0, [x14, #0x10]\n" - "cmp x16, x15, LSL #4\n" "ldr q1, [x14, #0x20]\n" "ldr q2, [x14, #0x30]\n" "ldr q3, [x14, #0x40]\n" @@ -103,165 +106,162 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "ldr q6, [x14, #0x70]\n" "ldr q7, [x14, #0x80]\n" "ldr q8, [x14, #0x90]\n" - "add x14, x14, #0xa0\n" - "ldp x26, x22, [x13, #0x0]\n" "ldr q9, [x26, x28]\n" - "ldr q10, [x22, x28]\n" - "ldp x25, x24, [x13, #0x10]\n" - "ldr q11, [x25, x28]\n" - "ldr q12, [x24, x28]\n" - "ldr x23, [x13, #0x20]\n" - "ldr q13, [x23, x28]\n" + "add x14, x14, #0xa0\n" + "ldr q10, [x25, x28]\n" + "ldr q11, [x24, x28]\n" + "ldr q12, [x23, x28]\n" + "ldr q13, [x22, x28]\n" "bge 2f\n" "1:" // Channel loop "mov v28.16b, v16.16b\n fmla v28.8h, v4.8h, v9.8h\n" "mov v29.16b, v16.16b\n fmla v29.8h, v3.8h, v9.8h\n" - "ldr x22, [x13, #0x28]\n" - "ldr x21, [x13, #0x30]\n" + "ldr x21, [x9, #0x28]\n" + "ldr x20, [x9, #0x30]\n" "mov v30.16b, v16.16b\n fmla v30.8h, v1.8h, v9.8h\n" "mov v31.16b, v16.16b\n fmla v31.8h, v0.8h, v9.8h\n" - "ldr q9, [x22, x28]\n" - "ldr q16, [x14, #0x0]\n" + "ldr q9, [x21, x28]\n" + "ldr x19, [x9, #0x38]\n" "fmla v28.8h, v0.8h, v10.8h\n" "fmla v29.8h, v2.8h, v11.8h\n" - "ldr q11, [x21, x28]\n" - "ldr x20, [x13, #0x38]\n" + "ldr q11, [x20, x28]\n" + "ldr x25, [x9, #0x48]\n" "fmla v30.8h, v2.8h, v12.8h\n" "fmla v31.8h, v1.8h, v12.8h\n" - "ldr x22, [x13, #0x48]\n" - "ldr q10, [x22, x28]\n" + "ldr x26, [x9, #0x40]\n" + "ldr q10, [x25, x28]\n" "fmla v28.8h, v5.8h, v12.8h\n" "fmla v29.8h, v4.8h, v12.8h\n" - "ldr q12, [x20, x28]\n" - "ldr x26, [x13, #0x40]\n" + "ldr q12, [x19, x28]\n" + "ldr x24, [x9, #0x50]\n" "fmla v30.8h, v6.8h, v9.8h\n" - "ldr q9, [x26, x28]\n" "fmla v31.8h, v3.8h, v13.8h\n" - "ldr x25, [x13, #0x50]\n" + "ldr q9, [x26, x28]\n" + "ldr x23, [x9, #0x58]\n" "fmla v28.8h, v7.8h, v13.8h\n" "fmla v29.8h, v6.8h, v13.8h\n" - "ldr x24, [x13, #0x58]\n" - "ldr x23, [x13, #0x60]\n" + "ldr x22, [x9, #0x60]\n" + "ldr x21, [x9, #0x68]\n" "fmla v30.8h, v4.8h, v13.8h\n" "fmla v31.8h, v8.8h, v11.8h\n" - "ldr q11, [x25, x28]\n" - "ldr x22, [x13, #0x68]\n" + "ldr q11, [x24, x28]\n" + "ldr x20, [x9, #0x70]\n" "fmla v28.8h, v1.8h, v12.8h\n" "fmla v29.8h, v0.8h, v12.8h\n" - "ldr q12, [x24, x28]\n" - "ldr x21, [x13, #0x70]\n" + "ldr q12, [x23, x28]\n" + "ldr x19, [x9, #0x78]\n" "fmla v30.8h, v5.8h, v10.8h\n" "fmla v31.8h, v4.8h, v10.8h\n" - "ldr q4, [x14, #0x50]\n" - "ldr x20, [x13, #0x78]\n" + "ldp x26, x25, [x9, #0x0]\n" + "ldp x24, x23, [x9, #0x10]\n" "fmla v28.8h, v2.8h, v9.8h\n" "fmla v29.8h, v1.8h, v9.8h\n" - "ldr q9, [x23, x28]\n" - "ldr q1, [x14, #0x20]\n" + "ldr q9, [x22, x28]\n" + "ldr x22, [x9, #0x20]\n" "fmla v30.8h, v0.8h, v11.8h\n" - "ldr q0, [x14, #0x10]\n" "fmla v31.8h, v2.8h, v12.8h\n" - "ldr q2, [x14, #0x30]\n" + "ldr q13, [x22, x16]\n" + "add x27, x27, #0x10\n" "fmla v28.8h, v8.8h, v10.8h\n" "fmla v29.8h, v7.8h, v10.8h\n" - "ldr q10, [x22, x28]\n" - "ldp x26, x22, [x13, #0x0]\n" + "ldr q10, [x21, x28]\n" + "ldr q16, [x14, #0x0]\n" "fmla v30.8h, v3.8h, v9.8h\n" "fmla v31.8h, v5.8h, v10.8h\n" - "ldp x25, x24, [x13, #0x10]\n" - "ldr x23, [x13, #0x20]\n" - "ldr q13, [x23, x16]\n" + "ldr q0, [x14, #0x10]\n" + "ldr q1, [x14, #0x20]\n" "fmla v28.8h, v3.8h, v11.8h\n" - "ldr q11, [x21, x28]\n" + "ldr q11, [x20, x28]\n" "fmla v29.8h, v5.8h, v12.8h\n" - "ldr q12, [x20, x28]\n" - "ldr q3, [x14, #0x40]\n" + "ldr q12, [x19, x28]\n" "fmla v30.8h, v7.8h, v11.8h\n" "fmla v31.8h, v6.8h, v11.8h\n" - "ldr q11, [x25, x16]\n" - "ldr q5, [x14, #0x60]\n" + "ldr q11, [x24, x16]\n" + "add x28, x28, #0x10\n" "fmla v28.8h, v6.8h, v9.8h\n" "fmla v29.8h, v8.8h, v10.8h\n" + "fmax v28.8h, v28.8h, v18.8h\n" "ldr q9, [x26, x16]\n" - "ldr q10, [x22, x16]\n" "fmla v30.8h, v8.8h, v12.8h\n" "fmla v31.8h, v7.8h, v12.8h\n" - "ldr q12, [x24, x16]\n" - "ldr q6, [x14, #0x70]\n" - "fmax v28.8h, v28.8h, v18.8h\n" "fmax v29.8h, v29.8h, v18.8h\n" - "ldr q7, [x14, #0x80]\n" - "ldr q8, [x14, #0x90]\n" + "ldr q10, [x25, x16]\n" "fmax v30.8h, v30.8h, v18.8h\n" "fmax v31.8h, v31.8h, v18.8h\n" + "ldr q12, [x23, x16]\n" "add x16, x16, #0x10\n" - "add x27, x27, #0x10\n" + "cmp x16, x15, LSL #4\n" "fmin v28.8h, v28.8h, v17.8h\n" "fmin v29.8h, v29.8h, v17.8h\n" - "cmp x16, x15, LSL #4\n" + "str q28, [x13, x27]\n" "fmin v30.8h, v30.8h, v17.8h\n" "fmin v31.8h, v31.8h, v17.8h\n" - "add x28, x28, #0x10\n" - "str q28, [x12, x27]\n" + "str q29, [x12, x27]\n" + "ldr q2, [x14, #0x30]\n" + "str q30, [x11, x27]\n" + "ldr q3, [x14, #0x40]\n" + "ldr q4, [x14, #0x50]\n" + "str q31, [x10, x27]\n" + "ldr q5, [x14, #0x60]\n" + "ldr q6, [x14, #0x70]\n" + "ldr q7, [x14, #0x80]\n" + "ldr q8, [x14, #0x90]\n" "add x14, x14, #0xa0\n" - "str q29, [x11, x27]\n" - "str q30, [x10, x27]\n" - "str q31, [x9, x27]\n" "blt 1b\n" "2:" // Channel tail "mov v28.16b, v16.16b\n fmla v28.8h, v4.8h, v9.8h\n" "mov v29.16b, v16.16b\n fmla v29.8h, v3.8h, v9.8h\n" - "ldr x22, [x13, #0x28]\n" - "ldr x21, [x13, #0x30]\n" + "ldr x21, [x9, #0x28]\n" + "ldr x20, [x9, #0x30]\n" "mov v30.16b, v16.16b\n fmla v30.8h, v1.8h, v9.8h\n" "mov v31.16b, v16.16b\n fmla v31.8h, v0.8h, v9.8h\n" - "ldr q9, [x22, x28]\n" - "ldr x20, [x13, #0x38]\n" + "ldr q9, [x21, x28]\n" + "ldr x19, [x9, #0x38]\n" "fmla v28.8h, v0.8h, v10.8h\n" "fmla v29.8h, v2.8h, v11.8h\n" - "ldr q11, [x21, x28]\n" - "ldr x22, [x13, #0x48]\n" - "ldr q10, [x22, x28]\n" + "ldr q11, [x20, x28]\n" + "ldr x25, [x9, #0x48]\n" "fmla v30.8h, v2.8h, v12.8h\n" "fmla v31.8h, v1.8h, v12.8h\n" - "ldr x26, [x13, #0x40]\n" + "ldr x26, [x9, #0x40]\n" + "ldr q10, [x25, x28]\n" "fmla v28.8h, v5.8h, v12.8h\n" "fmla v29.8h, v4.8h, v12.8h\n" - "ldr q12, [x20, x28]\n" - "ldr x25, [x13, #0x50]\n" + "ldr q12, [x19, x28]\n" + "ldr x24, [x9, #0x50]\n" "fmla v30.8h, v6.8h, v9.8h\n" - "ldr q9, [x26, x28]\n" "fmla v31.8h, v3.8h, v13.8h\n" - "ldr x24, [x13, #0x58]\n" + "ldr q9, [x26, x28]\n" + "ldr x23, [x9, #0x58]\n" "fmla v28.8h, v7.8h, v13.8h\n" "fmla v29.8h, v6.8h, v13.8h\n" - "ldr x23, [x13, #0x60]\n" - "ldr x22, [x13, #0x68]\n" + "ldr x22, [x9, #0x60]\n" + "ldr x21, [x9, #0x68]\n" "fmla v30.8h, v4.8h, v13.8h\n" "fmla v31.8h, v8.8h, v11.8h\n" - "ldr q11, [x25, x28]\n" - "ldr x21, [x13, #0x70]\n" + "ldr q11, [x24, x28]\n" + "ldr x20, [x9, #0x70]\n" "fmla v28.8h, v1.8h, v12.8h\n" "fmla v29.8h, v0.8h, v12.8h\n" - "ldr q12, [x24, x28]\n" - "ldr x20, [x13, #0x78]\n" + "ldr q12, [x23, x28]\n" + "ldr x19, [x9, #0x78]\n" "fmla v30.8h, v5.8h, v10.8h\n" "fmla v31.8h, v4.8h, v10.8h\n" "add x27, x27, #0x10\n" "fmla v28.8h, v2.8h, v9.8h\n" "fmla v29.8h, v1.8h, v9.8h\n" - "ldr q9, [x23, x28]\n" + "ldr q9, [x22, x28]\n" "fmla v30.8h, v0.8h, v11.8h\n" "fmla v31.8h, v2.8h, v12.8h\n" "fmla v28.8h, v8.8h, v10.8h\n" "fmla v29.8h, v7.8h, v10.8h\n" - "ldr q10, [x22, x28]\n" + "ldr q10, [x21, x28]\n" "fmla v30.8h, v3.8h, v9.8h\n" "fmla v31.8h, v5.8h, v10.8h\n" "fmla v28.8h, v3.8h, v11.8h\n" - "ldr q11, [x21, x28]\n" + "ldr q11, [x20, x28]\n" "fmla v29.8h, v5.8h, v12.8h\n" - "ldr q12, [x20, x28]\n" + "ldr q12, [x19, x28]\n" "fmla v30.8h, v7.8h, v11.8h\n" "fmla v31.8h, v6.8h, v11.8h\n" "add x28, x28, #0x10\n" @@ -275,92 +275,92 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "fmax v31.8h, v31.8h, v18.8h\n" "fmin v28.8h, v28.8h, v17.8h\n" "fmin v29.8h, v29.8h, v17.8h\n" - "str q28, [x12, x27]\n" + "str q28, [x13, x27]\n" "fmin v30.8h, v30.8h, v17.8h\n" "fmin v31.8h, v31.8h, v17.8h\n" - "str q29, [x11, x27]\n" - "str q30, [x10, x27]\n" - "str q31, [x9, x27]\n" + "str q29, [x12, x27]\n" + "str q30, [x11, x27]\n" + "str q31, [x10, x27]\n" "3:" // Oddments "tst %x[n_channels], #0x7\n" "beq 56f\n" - "ldr q16, [x14, #0x0]\n" - "ldr q0, [x14, #0x10]\n" "mov x27, x28\n" + "ldr x26, [x9, #0x0]\n" + "ldr x25, [x9, #0x8]\n" + "ldr x24, [x9, #0x10]\n" + "add x13, x13, x27\n" "add x12, x12, x27\n" - "ldr q1, [x14, #0x20]\n" - "ldr q2, [x14, #0x30]\n" + "ldr x23, [x9, #0x18]\n" + "ldr x22, [x9, #0x20]\n" "add x11, x11, x27\n" "add x10, x10, x27\n" + "ldr q16, [x14, #0x0]\n" + "ldr q0, [x14, #0x10]\n" + "add x26, x26, x28\n" + "add x25, x25, x28\n" + "ldr q1, [x14, #0x20]\n" + "ldr q2, [x14, #0x30]\n" + "add x24, x24, x28\n" + "add x23, x23, x28\n" "ldr q3, [x14, #0x40]\n" "ldr q4, [x14, #0x50]\n" - "add x9, x9, x27\n" + "add x22, x22, x28\n" "ldr q5, [x14, #0x60]\n" "ldr q6, [x14, #0x70]\n" "ldr q7, [x14, #0x80]\n" "ldr q8, [x14, #0x90]\n" - "ldr x24, [x13, #0x0]\n" - "ldr x23, [x13, #0x8]\n" - "add x24, x24, x28\n" - "add x23, x23, x28\n" - "ldr x22, [x13, #0x10]\n" - "ldr x21, [x13, #0x18]\n" - "add x22, x22, x28\n" - "add x21, x21, x28\n" - "ldr x20, [x13, #0x20]\n" - "add x20, x20, x28\n" "tbz %x[n_channels], #2, 5f\n" - "ld1 { v9.d }[0], [x24], #0x8\n" - "ld1 { v10.d }[0], [x23], #0x8\n" - "ld1 { v11.d }[0], [x22], #0x8\n" - "ld1 { v12.d }[0], [x21], #0x8\n" - "ld1 { v13.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x26], #0x8\n" + "ld1 { v10.d }[0], [x25], #0x8\n" + "ld1 { v11.d }[0], [x24], #0x8\n" + "ld1 { v12.d }[0], [x23], #0x8\n" + "ld1 { v13.d }[0], [x22], #0x8\n" "tbz %x[n_channels], #1, 4f\n" - "ld1 { v9.s }[2], [x24], #0x4\n" - "ld1 { v10.s }[2], [x23], #0x4\n" - "ld1 { v11.s }[2], [x22], #0x4\n" - "ld1 { v12.s }[2], [x21], #0x4\n" - "ld1 { v13.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x26], #0x4\n" + "ld1 { v10.s }[2], [x25], #0x4\n" + "ld1 { v11.s }[2], [x24], #0x4\n" + "ld1 { v12.s }[2], [x23], #0x4\n" + "ld1 { v13.s }[2], [x22], #0x4\n" "tbz %x[n_channels], #0, 7f\n" - "ld1 { v9.h }[6], [x24], #0x2\n" - "ld1 { v10.h }[6], [x23], #0x2\n" - "ld1 { v11.h }[6], [x22], #0x2\n" - "ld1 { v12.h }[6], [x21], #0x2\n" - "ld1 { v13.h }[6], [x20], #0x2\n" + "ld1 { v9.h }[6], [x26], #0x2\n" + "ld1 { v10.h }[6], [x25], #0x2\n" + "ld1 { v11.h }[6], [x24], #0x2\n" + "ld1 { v12.h }[6], [x23], #0x2\n" + "ld1 { v13.h }[6], [x22], #0x2\n" "b 7f\n" "4:" // Oddments: Load inputs (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 7f\n" - "ld1 { v9.h }[4], [x24], #0x2\n" - "ld1 { v10.h }[4], [x23], #0x2\n" - "ld1 { v11.h }[4], [x22], #0x2\n" - "ld1 { v12.h }[4], [x21], #0x2\n" - "ld1 { v13.h }[4], [x20], #0x2\n" + "ld1 { v9.h }[4], [x26], #0x2\n" + "ld1 { v10.h }[4], [x25], #0x2\n" + "ld1 { v11.h }[4], [x24], #0x2\n" + "ld1 { v12.h }[4], [x23], #0x2\n" + "ld1 { v13.h }[4], [x22], #0x2\n" "b 7f\n" "5:" // Oddments: Load inputs (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: Unset "tbz %x[n_channels], #1, 6f\n" - "ld1 { v9.s }[0], [x24], #0x4\n" - "ld1 { v10.s }[0], [x23], #0x4\n" - "ld1 { v11.s }[0], [x22], #0x4\n" - "ld1 { v12.s }[0], [x21], #0x4\n" - "ld1 { v13.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x26], #0x4\n" + "ld1 { v10.s }[0], [x25], #0x4\n" + "ld1 { v11.s }[0], [x24], #0x4\n" + "ld1 { v12.s }[0], [x23], #0x4\n" + "ld1 { v13.s }[0], [x22], #0x4\n" "tbz %x[n_channels], #0, 7f\n" - "ld1 { v9.h }[2], [x24], #0x2\n" - "ld1 { v10.h }[2], [x23], #0x2\n" - "ld1 { v11.h }[2], [x22], #0x2\n" - "ld1 { v12.h }[2], [x21], #0x2\n" - "ld1 { v13.h }[2], [x20], #0x2\n" + "ld1 { v9.h }[2], [x26], #0x2\n" + "ld1 { v10.h }[2], [x25], #0x2\n" + "ld1 { v11.h }[2], [x24], #0x2\n" + "ld1 { v12.h }[2], [x23], #0x2\n" + "ld1 { v13.h }[2], [x22], #0x2\n" "b 7f\n" "6:" // Oddments: Load inputs (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: Unset: Bit 1: Unset - "ld1 { v9.h }[0], [x24], #0x2\n" - "ld1 { v10.h }[0], [x23], #0x2\n" - "ld1 { v11.h }[0], [x22], #0x2\n" - "ld1 { v12.h }[0], [x21], #0x2\n" - "ld1 { v13.h }[0], [x20], #0x2\n" + "ld1 { v9.h }[0], [x26], #0x2\n" + "ld1 { v10.h }[0], [x25], #0x2\n" + "ld1 { v11.h }[0], [x24], #0x2\n" + "ld1 { v12.h }[0], [x23], #0x2\n" + "ld1 { v13.h }[0], [x22], #0x2\n" "7:" // Oddments: Load inputs (1, 1), (0, 0), (0, 3), (1, 2), (2, 1): Bit 2: End "mov v28.16b, v16.16b\n fmla v28.8h, v4.8h, v9.8h\n" "mov v29.16b, v16.16b\n fmla v29.8h, v3.8h, v9.8h\n" - "ldr x20, [x13, #0x28]\n" - "add x20, x20, x28\n" + "ldr x21, [x9, #0x28]\n" + "add x21, x21, x28\n" "mov v30.16b, v16.16b\n fmla v30.8h, v1.8h, v9.8h\n" "mov v31.16b, v16.16b\n fmla v31.8h, v0.8h, v9.8h\n" "fmla v28.8h, v0.8h, v10.8h\n" @@ -370,27 +370,27 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "fmla v30.8h, v2.8h, v12.8h\n" "fmla v31.8h, v1.8h, v12.8h\n" "tbz %x[n_channels], #2, 9f\n" - "ld1 { v9.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x21], #0x8\n" "tbz %x[n_channels], #1, 8f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #0, 11f\n" - "ld1 { v9.h }[6], [x20], #0x2\n" + "ld1 { v9.h }[6], [x21], #0x2\n" "b 11f\n" "8:" // Oddments: Load input (3, 0): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 11f\n" - "ld1 { v9.h }[4], [x20], #0x2\n" + "ld1 { v9.h }[4], [x21], #0x2\n" "b 11f\n" "9:" // Oddments: Load input (3, 0): Bit 2: Unset "tbz %x[n_channels], #1, 10f\n" - "ld1 { v9.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x21], #0x4\n" "tbz %x[n_channels], #0, 11f\n" - "ld1 { v9.h }[2], [x20], #0x2\n" + "ld1 { v9.h }[2], [x21], #0x2\n" "b 11f\n" "10:" // Oddments: Load input (3, 0): Bit 2: Unset: Bit 1: Unset - "ld1 { v9.h }[0], [x20], #0x2\n" + "ld1 { v9.h }[0], [x21], #0x2\n" "11:" // Oddments: Load input (3, 0): Bit 2: End "fmla v30.8h, v6.8h, v9.8h\n" - "ldr x20, [x13, #0x30]\n" + "ldr x20, [x9, #0x30]\n" "fmla v28.8h, v7.8h, v13.8h\n" "add x20, x20, x28\n" "fmla v29.8h, v6.8h, v13.8h\n" @@ -416,176 +416,176 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "14:" // Oddments: Load input (3, 3): Bit 2: Unset: Bit 1: Unset "ld1 { v11.h }[0], [x20], #0x2\n" "15:" // Oddments: Load input (3, 3): Bit 2: End - "ldr x20, [x13, #0x38]\n" + "ldr x19, [x9, #0x38]\n" "fmla v31.8h, v8.8h, v11.8h\n" - "add x20, x20, x28\n" + "add x19, x19, x28\n" "tbz %x[n_channels], #2, 17f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x19], #0x8\n" "tbz %x[n_channels], #1, 16f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v12.h }[6], [x20], #0x2\n" + "ld1 { v12.h }[6], [x19], #0x2\n" "b 19f\n" "16:" // Oddments: Load input (0, 1): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 19f\n" - "ld1 { v12.h }[4], [x20], #0x2\n" + "ld1 { v12.h }[4], [x19], #0x2\n" "b 19f\n" "17:" // Oddments: Load input (0, 1): Bit 2: Unset "tbz %x[n_channels], #1, 18f\n" - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x19], #0x4\n" "tbz %x[n_channels], #0, 19f\n" - "ld1 { v12.h }[2], [x20], #0x2\n" + "ld1 { v12.h }[2], [x19], #0x2\n" "b 19f\n" "18:" // Oddments: Load input (0, 1): Bit 2: Unset: Bit 1: Unset - "ld1 { v12.h }[0], [x20], #0x2\n" + "ld1 { v12.h }[0], [x19], #0x2\n" "19:" // Oddments: Load input (0, 1): Bit 2: End - "ldr x20, [x13, #0x40]\n" + "ldr x26, [x9, #0x40]\n" "fmla v28.8h, v1.8h, v12.8h\n" "fmla v29.8h, v0.8h, v12.8h\n" - "add x20, x20, x28\n" + "add x26, x26, x28\n" "tbz %x[n_channels], #2, 21f\n" - "ld1 { v9.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x26], #0x8\n" "tbz %x[n_channels], #1, 20f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x26], #0x4\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v9.h }[6], [x20], #0x2\n" + "ld1 { v9.h }[6], [x26], #0x2\n" "b 23f\n" "20:" // Oddments: Load input (0, 2): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 23f\n" - "ld1 { v9.h }[4], [x20], #0x2\n" + "ld1 { v9.h }[4], [x26], #0x2\n" "b 23f\n" "21:" // Oddments: Load input (0, 2): Bit 2: Unset "tbz %x[n_channels], #1, 22f\n" - "ld1 { v9.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x26], #0x4\n" "tbz %x[n_channels], #0, 23f\n" - "ld1 { v9.h }[2], [x20], #0x2\n" + "ld1 { v9.h }[2], [x26], #0x2\n" "b 23f\n" "22:" // Oddments: Load input (0, 2): Bit 2: Unset: Bit 1: Unset - "ld1 { v9.h }[0], [x20], #0x2\n" + "ld1 { v9.h }[0], [x26], #0x2\n" "23:" // Oddments: Load input (0, 2): Bit 2: End - "ldr x20, [x13, #0x48]\n" + "ldr x25, [x9, #0x48]\n" "fmla v28.8h, v2.8h, v9.8h\n" "fmla v29.8h, v1.8h, v9.8h\n" - "add x20, x20, x28\n" + "add x25, x25, x28\n" "tbz %x[n_channels], #2, 25f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x25], #0x8\n" "tbz %x[n_channels], #1, 24f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x25], #0x4\n" "tbz %x[n_channels], #0, 27f\n" - "ld1 { v10.h }[6], [x20], #0x2\n" + "ld1 { v10.h }[6], [x25], #0x2\n" "b 27f\n" "24:" // Oddments: Load input (2, 2): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 27f\n" - "ld1 { v10.h }[4], [x20], #0x2\n" + "ld1 { v10.h }[4], [x25], #0x2\n" "b 27f\n" "25:" // Oddments: Load input (2, 2): Bit 2: Unset "tbz %x[n_channels], #1, 26f\n" - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x25], #0x4\n" "tbz %x[n_channels], #0, 27f\n" - "ld1 { v10.h }[2], [x20], #0x2\n" + "ld1 { v10.h }[2], [x25], #0x2\n" "b 27f\n" "26:" // Oddments: Load input (2, 2): Bit 2: Unset: Bit 1: Unset - "ld1 { v10.h }[0], [x20], #0x2\n" + "ld1 { v10.h }[0], [x25], #0x2\n" "27:" // Oddments: Load input (2, 2): Bit 2: End - "ldr x20, [x13, #0x50]\n" + "ldr x24, [x9, #0x50]\n" "fmla v28.8h, v8.8h, v10.8h\n" "fmla v29.8h, v7.8h, v10.8h\n" - "add x20, x20, x28\n" + "add x24, x24, x28\n" "fmla v30.8h, v5.8h, v10.8h\n" "fmla v31.8h, v4.8h, v10.8h\n" "tbz %x[n_channels], #2, 29f\n" - "ld1 { v11.d }[0], [x20], #0x8\n" + "ld1 { v11.d }[0], [x24], #0x8\n" "tbz %x[n_channels], #1, 28f\n" - "ld1 { v11.s }[2], [x20], #0x4\n" + "ld1 { v11.s }[2], [x24], #0x4\n" "tbz %x[n_channels], #0, 31f\n" - "ld1 { v11.h }[6], [x20], #0x2\n" + "ld1 { v11.h }[6], [x24], #0x2\n" "b 31f\n" "28:" // Oddments: Load input (1, 0): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 31f\n" - "ld1 { v11.h }[4], [x20], #0x2\n" + "ld1 { v11.h }[4], [x24], #0x2\n" "b 31f\n" "29:" // Oddments: Load input (1, 0): Bit 2: Unset "tbz %x[n_channels], #1, 30f\n" - "ld1 { v11.s }[0], [x20], #0x4\n" + "ld1 { v11.s }[0], [x24], #0x4\n" "tbz %x[n_channels], #0, 31f\n" - "ld1 { v11.h }[2], [x20], #0x2\n" + "ld1 { v11.h }[2], [x24], #0x2\n" "b 31f\n" "30:" // Oddments: Load input (1, 0): Bit 2: Unset: Bit 1: Unset - "ld1 { v11.h }[0], [x20], #0x2\n" + "ld1 { v11.h }[0], [x24], #0x2\n" "31:" // Oddments: Load input (1, 0): Bit 2: End - "ldr x20, [x13, #0x58]\n" + "ldr x23, [x9, #0x58]\n" "fmla v28.8h, v3.8h, v11.8h\n" "fmla v30.8h, v0.8h, v11.8h\n" - "add x20, x20, x28\n" + "add x23, x23, x28\n" "tbz %x[n_channels], #2, 33f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x23], #0x8\n" "tbz %x[n_channels], #1, 32f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x23], #0x4\n" "tbz %x[n_channels], #0, 35f\n" - "ld1 { v12.h }[6], [x20], #0x2\n" + "ld1 { v12.h }[6], [x23], #0x2\n" "b 35f\n" "32:" // Oddments: Load input (1, 3): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 35f\n" - "ld1 { v12.h }[4], [x20], #0x2\n" + "ld1 { v12.h }[4], [x23], #0x2\n" "b 35f\n" "33:" // Oddments: Load input (1, 3): Bit 2: Unset "tbz %x[n_channels], #1, 34f\n" - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x23], #0x4\n" "tbz %x[n_channels], #0, 35f\n" - "ld1 { v12.h }[2], [x20], #0x2\n" + "ld1 { v12.h }[2], [x23], #0x2\n" "b 35f\n" "34:" // Oddments: Load input (1, 3): Bit 2: Unset: Bit 1: Unset - "ld1 { v12.h }[0], [x20], #0x2\n" + "ld1 { v12.h }[0], [x23], #0x2\n" "35:" // Oddments: Load input (1, 3): Bit 2: End - "ldr x20, [x13, #0x60]\n" + "ldr x22, [x9, #0x60]\n" "fmla v29.8h, v5.8h, v12.8h\n" "fmla v31.8h, v2.8h, v12.8h\n" - "add x20, x20, x28\n" + "add x22, x22, x28\n" "tbz %x[n_channels], #2, 37f\n" - "ld1 { v9.d }[0], [x20], #0x8\n" + "ld1 { v9.d }[0], [x22], #0x8\n" "tbz %x[n_channels], #1, 36f\n" - "ld1 { v9.s }[2], [x20], #0x4\n" + "ld1 { v9.s }[2], [x22], #0x4\n" "tbz %x[n_channels], #0, 39f\n" - "ld1 { v9.h }[6], [x20], #0x2\n" + "ld1 { v9.h }[6], [x22], #0x2\n" "b 39f\n" "36:" // Oddments: Load input (2, 0): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 39f\n" - "ld1 { v9.h }[4], [x20], #0x2\n" + "ld1 { v9.h }[4], [x22], #0x2\n" "b 39f\n" "37:" // Oddments: Load input (2, 0): Bit 2: Unset "tbz %x[n_channels], #1, 38f\n" - "ld1 { v9.s }[0], [x20], #0x4\n" + "ld1 { v9.s }[0], [x22], #0x4\n" "tbz %x[n_channels], #0, 39f\n" - "ld1 { v9.h }[2], [x20], #0x2\n" + "ld1 { v9.h }[2], [x22], #0x2\n" "b 39f\n" "38:" // Oddments: Load input (2, 0): Bit 2: Unset: Bit 1: Unset - "ld1 { v9.h }[0], [x20], #0x2\n" + "ld1 { v9.h }[0], [x22], #0x2\n" "39:" // Oddments: Load input (2, 0): Bit 2: End - "ldr x20, [x13, #0x68]\n" + "ldr x21, [x9, #0x68]\n" "fmla v28.8h, v6.8h, v9.8h\n" "fmla v30.8h, v3.8h, v9.8h\n" - "add x20, x20, x28\n" + "add x21, x21, x28\n" "tbz %x[n_channels], #2, 41f\n" - "ld1 { v10.d }[0], [x20], #0x8\n" + "ld1 { v10.d }[0], [x21], #0x8\n" "tbz %x[n_channels], #1, 40f\n" - "ld1 { v10.s }[2], [x20], #0x4\n" + "ld1 { v10.s }[2], [x21], #0x4\n" "tbz %x[n_channels], #0, 43f\n" - "ld1 { v10.h }[6], [x20], #0x2\n" + "ld1 { v10.h }[6], [x21], #0x2\n" "b 43f\n" "40:" // Oddments: Load input (2, 3): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 43f\n" - "ld1 { v10.h }[4], [x20], #0x2\n" + "ld1 { v10.h }[4], [x21], #0x2\n" "b 43f\n" "41:" // Oddments: Load input (2, 3): Bit 2: Unset "tbz %x[n_channels], #1, 42f\n" - "ld1 { v10.s }[0], [x20], #0x4\n" + "ld1 { v10.s }[0], [x21], #0x4\n" "tbz %x[n_channels], #0, 43f\n" - "ld1 { v10.h }[2], [x20], #0x2\n" + "ld1 { v10.h }[2], [x21], #0x2\n" "b 43f\n" "42:" // Oddments: Load input (2, 3): Bit 2: Unset: Bit 1: Unset - "ld1 { v10.h }[0], [x20], #0x2\n" + "ld1 { v10.h }[0], [x21], #0x2\n" "43:" // Oddments: Load input (2, 3): Bit 2: End - "ldr x20, [x13, #0x70]\n" + "ldr x20, [x9, #0x70]\n" "fmla v29.8h, v8.8h, v10.8h\n" "fmla v31.8h, v5.8h, v10.8h\n" "add x20, x20, x28\n" @@ -609,29 +609,29 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "46:" // Oddments: Load input (3, 1): Bit 2: Unset: Bit 1: Unset "ld1 { v11.h }[0], [x20], #0x2\n" "47:" // Oddments: Load input (3, 1): Bit 2: End - "ldr x20, [x13, #0x78]\n" + "ldr x19, [x9, #0x78]\n" "fmla v30.8h, v7.8h, v11.8h\n" "fmla v31.8h, v6.8h, v11.8h\n" - "add x20, x20, x28\n" + "add x19, x19, x28\n" "tbz %x[n_channels], #2, 49f\n" - "ld1 { v12.d }[0], [x20], #0x8\n" + "ld1 { v12.d }[0], [x19], #0x8\n" "tbz %x[n_channels], #1, 48f\n" - "ld1 { v12.s }[2], [x20], #0x4\n" + "ld1 { v12.s }[2], [x19], #0x4\n" "tbz %x[n_channels], #0, 51f\n" - "ld1 { v12.h }[6], [x20], #0x2\n" + "ld1 { v12.h }[6], [x19], #0x2\n" "b 51f\n" "48:" // Oddments: Load input (3, 2): Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 51f\n" - "ld1 { v12.h }[4], [x20], #0x2\n" + "ld1 { v12.h }[4], [x19], #0x2\n" "b 51f\n" "49:" // Oddments: Load input (3, 2): Bit 2: Unset "tbz %x[n_channels], #1, 50f\n" - "ld1 { v12.s }[0], [x20], #0x4\n" + "ld1 { v12.s }[0], [x19], #0x4\n" "tbz %x[n_channels], #0, 51f\n" - "ld1 { v12.h }[2], [x20], #0x2\n" + "ld1 { v12.h }[2], [x19], #0x2\n" "b 51f\n" "50:" // Oddments: Load input (3, 2): Bit 2: Unset: Bit 1: Unset - "ld1 { v12.h }[0], [x20], #0x2\n" + "ld1 { v12.h }[0], [x19], #0x2\n" "51:" // Oddments: Load input (3, 2): Bit 2: End "fmla v30.8h, v8.8h, v12.8h\n" "fmla v31.8h, v7.8h, v12.8h\n" @@ -644,50 +644,52 @@ void a64_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( "fmin v30.8h, v30.8h, v17.8h\n" "fmin v31.8h, v31.8h, v17.8h\n" "tbz %x[n_channels], #2, 53f\n" - "st1 { v28.d }[0], [x12], #0x8\n" - "st1 { v29.d }[0], [x11], #0x8\n" - "st1 { v30.d }[0], [x10], #0x8\n" - "st1 { v31.d }[0], [x9], #0x8\n" + "st1 { v28.d }[0], [x13], #0x8\n" + "st1 { v29.d }[0], [x12], #0x8\n" + "st1 { v30.d }[0], [x11], #0x8\n" + "st1 { v31.d }[0], [x10], #0x8\n" "tbz %x[n_channels], #1, 52f\n" - "st1 { v28.s }[2], [x12], #0x4\n" - "st1 { v29.s }[2], [x11], #0x4\n" - "st1 { v30.s }[2], [x10], #0x4\n" - "st1 { v31.s }[2], [x9], #0x4\n" + "st1 { v28.s }[2], [x13], #0x4\n" + "st1 { v29.s }[2], [x12], #0x4\n" + "st1 { v30.s }[2], [x11], #0x4\n" + "st1 { v31.s }[2], [x10], #0x4\n" "tbz %x[n_channels], #0, 55f\n" - "st1 { v28.h }[6], [x12], #0x2\n" - "st1 { v29.h }[6], [x11], #0x2\n" - "st1 { v30.h }[6], [x10], #0x2\n" - "st1 { v31.h }[6], [x9], #0x2\n" + "st1 { v28.h }[6], [x13], #0x2\n" + "st1 { v29.h }[6], [x12], #0x2\n" + "st1 { v30.h }[6], [x11], #0x2\n" + "st1 { v31.h }[6], [x10], #0x2\n" "b 55f\n" "52:" // Oddments: Store: Bit 2: Bit 1: Unset "tbz %x[n_channels], #0, 55f\n" - "st1 { v28.h }[4], [x12], #0x2\n" - "st1 { v29.h }[4], [x11], #0x2\n" - "st1 { v30.h }[4], [x10], #0x2\n" - "st1 { v31.h }[4], [x9], #0x2\n" + "st1 { v28.h }[4], [x13], #0x2\n" + "st1 { v29.h }[4], [x12], #0x2\n" + "st1 { v30.h }[4], [x11], #0x2\n" + "st1 { v31.h }[4], [x10], #0x2\n" "b 55f\n" "53:" // Oddments: Store: Bit 2: Unset "tbz %x[n_channels], #1, 54f\n" - "st1 { v28.s }[0], [x12], #0x4\n" - "st1 { v29.s }[0], [x11], #0x4\n" - "st1 { v30.s }[0], [x10], #0x4\n" - "st1 { v31.s }[0], [x9], #0x4\n" + "st1 { v28.s }[0], [x13], #0x4\n" + "st1 { v29.s }[0], [x12], #0x4\n" + "st1 { v30.s }[0], [x11], #0x4\n" + "st1 { v31.s }[0], [x10], #0x4\n" "tbz %x[n_channels], #0, 55f\n" - "st1 { v28.h }[2], [x12], #0x2\n" - "st1 { v29.h }[2], [x11], #0x2\n" - "st1 { v30.h }[2], [x10], #0x2\n" - "st1 { v31.h }[2], [x9], #0x2\n" + "st1 { v28.h }[2], [x13], #0x2\n" + "st1 { v29.h }[2], [x12], #0x2\n" + "st1 { v30.h }[2], [x11], #0x2\n" + "st1 { v31.h }[2], [x10], #0x2\n" "b 55f\n" "54:" // Oddments: Store: Bit 2: Unset: Bit 1: Unset - "st1 { v28.h }[0], [x12], #0x2\n" - "st1 { v29.h }[0], [x11], #0x2\n" - "st1 { v30.h }[0], [x10], #0x2\n" - "st1 { v31.h }[0], [x9], #0x2\n" + "st1 { v28.h }[0], [x13], #0x2\n" + "st1 { v29.h }[0], [x12], #0x2\n" + "st1 { v30.h }[0], [x11], #0x2\n" + "st1 { v31.h }[0], [x10], #0x2\n" "55:" // Oddments: Store: Bit 2: End + "56:" // End + : : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) - : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v16", "v17", "v18", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" + : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v16", "v17", "v18", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28" ); } |