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-rw-r--r--src/core/CL/CLUtils.cpp114
1 files changed, 2 insertions, 112 deletions
diff --git a/src/core/CL/CLUtils.cpp b/src/core/CL/CLUtils.cpp
index 03f78697bc..7e56a3ba18 100644
--- a/src/core/CL/CLUtils.cpp
+++ b/src/core/CL/CLUtils.cpp
@@ -23,16 +23,14 @@
*/
#include "src/core/CL/CLUtils.h"
-#include "arm_compute/core/utils/ActivationFunctionUtils.h"
#include "arm_compute/core/CL/CLCompileContext.h"
#include "arm_compute/core/CL/CLKernelLibrary.h"
#include "arm_compute/core/CL/ICLTensor.h"
#include "arm_compute/core/Validate.h"
+#include "arm_compute/core/utils/ActivationFunctionUtils.h"
#include "arm_compute/core/utils/StringUtils.h"
#include "support/StringSupport.h"
-#include "src/core/experimental/PostOpUtils.h"
-
namespace arm_compute
{
cl::Image2D create_image2d_from_tensor(const ICLTensor *tensor, CLImage2DType image_type)
@@ -40,7 +38,7 @@ cl::Image2D create_image2d_from_tensor(const ICLTensor *tensor, CLImage2DType im
ARM_COMPUTE_ERROR_ON_NULLPTR(tensor);
const cl::Context &ctx = CLKernelLibrary::get().context();
- const cl::Buffer &buffer = tensor->cl_buffer();
+ const cl::Buffer &buffer = tensor->cl_buffer();
const ITensorInfo *info = tensor->info();
ARM_COMPUTE_ERROR_ON_MSG(info->lock_paddings(),
"Tensor paddings must not be locked to allow extending paddings to satisfy cl_image pitch alignment requirement");
@@ -113,112 +111,4 @@ cl::Image2D create_image2d_from_buffer(const cl::Context &ctx, const cl::Buffer
return cl::Image2D(cl_image);
}
-
-namespace experimental
-{
-PostOpCLKernelUtils::PostOpCLKernelUtils(const Config &supported_config)
- : _supported_config(supported_config)
-{
- ARM_COMPUTE_ERROR_ON_MSG(supported_config.empty(), "Empty PostOp CL kernel support configuration is not allowed");
- for(auto it = _supported_config.begin(); it != _supported_config.end(); ++it)
- {
- auto post_op_sequence = it->first;
- auto post_op_slots = std::get<1>(it->second);
- ARM_COMPUTE_ERROR_ON_MSG(post_op_sequence.size() != post_op_slots.size(), "The number of PostOps must be the same as that of the assigned slots");
- }
-}
-
-bool PostOpCLKernelUtils::are_post_op_shapes_compliant(const ITensorInfo *dst, const experimental::PostOpList<ITensorInfo *> &post_ops)
-{
- for(const auto &op : post_ops.get_list())
- {
- for(const auto &tensor : op->arguments())
- {
- const TensorShape &out_shape = TensorShape::broadcast_shape(dst->tensor_shape(), (*tensor)->tensor_shape());
- // All post ops must be elementwise and must not alter the shape of the original dst tensor after broadcasting
- if(detail::have_different_dimensions(out_shape, dst->tensor_shape(), 0))
- {
- return false;
- }
- // NOTE: Kernel limitation: currently only the following broadcasting types are supported:
- // 1. Post op arg is scalar, broadcast in both first and second dims
- // 2. Post op arg is of shape: second dim=1, first dim=N, broadcast only in second dim
- // This means this case: Post op arg is of shape: second dim=M, first dim=1, broadcast only in first dim, is NOT supported
- if(dst->dimension(0) > 1 && dst->dimension(1) > 1 && (*tensor)->dimension(0) == 1 && (*tensor)->dimension(1) > 1)
- {
- return false;
- }
- }
- }
- return true;
-}
-
-bool PostOpCLKernelUtils::is_post_op_sequence_supported(const PostOpList<ITensorInfo *> &post_ops) const
-{
- if(post_ops.size() == 0)
- {
- return true; // Always support cases where no post op is specified
- }
- const auto post_op_sequence = get_post_op_sequence(post_ops);
-
- return _supported_config.find(post_op_sequence) != _supported_config.end();
-}
-
-void PostOpCLKernelUtils::set_post_ops_cl_build_options(CLBuildOptions &build_opts, const PostOpList<ITensorInfo *> &post_ops) const
-{
- const auto post_op_sequence = get_post_op_sequence(post_ops);
- const auto slots = std::get<1>(_supported_config.at(post_op_sequence));
- for(size_t post_op_id = 0; post_op_id < post_ops.size(); ++post_op_id)
- {
- const auto &post_op = post_ops.get_list().at(post_op_id);
- const auto slot_prefix = "-DP" + support::cpp11::to_string(slots[post_op_id]);
- if(post_op->type() == experimental::PostOpType::Activation)
- {
- const auto _post_op = utils::cast::polymorphic_downcast<const experimental::PostOpAct<ITensorInfo *> *>(post_op.get());
- const auto act_type = slot_prefix + "_ACTIVATION_TYPE=" + lower_string(string_from_activation_func(_post_op->_act_info.activation()));
- const auto act_a_val = slot_prefix + "_ACTIVATION_A_VAL=" + float_to_string_with_full_precision(_post_op->_act_info.a());
- const auto act_b_val = slot_prefix + "_ACTIVATION_B_VAL=" + float_to_string_with_full_precision(_post_op->_act_info.b());
- build_opts.add_option(act_type);
- build_opts.add_option(act_a_val);
- build_opts.add_option(act_b_val);
- }
- else if(post_op->type() == experimental::PostOpType::Eltwise_Add)
- {
- size_t arg_id = 1;
- const auto eltwise_op = slot_prefix + "_ELTWISE_OP=ADD" + "_X_POS_" + support::cpp11::to_string(post_op->prev_dst_pos());
- build_opts.add_option(eltwise_op);
- for(const auto &tensor : post_op->arguments())
- {
- const auto height = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_HEIGHT=" + support::cpp11::to_string((*tensor)->dimension(1));
- const auto width = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_WIDTH=" + support::cpp11::to_string((*tensor)->dimension(0));
- build_opts.add_option(height);
- build_opts.add_option(width);
- ++arg_id;
- }
- }
- else if(post_op->type() == experimental::PostOpType::Eltwise_PRelu)
- {
- size_t arg_id = 1;
- const auto eltwise_op = slot_prefix + "_ELTWISE_OP=PRELU" + "_X_POS_" + support::cpp11::to_string(post_op->prev_dst_pos());
- build_opts.add_option(eltwise_op);
- for(const auto &tensor : post_op->arguments())
- {
- const auto height = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_HEIGHT=" + support::cpp11::to_string((*tensor)->dimension(1));
- const auto width = slot_prefix + "_ELTWISE_ARG" + support::cpp11::to_string(arg_id) + "_WIDTH=" + support::cpp11::to_string((*tensor)->dimension(0));
- build_opts.add_option(height);
- build_opts.add_option(width);
- ++arg_id;
- }
- }
- }
-}
-
-void PostOpCLKernelUtils::set_post_ops_cl_kernel_name(std::string &kernel_name, const PostOpList<ITensorInfo *> &post_ops) const
-{
- const auto post_op_sequence = get_post_op_sequence(post_ops);
- const auto postfix = std::get<0>(_supported_config.at(post_op_sequence));
- kernel_name += postfix;
-}
-} // namespace experimental
-
} // namespace arm_compute
generated by cgit v1.2.1 (git 2.23.0) at 2024-05-19 22:36:09 +0000