6 files changed, 50 insertions, 91 deletions
diff --git a/src/common/cpuinfo/CpuInfo.cpp b/src/common/cpuinfo/CpuInfo.cpp
index 436e7ea803..32504acc44 100644
--- a/src/common/cpuinfo/CpuInfo.cpp
+++ b/src/common/cpuinfo/CpuInfo.cpp
@@ -25,7 +25,6 @@
 
 #include "arm_compute/core/Error.h"
 #include "arm_compute/core/Log.h"
-#include "src/common/cpuinfo/target/CpuInfoSveUtils.h"
 #include "support/StringSupport.h"
 #include "support/ToolchainSupport.h"
 
@@ -260,6 +259,20 @@ int get_max_cpus()
     return max_cpus;
 }
 #endif /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */
+
+#if defined(BARE_METAL) && defined(__aarch64__)
+uint64_t get_sve_feature_reg()
+{
+    uint64_t svefr0 = 0;
+    __asm __volatile(
+        ".inst 0xd5380483 // mrs x3, ID_AA64ZFR0_EL1\n"
+        "MOV  %0, X3"
+        : "=r"(svefr0)
+        :
+        : "x3");
+    return svefr0;
+}
+#endif /* defined(BARE_METAL) && defined(__aarch64__) */
 } // namespace
 
 CpuInfo::CpuInfo(CpuIsaInfo isa, std::vector<CpuModel> cpus)
diff --git a/src/common/cpuinfo/CpuInfo.h b/src/common/cpuinfo/CpuInfo.h
index f3056d2faf..c04c9f4ec8 100644
--- a/src/common/cpuinfo/CpuInfo.h
+++ b/src/common/cpuinfo/CpuInfo.h
@@ -79,17 +79,25 @@ public:
     {
         return _isa.bf16;
     }
+    bool has_svebf16() const
+    {
+        return _isa.svebf16;
+    }
     bool has_dotprod() const
     {
         return _isa.dot;
     }
-    bool has_immla() const
+    bool has_i8mm() const
+    {
+        return _isa.i8mm;
+    }
+    bool has_svei8mm() const
     {
-        return _isa.immla;
+        return _isa.svei8mm;
     }
-    bool has_fmmla() const
+    bool has_svef32mm() const
     {
-        return _isa.fmmla;
+        return _isa.svef32mm;
     }
 
     CpuModel cpu_model(uint32_t cpuid) const;
diff --git a/src/common/cpuinfo/CpuIsaInfo.cpp b/src/common/cpuinfo/CpuIsaInfo.cpp
index d99f9aec29..14466ef4e7 100644
--- a/src/common/cpuinfo/CpuIsaInfo.cpp
+++ b/src/common/cpuinfo/CpuIsaInfo.cpp
@@ -90,6 +90,10 @@ void decode_hwcaps(CpuIsaInfo &isa, const uint32_t hwcaps, const uint32_t hwcaps
     {
         isa.bf16 = true;
     }
+    if(hwcaps2 & ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEBF16)
+    {
+        isa.svebf16 = true;
+    }
 
     // Instruction extensions
     if(hwcaps & ARM_COMPUTE_CPU_FEATURE_HWCAP_ASIMDDP)
@@ -98,11 +102,15 @@ void decode_hwcaps(CpuIsaInfo &isa, const uint32_t hwcaps, const uint32_t hwcaps
     }
     if(hwcaps2 & ARM_COMPUTE_CPU_FEATURE_HWCAP2_I8MM)
     {
-        isa.immla = true;
+        isa.i8mm = true;
+    }
+    if(hwcaps2 & ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEI8MM)
+    {
+        isa.svei8mm = true;
     }
     if(hwcaps2 & ARM_COMPUTE_CPU_FEATURE_HWCAP2_SVEF32MM)
     {
-        isa.fmmla = true;
+        isa.svef32mm = true;
     }
 }
 #else  /* defined(__aarch64__) */
@@ -133,6 +141,10 @@ void decode_regs(CpuIsaInfo &isa, const uint64_t isar0, const uint64_t isar1, co
     {
         isa.bf16 = true;
     }
+    if((svefr0 >> 20) & 0xf)
+    {
+        isa.svebf16 = true;
+    }
 
     // Instruction extensions
     if((isar0 >> 44) & 0xf)
@@ -141,11 +153,15 @@ void decode_regs(CpuIsaInfo &isa, const uint64_t isar0, const uint64_t isar1, co
     }
     if((isar1 >> 48) & 0xf)
     {
-        isa.immla = true;
+        isa.i8mm = true;
+    }
+    if((svefr0 >> 44) & 0xf)
+    {
+        isa.svei8mm = true;
     }
     if((svefr0 >> 52) & 0xf)
     {
-        isa.fmmla = true;
+        isa.svef32mm = true;
     }
 }
 
diff --git a/src/common/cpuinfo/CpuIsaInfo.h b/src/common/cpuinfo/CpuIsaInfo.h
index 1125f766dd..a2aace1b80 100644
--- a/src/common/cpuinfo/CpuIsaInfo.h
+++ b/src/common/cpuinfo/CpuIsaInfo.h
@@ -44,11 +44,13 @@ struct CpuIsaInfo
     /* Data-type extensions support */
     bool fp16{ false };
     bool bf16{ false };
+    bool svebf16{ false };
 
     /* Instruction support */
     bool dot{ false };
-    bool immla{ false };
-    bool fmmla{ false };
+    bool i8mm{ false };
+    bool svei8mm{ false };
+    bool svef32mm{ false };
 };
 
 /** Identify ISA related information through system information
diff --git a/src/common/cpuinfo/target/CpuInfoSveUtils.cpp b/src/common/cpuinfo/target/CpuInfoSveUtils.cpp
deleted file mode 100644
index 750a1b01d1..0000000000
--- a/src/common/cpuinfo/target/CpuInfoSveUtils.cpp
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#include "src/common/cpuinfo/target/CpuInfoSveUtils.h"
-
-namespace arm_compute
-{
-namespace cpuinfo
-{
-uint64_t get_sve_feature_reg()
-{
-    uint64_t reg = 0;
-#if defined(ENABLE_SVE)
-    __asm __volatile("MRS %0, ID_AA64ZFR0_EL1"
-                     : "=r"(reg));
-#endif /* defined(DENABLE_SVE) */
-    return reg;
-}
-} // namespace cpuinfo
-} // namespace arm_compute
diff --git a/src/common/cpuinfo/target/CpuInfoSveUtils.h b/src/common/cpuinfo/target/CpuInfoSveUtils.h
deleted file mode 100644
index 73862b131c..0000000000
--- a/src/common/cpuinfo/target/CpuInfoSveUtils.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef SRC_COMMON_CPUINFO_TARGET_CPUINFO_SVE_UTILS_H
-#define SRC_COMMON_CPUINFO_TARGET_CPUINFO_SVE_UTILS_H
-
-#include <cstdint>
-
-namespace arm_compute
-{
-namespace cpuinfo
-{
-/** Returns the contents of the SVE feature register (ID_AA64ZFR0_EL1)
- *
- * @return uint64_t The value of the register
- */
-uint64_t get_sve_feature_reg();
-} // namespace cpuinfo
-} // namespace arm_compute
-#endif /* SRC_COMMON_CPUINFO_CPUISAINFO_H */