1 files changed, 48 insertions, 35 deletions

diff --git a/src/common/cpuinfo/CpuModel.cpp b/src/common/cpuinfo/CpuModel.cpp
index 9f4d5d1433..8c3f8a8faf 100644
--- a/src/common/cpuinfo/CpuModel.cpp
+++ b/src/common/cpuinfo/CpuModel.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021-2023 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -29,12 +29,12 @@ namespace cpuinfo
 {
 std::string cpu_model_to_string(CpuModel model)
 {
-    switch(model)
+    switch (model)
     {
 #define X(MODEL)          \
-case CpuModel::MODEL: \
-    return #MODEL;
-            ARM_COMPUTE_CPU_MODEL_LIST
+    case CpuModel::MODEL: \
+        return #MODEL;
+        ARM_COMPUTE_CPU_MODEL_LIST
 #undef X
         default:
         {
@@ -45,13 +45,16 @@ case CpuModel::MODEL: \
 
 bool model_supports_fp16(CpuModel model)
 {
-    switch(model)
+    switch (model)
     {
         case CpuModel::GENERIC_FP16:
         case CpuModel::GENERIC_FP16_DOT:
         case CpuModel::A55r1:
+        case CpuModel::A510:
         case CpuModel::X1:
-        case CpuModel::KLEIN:
+        case CpuModel::V1:
+        case CpuModel::A64FX:
+        case CpuModel::N1:
             return true;
         default:
             return false;
@@ -60,23 +63,14 @@ bool model_supports_fp16(CpuModel model)
 
 bool model_supports_dot(CpuModel model)
 {
-    switch(model)
+    switch (model)
     {
         case CpuModel::GENERIC_FP16_DOT:
         case CpuModel::A55r1:
+        case CpuModel::A510:
         case CpuModel::X1:
-        case CpuModel::KLEIN:
-            return true;
-        default:
-            return false;
-    }
-}
-
-bool model_supports_sve(CpuModel model)
-{
-    switch(model)
-    {
-        case CpuModel::KLEIN:
+        case CpuModel::V1:
+        case CpuModel::N1:
             return true;
         default:
             return false;
@@ -92,17 +86,17 @@ CpuModel midr_to_model(uint32_t midr)
     const int variant     = (midr >> 20) & 0xF;
     const int cpunum      = (midr >> 4) & 0xFFF;
 
-    if(implementer == 0x41) // Arm CPUs
+    // Only CPUs we have code paths for are detected.  All other CPUs can be safely classed as "GENERIC"
+    if (implementer == 0x41) // Arm CPUs
     {
-        // Only CPUs we have code paths for are detected.  All other CPUs can be safely classed as "GENERIC"
-        switch(cpunum)
+        switch (cpunum)
         {
             case 0xd03: // A53
             case 0xd04: // A35
                 model = CpuModel::A53;
                 break;
             case 0xd05: // A55
-                if(variant != 0)
+                if (variant != 0)
                 {
                     model = CpuModel::A55r1;
                 }
@@ -115,7 +109,7 @@ CpuModel midr_to_model(uint32_t midr)
                 model = CpuModel::A73;
                 break;
             case 0xd0a: // A75
-                if(variant != 0)
+                if (variant != 0)
                 {
                     model = CpuModel::GENERIC_FP16_DOT;
                 }
@@ -124,9 +118,11 @@ CpuModel midr_to_model(uint32_t midr)
                     model = CpuModel::GENERIC_FP16;
                 }
                 break;
+            case 0xd0c: // N1
+                model = CpuModel::N1;
+                break;
             case 0xd06: // A65
             case 0xd0b: // A76
-            case 0xd0c: // N1
             case 0xd0d: // A77
             case 0xd0e: // A76AE
             case 0xd41: // A78
@@ -134,21 +130,39 @@ CpuModel midr_to_model(uint32_t midr)
             case 0xd4a: // E1
                 model = CpuModel::GENERIC_FP16_DOT;
                 break;
+            case 0xd40: // V1
+                model = CpuModel::V1;
+                break;
             case 0xd44: // X1
                 model = CpuModel::X1;
                 break;
-            case 0xd46:
-                model = CpuModel::KLEIN;
+            case 0xd46: // A510
+            case 0xd80: // A520
+                model = CpuModel::A510;
+                break;
+            case 0xd15: // R82
+                model = CpuModel::A55r1;
+                break;
+            default:
+                model = CpuModel::GENERIC;
+                break;
+        }
+    }
+    else if (implementer == 0x46)
+    {
+        switch (cpunum)
+        {
+            case 0x001: // A64FX
+                model = CpuModel::A64FX;
                 break;
             default:
                 model = CpuModel::GENERIC;
                 break;
         }
     }
-    else if(implementer == 0x48)
+    else if (implementer == 0x48)
     {
-        // Only CPUs we have code paths for are detected.  All other CPUs can be safely classed as "GENERIC"
-        switch(cpunum)
+        switch (cpunum)
         {
             case 0xd40: // A76
                 model = CpuModel::GENERIC_FP16_DOT;
@@ -158,10 +172,9 @@ CpuModel midr_to_model(uint32_t midr)
                 break;
         }
     }
-    else if(implementer == 0x51)
+    else if (implementer == 0x51)
     {
-        // Only CPUs we have code paths for are detected.  All other CPUs can be safely classed as "GENERIC"
-        switch(cpunum)
+        switch (cpunum)
         {
             case 0x800: // A73
                 model = CpuModel::A73;
@@ -187,4 +200,4 @@ CpuModel midr_to_model(uint32_t midr)
     return model;
 }
 } // namespace cpuinfo
-} // namespace arm_compute
\ No newline at end of file
+} // namespace arm_compute