diff options
Diffstat (limited to 'docs/user_guide')
| -rw-r--r-- | docs/user_guide/advanced.dox | 139 | ||||
| -rw-r--r-- | docs/user_guide/conv2d_heuristic.dox | 89 | ||||
| -rw-r--r-- | docs/user_guide/data_layout.dox | 64 | ||||
| -rw-r--r-- | docs/user_guide/data_type.dox | 47 | ||||
| -rw-r--r-- | docs/user_guide/errata.dox | 136 | ||||
| -rw-r--r-- | docs/user_guide/how_to_build_and_run_examples.dox | 569 | ||||
| -rw-r--r-- | docs/user_guide/introduction.dox | 120 | ||||
| -rw-r--r-- | docs/user_guide/library.dox | 615 | ||||
| -rw-r--r-- | docs/user_guide/operator_list.dox | 3258 | ||||
| -rw-r--r-- | docs/user_guide/release_version_and_change_log.dox | 1719 | ||||
| -rw-r--r-- | docs/user_guide/tests.dox | 385 |
11 files changed, 7141 insertions, 0 deletions
diff --git a/docs/user_guide/advanced.dox b/docs/user_guide/advanced.dox new file mode 100644 index 0000000000..2b9e0d02f7 --- /dev/null +++ b/docs/user_guide/advanced.dox @@ -0,0 +1,139 @@ +/// +/// Copyright (c) 2017-2021 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** @page advanced Advanced + +@tableofcontents + +@section S1_8_cl_tuner OpenCL Tuner + +The OpenCL tuner, a.k.a. CLTuner, is a module of Arm Compute Library that can improve the performance of the OpenCL kernels tuning the Local-Workgroup-Size (LWS). +The optimal LWS for each unique OpenCL kernel configuration is stored in a table. This table can be either imported or exported from/to a file. +The OpenCL tuner runs the same OpenCL kernel for a range of local workgroup sizes and keeps the local workgroup size of the fastest run to use in subsequent calls to the kernel. It supports three modes of tuning with different trade-offs between the time taken to tune and the kernel execution time achieved using the best LWS found. In the Exhaustive mode, it searches all the supported values of LWS. This mode takes the longest time to tune and is the most likely to find the optimal LWS. Normal mode searches a subset of LWS values to yield a good approximation of the optimal LWS. It takes less time to tune than Exhaustive mode. Rapid mode takes the shortest time to tune and finds an LWS value that is at least as good or better than the default LWS value. The mode affects only the search for the optimal LWS and has no effect when the LWS value is imported from a file. +In order for the performance numbers to be meaningful you must disable the GPU power management and set it to a fixed frequency for the entire duration of the tuning phase. + +If you wish to know more about LWS and the important role on improving the GPU cache utilization, we suggest having a look at the presentation "Even Faster CNNs: Exploring the New Class of Winograd Algorithms available at the following link: + +https://www.embedded-vision.com/platinum-members/arm/embedded-vision-training/videos/pages/may-2018-embedded-vision-summit-iodice + +Tuning a network from scratch can be long and affect considerably the execution time for the first run of your network. It is recommended for this reason to store the CLTuner's result in a file to amortize this time when you either re-use the same network or the functions with the same configurations. The tuning is performed only once for each OpenCL kernel. + +CLTuner looks for the optimal LWS for each unique OpenCL kernel configuration. Since a function (i.e. Convolution Layer, Pooling Layer, Fully Connected Layer ...) can be called multiple times but with different parameters, we associate an "id" (called "config_id") to each kernel to distinguish the unique configurations. + + #Example: 2 unique Matrix Multiply configurations +@code{.cpp} + TensorShape a0 = TensorShape(32,32); + TensorShape b0 = TensorShape(32,32); + TensorShape c0 = TensorShape(32,32); + TensorShape a1 = TensorShape(64,64); + TensorShape b1 = TensorShape(64,64); + TensorShape c1 = TensorShape(64,64); + + Tensor a0_tensor; + Tensor b0_tensor; + Tensor c0_tensor; + Tensor a1_tensor; + Tensor b1_tensor; + Tensor c1_tensor; + + a0_tensor.allocator()->init(TensorInfo(a0, 1, DataType::F32)); + b0_tensor.allocator()->init(TensorInfo(b0, 1, DataType::F32)); + c0_tensor.allocator()->init(TensorInfo(c0, 1, DataType::F32)); + a1_tensor.allocator()->init(TensorInfo(a1, 1, DataType::F32)); + b1_tensor.allocator()->init(TensorInfo(b1, 1, DataType::F32)); + c1_tensor.allocator()->init(TensorInfo(c1 1, DataType::F32)); + + CLGEMM gemm0; + CLGEMM gemm1; + + // Configuration 0 + gemm0.configure(&a0, &b0, nullptr, &c0, 1.0f, 0.0f); + + // Configuration 1 + gemm1.configure(&a1, &b1, nullptr, &c1, 1.0f, 0.0f); +@endcode + +@subsection S1_8_1_cl_tuner_how_to How to use it + +All the graph examples in the Compute Library's folder "examples" and the arm_compute_benchmark accept an argument to enable the OpenCL tuner and an argument to export/import the LWS values to/from a file + + #Enable CL tuner + ./graph_mobilenet --enable-tuner –-target=CL + ./arm_compute_benchmark --enable-tuner + + #Export/Import to/from a file + ./graph_mobilenet --enable-tuner --target=CL --tuner-file=acl_tuner.csv + ./arm_compute_benchmark --enable-tuner --tuner-file=acl_tuner.csv + +If you are importing the CLTuner'results from a file, the new tuned LWS values will be appended to it. + +Either you are benchmarking the graph examples or the test cases in the arm_compute_benchmark remember to: + + -# Disable the power management + -# Keep the GPU frequency constant + -# Run multiple times the network (i.e. 10). + +If you are not using the graph API or the benchmark infrastructure you will need to manually pass a CLTuner object to CLScheduler before configuring any function. + +@code{.cpp} +CLTuner tuner; + +// Setup Scheduler +CLScheduler::get().default_init(&tuner); +@endcode + +After the first run, the CLTuner's results can be exported to a file using the method "save_to_file()". +- tuner.save_to_file("results.csv"); + +This file can be also imported using the method "load_from_file("results.csv")". +- tuner.load_from_file("results.csv"); + +@section Security Concerns +Here are some security concerns that may affect Compute Library. + +@subsection A process running under the same uid could read another process memory + +Processes running under same user ID (UID) may be able to read each other memory and running state. Hence, This can +lead to information disclosure and sensitive data can be leaked, such as the weights of the model currently executing. +This mainly affects Linux systems and it's the responsibility of the system owner to make processes secure against +this vulnerability. Moreover, the YAMA security kernel module can be used to detect and stop such a trial of hacking, +it can be selected at the kernel compile time by CONFIG_SECURITY_YAMA and configured during runtime changing the +ptrace_scope in /proc/sys/kernel/yama. + +Please refer to: https://www.kernel.org/doc/html/v4.15/admin-guide/LSM/Yama.html for more information on this regard. + +@subsection Malicious users could alter Compute Library related files + +Extra care must be taken in order to reduce the posibility of a user altering sensitive files. CLTuner files +should be protected by arbitrary writes since this can lead Compute Library to crash or waste all system's resources. + +@subsection Various concerns + +Sensitive applications that use Compute Library should consider posible attack vectors such as shared library hooking, +information leakage from the underlying OpenCL driver or previous excecution and running arbitrary networks that consume +all the available resources on the system, leading to denial of service. + +*/ +} // namespace
\ No newline at end of file diff --git a/docs/user_guide/conv2d_heuristic.dox b/docs/user_guide/conv2d_heuristic.dox new file mode 100644 index 0000000000..edd24a3d36 --- /dev/null +++ b/docs/user_guide/conv2d_heuristic.dox @@ -0,0 +1,89 @@ +/// +/// Copyright (c) 2023 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// + +namespace arm_compute +{ +/** +@page conv2d_heuristic Convolution 2D heuristic + +@section conv2d_heuristic_algorithms_used Convolution 2D heuristic: algorithm selection + +The convolution 2D (in short, conv2D) is certainly one of the most compute intensive and performance critical operators in ML workloads. +This operator can be implemented with different algorithms, which differ in terms of accuracy, kernel size support, and additional memory required. +Unfortunately, it does not exist a single algorithm that can be used in all scenarios to achieve the best performance. +Therefore, the Arm Compute Library integrates an heuristic within the conv2d operators to select the most efficient algorithm, depending on input and kernel shapes and desired level of accuracy. +The heuristic depends on the target backend (either NEON™ for Arm® CPUs or OpenCL for Arm® GPUs) and the following subsections will provide the main details behind the selection of the algorithm. + +⚠ Attention: The heuristics presented in the following subsections will only refer to the NHWC data layout, which is the optimal and recommended layout for the Arm Compute Library. + +@subsection conv2d_heuristic_on_cpu Convolution 2D heuristic: Arm® Cortex®-based CPUs + +The conv2d heuristic for Arm® Cortex®-based CPUs is inside the get_convolution_method() method in the CpuConv2d function. +The algorithms used in the get_convolution_method() function are the following: +- Direct-Conv2D +- Im2Col+GeMM-based +- Indirect-GeMM (a.k.a. GEMMCONV2D) +- GeMM +- Winograd + +⚠ Attention: Winograd only works with floating-point data types (F32, F16) + +The heuristic first checks less frequent cases that we may have in ML workloads for edge devices. These cases are the following: +-# Non unit dilation: We call Im2Col+GeMM +-# Large input and kernel shapes: We call Direct-Conv2D because it is the only algorithm that does not extra additionally temporary memory +-# Small Input-Feature-Maps (IFM): In this scenario, we have found that the GeMM implementation is generally the most efficient algorithm compared to Winograd and Indirect-GeMM + +If we have a most frequent case, such as unit dilations, of larger IFM, we evaluate the following conditions instead: +-# Unit kernel size (1x1): In this scenario, the conv2d operations corresponds to a matrix multiplication and we call GeMM. +-# Winograd. Winograd only works with unit strides and supports a limited number of kernel sizes, such as 3x3, 3x1, 1x3, 5x1, 1x5 and 5x5 +-# Indirect-GeMM: It should be used in all cases expect when the kernel size is 1x1 or when the IFM is small + +If the preceding cases are not met, we will fall-back to the Im2Col+GeMM-based algorithm. + +@subsection conv2d_heuristic_on_gpu Convolution 2D heuristic: Arm® Mali™-based GPUs + +The conv2d heuristic for Arm® Mali™-based GPUs is inside the get_convolution_method() method in the ClConv2d function. + +The algorithms used in the get_convolution_method() function are the following: +- Direct-Conv2D +- Im2Col+GeMM-based +- Indirect-GeMM +- GeMM +- Winograd + +⚠ Attention: Winograd only works with floating-point data types (F32, F16) + +The heuristic first checks less frequent cases that we may have in ML workloads for edge devices. These cases are the following: +-# Non unit dilation: We call Im2Col+GeMM +-# Large input and kernel shapes: We call Direct-Conv2D because it is the only algorithm that does not extra additionally temporary memory + +In all the other cases, the GPU heuristic evaluates the suitability of Winograd and Direct-Conv2D/Indirect-Conv2D. +In particular, Winograd is adopted when the convolution parameters (kernel size and strides) are supported by the algorithm and when the IFM is not small (for example, greater than 8). +The conditions for using the Direct-Conv2D algorithms are several and we recommend you look at the heuristic directly. +In general, the Direct-Conv2D operators is used in almost all cases where kernel size is not 1x1. +The Indirect-GeMM algorithm is used in alternative to Direct-Conv2D only for Arm® Mali™-G77 GPU. +If neither Winograd nor Direct-Conv2D can be used, we will fall-back to either GeMM (when the kernel size is 1x1) or the Im2Col+GeMM-based algorithm. + +*/ +} // namespace diff --git a/docs/user_guide/data_layout.dox b/docs/user_guide/data_layout.dox new file mode 100644 index 0000000000..711b85f08c --- /dev/null +++ b/docs/user_guide/data_layout.dox @@ -0,0 +1,64 @@ +/// +/// Copyright (c) 2021-2022 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// + +namespace arm_compute +{ +/** +@page data_layout_support Data Layout Support + +@section data_layout_support_supported_data_layout Supported Data Layouts + +With regard to convolution layers, Compute Library supports the following data layouts for input and output tensors: + +- NHWC: The native layout of Compute Library that delivers the best performance where channels are in the fastest changing dimension +- NCHW: Legacy layout where width is in the fastest changing dimension +- NDHWC: New data layout for supporting 3D operators + +, where N = batch, C = channel, H = height, W = width, D = depth. + +Note: The right-most letter represents the fastest changing dimension, which is the "lower dimension". +The corresponding @ref TensorShape for each of the data layout would be initialized as: + +- NHWC: TensorShape(C, W, H, N) +- NCHW: TensorShape(W, H, C, N) +- NDHWC: TensorShape(C, W, H, D, N) + +For 2d Conv, the weight / filter tensors are arranged in 4 dimensions: Height (H), Width (W), Input channel (I), Output channel (O) +For 3d Conv, the additional Depth dimension means exactly the same as the Depth in the input / output layout. + +The layout of weight tensors change with that of the input / output tensors, and the dimensions can be mapped as: + +- Weight Height -> Height +- Weight Width -> Width +- Weight Input channel -> Channel +- Weight Output channel -> Batch + +Therefore, the corresponding weight layouts for each input / output layout are: + +- (input/output tensor) NHWC: (weight tensor) OHWI +- (input/output tensor) NCHW: (weight tensor) OIHW +- (input/output tensor) NDHWC: (weight tensor) ODHWI + +*/ +} // namespace diff --git a/docs/user_guide/data_type.dox b/docs/user_guide/data_type.dox new file mode 100644 index 0000000000..7083270a07 --- /dev/null +++ b/docs/user_guide/data_type.dox @@ -0,0 +1,47 @@ +/// +/// Copyright (c) 2021 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** +@page data_type_support Data Type Support + +@tableofcontents + +@section data_type_support_supported_data_type Supported Data Types + +Compute Library supports the following list of data types. More detailed information +can be found from the documentation of each operator since the data types supported +by each operator vary. + +- BFLOAT16: 16-bit non-standard brain floating point +- QASYMM8: 8-bit unsigned asymmetric quantized +- QASYMM8_SIGNED: 8-bit signed asymmetric quantized +- QSYMM8_PER_CHANNEL: 8-bit signed symmetric quantized (Used for the weights) +- QSYMM8: 8-bit unsigned symmetric quantized +- QSYMM16: 16-bit unsigned symmetric quantized +- F32: 32-bit single precision floating point +- F16: 16-bit half precision floating point +- S32: 32-bit signed integer +*/ +} // namespace diff --git a/docs/user_guide/errata.dox b/docs/user_guide/errata.dox new file mode 100644 index 0000000000..056e45a432 --- /dev/null +++ b/docs/user_guide/errata.dox @@ -0,0 +1,136 @@ +/// +/// Copyright (c) 2019-2023 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** +@page errata Errata + +@tableofcontents + +@section S7_1_errata Errata + +- (COMPMID-6493) Crash when running Arm Compute Library compiled for SVE2 on a computer that support SVE only. + - Versions: >= v21.02 && <=v23.08 + - OSs: Linux, Android. + - Conditions: + - Compile the latest Arm Compute Library for SVE2 (arch=armv8.6-a-sve2). + - multi_isa = 0 + - Device with SVE but without SVE2 support. + - Result: + - Crash due to illegal instruction. + - To run SVE only, build with arch="armv8.2-a-sve", arch="armv8.6-a-sve", or with multi_isa=1. + +- (COMPMID-6404) Under certain conditions, CLTile may produce incorrect result. + - Versions: >= v19.02 && < v23.08 + - OSs: Linux, Android. + - Conditions: + - The size of the lowest dimension of the input tensor is greater than 16 bytes. + - The size of the lowest dimension of the input tensor is not a multiple of 16. + - Result: + - Incorrect result is produced. + +- (COMPMID-6271) Under certain conditions, CLArgMinMaxLayer validation tests may fail + - Versions Affected: >= v20.02 && < v23.08 + - OSs Affected: Linux + - Conditions: + - Backend: OpenCL + - Axis == 0 + - Result: + - Sporadic mismatches only on certain devices + +- (COMPMID-5324) Issue identified with direct and depthwise convolutions for certain Arm® Mali™ DDK versions. + - Versions Affected: < v22.08 + - Conditions: + - Arm® Mali™ DDK Versions : >= r23p0 && <= r38p0 + - Mali™ GPUs: Bifrost GPU family with the exception of G71 + - Backend: OpenCL + - Build options Include : "cl-fast-relaxed-math" + - Result: Reduced accuracy issue, while using direct and depthwise convolutions fused with LU_BOUNDED_RELU activation. + +- (COMPMID-5134) An issue has been identified when running the graph_deepspeech_v0_4_1 graph example. + - Versions Affected: >= v21.08 + - Conditions: + - Data type input: F32 + - Backend: OpenCL + - Result: The execution of the graph_deepspeech_v0_4_1 could fail on OpenCL backend for systems with a small RAM. The issue is due to the extra temporary memory required to reshape the network weights + +- (COMPMID-4013) Experimented performance regressions for some networks on OpenCL when using Arm® Mali™ DDK r8p0 + - Versions Affected: v21.05 + - OSs Affected: All + - Conditions: + - Arm® Mali™ DDK r8p0 + +- (COMPMID-5146) Under certain conditions, CLFullyConnectedLayer quantized tests may fail due to an issue in the test framework. + - Versions Affected: v21.02 + - OSs Affected: Linux + - Conditions: + - armv7a architecture + - release mode + - asserts enabled + +- (COMPMID-4367) Performance regression in Convolution Layer OpenCL backend on Mali™ G77 when QSYMM8_PER_CHANNEL is used as weights' data type. + - Versions Affected: >= v20.11 && < v21.08 + - OSs Affected: All + - Conditions: + - Mali™ G77 + - Convolution Layer in use + - OpenCL backend + - Convolution Layer uses QSYMM8_PER_CHANNEL as the data type of its weight + +- (COMPMID-4306) A wrong test configuration has been found in CLGEMMMatrixMultiplyReshapedOnlyRHS set of tests. + - Versions Affected: >= v20.11 && < v21.05 + - Conditions: + - Data type input: F32/F16 + - Fused bounded relu activation with coefficient 'a' being negative + +- (COMPMID-5135) Under certain conditions, the validation test case 'CL/DirectConvolutionLayer/Float/FP32/RunSmall9x9\@InputShape=32x37x3x4:StrideX=1:StrideY=1:PadX=0:PadY=0:KernelSize=9:NumKernels=1:DataType=F32:ActivationInfo=LU_BOUNDED_RELU:DataLayout=NHWC' may fail. + - Versions Affected: >= v20.08 + - Conditions: + - The validation suite has to run in nightly mode and execute 40k+ test cases before the test mentioned above + +- (COMPMID-5136) Under certain conditions, benchmark examples can hang when OpenCL profiling queues are enabled. + - Versions Affected: >= v19.11 + - OSs Affected: Linux + - Conditions: + - Arm® Mali™ DDK r1p0 - r8p0, and + - Linux kernel >= 4.4 + +- (COMPMID-5137) On Android with armv8a/armv8.2-a architecture, Arm® Neon™ validation tests can fail when compiled using Android Ndk + >= r18b in debug mode (https://github.com/android/ndk/issues/1135). + - Versions Affected: >= v19.11 + - OSs Affected: Android + - Conditions: + - armv8a/armv8.2-a architecture, and + - Compiled using Android NDK >= r18b in debug mode. + +- (COMPMID-4288) An issue has been identified with CLCast. + - Versions Affected: >= v18.11 && < v21.05 + - Conditions: + - Data type input: F32 + - Data type output: All integer types + - Conversion policy: SATURATE + - Result: OpenCL backend will always wrap around instead of saturating for out-of-range inputs + +*/ +} // namespace diff --git a/docs/user_guide/how_to_build_and_run_examples.dox b/docs/user_guide/how_to_build_and_run_examples.dox new file mode 100644 index 0000000000..0b8a23b368 --- /dev/null +++ b/docs/user_guide/how_to_build_and_run_examples.dox @@ -0,0 +1,569 @@ +/// +/// Copyright (c) 2017-2024 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** @page how_to_build How to Build and Run Examples + +@tableofcontents + +@section S1_1_build_options Build options + +scons 2.3 or above is required to build the library. +To see the build options available simply run ```scons -h``` + +@section S1_2_linux Building for Linux + +@subsection S1_2_1_library How to build the library ? + +For Linux, the library was successfully built and tested using the following Linaro GCC toolchain: + + - gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf + - gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu + +To cross-compile the library in debug mode, with Arm® Neon™ only support, for Linux 32bit: + + scons Werror=1 -j8 debug=1 neon=1 opencl=0 os=linux arch=armv7a + +To cross-compile the library in asserts mode, with OpenCL only support, for Linux 64bit: + + scons Werror=1 -j8 debug=0 asserts=1 neon=0 opencl=1 embed_kernels=1 os=linux arch=armv8a + +You can also compile the library natively on an Arm device by using <b>build=native</b>: + + scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=linux arch=armv8a build=native + scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=linux arch=armv7a build=native + +@note g++ for Arm is mono-arch, therefore if you want to compile for Linux 32bit on a Linux 64bit platform you will have to use a cross compiler. + +For example on a 64bit Debian based system you would have to install <b>g++-arm-linux-gnueabihf</b> + + apt-get install g++-arm-linux-gnueabihf + +Then run + + scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=linux arch=armv7a build=cross_compile + +or simply remove the build parameter as build=cross_compile is the default value: + + scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=linux arch=armv7a + +@subsection S1_2_2_examples How to manually build the examples ? + +The examples get automatically built by scons as part of the build process of the library described above. This section just describes how you can build and link your own application against our library. + +@note The following command lines assume the arm_compute libraries are present in the current directory or in the system library path. If this is not the case you can specify the location of the pre-built libraries with the compiler option -L. When building the OpenCL example the commands below assume that the CL headers are located in the include folder where the command is executed. + +To cross compile a Arm® Neon™ example for Linux 32bit: + + arm-linux-gnueabihf-g++ examples/neon_cnn.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -mfpu=neon -L. -larm_compute -o neon_cnn + +To cross compile a Arm® Neon™ example for Linux 64bit: + + aarch64-linux-gnu-g++ examples/neon_cnn.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -L. -larm_compute -o neon_cnn + +(notice the only difference with the 32 bit command is that we don't need the -mfpu option and the compiler's name is different) + +To cross compile an OpenCL example for Linux 32bit: + + arm-linux-gnueabihf-g++ examples/cl_sgemm.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -mfpu=neon -L. -larm_compute -o cl_sgemm -DARM_COMPUTE_CL + +To cross compile an OpenCL example for Linux 64bit: + + aarch64-linux-gnu-g++ examples/cl_sgemm.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -L. -larm_compute -o cl_sgemm -DARM_COMPUTE_CL + +(notice the only difference with the 32 bit command is that we don't need the -mfpu option and the compiler's name is different) + +To cross compile the examples with the Graph API, such as graph_lenet.cpp, you need to link the examples against arm_compute_graph.so too. + +i.e. to cross compile the "graph_lenet" example for Linux 32bit: + + arm-linux-gnueabihf-g++ examples/graph_lenet.cpp utils/Utils.cpp utils/GraphUtils.cpp utils/CommonGraphOptions.cpp -I. -Iinclude -std=c++14 -mfpu=neon -L. -larm_compute_graph -larm_compute -Wl,--allow-shlib-undefined -o graph_lenet + +i.e. to cross compile the "graph_lenet" example for Linux 64bit: + + aarch64-linux-gnu-g++ examples/graph_lenet.cpp utils/Utils.cpp utils/GraphUtils.cpp utils/CommonGraphOptions.cpp -I. -Iinclude -std=c++14 -L. -larm_compute_graph -larm_compute -Wl,--allow-shlib-undefined -o graph_lenet + +(notice the only difference with the 32 bit command is that we don't need the -mfpu option and the compiler's name is different) + +@note If compiling using static libraries, this order must be followed when linking: arm_compute_graph_static, arm_compute + +To compile natively (i.e directly on an Arm device) for Arm® Neon™ for Linux 32bit: + + g++ examples/neon_cnn.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -mfpu=neon -larm_compute -o neon_cnn + +To compile natively (i.e directly on an Arm device) for Arm® Neon™ for Linux 64bit: + + g++ examples/neon_cnn.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute -o neon_cnn + +(notice the only difference with the 32 bit command is that we don't need the -mfpu option) + +To compile natively (i.e directly on an Arm device) for OpenCL for Linux 32bit or Linux 64bit: + + g++ examples/cl_sgemm.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute -o cl_sgemm -DARM_COMPUTE_CL + +To compile natively the examples with the Graph API, such as graph_lenet.cpp, you need to link the examples against arm_compute_graph.so too. + +i.e. to natively compile the "graph_lenet" example for Linux 32bit: + + g++ examples/graph_lenet.cpp utils/Utils.cpp utils/GraphUtils.cpp utils/CommonGraphOptions.cpp -I. -Iinclude -std=c++14 -mfpu=neon -L. -larm_compute_graph -larm_compute -Wl,--allow-shlib-undefined -o graph_lenet + +i.e. to natively compile the "graph_lenet" example for Linux 64bit: + + g++ examples/graph_lenet.cpp utils/Utils.cpp utils/GraphUtils.cpp utils/CommonGraphOptions.cpp -I. -Iinclude -std=c++14 -L. -larm_compute_graph -larm_compute -Wl,--allow-shlib-undefined -o graph_lenet + +(notice the only difference with the 32 bit command is that we don't need the -mfpu option) + +@note If compiling using static libraries, this order must be followed when linking: arm_compute_graph_static, arm_compute + +@note These two commands assume libarm_compute.so is available in your library path, if not add the path to it using -L (e.g. -Llib/linux-armv8a-neon-cl-asserts/) +@note You might need to export the path to OpenCL library as well in your LD_LIBRARY_PATH if Compute Library was built with OpenCL enabled. + +To run the built executable simply run: + + LD_LIBRARY_PATH=build ./neon_cnn + +or + + LD_LIBRARY_PATH=build ./cl_sgemm + +@note Examples accept different types of arguments, to find out what they are run the example with \a --help as an argument. If no arguments are specified then random values will be used to execute the graph. + +For example: + + LD_LIBRARY_PATH=. ./graph_lenet --help + +Below is a list of the common parameters among the graph examples : +@snippet utils/CommonGraphOptions.h Common graph examples parameters + +@subsection S1_2_3_sve Build for SVE or SVE2 + +In order to build for SVE or SVE2 you need a compiler that supports them. You can find more information in the following these links: + -# GCC: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/sve-support + -# LLVM: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/llvm-toolchain/sve-support + +@note You the need to indicate the toolchains using the scons "toolchain_prefix" parameter. + +An example build command with SVE is: + + scons arch=armv8.2-a-sve os=linux build_dir=arm64 -j55 standalone=0 opencl=0 openmp=0 validation_tests=1 neon=1 cppthreads=1 toolchain_prefix=aarch64-none-linux-gnu- + +@subsection S1_2_4_sme Build for SME2 + +In order to build for SME2 you need to use a compiler that supports SVE2 and enable SVE2 in the build as well. + +@note You the need to indicate the toolchains using the scons "toolchain_prefix" parameter. + +An example build command with SME2 is: + + scons arch=armv8.6-a-sve2-sme2 os=linux build_dir=arm64 -j55 standalone=0 opencl=0 openmp=0 validation_tests=1 neon=1 cppthreads=1 toolchain_prefix=aarch64-none-linux-gnu- + +@subsection S1_2_5_clang_build_linux Building with LLVM+Clang Natively on Linux + +The library can be built with LLVM+Clang by specifying CC and CXX environment variables appropriately as below. The **minimum** supported clang version is 11, as LLVM 11 introduces SVE/SVE2 VLA intrinsics: https://developer.arm.com/Tools%20and%20Software/LLVM%20Toolchain#Supported-Devices. + + CC=clang CXX=clang++ <build command> + +Or, if the environment has multiple clang versions: + + CC=clang-16 CXX=clang++-16 + +Examples for different build tools look like below. + +(experimental) CMake: + + mkdir build + cd build + CC=clang CXX=clang++ cmake .. -DCMAKE_BUILD_TYPE=Release -DARM_COMPUTE_OPENMP=1 -DARM_COMPUTE_WERROR=0 -DARM_COMPUTE_BUILD_EXAMPLES=1 -DARM_COMPUTE_BUILD_TESTING=1 -DCMAKE_INSTALL_LIBDIR=. + CC=clang CXX=clang++ cmake --build . -j32 + +(experimental) Bazel: + + CC=clang CXX=clang++ bazel build //... + +Scons: + + CC=clang CXX=clang++ scons -j32 Werror=1 debug=0 neon=1 openmp=1 cppthreads=1 os=linux arch=armv8a multi_isa=1 build=native validation_tests=1 + +Configurations supported are limited to the configurations supported by our CMake, Bazel and Multi ISA Scons builds. For more details on CMake and Bazel builds, please see @ref S1_8_experimental_builds + +@section S1_3_android Building for Android + +For Android, the library was successfully built and tested using Google's standalone toolchains: + - clang++ from NDK r20b for armv8a + - clang++ from NDK r20b for armv8.2-a with FP16 support + +(From 23.02, NDK >= r20b is highly recommended) For NDK r18 or older, here is a guide to <a href="https://developer.android.com/ndk/guides/standalone_toolchain.html">create your Android standalone toolchains from the NDK</a>: +- Download the NDK r18b from here: https://developer.android.com/ndk/downloads/index.html to directory $NDK +- Make sure you have Python 2.7 installed on your machine. +- Generate the 32 and/or 64 toolchains by running the following commands to your toolchain directory $MY_TOOLCHAINS: + + $NDK/build/tools/make_standalone_toolchain.py --arch arm64 --install-dir $MY_TOOLCHAINS/aarch64-linux-android-ndk-r18b --stl libc++ --api 21 + + $NDK/build/tools/make_standalone_toolchain.py --arch arm --install-dir $MY_TOOLCHAINS/arm-linux-android-ndk-r18b --stl libc++ --api 21 + +For NDK r19 or newer, you can directly <a href="https://developer.android.com/ndk/downloads">Download</a> the NDK package for your development platform, without the need to launch the make_standalone_toolchain.py script. You can find all the prebuilt binaries inside $NDK/toolchains/llvm/prebuilt/$OS_ARCH/bin/. + +@parblock +@attention The building script will look for a binary named "aarch64-linux-android-clang++", while the prebuilt binaries will have their API version as a suffix to their filename (e.g. "aarch64-linux-android21-clang++"). You can instruct scons to use the correct version by using a combination of the toolchain_prefix and the "CC" "CXX" environment variables. +@attention For this particular example, you can specify: + + CC=clang CXX=clang++ scons toolchain_prefix=aarch64-linux-android21- + +@attention or: + + CC=aarch64-linux-android21-clang CXX=aarch64-linux-android21-clang++ scons toolchain_prefix="" + +@endparblock + +@parblock +@attention We used to use gnustl but as of NDK r17 it is deprecated so we switched to libc++ +@endparblock + +@note Make sure to add the toolchains to your PATH: + + export PATH=$PATH:$MY_TOOLCHAINS/aarch64-linux-android-ndk-r18b/bin:$MY_TOOLCHAINS/arm-linux-android-ndk-r18b/bin + +@subsection S1_3_1_library How to build the library ? + +To cross-compile the library in debug mode, with Arm® Neon™ only support, for Android 32bit: + + CXX=clang++ CC=clang scons Werror=1 -j8 debug=1 neon=1 opencl=0 os=android arch=armv7a + +To cross-compile the library in asserts mode, with OpenCL only support, for Android 64bit: + + CXX=clang++ CC=clang scons Werror=1 -j8 debug=0 asserts=1 neon=0 opencl=1 embed_kernels=1 os=android arch=armv8a + +@subsection S1_3_2_examples How to manually build the examples ? + +The examples get automatically built by scons as part of the build process of the library described above. This section just describes how you can build and link your own application against our library. + +@note The following command lines assume the arm_compute libraries are present in the current directory or in the system library path. If this is not the case you can specify the location of the pre-built libraries with the compiler option -L. When building the OpenCL example the commands below assume that the CL headers are located in the include folder where the command is executed. + +Once you've got your Android standalone toolchain built and added to your path you can do the following: + +To cross compile a Arm® Neon™ example: + + #32 bit: + arm-linux-androideabi-clang++ examples/neon_cnn.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute-static -L. -o neon_cnn_arm -static-libstdc++ -pie + #64 bit: + aarch64-linux-android-clang++ examples/neon_cnn.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute-static -L. -o neon_cnn_aarch64 -static-libstdc++ -pie + +To cross compile an OpenCL example: + + #32 bit: + arm-linux-androideabi-clang++ examples/cl_sgemm.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute-static -L. -o cl_sgemm_arm -static-libstdc++ -pie -DARM_COMPUTE_CL + #64 bit: + aarch64-linux-android-clang++ examples/cl_sgemm.cpp utils/Utils.cpp -I. -Iinclude -std=c++14 -larm_compute-static -L. -o cl_sgemm_aarch64 -static-libstdc++ -pie -DARM_COMPUTE_CL + +To cross compile the examples with the Graph API, such as graph_lenet.cpp, you need to link the library arm_compute_graph also. + + #32 bit: + arm-linux-androideabi-clang++ examples/graph_lenet.cpp utils/Utils.cpp utils/GraphUtils.cpp utils/CommonGraphOptions.cpp -I. -Iinclude -std=c++14 -Wl,--whole-archive -larm_compute_graph-static -Wl,--no-whole-archive -larm_compute-static -L. -o graph_lenet_arm -static-libstdc++ -pie -DARM_COMPUTE_CL + #64 bit: + aarch64-linux-android-clang++ examples/graph_lenet.cpp utils/Utils.cpp utils/GraphUtils.cpp utils/CommonGraphOptions.cpp -I. -Iinclude -std=c++14 -Wl,--whole-archive -larm_compute_graph-static -Wl,--no-whole-archive -larm_compute-static -L. -o graph_lenet_aarch64 -static-libstdc++ -pie -DARM_COMPUTE_CL + +@note Due to some issues in older versions of the Arm® Mali™ OpenCL DDK (<= r13p0), we recommend to link arm_compute statically on Android. +@note When linked statically the arm_compute_graph library currently needs the --whole-archive linker flag in order to work properly + +Then you need to do is upload the executable and the shared library to the device using ADB: + + adb push neon_cnn_arm /data/local/tmp/ + adb push cl_sgemm_arm /data/local/tmp/ + adb push gc_absdiff_arm /data/local/tmp/ + adb shell chmod 777 -R /data/local/tmp/ + +And finally to run the example: + + adb shell /data/local/tmp/neon_cnn_arm + adb shell /data/local/tmp/cl_sgemm_arm + adb shell /data/local/tmp/gc_absdiff_arm + +For 64bit: + + adb push neon_cnn_aarch64 /data/local/tmp/ + adb push cl_sgemm_aarch64 /data/local/tmp/ + adb push gc_absdiff_aarch64 /data/local/tmp/ + adb shell chmod 777 -R /data/local/tmp/ + +And finally to run the example: + + adb shell /data/local/tmp/neon_cnn_aarch64 + adb shell /data/local/tmp/cl_sgemm_aarch64 + adb shell /data/local/tmp/gc_absdiff_aarch64 + +@note Examples accept different types of arguments, to find out what they are run the example with \a --help as an argument. If no arguments are specified then random values will be used to execute the graph. + +For example: + adb shell /data/local/tmp/graph_lenet --help + +In this case the first argument of LeNet (like all the graph examples) is the target (i.e 0 to run on Neon™, 1 to run on OpenCL if available, 2 to run on OpenCL using the CLTuner), the second argument is the path to the folder containing the npy files for the weights and finally the third argument is the number of batches to run. + +@section S1_4_macos Building for macOS + +The library was successfully natively built for Apple Silicon under macOS 11.1 using clang v12.0.0. + +To natively compile the library with accelerated CPU support: + + scons Werror=1 -j8 neon=1 opencl=0 os=macos arch=armv8a build=native + +@note Initial support disables feature discovery through HWCAPS and thread scheduling affinity controls + +@section S1_5_bare_metal Building for bare metal + +For bare metal, the library was successfully built using linaro's latest (gcc-linaro-6.3.1-2017.05) bare metal toolchains: + - arm-eabi for armv7a + - aarch64-elf for armv8a + +Download linaro for <a href="https://releases.linaro.org/components/toolchain/binaries/6.3-2017.05/arm-eabi/">armv7a</a> and <a href="https://releases.linaro.org/components/toolchain/binaries/6.3-2017.05/aarch64-elf/">armv8a</a>. + +@note Make sure to add the toolchains to your PATH: export PATH=$PATH:$MY_TOOLCHAINS/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-elf/bin:$MY_TOOLCHAINS/gcc-linaro-6.3.1-2017.05-x86_64_arm-eabi/bin + +@subsection S1_5_1_library How to build the library ? + +To cross-compile the library with Arm® Neon™ support for baremetal armv8a: + + scons Werror=1 -j8 debug=0 neon=1 opencl=0 os=bare_metal arch=armv8a build=cross_compile cppthreads=0 openmp=0 standalone=1 + +@subsection S1_5_2_examples How to manually build the examples ? + +Examples are disabled when building for bare metal. If you want to build the examples you need to provide a custom bootcode depending on the target architecture and link against the compute library. More information about bare metal bootcode can be found <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0527a/index.html">here</a>. + +@section S1_6_windows_host Building on a Windows® host system (cross-compile) + +Using `scons` directly from the Windows® command line is known to cause +problems. The reason seems to be that if `scons` is setup for cross-compilation +it gets confused about Windows® style paths (using backslashes). Thus it is +recommended to follow one of the options outlined below. + +@subsection S1_6_1_ubuntu_on_windows Bash on Ubuntu on Windows® (cross-compile) + +The best and easiest option is to use +<a href="https://msdn.microsoft.com/en-gb/commandline/wsl/about">Ubuntu on Windows®</a>. +This feature is still marked as *beta* and thus might not be available. +However, if it is building the library is as simple as opening a *Bash on +Ubuntu on Windows®* shell and following the general guidelines given above. + +@subsection S1_6_2_cygwin Cygwin (cross-compile) + +If the Windows® subsystem for Linux is not available <a href="https://www.cygwin.com/">Cygwin</a> +can be used to install and run `scons`, the minimum Cygwin version must be 3.0.7 or later. In addition +to the default packages installed by Cygwin `scons` has to be selected in the installer. (`git` might +also be useful but is not strictly required if you already have got the source +code of the library.) Linaro provides pre-built versions of +<a href="http://releases.linaro.org/components/toolchain/binaries/">GCC cross-compilers</a> +that can be used from the Cygwin terminal. When building for Android the +compiler is included in the Android standalone toolchain. After everything has +been set up in the Cygwin terminal the general guide on building the library +can be followed. + +@subsection S1_6_3_WoA Windows® on Arm™ (native build) + + Native builds on Windows® are experimental and some features from the library interacting with the OS are missing. + +It's possible to build Compute Library natively on a Windows® system running on Arm™. + +Windows® on Arm™ (WoA) systems provide compatibility emulating x86 binaries on aarch64. Unfortunately Visual Studio 2022 does not work on aarch64 systems because it's an x86_64bit application and these binaries cannot be exectuted on WoA yet. + +Because we cannot use Visual Studio to build Compute Library we have to set up a native standalone toolchain to compile C++ code for arm64 on Windows®. + +Native arm64 toolchain installation for WoA: +- LLVM+Clang-12 which can be downloaded from: https://github.com/llvm/llvm-project/releases/download/llvmorg-12.0.0/LLVM-12.0.0-woa64.exe +- Arm64 VC Runtime which can be downloaded from https://aka.ms/vs/17/release/vc_redist.arm64.exe + +- While full VS22 cannot be installed on WoA, we can install some components + -# Desktop development with C++ and all Arm64 components for Visual Studio, refer to: https://developer.arm.com/documentation/102528/0100/Install-Visual-Studio + -# VS22 build tools: https://visualstudio.microsoft.com/downloads/#build-tools-for-visual-studio-2022 + +There are some additional tools we need to install to build Compute Library: + +- git https://git-scm.com/download/win +- python 3 https://www.python.org/downloads/windows/ +- scons can be installed with pip install scons + +In order to use clang to build Windows® binaries natively we have to initialize the environment variables from VS22 correctly so that the compiler could find the arm64 C++ libraries. This can be done by pressing the key windows + r and running the command: + + cmd /k "C:\Program Files (x86)\Microsoft Visual Studio\2022\BuildTools\VC\Auxiliary\Build\vcvarsx86_arm64.bat" + +To build Compute Library type: + + scons opencl=0 neon=1 os=windows examples=0 validation_tests=1 benchmark_examples=0 build=native arch=armv8a Werror=0 exceptions=1 standalone=1 + +@section S1_7_cl_requirements OpenCL DDK Requirements + +@subsection S1_7_1_cl_hard_requirements Hard Requirements + +Compute Library requires OpenCL 1.1 and above with support of non uniform workgroup sizes, which is officially supported in the Arm® Mali™ OpenCL DDK r8p0 and above as an extension (respective extension flag is \a -cl-arm-non-uniform-work-group-size). + +Enabling 16-bit floating point calculations require \a cl_khr_fp16 extension to be supported. All Arm® Mali™ GPUs with compute capabilities have native support for half precision floating points. + +@subsection S1_7_2_cl_performance_requirements Performance improvements + +Integer dot product built-in function extensions (and therefore optimized kernels) are available with Arm® Mali™ OpenCL DDK r22p0 and above for the following GPUs : G71, G76. The relevant extensions are \a cl_arm_integer_dot_product_int8, \a cl_arm_integer_dot_product_accumulate_int8 and \a cl_arm_integer_dot_product_accumulate_int16. + +OpenCL kernel level debugging can be simplified with the use of printf, this requires the \a cl_arm_printf extension to be supported. + +SVM allocations are supported for all the underlying allocations in Compute Library. To enable this OpenCL 2.0 and above is a requirement. + +@section S1_8_experimental_builds Experimental Bazel and CMake builds + +In addition to the scons build the repository includes experimental Bazel and CMake builds. +These builds currently support a limited range of options. Both are similar to the scons multi_isa build. It compiles all libraries with Neon (TM) support, as well as SVE and SVE2 libraries. The build is CPU only, not including OpenCL support. Only Linux environment is targeted for now. Both were successfully built with gcc / g++ version 10.2. + +@subsection S1_8_1_bazel_build Bazel build + +@subsubsection S1_8_1_1_file_structure File structure + +File structure for all files included in the Bazel build: + + . + ├── .bazelrc + ├── BUILD + ├── WORKSPACE + ├── arm_compute + │ └── BUILD + ├── examples + │ └── BUILD + ├── include + │ └── BUILD + ├── scripts + │ ├── print_version_file.py + │ └── BUILD + ├── src + │ └── BUILD + ├── support + │ └── BUILD + ├── tests + │ ├── BUILD + │ └── framework + │ └── BUILD + └── utils + └── BUILD + +@subsubsection S1_8_1_2_build_options Build options + +Available build options: + + - debug: Enable ['-O0','-g','-gdwarf-2'] compilation flags + - Werror: Enable -Werror compilation flag + - logging: Enable logging + - cppthreads: Enable C++11 threads backend + - openmp: Enable OpenMP backend + +@subsubsection S1_8_1_3_example_builds Example builds + +Build everything (libraries, examples, tests): + + bazel build //... + +Build libraries: + + bazel build //:all + +Build arm_compute only: + + bazel build //:arm_compute + +Build examples: + + bazel build //examples:all + +Build resnet50 example: + + bazel build //examples:graph_resnet50 + +Build validation and benchmarking: + + bazel build //tests:all + +@subsection S1_8_2_cmake_build CMake build + +@subsubsection S1_8_2_1_file_structure File structure + +File structure for all files included in the CMake build: + + . + ├── CMakeLists.txt + ├── cmake + │ ├── Options.cmake + │ ├── Version.cmake + │ └── toolchains + │ └── aarch64_linux_toolchain.cmake + ├── examples + │ └── CMakeLists.txt + ├── src + │ └── CMakeLists.txt + └── tests + ├── CMakeLists.txt + ├── benchmark + │ └── CMakeLists.txt + └── validation + └── CMakeLists.txt + +@subsubsection S1_8_2_2_build_options Build options + +Available build options: + + - CMAKE_BUILD_TYPE: "Release" (default) enables ['-O3', '-DNDEBUG'] compilation flags, "Debug" enables ['-O0','-g','-gdwarf-2', '-DARM_COMPUTE_ASSERTS_ENABLED'] + - ARM_COMPUTE_WERROR: Enable -Werror compilation flag + - ARM_COMPUTE_EXCEPTIONS: If disabled ARM_COMPUTE_EXCEPTIONS_DISABLED is enabled + - ARM_COMPUTE_LOGGING: Enable logging + - ARM_COMPUTE_BUILD_EXAMPLES: Build examples + - ARM_COMPUTE_BUILD_TESTING: Build tests + - ARM_COMPUTE_CPPTHREADS: Enable C++11 threads backend + - ARM_COMPUTE_OPENMP: Enable OpenMP backend + +@subsubsection S1_8_2_3_example_builds Example builds + +To build libraries, examples and tests: + + mkdir build + cd build + cmake .. -DCMAKE_BUILD_TYPE=Release -DARM_COMPUTE_OPENMP=1 -DARM_COMPUTE_WERROR=0 -DARM_COMPUTE_BUILD_EXAMPLES=1 -DARM_COMPUTE_BUILD_TESTING=1 -DCMAKE_INSTALL_LIBDIR=. + cmake --build . -j32 + +@section S1_9_fixed_format Building with support for fixed format kernels + +@subsection S1_9_1_intro_to_fixed_format_kernels What are fixed format kernels? + +The GEMM kernels used for convolutions and fully-connected layers in Compute Library employ memory layouts optimized for each kernel implementation. This then requires the supplied weights to be re-ordered into a buffer ready for consumption by the GEMM kernel. Where Compute Library is being called from a framework or library which implements operator caching, the re-ordering of the inputted weights into an intermediate buffer may no longer be desirable. When using a cached operator, the caller may wish to re-write the weights tensor, and re-run the operator using the updated weights. With the default GEMM kernels in Compute Library, the GEMM will be executed with the old weights, leading to incorrect results. + +To address this, Compute Library provides a set of GEMM kernels which use a common blocked memory format. These kernels consume the input weights directly from the weights buffer and do not execute an intermediate pre-transpose step. With this approach, it is the responsibility of the user (in this case the calling framework) to ensure that the weights are re-ordered into the required memory format. @ref NEGEMM::has_opt_impl is a static function that queries whether there exists fixed-format kernel, and if so will return in the expected weights format. The supported weight formats are enumerated in @ref arm_compute::WeightFormat. + +@subsection S1_9_2_building_fixed_format Building with fixed format kernels + +Fixed format kernels are only available for the CPU backend. To build Compute Library with fixed format kernels set fixed_format_kernels=1: + + scons Werror=1 debug=0 neon=1 opencl=0 embed_kernels=0 os=linux multi_isa=1 build=native cppthreads=1 openmp=0 fixed_format_kernels=1 + +@section S1_10_doxygen Building the Doxygen Documentation + +This documentation has been generated using the following shell command: + + $ ./scripts/generate_documentation.sh + +This requires Doxygen to be installed and available on your system. + +*/ + +} // namespace arm_compute diff --git a/docs/user_guide/introduction.dox b/docs/user_guide/introduction.dox new file mode 100644 index 0000000000..15c95f7103 --- /dev/null +++ b/docs/user_guide/introduction.dox @@ -0,0 +1,120 @@ +/// +/// Copyright (c) 2017-2024 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** +@mainpage Introduction +@copydoc introduction + +@page introduction Introduction + +@tableofcontents + +The Compute Library is a collection of low-level machine learning functions optimized for both Arm CPUs and GPUs using SIMD technologies. + +Several builds of the library are available using various configurations: + - OS: Linux®, Android™, macOS or bare metal. + - Architecture: armv7a (32bit) or armv8a (64bit). + - Technology: Arm® Neon™ / OpenCL / Arm® Neon™ and OpenCL. + - Debug / Asserts / Release: Use a build with asserts enabled to debug your application and enable extra validation. Once you are sure your application works as expected you can switch to a release build of the library for maximum performance. + +@warning Depecation Notice from 24.01: NCHW data format specific optimizations will gradually be removed from the code base in + future releases. The implication of this is that the user is expected to translate NCHW models into NHWC in + order to benefit from the optimizations. + +@b Minimum toolchains requirements are shown below: + +<table> +<tr> + <th>Operating System + <th>Architecture + <th>Minimum Toolchain +<tr> + <td rowspan="4">Linux® + <td>armv7a + <td>gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf + <tr> + <td>armv8a + <td rowspan="2">gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu + <tr> + <td>armv8.2-a + <tr> + <td>armv8.2-a-sve + <td>gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu +<tr> + <td rowspan="3">Android™ + <td>armv8a + <td rowspan="2">NDK r20b + <tr> + <td>armv8.2-a + <tr> + <td>armv8.2-a-sve + <td>NDK r23b +<tr> + <td rowspan="1">macOS + <td>armv8.2-a + <td>Monterey (OS version): clang 13 (native) +</table> + +@section S0_1_contact Contact / Support + +Please create an issue on <a href="https://github.com/ARM-software/ComputeLibrary/issues">Github</a>. + +In order to facilitate the work of the support team please provide the build information of the library you are using. To get the version of the library you are using simply run: + + $ strings android-armv8a-cl-asserts/libarm_compute.so | grep arm_compute_version + arm_compute_version=v16.12 Build options: {'embed_kernels': '1', 'opencl': '1', 'arch': 'armv8a', 'neon': '0', 'asserts': '1', 'debug': '0', 'os': 'android', 'Werror': '1'} Git hash=f51a545d4ea12a9059fe4e598a092f1fd06dc858 + +@section S0_2_prebuilt_binaries Pre-built binaries + +For each release we provide some pre-built binaries of the library [here](https://github.com/ARM-software/ComputeLibrary/releases). + +These binaries have been built using the following toolchains: + - Linux® armv7a: gcc-linaro-7.2.1-2017.11-x86_64_arm-linux-gnueabihf + - Linux® armv8a: gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu + - Linux® armv8.2-a: gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu + - Linux® armv8.2-a (multi-ISA binary): gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu + - Linux® armv8.2-a-sve: gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu + - Android™ armv8a: clang++ / libc++ NDK r20b + - Android™ armv8.2-a: clang++ / libc++ NDK r20b + - Android™ armv8.2-a-sve: clang++ / libc++ NDK r23b + +@warning Make sure to use a compatible toolchain to build your application or you will get some std::bad_alloc errors at runtime. + +@section S0_3_file_organisation File organisation + +This archive contains: + - The arm_compute header and source files + - The latest Khronos OpenCL 1.2 C headers from the <a href="https://www.khronos.org/registry/cl/">Khronos OpenCL registry</a> + - The latest Khronos cl2.hpp from the <a href="https://www.khronos.org/registry/cl/">Khronos OpenCL registry</a> (API version 2.1 when this document was written) + - The latest Khronos EGL 1.5 C headers from the <a href="https://www.khronos.org/registry/gles/">Khronos EGL registry</a> + - The sources for a stub version of libOpenCL.so, libGLESv1_CM.so, libGLESv2.so and libEGL.so to help you build your application. + - An examples folder containing a few examples to compile and link against the library. + - A utils folder containing headers with some boiler plate code used by the examples. + - This documentation. + + For detailed information about file organization, please refer to Files -> File List section of this documentation. + +*/ +} // namespace arm_compute diff --git a/docs/user_guide/library.dox b/docs/user_guide/library.dox new file mode 100644 index 0000000000..5a337c374b --- /dev/null +++ b/docs/user_guide/library.dox @@ -0,0 +1,615 @@ +/// +/// Copyright (c) 2017-2021, 2023-2024 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** +@page architecture Library Architecture + +@tableofcontents + +@section architecture_compute_library Compute Library architecture + +The Compute Library is a collection of low level algorithm implementations known as kernels @ref IKernel. +These kernels are implemented as operators @ref IOperator that do not allocate any memory (i.e. all the memory allocations/mappings have to be handled by the caller) +and are are designed to be embedded in existing projects and applications. + +A higher-level interface wraps the operators into functions @ref IFunction that: +- Performs memory allocation of images and tensors through the use of standard malloc(). +- Enables multi-threading of Arm® Neon™ code in a very basic way using a very simple pool of threads. +- For OpenCL, uses the default CLScheduler command queue for all mapping operations and kernels. + +For maximum performance, it is expected that the users would re-implement an equivalent to the function interface which suits better their needs (With a more clever multi-threading strategy, load-balancing between Arm® Neon™ and OpenCL, etc.) + +@section architecture_fast_math Fast-math support + +Compute Library supports different types of convolution methods, fast-math flag is only used for the Winograd algorithm. +When the fast-math flag is enabled, both Arm® Neon™ and CL convolution layers will try to dispatch the fastest implementation available, which may introduce a drop in accuracy as well. The different scenarios involving the fast-math flag are presented below: +- For FP32: + - no-fast-math: Only supports Winograd 3x3,3x1,1x3,5x1,1x5,7x1,1x7 + - fast-math: Supports Winograd 3x3,3x1,1x3,5x1,1x5,7x1,1x7,5x5,7x7 +- For fp16: + - no-fast-math: No Winograd support + - fast-math: Supports Winograd 3x3,3x1,1x3,5x1,1x5,7x1,1x7,5x5,7x7 + +@section bf16_acceleration BF16 acceleration + +Required toolchain: android-ndk-r23-beta5 or later. + +To build for BF16: "neon" flag should be set "=1" and "arch" has to be "=armv8.6-a", "=armv8.6-a-sve", or "=armv8.6-a-sve2". For example: + + scons arch=armv8.6-a-sve neon=1 opencl=0 extra_cxx_flags="-fPIC" benchmark_tests=0 validation_tests=0 validation_examples=1 os=android Werror=0 toolchain_prefix=aarch64-linux-android29 + +To enable BF16 acceleration when running FP32 "fast-math" has to be enabled and that works only for Neon convolution layer using cpu gemm. +In this scenario on CPU: the CpuGemmConv2d kernel performs the conversion from FP32, type of input tensor, to BF16 at block level to exploit the arithmetic capabilities dedicated to BF16. Then transforms back to FP32, the output tensor type. + +@section architecture_thread_safety Thread-safety + +Although the library supports multi-threading during workload dispatch, thus parallelizing the execution of the workload at multiple threads, the current runtime module implementation is not thread-safe in the sense of executing different functions from separate threads. +This lies to the fact that the provided scheduling mechanism wasn't designed with thread-safety in mind. +As it is true with the rest of the runtime library a custom scheduling mechanism can be re-implemented to account for thread-safety if needed and be injected as the library's default scheduler. + +@section architecture__algorithms Algorithms + +All computer vision algorithms in this library have been implemented following the [OpenVX 1.1 specifications](https://www.khronos.org/registry/vx/specs/1.1/html/). Please refer to the Khronos documentation for more information. + +@section architecture_images_tensors Images, padding, border modes and tensors + +Most kernels and functions in the library process images, however, in order to be future proof most of the kernels actually accept tensors. See below for more information about how they are related. + +@attention Each memory object can be written by only one kernel, however it can be read by several kernels. Writing to the same object from several kernels will result in undefined behavior. The kernel writing to an object must be configured before the kernel(s) reading from it. + +@subsection architecture_images_tensors_padding_and_border Padding and border modes + +Several algorithms require a neighborhood around the current pixel to compute it's value. This means the algorithm will not be able to process the borders of the image unless you give it more information about how those border pixels should be processed. The @ref BorderMode enum is used for this purpose. + +You have 3 types of @ref BorderMode : + +- @ref BorderMode::UNDEFINED : Neighbor pixels outside of the image are treated as undefined. As a result all the pixels which are on the border will have a value which is undefined. +- @ref BorderMode::REPLICATE : Neighbor pixels outside of the image are treated as having the same value as the closest valid pixel. +- @ref BorderMode::CONSTANT : Neighbor pixels outside of the image are treated as having the same constant value. (The user can choose what this value should be). + +Moreover both OpenCL and Arm® Neon™ use vector loads and stores instructions to access the data in buffers, so in order to avoid having special cases to handle for the borders all the images and tensors used in this library must be padded. + +@subsubsection architecture_images_tensors_padding Padding + +There are different ways padding can be calculated: + +- Accurate padding: + +@note It's important to call allocate @b after the function is configured: if the image / tensor is already allocated then the function will shrink its execution window instead of increasing the padding. (See below for more details). + +- Manual padding / no padding / auto padding: You can allocate your images / tensors up front (before configuring your functions). In that case the function will use whatever padding is available and will shrink its execution window if there isn't enough padding available (which translates into a smaller valid region for the output). See also @ref architecture_images_tensors_valid_region). +If you don't want to manually set the padding but still want to allocate your objects upfront then you can use auto_padding. It guarantees that the allocation will have enough padding to run any of the provided functions. + +@code{.cpp} +Image src{}, dst{}; +NEScale scale{}; + +// Create an empty grayscale 640x480 image +src.allocator()->init(TensorInfo(640, 480, Format::U8)); + +constexpr int scale_factor = 2; +TensorInfo dst_tensor_info(src.info()->dimension(0) / scale_factor, src.info()->dimension(1) / scale_factor, + Format::U8); + +// Configure the destination image +dst.allocator()->init(dst_tensor_info); + +// Configure Scale function object: +scale.configure(&src, &dst, ScaleKernelInfo{ + InterpolationPolicy::NEAREST_NEIGHBOR, + BorderMode::UNDEFINED, + PixelValue(), + SamplingPolicy::CENTER, + false +}); + +// Allocate all the images +src.allocator()->allocate(); +dst.allocator()->allocate(); +// Fill the input image with the content of the PPM image if a filename was provided: +fill_image(src); + +// Run the scale operation: +scale.run(); +@endcode + +The full example is provided in examples/neon_scale.cpp + +@warning Some kernels need up to 3 neighbor values to calculate the value of a given pixel. Therefore, to be safe, we use a 4-pixel padding all around the image. In addition, some kernels read and write up to 32 pixels at the same time. To cover that case as well we add an extra 32 pixels of padding at the end of each row. As a result auto padded buffers waste a lot of memory and are less cache friendly. It is therefore recommended to use accurate padding or manual padding wherever possible. + +@subsubsection architecture_images_tensors_valid_region Valid regions + +Some kernels (like edge detectors for example) need to read values of neighboring pixels to calculate the value of a given pixel, it is therefore not possible to calculate the values of the pixels on the edges. + +Another case is: if a kernel processes 8 pixels per iteration and the image's dimensions are not a multiple of 8 and not enough padding is available then the kernel will not be able to process the pixels near the right edge. As a result these pixels will be left undefined. + +In order to know which pixels have been calculated, each kernel sets a valid region for each output image or tensor. See also @ref TensorInfo::valid_region(), @ref ValidRegion + +@subsection architecture_images_tensors_tensors Tensors + +Tensors are multi-dimensional arrays with a maximum of @ref Coordinates::num_max_dimensions dimensions. + +Depending on the number of dimensions tensors can be interpreted as various objects. A scalar can be represented as a zero-dimensional tensor and a vector of numbers can be represented as an one-dimensional tensor. Further, an image is actually just a 2D tensor, a 3D tensor can be seen as an array of images and a 4D tensor as a 2D array of images, etc. + +@note Most algorithms process images (i.e a 2D slice of the tensor), therefore only padding along the X and Y axes is required (2D slices can be stored contiguously in memory). + +@subsection architecture_images_tensors_description_conventions Images and Tensors description conventions + +Image objects are defined by a @ref Format and dimensions expressed as [width, height, batch] + +Tensors are defined by a @ref DataType plus a number of channels (Always expected to be 1 for now) and their dimensions are expressed as [width, height, feature_maps, batch]. + +In other words, the lower three dimensions of a tensor specify a single input in [width, height, feature_maps], while any other specified dimension represents a batch in the appropriate dimension space. +For example, a tensor with dimensions [128, 128, 64, 16] represents a 1D batch space with 16 batches of 128 elements in width and height and 64 feature maps each. +Each kernel specifies the expected layout of each of its tensors in its documentation. + +@note Unless specified otherwise in the kernel's or function's documentation all tensors and images parameters passed must have identical dimensions. + +@note Unless specified otherwise in the kernel's or function's documentation the number of channels for tensors is expected to be 1 (For images, the number of channels is inferred from the @ref Format). + +@attention Regardless of the @ref DataType used by a tensor the @ref ITensor::buffer() method will always return a uint8_t pointer, and all the metadata in @ref TensorInfo will be expressed in bytes. It is the user's responsibility to cast the pointer to the correct type. + +For example, to read the element located at the coordinates (x,y) of a float tensor: + +@code{.cpp} +float value = *reinterpret_cast<float*>(input.buffer() + input.info()->offset_element_in_bytes(Coordinates(x,y))); +@endcode + +@subsection architecture_images_tensors_working_with_objects Working with Images and Tensors using iterators + +The library provides some iterators to access objects' data. +Iterators are created by associating a data object (An image or a tensor for example) with an iteration window. + +Iteration windows are defined by an array of dimensions, each of which consists of a start, end and step. + +The @ref execute_window_loop function takes an execution window, a lambda function and one or more iterators. +It will iterate through every element of the execution window and for each element it will update the iterators accordingly and call the lambda function. + +Here are a couple of examples of how to use the iterators to fill / read tensors: + +@snippet examples/neon_copy_objects.cpp Copy objects example + +@subsection architecture_images_tensors_sub_tensors Sub-tensors + +Sub-tensors are aliases to existing Tensors, as a result creating a sub-tensor does not result in any underlying memory allocation. + +Sub-tensors can be used to access a sub-set of the parent tensor, something that can be useful in case different operations need to be performed on different parts of a tensor. + +Moreover, sub-tensors can be used to perform zero copy tensor concatenation. + +The API for creating a sub-tensor is the following: +@code{.cpp} +SubTensor(ITensor *parent, const TensorShape &tensor_shape, const Coordinates &coords) +@endcode + +Where \a parent is the parent tensor which we want to create an alias for, \a tensor_shape is the shape of the sub-tensor and \a coords are the starting indexing coordinates of the sub-tensor within the parent tensor. + +@note Two sub-tensor concrete classes for different targets are currently supported : @ref CLSubTensor and @ref SubTensor + +@warning Limitation of the sub-tensor is that it cannot be extracted spatially, meaning sub-tensors should have the same width and height as the parent tensor. The main reasons for this is the fact that individual kernels might need to operate with a step size that is not a multiple of the sub-tensor spatial dimension. This could lead to elements being overwritten by different kernels operating on different sub-tensors of the same underlying tensor. + +@section architecture_memory_manager MemoryManager + +@ref IMemoryManager is a memory managing interface that can be used to reduce the memory requirements of a given pipeline by recycling temporary buffers. + +@subsection architecture_memory_manager_component MemoryGroup, MemoryPool and MemoryManager Components + +@subsubsection architecture_memory_manager_component_memory_group MemoryGroup + +@ref IMemoryGroup defines the memory managing granularity. + +MemoryGroup binds a number of objects to a bucket of memory requirements that need to be fulfilled in order for an operation or list of operations to be executed. + +Requesting backing memory for a specific group can be done using @ref IMemoryGroup::acquire and releasing the memory back using @ref IMemoryGroup::release. + +@subsubsection architecture_memory_manager_component_memory_pool MemoryPool + +@ref IMemoryPool defines a pool of memory that can be used to provide backing memory to a memory group. + +@note @ref BlobMemoryPool is currently implemented which models the memory requirements as a vector of distinct memory blobs. + +@subsubsection architecture_memory_manager_component_memory_manager_components MemoryManager Components + +@ref IMemoryManager consists of two components: +- @ref ILifetimeManager that keeps track of the lifetime of the registered objects of the memory groups and given an @ref IAllocator creates an appropriate memory pool that fulfils the memory requirements of all the registered memory groups. +- @ref IPoolManager that safely manages the registered memory pools. + +@note @ref BlobLifetimeManager is currently implemented which models the memory requirements as a vector of distinct memory blobs. + +@subsection architecture_memory_manager_working_with_memory_manager Working with the Memory Manager +Using a memory manager to reduce the memory requirements of a pipeline can be summed in the following steps: + +Initially a memory manager must be set-up: +@code{.cpp} +Allocator allocator{}; // Create an allocator to use for the backing memory allocation +auto lifetime_mgr = std::make_shared<BlobLifetimeManager>(); // Create Lifetime Manager +auto pool_mgr = std::make_shared<PoolManager>(); // Create Pool Manager +auto mm = std::make_shared<MemoryManagerOnDemand>(lifetime_mgr, pool_mgr); // Create Memory Manager +@endcode + +Once done, memory groups can be registered to use the memory manager: +@code{.cpp} +MemoryGroup memory_group(mm); // Create a memory group and set the memory manager to use +@endcode + +@note If a memory manager is not specified then all allocation will be immediate instead of deferred through the memory manager. + +Next step is to set objects to be managed by the memory group. It is important though to note that the lifetime of an object is tracked from the @ref MemoryGroup::manage() and the @ref TensorAllocator::allocate calls. +@ref MemoryGroup::manage flags that the object will be needed starting now and when @ref TensorAllocator::allocate is called it signals the end of the object lifetime. +@code{.cpp} +Tensor tmp1, tmp2, tmp3; // Create example tensors +memory_group.manage(&tmp1); // Start managing object tmp1 and start its lifetime +memory_group.manage(&tmp2); // Start managing object tmp2 and start its lifetime + +operation1.configure(&tmp1, &tmp2); // Configure a function/kernel using tmp1 and tmp2 + +tmp1.allocator()->allocate(); // Flag that the lifetime of object tmp1 has ended + +memory_group.manage(&tmp3); // Start managing object tmp3 and start its lifetime + +operation2.configure(&tmp2, &tmp3); // Configure a function/kernel using tmp2 and tmp3 + +tmp2.allocator()->allocate(); // Flag that the lifetime of object tmp2 has ended +tmp3.allocator()->allocate(); // Flag that the lifetime of object tmp3 has ended +@endcode + +@warning The configuration step should be done sequentially by a single thread so that all the lifetimes are captured correctly. + +When configuration of all the operations is finished then the memory manager have to be populated: +@code{.cpp} +mm->populate(&allocator), 2 /* num_pools */); // Populate memory manager pools +@endcode + +Finally, during execution of the pipeline the memory of the appropriate memory group should be requested before running: +@code{.cpp} +memory_group.acquire(); // Request memory for the group + +operation1.run(); // Run operation1 +operation2.run(); // Run operation2 + +memory_group.release(); // Release memory so that it can be reused +@endcode +@note Execution of a pipeline can be done in a multi-threading environment as memory acquisition/release are thread safe. +@note If you are handling sensitive data and it's required to zero out the memory buffers before freeing, make sure to also zero out the intermediate buffers. You can access the buffers through the memory group's mappings. + +@subsection architecture_memory_manager_function_support Function support + +Most of the library's function have been ported to use @ref IMemoryManager for their internal temporary buffers. + +If that is the case, a memory manager can be passed to them during construction to reuse memory among these functions. +@code{.cpp} +// Setup Memory Manager +CLBufferAllocator allocator{}; // Create an allocator to use for the backing memory allocation +auto lifetime_mgr = std::make_shared<BlobLifetimeManager>(); // Create Lifetime Manager +auto pool_mgr = std::make_shared<PoolManager>(); // Create Pool Manager +auto mm = std::make_shared<MemoryManagerOnDemand>(lifetime_mgr, pool_mgr); // Create Memory Manager + +// Create two convolution layers and use the memory manager to manager their internal temporary buffers +CLConvolutionLayer conv1(mm), conv2(mm); + +// Configure layers +conv1.configure(...); +conv2.configure(...); + +// Populate memory manager +mm->populate(&allocator), 1 /* num_pools */); // Populate memory manager pools + +// Run layers (Memory will be recycled for internal buffers for conv1 and conv2 +conv1.run(); +conv2.run(); +@endcode + +@section architecture_import_memory Import Memory Interface + +The implemented @ref TensorAllocator and @ref CLTensorAllocator objects provide an interface capable of importing existing memory to a tensor as backing memory. + +A simple Arm® Neon™ example can be the following: +@code{.cpp} +// External backing memory +void* external_ptr = ...; + +// Create and initialize tensor +Tensor tensor; +tensor.allocator()->init(tensor_info); + +// Import existing pointer as backing memory +tensor.allocator()->import_memory(external_ptr); +@endcode + +It is important to note the following: +- Ownership of the backing memory is not transferred to the tensor itself. +- The tensor mustn't be memory managed. +- Padding requirements should be accounted by the client code. In other words, if padding is required by the tensor after the function configuration step, then the imported backing memory should account for it. Padding can be checked through the @ref TensorInfo::padding() interface. + +@section architecture_opencl_tuner OpenCL Tuner + +OpenCL kernels when dispatched to the GPU take two arguments: +- The Global Workgroup Size (GWS): That's the number of times to run an OpenCL kernel to process all the elements we want to process. +- The Local Workgroup Size (LWS): That's the number of elements we want to run in parallel on a GPU core at a given point in time. + +The LWS can be required by an algorithm (For example if it contains memory barriers or uses local memory) but it can also be used for performance reasons to tweak the performance of a kernel: the execution time of the overall kernel might vary significantly depending on how the GWS is broken down. + +However, there is no universal rule regarding which LWS is best for a given kernel, so instead we created the @ref CLTuner. + +When the @ref CLTuner is enabled ( Target = 2 for the graph examples), the first time an OpenCL kernel is executed the Compute Library will try to run it with a variety of LWS values and will remember which one performed best for subsequent runs. At the end of the run the @ref graph::Graph will try to save these tuning parameters to a file. + +However this process takes quite a lot of time, which is why it cannot be enabled all the time. @ref CLTuner supports three modes of tuning with different trade-offs between the time taken to tune and the kernel execution time achieved using the best LWS found. In the Exhaustive mode, it searches all the supported values of LWS. This mode takes the longest time to tune and is the most likely to find the optimal LWS. Normal mode searches a subset of LWS values to yield a good approximation of the optimal LWS. It takes less time to tune than Exhaustive mode. Rapid mode takes the shortest time to tune and finds an LWS value that is at least as good or better than the default LWS value. The mode affects only the search for the optimal LWS and has no effect when the LWS value is imported from a file. + +But, when the @ref CLTuner is disabled ( Target = 1 for the graph examples), the @ref graph::Graph will try to reload the file containing the tuning parameters, then for each executed kernel the Compute Library will use the fine tuned LWS if it was present in the file or use a default LWS value if it's not. + +@section architecture_cl_queue_priorities OpenCL Queue Priorities + +OpenCL 2.1 exposes the `cl_khr_priority_hints` extensions that if supported by an underlying implementation allows the user to specify priority hints to the created command queues. +Is important to note that this does not specify guarantees or the explicit scheduling behavior, this is something that each implementation needs to expose. + +In some cases, priority queues can be used when there is an implicit internal priority between graphics and compute queues and thus allow some level of priority control between them. +At the moment three priority level can be specified: +- CL_QUEUE_PRIORITY_HIGH_KHR +- CL_QUEUE_PRIORITY_MED_KHR +- CL_QUEUE_PRIORITY_LOW_KHR + +Compute Library allows extraction of the internal OpenCL queue or the ability to inject directly a user-defined queue to the @ref CLScheduler. +This way the user can utilize this extension to define priorities between the queues and setup the OpenCL scheduler mechanism to utilize them. + +@code{.cpp} +cl_queue_properties queue_properties[] = {CL_QUEUE_PRIORITY_KHR, CL_QUEUE_PRIORITY_HIGH_KHR, 0}; +cl_command_queue priority_queue = clCreateCommandQueueWithProperties(ctx, dev, queue_properties, &error); +CLScheduler::get().set_queue(::cl::CommandQueue(priority_queue)); +@endcode + +@section architecture_weights_manager Weights Manager + +@ref IWeightsManager is a weights managing interface that can be used to reduce the memory requirements of a given pipeline by reusing transformed weights across multiple function executions. +@ref IWeightsManager is responsible for managing weight tensors alongside with their transformations. +@ref ITransformWeights provides an interface for running the desired transform function. This interface is used by the weights manager. + +@subsection architecture_weights_manager_working_with_weights_manager Working with the Weights Manager +Following is a simple example that uses the weights manager: + +Initially a weights manager must be set-up: +@code{.cpp} +auto wm = std::make_shared<IWeightsManager>(); // Create a weights manager +@endcode + +Once done, weights can be managed, configured and run: +@code{.cpp} +wm->manage(weights); // Manage the weights +wm->acquire(weights, &_reshape_weights_managed_function); // Acquire the address of the transformed weights based on the transform function +wm->run(weights, &_reshape_weights_managed_function); // Run the transpose function +@endcode + +@section programming_model Programming Model +@subsection programming_model_functions Functions + +Functions will automatically allocate the temporary buffers mentioned above, and will automatically multi-thread kernels' executions using the very basic scheduler described in the previous section. + +Simple functions only call a single kernel (e.g NEConvolution3x3), while more complex ones consist of several kernels pipelined together (e.g @ref NEFullyConnectedLayer ). Check their documentation to find out which kernels are used by each function. + +@code{.cpp} +//Create a function object: +MyFunction function; +// Initialize the function with the input/output and options you want to use: +function.configure( input, output, option0, option1); +// Execute the function: +function.run(); +@endcode + +@warning The Compute Library requires Arm® Mali™ OpenCL DDK r8p0 or higher (OpenCL kernels are compiled using the -cl-arm-non-uniform-work-group-size flag) + +@note All OpenCL functions and objects in the runtime library use the command queue associated with CLScheduler for all operations, a real implementation would be expected to use different queues for mapping operations and kernels in order to reach a better GPU utilization. + +@subsection programming_model_scheduler OpenCL Scheduler + +The Compute Library runtime uses a single command queue and context for all the operations. + +The user can get / set this context and command queue through CLScheduler's interface. + +The user can get / set the target GPU device through the CLScheduler's interface. + +@attention Make sure the application is using the same context as the library as in OpenCL it is forbidden to share objects across contexts. This is done by calling @ref CLScheduler::init() or @ref CLScheduler::default_init() at the beginning of your application. + +@attention Make sure the scheduler's target is not changed after function classes are created. + +@subsection programming_model__events_sync OpenCL events and synchronization + +In order to block until all the jobs in the CLScheduler's command queue are done executing the user can call @ref CLScheduler::sync() or create a sync event using @ref CLScheduler::enqueue_sync_event() + +@subsection programming_model_cl_neon OpenCL / Arm® Neon™ interoperability + +You can mix OpenCL and Arm® Neon™ kernels and functions. However it is the user's responsibility to handle the mapping/unmapping of OpenCL objects. + +@section architecture_experimental Experimental Features + +@subsection architecture_experimental_run_time_context Run-time Context + +Some of the Compute Library components are modelled as singletons thus posing limitations to supporting some use-cases and ensuring a more client-controlled API. +Thus, we are introducing an aggregate service interface @ref IRuntimeContext which will encapsulate the services that the singletons were providing and allow better control of these by the client code. +Run-time context encapsulates a list of mechanisms, some of them are: scheduling, memory management, kernel caching and others. +Consequently, this will allow finer control of these services among pipelines when Compute Library is integrated in higher level frameworks. + +This feature introduces some changes to our API. +All the kernels/functions will now accept a Runtime Context object which will allow the function to use the mentioned services. + +Finally, we will try to adapt our code-base progressively to use the new mechanism but will continue supporting the legacy mechanism to allow a smooth transition. Changes will apply to all our backends: Neon™ and OpenCL. + +@subsection architecture_experimental_clvk CLVK + +Compute Library offers experimental support for [CLVK](https://github.com/kpet/clvk). If CLVK is installed in the system, users can select the backend when running a graph example with --target=clvk. +If no target is specified and more that one OpenCL implementations are present, Compute Library will pick the first available. + +@section architecture_experimental_api Experimental Application Programming Interface + +@subsection architecture_experimental_api_overview Overview + +In this section we present Compute Library's experimental application programming interface (API) architecture along with +a detailed explanation of its components. Compute Library's API consists of multiple high-level operators and +even more internally distinct computational blocks that can be executed on a command queue. +Operators can be bound to multiple Tensor objects and executed concurrently or asynchronously if needed. +All operators and associated objects are encapsulated in a Context-based mechanism, which provides all related +construction services. + +@subsection architecture_experimental_api_objects Fundamental objects + +Compute Library consists of a list of fundamental objects that are responsible for creating and orchestrating operator execution. +Below we present these objects in more detail. + +@subsubsection architecture_experimental_api_objects_context AclContext or Context + +AclContext or Context acts as a central creational aggregate service. All other objects are bound to or created from a context. +It provides, internally, common facilities such as +- allocators for object creation or backing memory allocation +- serialization interfaces +- any other modules that affect the construction of objects (e.g., program cache for OpenCL). + +The followings sections will describe parameters that can be given on the creation of Context. + +@paragraph architecture_experimental_api_object_context_target AclTarget +Context is initialized with a backend target (AclTarget) as different backends might have a different subset of services. +Currently the following targets are supported: +- #AclCpu: a generic CPU target that accelerates primitives through SIMD technologies +- #AclGpuOcl: a target for GPU acceleration using OpenCL + +@paragraph architecture_experimental_api_object_context_execution_mode AclExecutionMode +An execution mode (AclExecutionMode) can be passed as an argument that affects the operator creation. +At the moment the following execution modes are supported: +- #AclPreferFastRerun: Provides faster re-run. It can be used when the operators are expected to be executed multiple +times under the same execution context +- #AclPreferFastStart: Provides faster single execution. It can be used when the operators will be executed only once, +thus reducing their latency is important (Currently, it is not implemented) + +@paragraph architecture_experimental_api_object_context_capabilities AclTargetCapabilities +Context creation can also have a list of capabilities of hardware as one of its parameters. This is currently +available only for the CPU backend. A list of architecture capabilities can be passed to influence the selection +of the underlying kernels. Such capabilities can be for example the enablement of SVE or the dot product +instruction explicitly. +@note The underlying hardware should support the given capability list. + +@paragraph architecture_experimental_api_object_context_allocator Allocator +An allocator object that implements @ref AclAllocator can be passed to the Context upon its creation. +This user-provided allocator will be used for allocation of any internal backing memory. + +@note To enable interoperability with OpenCL, additional entrypoints are provided +to extract (@ref AclGetClContext) or set (@ref AclSetClContext) the internal OpenCL context. + +@subsubsection architecture_experimental_api_objects_tensor AclTensor or Tensor + +A tensor is a mathematical object that can describe physical properties like matrices. +It can be also considered a generalization of matrices that can represent arbitrary +dimensionalities. AclTensor is an abstracted interface that represents a tensor. + +AclTensor, in addition to the elements of the physical properties they represent, +also contains the information such as shape, data type, data layout and strides to not only +fully describe the characteristics of the physical properties but also provide information +how the object stored in memory should be traversed. @ref AclTensorDescriptor is a dedicated +object to represent such metadata. + +@note The allocation of an AclTensor can be deferred until external memory is imported +as backing memory to accomplish a zero-copy context. + +@note To enable interoperability with OpenCL, additional entrypoints are provided +to extract (@ref AclGetClMem) the internal OpenCL memory object. + +As Tensors can reside in different memory spaces, @ref AclMapTensor and @ref AclUnmapTensor entrypoints +are provided to map Tensors in and out of the host memory system, respectively. + +@subsubsection architecture_experimental_api_objects_queue AclQueue or Queue + +AclQueue acts as a runtime aggregate service. It provides facilities to schedule +and execute operators using underlying hardware. It also contains services like +tuning mechanisms (e.g., Local workgroup size tuning for OpenCL) that can be specified +during operator execution. + +@note To enable interoperability with OpenCL, additional entrypoints are provided +to extract (@ref AclGetClQueue) or set (@ref AclSetClQueue) the internal OpenCL queue. + +@subsection architecture_experimental_api_internal Internal +@subsubsection architecture_experimental_api_internal_operator_vs_kernels Operators vs Kernels + +Internally, Compute Library separates the executable primitives in two categories: kernels and operators +which operate in a hierarchical way. + +A kernel is the lowest-level computation block whose responsibility is performing a task on a given group of data. +For design simplicity, kernels computation does NOT involve the following: + +- Memory allocation: All the memory manipulation should be handled by the caller. +- Multi-threading: The information on how the workload can be split is provided by kernels, +so the caller can effectively distribute the workload to multiple threads. + +On the other hand, operators combine one or multiple kernels to achieve more complex calculations. +The responsibilities of the operators can be summarized as follows: + +- Defining the scheduling policy and dispatching of the underlying kernels to the hardware backend +- Providing information to the caller required by the computation (e.g., memory requirements) +- Allocation of any required auxiliary memory if it isn't given by its caller explicitly + +@subsection architecture_experimental_build_multi_isa Build multi-ISA binary + +Selecting multi_isa when building Compute Library, will create a library that contains all the supported ISA features. +Based on the CPU support, the appropriate kernel will be selected at runtime for execution. Currently this option is +supported in two configurations: (i) with armv8.2-a (ii) with armv8-a. In both cases all the supported ISA features are enabled +in the build. + +The arch option in a multi_isa build sets the minimum architecture required to run the resulting binary. +For example a multi_isa build for armv8-a will run on any armv8-a or later, when the binary is executed on a armv8.2-a device +it will use the additional cpu features present in this architecture: FP16 and dot product. +In order to have a binary like this (multi_isa+armv8-a) the FP16 and dot product kernels in the library are compiled for the +target armv8.2-a and all other common code for armv8-a. + +@subsection architecture_experimental_per_operator_build Per-operator build + +Dependencies for all operators have been explicitly defined, this provides the ability to users to generate Compute Library +binaries that include a user-defined list of operators. + +An experimental flag 'build_config' has been introduced where a JSON configuration file can be provided and consumed. +An example config looks like: +@code{.py} +{ + "operators": [ + "Activation", + "DepthwiseConv2d", + "Conv2d", + "Permute", + "Pool2d", + "Reshape" + ], + "data_types": [ + "NHWC" + ] +} +@endcode + +Supported data-types options are: +- "NHWC" +- "NCHW" + +The list of supported operators can be found in filelist.json in the root of Compute Library repo. + +@subsection architecture_experimental_build_high_priority_operators Build high priority operators + +Selecting high_priority when building Compute Library, one new library will be created: libarm_compute_hp and +will contain a selected subset of the libary operators. Currently the operators are staticly set. + +*/ +} // namespace arm_compute diff --git a/docs/user_guide/operator_list.dox b/docs/user_guide/operator_list.dox new file mode 100644 index 0000000000..e7f1823f8b --- /dev/null +++ b/docs/user_guide/operator_list.dox @@ -0,0 +1,3258 @@ +/// +/// Copyright (c) 2021-2024 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** +@page operators_list Supported Operators + +@tableofcontents + +@section S9_1_operators_list Supported Operators + +Compute Library supports operators that are listed in below table. + +Compute Library supports a wide list of data-types, information can been directly found in the documentation of each kernel/function. +The main data-types that the Machine Learning functions support are the following: + <ul> + <li>BFLOAT16: 16-bit non-standard brain floating point + <li>QASYMM8: 8-bit unsigned asymmetric quantized + <li>QASYMM8_SIGNED: 8-bit signed asymmetric quantized + <li>QSYMM8_PER_CHANNEL: 8-bit signed symmetric quantized (Used for the weights) + <li>QSYMM8: 8-bit unsigned symmetric quantized + <li>QSYMM16: 16-bit unsigned symmetric quantized + <li>F32: 32-bit single precision floating point + <li>F16: 16-bit half precision floating point + <li>S32: 32-bit signed integer + <li>U8: 8-bit unsigned char + <li>All: Agnostic to any specific data type + </ul> + +Compute Library supports the following data layouts (fast changing dimension from right to left): + <ul> + <li>NHWC: The native layout of Compute Library that delivers the best performance where channels are in the fastest changing dimension + <li>NCHW: Legacy layout where width is in the fastest changing dimension + <li>NDHWC: New data layout for supporting 3D operators + <li>All: Agnostic to any specific data layout + </ul> +where N = batches, C = channels, H = height, W = width, D = depth + +<table> +<caption id="multi_row"></caption> +<tr> + <th>Function + <th>Description + <th>Equivalent Android NNAPI Op + <th>Backends + <th>Data Layouts + <th>Data Types +<tr> + <td rowspan="2">ActivationLayer + <td rowspan="2" style="width:200px;"> Function to simulate an activation layer with the specified activation function. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_ELU + <li>ANEURALNETWORKS_HARD_SWISH + <li>ANEURALNETWORKS_LOGISTIC + <li>ANEURALNETWORKS_RELU + <li>ANEURALNETWORKS_RELU1 + <li>ANEURALNETWORKS_RELU6 + <li>ANEURALNETWORKS_TANH + </ul> + <td>NEActivationLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16 + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLActivationLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16 + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="1">AddMulAdd + <td rowspan="1" style="width:200px;"> Performs a fused Add + Mul + Add [+ Relu-based-Activation] operation. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>NEAddMulAdd + <td> + <ul> + <li>Any + </ul> + <td> + <table> + <tr><th>input1<th>input2<th>bn_mul<th>bn_add<th>add_output<th>final_output + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8<td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16<td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="2">ArgMinMaxLayer + <td rowspan="2" style="width:200px;"> Function to calculate the index of the minimum or maximum values in a tensor based on an axis. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_ARGMAX + <li>ANEURALNETWORKS_ARGMIN + </ul> + <td>NEArgMinMaxLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>U32, S32 + <tr><td>QASYMM8_SIGNED<td>U32, S32 + <tr><td>S32<td>U32, S32, S64 + <tr><td>F16<td>U32, S32 + <tr><td>F32<td>U32, S32 + </table> +<tr> + <td>CLArgMinMaxLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>U32, S32 + <tr><td>QASYMM8_SIGNED<td>U32, S32 + <tr><td>S32<td>U32, S32 + <tr><td>F16<td>U32, S32 + <tr><td>F32<td>U32, S32 + </table> +<tr> + <td rowspan="1">ArithmeticAddition + <td rowspan="1" style="width:200px;"> Function to add 2 tensors. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_ADD + </ul> + <td>NEArithmeticAddition + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>QSYMM16<td>QSYMM16<td>S32 + <tr><td>U8<td>U8<td>U8 + <tr><td>S16<td>S16<td>S16 + <tr><td>S32<td>S32<td>S32 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="1">ArithmeticSubtraction + <td rowspan="1" style="width:200px;"> Function to substract 2 tensors. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_SUB + </ul> + <td>NEArithmeticSubtraction + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>QSYMM16<td>QSYMM16<td>S32 + <tr><td>U8<td>U8<td>U8 + <tr><td>S16<td>S16<td>S16 + <tr><td>S32<td>S32<td>S32 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="2">BatchNormalizationLayer + <td rowspan="2" style="width:200px;"> Function to perform batch normalization. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEBatchNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td>CLBatchNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">BatchToSpaceLayer + <td rowspan="2" style="width:200px;"> Batch to space transformation. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_BATCH_TO_SPACE_ND + </ul> + <td>NEBatchToSpaceLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>All<td>s32<td>All + </table> +<tr> + <td>CLBatchToSpaceLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>All<td>s32<td>All + </table> +<tr> + <td rowspan="2">BitwiseAnd + <td rowspan="2" style="width:200px;"> Function to perform bitwise AND between 2 tensors. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_LOGICAL_AND + </ul> + <td>NEBitwiseAnd + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td>CLBitwiseAnd + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td rowspan="2">BitwiseNot + <td rowspan="2" style="width:200px;"> Function to perform bitwise NOT. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_LOGICAL_NOT + </ul> + <td>NEBitwiseNot + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td>CLBitwiseNot + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td rowspan="2">BitwiseOr + <td rowspan="2" style="width:200px;"> Function to perform bitwise OR between 2 tensors. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_LOGICAL_OR + </ul> + <td>NEBitwiseOr + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td>CLBitwiseOr + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td rowspan="2">BitwiseXor + <td rowspan="2" style="width:200px;"> Function to perform bitwise XOR between 2 tensors. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEBitwiseXor + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td>CLBitwiseXor + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td rowspan="2">BoundingBoxTransform + <td rowspan="2" style="width:200px;"> Transform proposal bounding boxes to target bounding box using bounding box deltas. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEBoundingBoxTransform + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM16<td>QASYMM8<td>QASYMM16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLBoundingBoxTransform + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM16<td>QASYMM8<td>QASYMM16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="2">Cast + <td rowspan="2" style="width:200px;"> Function to cast a tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CAST + </ul> + <td>NECast + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8_SIGNED<td>S16, S32, F32, F16 + <tr><td>QASYMM8<td>U16, S16, S32, F32, F16 + <tr><td>U8<td>U16, S16, S32, F32, F16 + <tr><td>U16<td>U8, U32 + <tr><td>S16<td>QASYMM8_SIGNED, U8, S32 + <tr><td>F16<td>QASYMM8_SIGNED, QASYMM8, F32, S32, U8 + <tr><td>S32<td>QASYMM8_SIGNED, QASYMM8, F16, F32, U8 + <tr><td>F32<td>QASYMM8_SIGNED, QASYMM8, BFLOAT16, F16, S32, U8 + </table> +<tr> + <td>CLCast + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>S8, U16, S16, U32, S32, F16, F32 + <tr><td>S8<td>U8, U16, S16, U32, S32, F16, F32 + <tr><td>U16<td>U8, S8, S16, U32, S32, F16, F32 + <tr><td>S16<td>U8, S8, U16, U32, S32, F16, F32 + <tr><td>U32<td>U8, S8, U16, S16, S32, F16, F32 + <tr><td>S32<td>U8, S8, U16, S16, U32, F16, F32 + <tr><td>U64<td>U8, S8, U16, S16, U32, S32, F16, F32 + <tr><td>S64<td>U8, S8, U16, S16, U32, S32, F16, F32 + <tr><td>F16<td>U8, S8, U16, S16, S32, U32, F32 + <tr><td>F32<td>U8, S8, U16, S16, S32, U32, F16 + </table> +<tr> + <td rowspan="2">ChannelShuffleLayer + <td rowspan="2" style="width:200px;"> Function to shuffle the channels of the input tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CHANNEL_SHUFFLE + </ul> + <td>NEChannelShuffleLayer + <td> + <ul> + <li>NCHW + <li>NHWC + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLChannelShuffleLayer + <td> + <ul> + <li>NCHW + <li>NHWC + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="1">Comparison + <td rowspan="1" style="width:200px;"> Function to compare 2 tensors. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_EQUAL + <li>ANEURALNETWORKS_GREATER + <li>ANEURALNETWORKS_GREATER_EQUAL + <li>ANEURALNETWORKS_LESS + <li>ANEURALNETWORKS_LESS_EQUAL + <li>ANEURALNETWORKS_NOT_EQUAL + </ul> + <td>CLComparison + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>All<td>All<td>U8 + </table> +<tr> + <td rowspan="2">ConcatenateLayer + <td rowspan="2" style="width:200px;"> Function to concatenate tensors along a given axis. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONCATENATION + </ul> + <td>NEConcatenateLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLConcatenateLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">ConvertFullyConnectedWeights + <td rowspan="2" style="width:200px;"> Function to transpose the weights for the fully connected layer. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEConvertFullyConnectedWeights + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLConvertFullyConnectedWeights + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">ConvolutionLayer + <td rowspan="2" style="width:200px;"> Function to compute a convolution layer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONV_2D + </ul> + <td>NEConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">Conv3D + <td rowspan="2" style="width:200px;"> Function to compute a 3d convolution layer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONV_3D + </ul> + <td>NEConv3D + <td> + <ul> + <li>NDHWC + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLConv3D + <td> + <ul> + <li>NDHWC + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">Copy + <td rowspan="2" style="width:200px;"> Function to copy a tensor. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NECopy + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLCopy + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="1">Crop + <td rowspan="1" style="width:200px;"> Performs a copy of input tensor to the output tensor. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>CLCrop + <td> + <ul> + <li>NHWC + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>F32 + </table> +<tr> + <td rowspan="2">CropResize + <td rowspan="2" style="width:200px;"> Function to perform cropping and resizing. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NECropResize + <td> + <ul> + <li>NHWC + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>All<td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLCropResize + <td> + <ul> + <li>NHWC + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>All<td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="2">DeconvolutionLayer + <td rowspan="2" style="width:200px;"> Function to compute a deconvolution or transpose convolution. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_TRANSPOSE_CONV_2D + </ul> + <td>NEDeconvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLDeconvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="1">DeconvolutionLayerUpsample + <td rowspan="1" style="width:200px;"> Function to execute deconvolution upsample on OpenCL. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_TRANSPOSE_CONV_2D + </ul> + <td>CLDeconvolutionLayerUpsample + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">DepthConvertLayer + <td rowspan="2" style="width:200px;"> Performs a down-scaling depth conversion. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEDepthConvertLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>F16, F32 + <tr><td>U8<td>U16, S16, S32 + <tr><td>U16<td>U8, U32 + <tr><td>S16<td>U8, S32 + <tr><td>BFLOAT16<td>F32 + <tr><td>F16<td>QASYMM8, F32 + <tr><td>F32<td>QASYMM8, F16, BFLOAT16 + </table> +<tr> + <td>CLDepthConvertLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>S8, U16, S16, U32, S32, F16, F32 + <tr><td>U16<td>U8, S8, S16, U32, S32, F16, F32 + <tr><td>S16<td>U8, S8, U16, U32, S32, F16, F32 + <tr><td>U32<td>U8, S8, U16, S16, S32, F16, F32 + <tr><td>S32<td>U8, S8, U16, S16, U32, F16, F32 + <tr><td>F16<td>U8, S8, U16, S16, U32, F32 + <tr><td>F32<td>U8, S8, U16, S16, U32, F16 + </table> +<tr> + <td rowspan="2">DepthToSpaceLayer + <td rowspan="2" style="width:200px;"> Depth to Space transformation. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_DEPTH_TO_SPACE + </ul> + <td>NEDepthToSpaceLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLDepthToSpaceLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">DepthwiseConvolutionLayer + <td rowspan="2" style="width:200px;"> Function to perform depthwise separable convolution. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_DEPTHWISE_CONV_2D + </ul> + <td>NEDepthwiseConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLDepthwiseConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">DequantizationLayer + <td rowspan="2" style="width:200px;"> Function to dequantize the values in a tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_DEQUANTIZE + </ul> + <td>NEDequantizationLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>F16, F32 + <tr><td>QASYMM8_SIGNED<td>F16, F32 + <tr><td>QSYMM8_PER_CHANNEL<td>F16, F32 + <tr><td>QSYMM8<td>F16, F32 + <tr><td>QSYMM16<td>F16, F32 + </table> +<tr> + <td>CLDequantizationLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>F16, F32 + <tr><td>QASYMM8_SIGNED<td>F16, F32 + <tr><td>QSYMM8_PER_CHANNEL<td>F16, F32 + <tr><td>QSYMM8<td>F16, F32 + <tr><td>QSYMM16<td>F16, F32 + </table> +<tr> + <td rowspan="1">DetectionPostProcessLayer + <td rowspan="1" style="width:200px;"> Function to generate the detection output based on center size encoded boxes, class prediction and anchors by doing non maximum suppression (NMS). + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_DETECTION_POSTPROCESSING + </ul> + <td>NEDetectionPostProcessLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0 - src2<th>dst0 - dst3 + <tr><td>QASYMM8<td>F32 + <tr><td>QASYMM8_SIGNED<td>F32 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">DirectConvolutionLayer + <td rowspan="2" style="width:200px;"> Function to compute direct convolution. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONV_2D + </ul> + <td>NEDirectConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLDirectConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="1">DirectDeconvolutionLayer + <td rowspan="1" style="width:200px;"> Function to run the deconvolution layer. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_TRANSPOSE_CONV_2D + </ul> + <td>CLDirectDeconvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="13">ElementwiseOperations + <td rowspan="13" style="width:200px;"> Function to perform in Cpu: - Div - Max - Min - Pow - SquaredDiff - Comparisons (Equal, greater, greater_equal, less, less_equal, not_equal) Function to perform in CL: - Add - Sub - Div - Max - Min - Pow - SquaredDiff + <td rowspan="13"> + <ul> + <li>ANEURALNETWORKS_MAXIMUM + <li>ANEURALNETWORKS_MINIMUM + <li>ANEURALNETWORKS_POW + <li>ANEURALNETWORKS_DIV + <li>ANEURALNETWORKS_ADD + <li>ANEURALNETWORKS_SUB + <li>ANEURALNETWORKS_EQUAL + <li>ANEURALNETWORKS_GREATER + <li>ANEURALNETWORKS_GREATER_EQUAL + <li>ANEURALNETWORKS_LESS + <li>ANEURALNETWORKS_LESS_EQUAL + <li>ANEURALNETWORKS_NOT_EQUAL + </ul> + <td>NEElementwiseMax + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>S32<td>S32<td>S32 + <tr><td>S16<td>S16<td>S16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>NEElementwiseMin + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>S32<td>S32<td>S32 + <tr><td>S16<td>S16<td>S16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>NEElementwiseSquaredDiff + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>S32<td>S32<td>S32 + <tr><td>S16<td>S16<td>S16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>NEElementwiseDivision + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>NEElementwisePower + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>NEElementwiseComparison + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>U8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>U8 + <tr><td>S32<td>S32<td>U8 + <tr><td>U8<td>U8<td>U8 + <tr><td>S16<td>S16<td>U8 + <tr><td>F16<td>F16<td>U8 + <tr><td>F32<td>F32<td>U8 + </table> +<tr> + <td>CLArithmeticAddition + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>U8<td>U8<td>U8 + <tr><td>U8<td>U8<td>S16 + <tr><td>U8<td>S16<td>S16 + <tr><td>S16<td>U8<td>S16 + <tr><td>S16<td>S16<td>S16 + <tr><td>S32<td>S32<td>S32 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLArithmeticSubtraction + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>U8<td>U8<td>U8 + <tr><td>U8<td>U8<td>S16 + <tr><td>U8<td>S16<td>S16 + <tr><td>S16<td>U8<td>S16 + <tr><td>S16<td>S16<td>S16 + <tr><td>S32<td>S32<td>S32 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLArithmeticDivision + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLElementwiseMax + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>U8<td>U8<td>U8 + <tr><td>S16<td>S16<td>S16 + <tr><td>S32<td>S32<td>S32 + <tr><td>U32<td>U32<td>U32 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLElementwiseMin + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>U8<td>U8<td>U8 + <tr><td>S16<td>S16<td>S16 + <tr><td>S32<td>S32<td>S32 + <tr><td>U32<td>U32<td>U32 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLElementwiseSquaredDiff + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>U8<td>U8<td>U8 + <tr><td>S16<td>S16<td>S16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLElementwisePower + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="8">ElementwiseUnaryLayer + <td rowspan="8" style="width:200px;"> Function to perform: - Rsqrt - Exp - Neg - Log - Abs - Round - Sin + <td rowspan="8"> + <ul> + <li>ANEURALNETWORKS_ABS + <li>ANEURALNETWORKS_EXP + <li>ANEURALNETWORKS_LOG + <li>ANEURALNETWORKS_NEG + <li>ANEURALNETWORKS_RSQRT + <li>ANEURALNETWORKS_SIN + </ul> + <td>NEElementwiseUnaryLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>S32<td>S32 + </table> +<tr> + <td>CLRsqrtLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLExpLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLNegLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>S32<td>S32 + </table> +<tr> + <td>CLSinLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLLogLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLAbsLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLRoundLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">FFT1D + <td rowspan="2" style="width:200px;"> Fast Fourier Transform 1D. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEFFT1D + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLFFT1D + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">FFT2D + <td rowspan="2" style="width:200px;"> Fast Fourier Transform 2D. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEFFT2D + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLFFT2D + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">FFTConvolutionLayer + <td rowspan="2" style="width:200px;"> Fast Fourier Transform Convolution. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONV_2D + </ul> + <td>NEFFTConvolutionLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLFFTConvolutionLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">Fill + <td rowspan="2" style="width:200px;"> Set the values of a tensor with a given value. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_FILL + </ul> + <td>NEFill + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLFill + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="1">FillBorder + <td rowspan="1" style="width:200px;"> Function to fill the borders within the XY-planes. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>NEFillBorder + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">FlattenLayer + <td rowspan="2" style="width:200px;"> Reshape a tensor to be 1D + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_RESHAPE + </ul> + <td>NEFlattenLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLFlattenLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Floor + <td rowspan="2" style="width:200px;"> Round the value to the lowest number. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_FLOOR + </ul> + <td>NEFloor + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td>CLFloor + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">FullyConnectedLayer + <td rowspan="2" style="width:200px;"> Function to perform a fully connected / dense layer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_FULLY_CONNECTED + </ul> + <td>NEFullyConnectedLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLFullyConnectedLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">FuseBatchNormalization + <td rowspan="2" style="width:200px;"> Function to fuse the batch normalization node to a preceding convolution node. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEFuseBatchNormalization + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td>CLFuseBatchNormalization + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">Gather + <td rowspan="2" style="width:200px;"> Performs the Gather operation along the chosen axis. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_GATHER + </ul> + <td>NEGather + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLGather + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">GEMM + <td rowspan="2" style="width:200px;"> General Matrix Multiplication. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEGEMM + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>BFLOAT16<td>BFLOAT16<td>BFLOAT16<td>BFLOAT16 + </table> +<tr> + <td>CLGEMM + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>F16<td>F16<td>F16<td>F16 + </table> +<tr> + <td rowspan="1">GEMMConv2d + <td rowspan="1" style="width:200px;"> General Matrix Multiplication. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_CONV_2D + </ul> + <td>NEGEMMConv2d + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>BFLOAT16<td>BFLOAT16<td>BFLOAT16<td>BFLOAT16 + </table> +<tr> + <td rowspan="2">GEMMConvolutionLayer + <td rowspan="2" style="width:200px;"> General Matrix Multiplication. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONV_2D + </ul> + <td>NEGEMMConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>BFLOAT16<td>BFLOAT16<td>BFLOAT16<td>BFLOAT16 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLGEMMConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="1">GEMMDeconvolutionLayer + <td rowspan="1" style="width:200px;"> General Matrix Multiplication. + <td rowspan="1"> + <ul> + <li>ANEURALNETWORKS_TRANSPOSE_CONV_2D + </ul> + <td>CLGEMMDeconvolutionLayer + <td> + <ul> + <li>NHWC + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">GEMMLowpMatrixMultiplyCore + <td rowspan="2" style="width:200px;"> General Matrix Multiplication. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEGEMMLowpMatrixMultiplyCore + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>S32 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>S32 + <tr><td>QASYMM8<td>QSYMM8<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QSYMM8<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>F32<td>F32 + </table> +<tr> + <td>CLGEMMLowpMatrixMultiplyCore + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QSYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QASYMM8<td>S32<td>S32 + <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>S32 + <tr><td>QASYMM8<td>QSYMM8<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QSYMM8<td>S32<td>QASYMM8_SIGNED + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>S32 + <tr><td>QASYMM8_SIGNED<td>QSYMM8<td>S32<td>S32 + </table> +<tr> + <td rowspan="2">GEMMLowpOutputStage + <td rowspan="2" style="width:200px;"> General Matrix Multiplication. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEGEMMLowpOutputStage + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>S32<td>S32<td>QASYMM8 + <tr><td>S32<td>S32<td>QASYMM8_SIGNED + <tr><td>S32<td>S32<td>QSYMM16 + </table> +<tr> + <td>CLGEMMLowpOutputStage + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>S32<td>S32<td>QASYMM8 + <tr><td>S32<td>S32<td>QASYMM8_SIGNED + <tr><td>S32<td>S32<td>QSYMM16 + </table> +<tr> + <td rowspan="2">GenerateProposalsLayer + <td rowspan="2" style="width:200px;"> Function to generate proposals for a RPN (Region Proposal Network). + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_GENERATE_PROPOSALS + </ul> + <td>NEGenerateProposalsLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QSYMM8<td>QSYMM16<td>QASYMM8 + </table> +<tr> + <td>CLGenerateProposalsLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QSYMM8<td>QSYMM16<td>QASYMM8 + </table> +<tr> + <td rowspan="2">InstanceNormalizationLayer + <td rowspan="2" style="width:200px;"> Function to perform a Instance normalization on a given axis. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_INSTANCE_NORMALIZATION + </ul> + <td>NEInstanceNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLInstanceNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">L2NormalizeLayer + <td rowspan="2" style="width:200px;"> Function to perform a L2 normalization on a given axis. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_L2_NORMALIZATION + </ul> + <td>NEL2NormalizeLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLL2NormalizeLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="3">Logical + <td rowspan="3" style="width:200px;"> Function to perform: - Logical AND - Logical OR - Logical NOT + <td rowspan="3"> + <ul> + <li>n/a + </ul> + <td>NELogicalAnd + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>U8<td>U8<td>U8 + </table> +<tr> + <td>NELogicalOr + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>U8<td>U8<td>U8 + </table> +<tr> + <td>NELogicalNot + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td rowspan="1">LogicalAnd + <td rowspan="1" style="width:200px;"> Function to perform Logical AND. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>CLLogicalAnd + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>U8<td>U8<td>U8 + </table> +<tr> + <td rowspan="1">LogicalOr + <td rowspan="1" style="width:200px;"> Function to perform Logical OR. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>CLLogicalOr + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>U8<td>U8<td>U8 + </table> +<tr> + <td rowspan="1">LogicalNot + <td rowspan="1" style="width:200px;"> Function to perform Logical NOT. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>CLLogicalNot + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>U8<td>U8 + </table> +<tr> + <td rowspan="2">LSTMLayer + <td rowspan="2" style="width:200px;"> Function to perform a single time step in a Long Short-Term Memory (LSTM) layer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_LSTM + </ul> + <td>NELSTMLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0 - src13<th>dst0 - dst3 + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLLSTMLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0 - src13<th>dst0 - dst3 + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">LSTMLayerQuantized + <td rowspan="2" style="width:200px;"> Function to perform quantized LSTM (Long Short-Term Memory) + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_QUANTIZED_LSTM + <li>ANEURALNETWORKS_QUANTIZED_16BIT_LSTM + </ul> + <td>NELSTMLayerQuantized + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0 - src8<th>src9 - src12<th>src13<th>src14<th>dst0<th>dst1 + <tr><td>QASYMM8<td>S32<td>QSYMM16<td>QASYMM8<td>QSYMM16<td>QASYMM8 + </table> +<tr> + <td>CLLSTMLayerQuantized + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0 - src8<th>src9 - src12<th>src13<th>src14<th>dst0<th>dst1 + <tr><td>QASYMM8<td>S32<td>QSYMM16<td>QASYMM8<td>QSYMM16<td>QASYMM8 + </table> +<tr> + <td rowspan="2">MatMul + <td rowspan="2" style="width:200px;"> Computes a matrix multiplication in batches. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_BATCH_MATMUL + </ul> + <td>NEMatMul + <td> + <ul> + <li>Any + </ul> + <td> + <table> + <tr><th>lhs<th>rhs<th>dst + <tr><td>F32<td>F32<td>F32 + <tr><td>F16<td>F16<td>F16 + <tr><td>BFLOAT16<td>BFLOAT16<td>BFLOAT16 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + </table> +<tr> + <td>CLMatMul + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>lhs<th>rhs<th>dst + <tr><td>F32<td>F32<td>F32 + <tr><td>F16<td>F16<td>F16 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + </table> +<tr> + <td rowspan="2">MaxUnpoolingLayer + <td rowspan="2" style="width:200px;"> Function to perform MaxUnpooling. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEMaxUnpoolingLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLMaxUnpoolingLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">MeanStdDevNormalizationLayer + <td rowspan="2" style="width:200px;"> Function to execute mean and standard deviation normalization. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEMeanStdDevNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td>CLMeanStdDevNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="2">NormalizationLayer + <td rowspan="2" style="width:200px;"> Function to compute normalization layer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION + </ul> + <td>NENormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td>CLNormalizationLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + </table> +<tr> + <td rowspan="1">NormalizePlanarYUVLayer + <td rowspan="1" style="width:200px;"> Function to compute normalization planar YUV layer. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>CLNormalizePlanarYUVLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + <tr><td>F16<td>F16 + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">PadLayer + <td rowspan="2" style="width:200px;"> Function to pad a tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_PAD + <li>ANEURALNETWORKS_PAD_V2 + </ul> + <td>NEPadLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLPadLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Permute + <td rowspan="2" style="width:200px;"> Function to transpose an ND tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_TRANSPOSE + </ul> + <td>NEPermute + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLPermute + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">PixelWiseMultiplication + <td rowspan="2" style="width:200px;"> Function to perform a multiplication. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_MUL + </ul> + <td>NEPixelWiseMultiplication + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>QSYMM16<td>QSYMM16<td>S32 + <tr><td>U8<td>U8<td>U8 + <tr><td>U8<td>U8<td>S16 + <tr><td>U8<td>S16<td>S16 + <tr><td>S16<td>U8<td>S16 + <tr><td>S16<td>S16<td>S16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>S32<td>F32 + </table> +<tr> + <td>CLPixelWiseMultiplication + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>QASYMM8<td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>QSYMM16<td>QSYMM16<td>QASYMM16 + <tr><td>QSYMM16<td>QSYMM16<td>S32 + <tr><td>U8<td>U8<td>U8 + <tr><td>U8<td>U8<td>S16 + <tr><td>U8<td>S16<td>S16 + <tr><td>S16<td>U8<td>S16 + <tr><td>S16<td>S16<td>S16 + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + <tr><td>S32<td>S32<td>S32 + </table> +<tr> + <td rowspan="2">PoolingLayer + <td rowspan="2" style="width:200px;"> Function to perform pooling with the specified pooling operation. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_AVERAGE_POOL_2D + <li>ANEURALNETWORKS_L2_POOL_2D + <li>ANEURALNETWORKS_MAX_POOL_2D + </ul> + <td>NEPoolingLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLPoolingLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">Pooling3dLayer + <td rowspan="2" style="width:200px;"> Function to perform pooling 3D with the specified pooling operation. + <td rowspan="2"> + <ul> + <li>N/A + </ul> + <td>NEPooling3dLayer + <td> + <ul> + <li>NDHWC + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLPooling3dLayer + <td> + <ul> + <li>NDHWC + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">PReluLayer + <td rowspan="2" style="width:200px;"> Function to compute the activation layer with the PRELU activation function. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_PRELU + </ul> + <td>NEPReluLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLPReluLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">PriorBoxLayer + <td rowspan="2" style="width:200px;"> Function to compute prior boxes and clip. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEPriorBoxLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLPriorBoxLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="2">QLSTMLayer + <td rowspan="2" style="width:200px;"> Function to perform quantized LSTM (Long Short-Term Memory). + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_QUANTIZED_LSTM + <li>ANEURALNETWORKS_QUANTIZED_16BIT_LSTM + </ul> + <td>NEQLSTMLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1 - src6<th>src7 -src9<th>src10<th>src11<th>dst0<th>dst1 - dst2 + <tr><td>QASYMM8_SIGNED<td>QASYMM8<td>S32<td>QSYMM16<td>QASYMM8_SIGNED<td>QSYMM16<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLQLSTMLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1 - src6<th>src7 -src9<th>src10<th>src11<th>dst0<th>dst1 - dst2 + <tr><td>QASYMM8_SIGNED<td>QASYMM8<td>S32<td>QSYMM16<td>QASYMM8_SIGNED<td>QSYMM16<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">QuantizationLayer + <td rowspan="2" style="width:200px;"> Function to perform quantization layer + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_QUANTIZE + </ul> + <td>NEQuantizationLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + <tr><td>QASYMM8_SIGNED<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + <tr><td>F16<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + <tr><td>F32<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + </table> +<tr> + <td>CLQuantizationLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + <tr><td>QASYMM8_SIGNED<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + <tr><td>F16<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + <tr><td>F32<td>QASYMM8, QASYMM8_SIGNED, QASYMM16 + </table> +<tr> + <td rowspan="2">Range + <td rowspan="2" style="width:200px;"> Function to generates a sequence of numbers starting from START and extends by increments of 'STEP' up to but not including 'END'. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NERange + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>dst + <tr><td>U8 + <tr><td>S8 + <tr><td>U16 + <tr><td>S16 + <tr><td>U32 + <tr><td>S32 + <tr><td>F16 + <tr><td>F32 + </table> +<tr> + <td>CLRange + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>dst + <tr><td>U8 + <tr><td>S8 + <tr><td>QASYMM8 + <tr><td>U16 + <tr><td>S16 + <tr><td>U32 + <tr><td>S32 + <tr><td>F16 + <tr><td>F32 + </table> +<tr> + <td rowspan="2">ReduceMean + <td rowspan="2" style="width:200px;"> Function to perform reduce mean operation. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_MEAN + </ul> + <td>NEReduceMean + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLReduceMean + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">ReductionOperation + <td rowspan="2" style="width:200px;"> Function to perform reduce with the following operations - ARG_IDX_MAX: Index of the max value - ARG_IDX_MIN: Index of the min value - MEAN_SUM: Mean of sum - PROD: Product - SUM_SQUARE: Sum of squares - SUM: Sum - MIN: Min - MAX: Max + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_REDUCE_ALL + <li>ANEURALNETWORKS_REDUCE_ANY + <li>ANEURALNETWORKS_REDUCE_MAX + <li>ANEURALNETWORKS_REDUCE_MIN + <li>ANEURALNETWORKS_REDUCE_PROD + <li>ANEURALNETWORKS_REDUCE_SUM + </ul> + <td>NEReductionOperation + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>S32<td>S32 + </table> +<tr> + <td>CLReductionOperation + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>S32<td>S32 + </table> +<tr> + <td rowspan="1">ReorderLayer + <td rowspan="1" style="width:200px;"> Reorders a tensor to a different weights format. + <td rowspan="1"> + <ul> + <li>n/a + </ul> + <td>NEReorderLayer + <td> + <ul> + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">ReorgLayer + <td rowspan="2" style="width:200px;"> Performs a reorganization layer of input tensor to the output tensor. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEReorgLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLReorgLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">ReshapeLayer + <td rowspan="2" style="width:200px;"> Function to reshape a tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_RESHAPE + <li>ANEURALNETWORKS_SQUEEZE + </ul> + <td>NEReshapeLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLReshapeLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Reverse + <td rowspan="2" style="width:200px;"> Function to reverse tensor according to axis. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEReverse + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>All<td>U32, S32<td>All + </table> +<tr> + <td>CLReverse + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>All<td>U32, S32<td>All + </table> +<tr> + <td rowspan="2">RNNLayer + <td rowspan="2" style="width:200px;"> Function to perform recurrent neural network layer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_RNN + </ul> + <td>NERNNLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>src3<th>dst0<th>dst1 + <tr><td>F16<td>F16<td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLRNNLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>src3<th>dst0<th>dst1 + <tr><td>F16<td>F16<td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32<td>F32<td>F32 + </table> +<tr> + <td rowspan="2">ROIAlignLayer + <td rowspan="2" style="width:200px;"> Function to perform ROI alignment. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_ROI_ALIGN + </ul> + <td>NEROIAlignLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM16<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM16<td>QASYMM8_SIGNED + </table> +<tr> + <td>CLROIAlignLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32 + <tr><td>QASYMM8<td>QASYMM16<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM16<td>QASYMM8_SIGNED + </table> +<tr> + <td rowspan="2">ROIPoolingLayer + <td rowspan="2" style="width:200px;"> Function to perform ROI pooling. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_ROI_POOLING + </ul> + <td>NEROIPoolingLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F32<td>U16<td>F32 + <tr><td>QASYMM8<td>U16<td>QASYMM8 + </table> +<tr> + <td>CLROIPoolingLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>dst + <tr><td>F16<td>U16<td>F16 + <tr><td>F32<td>U16<td>F32 + <tr><td>QASYMM8<td>U16<td>QASYMM8 + </table> +<tr> + <td rowspan="2">Scale + <td rowspan="2" style="width:200px;"> Function to perform resize a tensor using to interpolate: - Bilinear - Nearest neighbor + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_RESIZE_BILINEAR + <li>ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR + </ul> + <td>NEScale + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>U8<td>U8 + <tr><td>S8<td>S8 + <tr><td>S16<td>S16 + </table> +<tr> + <td>CLScale + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + <tr><td>U8<td>U8 + <tr><td>S16<td>S16 + </table> +<tr> + <td rowspan="2">Select + <td rowspan="2" style="width:200px;"> Function to select values from 2 tensors depending on an input tensor of booleans. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_SELECT + </ul> + <td>NESelect + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>U8<td>All<td>All<td>All + </table> +<tr> + <td>CLSelect + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>U8<td>All<td>All<td>All + </table> +<tr> + <td rowspan="2">Slice + <td rowspan="2" style="width:200px;"> Function to perform tensor slicing. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_SLICE + </ul> + <td>NESlice + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLSlice + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">SoftmaxLayer + <td rowspan="2" style="width:200px;"> Function to compute a SoftmaxLayer and a Log SoftmaxLayer. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_LOG_SOFTMAX + <li>ANEURALNETWORKS_SOFTMAX + </ul> + <td>NESoftmaxLayerGeneric + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td>CLSoftmaxLayerGeneric + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>QASYMM8<td>QASYMM8 + <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED + <tr><td>F16<td>F16 + <tr><td>F32<td>F32 + </table> +<tr> + <td rowspan="2">SpaceToBatchLayer + <td rowspan="2" style="width:200px;"> Function to divide a tensor spatially. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_SPACE_TO_BATCH_ND + </ul> + <td>NESpaceToBatchLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>All<td>S32<td>S32<td>All + </table> +<tr> + <td>CLSpaceToBatchLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>All<td>S32<td>S32<td>All + </table> +<tr> + <td rowspan="2">SpaceToDepthLayer + <td rowspan="2" style="width:200px;"> Function to rearrange blocks of spatial data into depth. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_SPACE_TO_DEPTH + </ul> + <td>NESpaceToDepthLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLSpaceToDepthLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Split + <td rowspan="2" style="width:200px;"> Function to split a tensor along a given axis. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_SPLIT + </ul> + <td>NESplit + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLSplit + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">StackLayer + <td rowspan="2" style="width:200px;"> Function to stack tensors along an axis. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEStackLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLStackLayer + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">StridedSlice + <td rowspan="2" style="width:200px;"> Function to extract a strided slice of a tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_STRIDED_SLICE + </ul> + <td>NEStridedSlice + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLStridedSlice + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Tile + <td rowspan="2" style="width:200px;"> Function to construct a tensor by tiling a given tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_TILE + </ul> + <td>NETile + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLTile + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Transpose + <td rowspan="2" style="width:200px;"> Function to transpose a 2D tensor. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_TRANSPOSE + </ul> + <td>NETranspose + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLTranspose + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">Unstack + <td rowspan="2" style="width:200px;"> Function to unpack a rank-R tensor into rank-(R-1) tensors. + <td rowspan="2"> + <ul> + <li>n/a + </ul> + <td>NEUnstack + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td>CLUnstack + <td> + <ul> + <li>All + </ul> + <td> + <table> + <tr><th>src<th>dst + <tr><td>All<td>All + </table> +<tr> + <td rowspan="2">WinogradConvolutionLayer + <td rowspan="2" style="width:200px;"> Function to do Winograd Convolution. + <td rowspan="2"> + <ul> + <li>ANEURALNETWORKS_CONV_2D + </ul> + <td>NEWinogradConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + </table> +<tr> + <td>CLWinogradConvolutionLayer + <td> + <ul> + <li>NHWC + <li>NCHW + </ul> + <td> + <table> + <tr><th>src0<th>src1<th>src2<th>dst + <tr><td>F16<td>F16<td>F16<td>F16 + <tr><td>F32<td>F32<td>F32<td>F32 + </table> +</table> + +*/ +} // namespace diff --git a/docs/user_guide/release_version_and_change_log.dox b/docs/user_guide/release_version_and_change_log.dox new file mode 100644 index 0000000000..a5f61d669d --- /dev/null +++ b/docs/user_guide/release_version_and_change_log.dox @@ -0,0 +1,1719 @@ +/// +/// Copyright (c) 2017-2024 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +/** @page versions_changelogs Release Versions and Changelog + +@tableofcontents + +@section S2_1_versions Release versions + +All releases are numbered vYY.MM Where YY are the last two digits of the year, and MM the month number. +If there is more than one release in a month then an extra sequential number is appended at the end: + + v17.03 (First release of March 2017) + v17.03.1 (Second release of March 2017) + v17.04 (First release of April 2017) + +@note We're aiming at releasing one major public release with new features per quarter. All releases in between will only contain bug fixes. +@note Starting from release 22.05, 'master' branch is no longer being used, it has been replaced by 'main'. Please update your clone jobs accordingly. + +@section S2_2_changelog Changelog + +v24.05 Public major release + - Add @ref CLScatter operator for FP32/16, S32/16/8, U32/16/8 data types + - Various fixes to enable FP16 kernels in armv8a multi_isa builds. + - Updated logic in the OpenMP scheduler to exclude LITTLE cores. + +v24.04 Public major release + - Add Bfloat16 data type support for @ref NEMatMul. + - Add support for SoftMax in SME2 for FP32, FP16, QASYMM8 and QASYMM8_SIGNED. + - Add support for in place accumulation to CPU GEMM kernels. + - Add low-precision Int8 * Int8 -> FP32 CPU GEMM which dequantizes after multiplication + - Add is_dynamic flag to QuantizationInfo to signal to operators that it may change after configuration + - Performance optimizations: + - Optimize start-up time of @ref NEConvolutionLayer for some input configurations where GeMM is selected as the convolution algorithm + - Optimize @ref NEConvolutionLayer for input tensor size > 1e7 bytes and weight tensor height > 7 + - Optimize @ref NESoftmaxLayer for axis != 0 by natively supporting higher axes up to axis 3. + +v24.02.1 Public patch release + - Fix performance regression in fixed-format kernels + - Fix compile and runtime errors in arm_compute_validation for Windows on Arm(WoA) + +v24.02 Public major release + - Replace template writer with compute kernel writer in dynamic fusion. + - Performance optimizations: + - Parallelize @ref NEDepthwiseConvolutionLayer over batches if there is only 1 row + +v24.01 Public major release + - Remove the legacy 'libarm_compute_core' library. This library is an artifact of Compute Library's legacy library architecture and no longer serves any purpose. + You should link only to the main `libarm_compute` library for core functionality. + - Expand GPUTarget list with Mali™ G720 and G620. + - Optimize CPU activation functions using LUT-based implementation: + - Sigmoid function for FP16. + - New features + - Add support for FP16 in all multi_isa builds. + - Performance optimizations: + - Optimize @ref NESoftmaxLayer + - Optimize @ref NEDepthToSpaceLayer. + +v23.11 Public major release + - New features + - Add support for input data type U64/S64 in CLCast and NECast. + - Add support for output data type S64 in NEArgMinMaxLayer and CLArgMinMaxLayer + - Port the following kernels in the experimental Dynamic Fusion interface to use the new Compute Kernel Writer interface: + - @ref experimental::dynamic_fusion::GpuCkwResize + - @ref experimental::dynamic_fusion::GpuCkwPool2d + - @ref experimental::dynamic_fusion::GpuCkwDepthwiseConv2d + - @ref experimental::dynamic_fusion::GpuCkwMatMul + - Add support for OpenCL™ comand buffer with mutable dispatch extension. + - Add support for Arm® Cortex®-A520 and Arm® Cortex®-R82. + - Add support for negative axis values and inverted axis values in @ref arm_compute::NEReverse and @ref arm_compute::CLReverse. + - Add new OpenCL™ kernels: + - @ref opencl::kernels::ClMatMulLowpNativeMMULKernel support for QASYMM8 and QASYMM8_SIGNED, with batch support + - Performance optimizations: + - Optimize @ref cpu::CpuReshape + - Optimize @ref opencl::ClTranspose + - Optimize @ref NEStackLayer + - Optimize @ref CLReductionOperation. + - Optimize @ref CLSoftmaxLayer. + - Optimize start-up time of @ref NEConvolutionLayer for some input configurations where GeMM is selected as the convolution algorithm + - Reduce CPU Overhead by optimal flushing of CL kernels. + - Deprecate support for Bfloat16 in @ref cpu::CpuCast. + - Support for U32 axis in @ref arm_compute::NEReverse and @ref arm_compute::CLReverse will be deprecated in 24.02. + - Remove legacy PostOps interface. PostOps was the experimental interface for kernel fusion and is replaced by the new Dynamic Fusion interface. + - Update OpenCL™ API headers to v2023.04.17 + +v23.08 Public major release + - Deprecate the legacy 'libarm_compute_core' library. This library is an artifact of Compute Library's legacy library architecture and no longer serves any purpose. + Users must no longer link their applications to this library and instead link only to the main `libarm_compute` library for core functionality. + - New features + - Rewrite CLArgMinMaxLayer for axis 0 and enable S64 output. + - Add multi-sketch support for dynamic fusion. + - Break up arm_compute/core/Types.h and utils/Utils.h a bit to reduce unused code in each inclusion of these headers. + - Add Fused Activation to CLMatMul. + - Implement FP32/FP16 @ref opencl::kernels::ClMatMulNativeMMULKernel using the MMUL extension. + - Use MatMul in fully connected layer with dynamic weights when supported. + - Optimize CPU depthwise convolution with channel multiplier. + - Add support in CpuCastKernel for conversion of S64/U64 to F32. + - Add new OpenCL™ kernels: + - @ref opencl::kernels::ClMatMulNativeMMULKernel support for FP32 and FP16, with batch support + - Enable transposed convolution with non-square kernels on CPU and GPU. + - Add support for input data type U64/S64 in CLCast. + - Add new Compute Kernel Writer (CKW) subproject that offers a C++ interface to generate tile-based OpenCL code in just-in-time fashion. + - Port the following kernels in the experimental Dynamic Fusion interface to use the new Compute Kernel Writer interface with support for FP16/FP32 only: + - @ref experimental::dynamic_fusion::GpuCkwActivation + - @ref experimental::dynamic_fusion::GpuCkwCast + - @ref experimental::dynamic_fusion::GpuCkwDirectConv2d + - @ref experimental::dynamic_fusion::GpuCkwElementwiseBinary + - @ref experimental::dynamic_fusion::GpuCkwStore + - Various optimizations and bug fixes. + +v23.05.1 Public patch release + - Enable CMake and Bazel option to build multi_isa without FP16 support. + - Fix compilation error in NEReorderLayer (aarch64 only). + - Disable invalid (false-negative) validation test with CPU scale layer on FP16. + - Various bug fixes + +v23.05 Public major release + - New features: + - Add new Arm® Neon™ kernels / functions: + - @ref NEMatMul for QASYMM8, QASYMM8_SIGNED, FP32 and FP16, with batch support. + - NEReorderLayer (aarch64 only) + - Add new OpenCL™ kernels / functions: + - @ref CLMatMul support for QASYMM8, QASYMM8_SIGNED, FP32 and FP16, with batch support. + - Add support for the multiple dimensions in the indices parameter for both the Arm® Neon™ and OpenCL™ implementations of the Gather Layer. + - Add support for dynamic weights in @ref CLFullyConnectedLayer and @ref NEFullyConnectedLayer for all data types. + - Add support for cropping in the Arm® Neon™ and OpenCL™: implementations of the BatchToSpace Layer for all data types. + - Add support for quantized data types for the ElementwiseUnary Operators for Arm® Neon™. + - Implement RSQRT for quantized data types on OpenCL™. + - Add FP16 depthwise convolution kernels for SME2. + - Performance optimizations: + - Improve CLTuner exhaustive mode tuning time. + - Deprecate dynamic block shape in @ref NEBatchToSpaceLayer and @ref CLBatchToSpaceLayer. + - Various optimizations and bug fixes. + +v23.02.1 Public patch release + - Allow mismatching data layouts between the source tensor and weights for \link cpu::CpuGemmDirectConv2d CpuGemmDirectConv2d \endlink with fixed format kernels. + - Fixes for experimental CPU only Bazel and CMake builds. + +v23.02 Public major release + - New features: + - Rework the experimental dynamic fusion interface by identifying auxiliary and intermediate tensors, and specifying an explicit output operator. + - Add the following operators to the experimental dynamic fusion API: + - GpuAdd, GpuCast, GpuClamp, GpuDepthwiseConv2d, GpuMul, GpuOutput, GpuPool2d, GpuReshape, GpuResize, GpuSoftmax, GpuSub. + - Add SME/SME2 kernels for GeMM, Winograd convolution, Depthwise convolution and Pooling. + - Add new CPU operator AddMulAdd for float and quantized types. + - Add new flag @ref ITensorInfo::lock_paddings() to tensors to prevent extending tensor paddings. + - Add experimental support for CPU only Bazel and CMake builds. + - Performance optimizations: + - Optimize CPU base-e exponential functions for FP32. + - Optimize CPU StridedSlice by copying first dimension elements in bulk where possible. + - Optimize CPU quantized Subtraction by reusing the quantized Addition kernel. + - Optimize CPU ReduceMean by removing quantization steps and performing the operation in integer domain. + - Optimize GPU Scale and Dynamic Fusion GpuResize by removing quantization steps and performing the operation in integer domain. + - Update the heuristic for CLDepthwiseConvolutionNative kernel. + - Add new optimized OpenCL kernel to compute indirect convolution: + - \link opencl::kernels::ClIndirectConv2dKernel ClIndirectConv2dKernel \endlink + - Add new optimized OpenCL kernel to compute transposed convolution: + - \link opencl::kernels::ClTransposedConvolutionKernel ClTransposedConvolutionKernel \endlink + - Update recommended/minimum NDK version to r20b. + - Various optimizations and bug fixes. + +v22.11 Public major release + - New features: + - Add new experimental dynamic fusion API. + - Add CPU batch matrix multiplication with adj_x = false and adj_y = false for FP32. + - Add CPU MeanStdDevNorm for QASYMM8. + - Add CPU and GPU GELU activation function for FP32 and FP16. + - Add CPU swish activation function for FP32 and FP16. + - Performance optimizations: + - Optimize CPU bilinear scale for FP32, FP16, QASYMM8, QASYMM8_SIGNED, U8 and S8. + - Optimize CPU activation functions using LUT-based implementation: + - Sigmoid function for QASYMM8 and QASYMM8_SIGNED. + - Hard swish function for QASYMM8_SIGNED. + - Optimize CPU addition for QASYMM8 and QASYMM8_SIGNED using fixed-point arithmetic. + - Optimize CPU multiplication, subtraction and activation layers by considering tensors as 1D. + - Optimize GPU depthwise convolution kernel and heuristic. + - Optimize GPU Conv2d heuristic. + - Optimize CPU MeanStdDevNorm for FP16. + - Optimize CPU tanh activation function for FP16 using rational approximation. + - Improve GPU GeMMLowp start-up time. + - Various optimizations and bug fixes. + +v22.08 Public major release + - Various bug fixes. + - Disable unsafe FP optimizations causing accuracy issues in: + - \link opencl::kernels::ClDirectConv2dKernel ClDirectConv2dKernel \endlink + - \link opencl::kernels::ClDirectConv2dKernel ClDirectConv3dKernel \endlink + - @ref CLDepthwiseConvolutionLayerNativeKernel + - Add Dynamic Fusion of Elementwise Operators: Div, Floor, Add. + - Optimize the gemm_reshaped_rhs_nly_nt OpenCL kernel using the arm_matrix_multiply extension available for Arm® Mali™-G715 and Arm® Mali™-G615. + - Add support for the arm_matrix_multiply extension in the gemmlowp_mm_reshaped_only_rhs_t OpenCL kernel. + - Expand GPUTarget list with missing Mali™ GPUs product names: G57, G68, G78AE, G610, G510, G310. + - Extend the direct convolution 2d interface to configure the block size. + - Update ClConv2D heuristic to use direct convolution. + - Use official Khronos® OpenCL extensions: + - Add cl_khr_integer_dot_product extension support. + - Add support of OpenCL 3.0 non-uniform workgroup. + - Cpu performance optimizations: + - Add LUT-based implementation of Hard Swish and Leaky ReLU activation function for aarch64 build. + - Optimize Add layer by considering the input tensors as 1D array. + - Add fixed-format BF16, FP16 and FP32 Neon™ GEMM kernels to support variable weights. + - Add new winograd convolution kernels implementation and update the ACL \link arm_compute::cpu::CpuWinogradConv2d CpuWinogradConv2d\endlink operator. + - Add experimental support for native builds for Windows® on Arm™. + - Build flag interpretation change: arch=armv8.6-a now translates to -march=armv8.6-a CXX flag instead of march=armv8.2-a + explicit selection of feature extensions. + - Build flag change: toolchain_prefix, compiler_prefix: + - Use empty string "" to suppress any prefixes. + - Use "auto" to use default (auto) prefixes chosen by the build script. This is the default behavior when unspecified. + - Any other string will be used as custom prefixes to the compiler and the rest of toolchain tools. + - The default behaviour when prefix is unspecified does not change, but its signifier has been changed from empty string "" to "auto". + - armv7a with Android build will no longer be tested or maintained. + +v22.05 Public major release + - Various bug fixes. + - Various optimizations. + - Add support for NDK r23b. + - Inclusive language adjustment. Please refer to @ref S5_0_inc_lang for details. + - New Arm® Neon™ kernels / functions : + - \link opencl::kernels::ClPool3dKernel ClPool3dKernel \endlink + - New OpenCL kernels / functions : + - \link cpu::kernels::CpuPool3dKernel CpuPool3dKernel \endlink + - Improve the start-up times for the following OpenCL kernels: + - \link opencl::kernels::ClWinogradInputTransformKernel ClWinogradInputTransformKernel \endlink + - \link opencl::kernels::ClWinogradOutputTransformKernel ClWinogradOutputTransformKernel \endlink + - \link opencl::kernels::ClWinogradFilterTransformKernel ClWinogradFilterTransformKernel \endlink + - \link opencl::kernels::ClHeightConcatenateKernel ClHeightConcatenateKernel \endlink + - Decouple the implementation of the following Cpu kernels into various data types (fp32, fp16, int): + - \link cpu::kernels::CpuDirectConv2dKernel CpuDirectConv2dKernel \endlink + - \link cpu::kernels::CpuDepthwiseConv2dNativeKernel CpuDepthwiseConv2dNativeKernel \endlink + - \link cpu::kernels::CpuGemmMatrixAdditionKernel CpuGemmMatrixAdditionKernel \endlink + - \link cpu::kernels::CpuGemmMatrixMultiplyKernel CpuGemmMatrixMultiplyKernel \endlink + - @ref NEFuseBatchNormalizationKernel + - @ref NEL2NormalizeLayerKernel + +v22.02 Public major release + - Various bug fixes. + - Various optimizations. + - Update A510 arm_gemm cpu Kernels. + - Inclusive language adjustment. Please refer to @ref S5_0_inc_lang for details. + - Improve the start-up time for the following OpenCL kernels: + - @ref CLScale + - @ref CLGEMM + - @ref CLDepthwiseConvolutionLayer + - \link opencl::kernels::ClIm2ColKernel ClIm2ColKernel \endlink + - \link opencl::kernels::ClDirectConv2dKernel ClDirectConv2dKernel \endlink + - Remove functions: + - CLRemap + - NERemap + - Remove padding from OpenCL kernels: + - \link opencl::kernels::ClDirectConv2dKernel ClDirectConv2dKernel \endlink + - Remove padding from Cpu kernels: + - \link cpu::kernels::CpuDirectConv2dKernel CpuDirectConv2dKernel \endlink + - Decouple the implementation of the following Cpu kernels into various data types (fp32, fp16, int): + - \link cpu::kernels::CpuActivationKernel CpuActivationKernel \endlink + - \link cpu::kernels::CpuAddKernel CpuAddKernel \endlink + - \link cpu::kernels::CpuElementwiseKernel CpuElementwiseKernel \endlink + - \link cpu::CpuSoftmaxGeneric CpuSoftmaxKernel \endlink + - @ref NEBoundingBoxTransformKernel + - @ref NECropKernel + - @ref NEComputeAllAnchorsKernel + - @ref NEInstanceNormalizationLayerKernel + - NEMaxUnpoolingLayerKernel + - @ref NEMeanStdDevNormalizationKernel + - @ref NERangeKernel + - @ref NEROIAlignLayerKernel + - @ref NESelectKernel + +v21.11 Public major release + - Various bug fixes. + - Various optimizations: + - Improve performance of bilinear and nearest neighbor Scale on both CPU and GPU for FP32, FP16, Int8, Uint8 data types + - Improve performance of Softmax on GPU for Uint8/Int8 + - New OpenCL kernels / functions: + - @ref CLConv3D + - New Arm® Neon™ kernels / functions: + - @ref NEConv3D + - Support configurable build by a selected subset of operator list + - Support MobileBert on Neon™ backend + - Improve operator/function logging + - Remove padding from OpenCL kernels: + - ClPool2dKernel + - ClScaleKernel + - ClGemmMatrixMultiplyReshapedKernel + - Remove padding from Cpu kernels: + - CpuPool2dKernel + - Remove Y padding from OpenCL kernels: + - ClGemmMatrixMultiplyKernel + - ClGemmReshapedRHSMatrixKernel + - Remove legacy GeMM kernels in gemm_v1.cl + +v21.08 Public major release + - Various bug fixes. + - Various optimizations: + - Improve LWS (Local-Workgroup-Size) heuristic in OpenCL for GeMM, Direct Convolution and Winograd Transformations when OpenCL tuner is not used + - Improve QASYMM8/QSYMM8 performance on OpenCL for various Arm® Mali™ GPU architectures + - Add dynamic weights support in Fully connected layer (CPU/GPU) + - Various performance optimizations for floating-point data types (CPU/GPU) + - Add a reduced core library build arm_compute_core_v2 + - Expose Operator API + - Support fat binary build for arm8.2-a via fat_binary build flag + - Add CPU discovery capabilities + - Add data type f16 support for: + - CLRemapKernel + - Port the following functions to stateless API: + - @ref CLConvolutionLayer + - @ref CLFlattenLayer + - @ref CLFullyConnectedLayer + - @ref CLGEMM + - @ref CLGEMMConvolutionLayer + - @ref CLGEMMLowpMatrixMultiplyCore + - @ref CLWinogradConvolutionLayer + - @ref NEConvolutionLayer + - @ref NEFlattenLayer + - @ref NEFullyConnectedLayer + - @ref NEGEMM + - @ref NEGEMMConv2d + - @ref NEGEMMConvolutionLayer + - @ref NEGEMMLowpMatrixMultiplyCore + - @ref NEWinogradConvolutionLayer + - Remove the following functions: + - CLWinogradInputTransform + - Remove CLCoreRuntimeContext + - Remove ICPPSimpleKernel + - Rename file arm_compute/runtime/CL/functions/CLElementWiseUnaryLayer.h to arm_compute/runtime/CL/functions/CLElementwiseUnaryLayer.h + +v21.05 Public major release + - Various bug fixes. + - Various optimisations. + - Various documentation updates: + - Add supported operators and corresponding Android NNAPI operators. + - Documentation reorg into user guide and contributor guide. + - Add support for a global allocator for OpenCL tensors + - Add experimental support for [CLVK](https://github.com/kpet/clvk). + - Add data type S32 support for: + - @ref opencl::kernels::ClArithmeticKernel + - Add data type QASYMM8 support for: + - @ref CLROIPoolingLayer + - @ref CLROIPoolingLayerKernel + - @ref NEROIPoolingLayer + - @ref NEROIPoolingLayerKernel + - Add per-channel quantization support for: + - @ref CLDeconvolutionLayer + - @ref CLDirectDeconvolutionLayer + - @ref NEConvolutionLayer + - @ref NEDeconvolutionLayer + - Remove padding from OpenCL kernels: + - @ref CLL2NormalizeLayerKernel + - CLDepthwiseConvolutionLayer3x3NHWCKernel + - @ref CLNormalizationLayerKernel + - @ref CLNormalizePlanarYUVLayerKernel + - @ref opencl::kernels::ClMulKernel + - @ref CLReductionOperationKernel + - @ref CLROIPoolingLayerKernel + - Remove computer vision support from Arm® Neon™ backend + - Remove the following functions: + - NEAbsoluteDifference + - NEAccumulate + - NEBox3x3 + - NECannyEdge + - NEChannelCombine + - NEChannelExtract + - NEColorConvert + - NEConvolution + - NEDerivative + - NEDilate + - NEEqualizeHistogram + - NEErode + - NEFastCorners + - NEGaussian3x3 + - NEGaussian5x5 + - NEGaussianPyramid + - NEHOGDescriptor + - NEHOGDetector + - NEHOGGradient + - NEHOGMultiDetection + - NEHarrisCorners + - NEHistogram + - NEIntegralImage + - NELaplacianPyramid + - NELaplacianReconstruct + - NEMagnitude + - NEMeanStdDev + - NEMedian3x3 + - NEMinMaxLocation + - NENonLinearFilter + - NEOpticalFlow + - NEPhase + - NEScharr3x3 + - NESobel3x3 + - NESobel5x5 + - NESobel7x7 + - NETableLookup + - NEThreshold + - NEWarpAffine + - NEWarpPerspectiveKernel + - Remove all GLES kernels / functions / tests / examples + - Remove computer vision support from CL backend + - Remove the following functions: + - CLAbsoluteDifference + - CLAccumulate + - CLBox3x3 + - CLCannyEdge + - CLChannelCombine + - CLChannelExtract + - CLColorConvert + - CLConvolution + - CLDerivative + - CLDilate + - CLEqualizeHistogram + - CLErode + - CLFastCorners + - CLGaussian3x3 + - CLGaussian5x5 + - CLGaussianPyramid + - CLHOGDescriptor + - CLHOGDetector + - CLHOGGradient + - CLHOGMultiDetection + - CLHarrisCorners + - CLHistogram + - CLIntegralImage + - CLLaplacianPyramid + - CLLaplacianReconstruct + - CLMagnitude + - CLMeanStdDev + - CLMedian3x3 + - CLMinMaxLocation + - CLNonLinearFilter + - CLOpticalFlow + - CLPhase + - CLScharr3x3 + - CLSobel3x3 + - CLSobel5x5 + - CLSobel7x7 + - CLTableLookup + - CLThreshold + - CLWarpAffine + - CLWarpPerspective + +v21.02 Public major release + - Various bug fixes. + - Various optimisations. + - Upgrade C++ standard to C++14 + - Add macOS support + - Add Armv8-R AArch64 architecture support + - Add SVE/SVE2 support for: + - NEScaleKernel + - @ref NEActivationLayer + - @ref NEArithmeticAddition + - @ref NEBatchNormalizationLayerKernel + - cpu::kernels::CpuLogits1DSoftmaxKernel + - cpu::kernels::CpuLogits1DMaxKernel + - @ref cpu::kernels::CpuElementwiseUnaryKernel + - Remove padding from OpenCL kernels: + - CLDirectConvolutionLayerKernel + - @ref CLArgMinMaxLayerKernel + - @ref CLPadLayerKernel + - @ref CLROIAlignLayerKernel + - @ref CLRangeKernel + - CLScaleKernel + - @ref CLSelectKernel + - @ref CLBitwiseKernel + - @ref opencl::kernels::ClFloorKernel + - CLTransposeKernel + - Deprecate functions in CLTuner: + - add_lws_to_table + - import_lws_table + - lws_table + - Remove functions: + - NELocallyConnectedLayer / CLLocallyConnectedLayer + - NEIm2Col + - NECol2Im + - NEGEMMInterleave4x4 + - NEGEMMTranspose1xW + - NEComputeAllAnchors / CLComputeAllAnchors + - NEGEMMAssemblyDispatch + - NEUpsampleLayer / CLUpsampleLayer + - Remove kernels: + - NEGEMMMatrixVectorMultiplyKernel + - NELocallyConnectedMatrixMultiplyKernel / CLLocallyConnectedMatrixMultiplyKernel + - NEUpsampleLayerKernel / CLUpsampleLayerKernel + - Extend OpenCL tuner with workgroup batch size support + - Experimental extension for the OpenCL tuner to tune the batches of work groups distribute to compute units + - Add functionality to load the OpenCL GEMM heuristics at runtime + - The GEMM heuristic file (MLGO) can be used to update the default GEMM heuristics available for OpenCL + - Note: there might be performance regressions against v20.08 in Inception v3 using int8 data types on Arm Mali-G77 GPUs. Currently under investigation + - Note: data-type decoupling is in progress and experimental. Warning of unused symbols might be raised + +v20.11 Public major release + - Various bug fixes. + - Various optimisations. + - Performance regressions can be noted when executing Depthwise Convolution on Arm® Neon™ with a depth multiplier > 1 for quantized data type. + This is planned to be resolved in 21.02 release. + - Added new data type QASYMM8_SIGNED support for @ref NEROIAlignLayer. + - Added new data type S32 support for: + - NEArithmeticSubtraction + - NEArithmeticSubtractionKernel + - @ref NEPixelWiseMultiplication + - NEPixelWiseMultiplicationKernel + - NEElementwiseDivision + - NEDivisionOperationKernel + - Interface change + - Properly support softmax axis to have the same meaning as other major frameworks. That is, axis now defines the dimension + on which Softmax/Logsoftmax is performed. E.g. for input of shape 4x5x6 and axis=1, softmax will be applied to 4x6=24 vectors of size 5. + The supported value range of axis is [-rank, rank). + This change applies to the following functions: + - @ref NESoftmaxLayer + - @ref NELogSoftmaxLayer + - @ref CLSoftmaxLayer + - @ref CLLogSoftmaxLayer + - GCSoftmaxLayer + - New OpenCL kernels / functions: + - CLGEMMLowpQuantizeDownInt32ScaleByFixedPointKernel + - @ref CLLogicalNot + - @ref CLLogicalAnd + - @ref CLLogicalOr + - New Arm® Neon™ kernels / functions: + - @ref NELogicalNot + - @ref NELogicalAnd + - @ref NELogicalOr + - Removed padding from Arm® Neon™ kernels: + - NEComplexPixelWiseMultiplicationKernel + - NENonMaximaSuppression3x3Kernel + - NERemapKernel + - NEGEMMInterleave4x4Kernel + - NEDirectConvolutionLayerKernel + - NEScaleKernel + - NELocallyConnectedMatrixMultiplyKernel + - NEGEMMLowpOffsetContributionKernel + - NEGEMMTranspose1xWKernel + - NEPoolingLayerKernel + - NEConvolutionKernel + - NEDepthwiseConvolutionLayerNativeKernel + - NEGEMMLowpMatrixMultiplyKernel + - NEGEMMMatrixMultiplyKernel + - NEDirectConvolutionLayerOutputStageKernel + - @ref NEReductionOperationKernel + - NEGEMMLowpMatrixAReductionKernel + - NEGEMMLowpMatrixBReductionKernel + - Removed padding from OpenCL kernels: + - CLBatchConcatenateLayerKernel + - CLElementwiseOperationKernel + - @ref CLBatchNormalizationLayerKernel + - CLPoolingLayerKernel + - CLWinogradInputTransformKernel + - CLGEMMLowpMatrixMultiplyNativeKernel + - CLGEMMLowpMatrixAReductionKernel + - CLGEMMLowpMatrixBReductionKernel + - CLGEMMLowpOffsetContributionOutputStageKernel + - CLGEMMLowpOffsetContributionKernel + - CLWinogradOutputTransformKernel + - CLGEMMLowpMatrixMultiplyReshapedKernel + - @ref CLFuseBatchNormalizationKernel + - @ref CLDepthwiseConvolutionLayerNativeKernel + - CLDepthConvertLayerKernel + - CLCopyKernel + - CLDepthwiseConvolutionLayer3x3NHWCKernel + - CLActivationLayerKernel + - CLWinogradFilterTransformKernel + - CLWidthConcatenateLayerKernel + - CLWidthConcatenate4TensorsKernel + - CLWidthConcatenate2TensorsKernel + - CLLogits1DMaxShiftExpSumKernel + - CLLogits1DNormKernel + - CLHeightConcatenateLayerKernel + - CLGEMMMatrixMultiplyKernel + - CLGEMMLowpQuantizeDownInt32ScaleKernel + - CLGEMMLowpQuantizeDownInt32ScaleByFloatKernel + - CLGEMMLowpMatrixMultiplyReshapedOnlyRHSKernel + - CLDepthConcatenateLayerKernel + - CLGEMMLowpQuantizeDownInt32ScaleByFixedPointKernel + - Removed OpenCL kernels / functions: + - CLGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel + - CLGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel + - CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel + - Deprecated OpenCL kernels / functions (If a kernel is used only by the function that is being deprecated, the kernel is deprecated together): + - CLLocallyConnectedLayer + - CLLocallyConnectedMatrixMultiplyKernel + - CLAbsoluteDifference + - CLAbsoluteDifferenceKernel + - CLAccumulate + - CLAccumulateKernel + - CLAccumulateSquared + - CLAccumulateSquaredKernel + - CLAccumulateWeighted + - CLAccumulateWeightedKernel + - CLAccumulateWeightedFP16Kernel + - CLBox3x3 + - CLBox3x3Kernel + - CLBox3x3FP16Kernel + - CLCannyEdge + - CLChannelCombine + - CLChannelCombineKernel + - CLChannelExtract + - CLChannelExtractKernel + - CLColorConvert + - CLColorConvertKernel + - CLConvolution3x3 + - CLConvolutionRectangle + - CLConvolutionRectangleKernel + - CLConvolutionSquare + - CLConvolutionKernel + - CLDerivative + - CLDerivativeKernel + - CLDilate + - CLDilateKernel + - CLEqualizeHistogram + - CLErode + - CLErodeKernel + - CLFastCorners + - CLFastCornersKernel + - CLGaussian3x3 + - CLGaussian3x3Kernel + - CLGaussian5x5 + - CLGaussian5x5HorKernel + - CLGaussian5x5VertKernel + - CLGaussianPyramid + - CLGaussianPyramidHalf + - CLGaussianPyramidOrb + - CLHarrisCorners + - CLHarrisScoreKernel + - CLHarrisScoreFP16Kernel + - CLHistogram + - CLHistogramKernel + - CLHOGOrientationBinningKernel + - CLHOGBlockNormalizationKernel + - CLHOGDetectorKernel + - CLHOGNonMaximaSuppressionKernel + - CLHOGDescriptor + - CLHOGDetector + - CLHOGGradient + - CLHOGMultiDetection + - CLHOGOrientationBinningKernel + - CLHOGBlockNormalizationKernel + - CLHOGDetectorKernel + - CLIntegralImage + - CLIntegralImageKernel + - CLLaplacianReconstruct + - CLLaplacianPyramid + - CLMagnitude + - CLMagnitudePhaseKernel + - CLMedian3x3 + - CLMedian3x3Kernel + - CLMinMaxLocation + - CLMinMaxLocationKernel + - CLNonLinearFilter + - CLNonLinearFilterKernel + - CLNonMaximaSuppression3x3 + - CLNonMaximaSuppression3x3FP16Kernel + - CLNonMaximaSuppression3x3Kernel + - CLOpticalFlow + - CLPhase + - CLRemap + - CLRemapKernel + - CLScharr3x3 + - CLScharr3x3Kernel + - CLSobel3x3 + - CLSobel3x3Kernel + - CLSobel5x5 + - CLSobel5x5HorKernel + - CLSobel5x5VertKernel + - CLSobel7x7 + - CLSobel7x7HorKernel + - CLSobel7x7VertKernel + - CLThreshold + - CLThresholdKernel + - CLWarpAffine + - CLWarpAffineKernel + - CLWarpPerspective + - CLWarpPerspectiveKernel + - Deprecated Arm® Neon™ kernels / functions (If a kernel is used only by the function that is being deprecated, the kernel is deprecated together): + - NELocallyConnectedLayer + - NELocallyConnectedMatrixMultiplyKernel + - NEAbsoluteDifference + - NEAbsoluteDifferenceKernel + - NEAccumulate + - NEAccumulateKernel + - NEAccumulateSquared + - NEAccumulateSquaredKernel + - NEAccumulateWeighted + - NEAccumulateWeightedKernel + - NEAccumulateWeightedFP16Kernel + - NEBox3x3 + - NEBox3x3Kernel + - NEBox3x3FP16Kernel + - NECannyEdge + - NEChannelCombine + - NEChannelCombineKernel + - NEChannelExtract + - NEChannelExtractKernel + - NEColorConvert + - NEColorConvertKernel + - NEConvolution3x3 + - NEConvolutionRectangle + - NEConvolutionRectangleKernel + - NEConvolutionSquare + - NEConvolutionKernel + - NEDerivative + - NEDerivativeKernel + - NEDilate + - NEDilateKernel + - NEEqualizeHistogram + - NEErode + - NEErodeKernel + - NEFastCorners + - NEFastCornersKernel + - NEGaussian3x3 + - NEGaussian3x3Kernel + - NEGaussian5x5 + - NEGaussian5x5HorKernel + - NEGaussian5x5VertKernel + - NEGaussianPyramid + - NEGaussianPyramidHalf + - NEGaussianPyramidOrb + - NEHarrisCorners + - NEHarrisScoreKernel + - NEHarrisScoreFP16Kernel + - NEHistogram + - NEHistogramKernel + - NEHOGOrientationBinningKernel + - NEHOGBlockNormalizationKernel + - NEHOGDetectorKernel + - NEHOGNonMaximaSuppressionKernel + - NEHOGDescriptor + - NEHOGDetector + - NEHOGGradient + - NEHOGMultiDetection + - NEHOGOrientationBinningKernel + - NEHOGBlockNormalizationKernel + - NEHOGDetectorKernel + - NEIntegralImage + - NEIntegralImageKernel + - NELaplacianReconstruct + - NELaplacianPyramid + - NEMagnitude + - NEMagnitudePhaseKernel + - NEMedian3x3 + - NEMedian3x3Kernel + - NEMinMaxLocation + - NEMinMaxLocationKernel + - NENonLinearFilter + - NENonLinearFilterKernel + - NENonMaximaSuppression3x3 + - NENonMaximaSuppression3x3FP16Kernel + - NENonMaximaSuppression3x3Kernel + - NEOpticalFlow + - NEPhase + - NERemap + - NERemapKernel + - NEScharr3x3 + - NEScharr3x3Kernel + - NESobel3x3 + - NESobel3x3Kernel + - NESobel5x5 + - NESobel5x5HorKernel + - NESobel5x5VertKernel + - NESobel7x7 + - NESobel7x7HorKernel + - NESobel7x7VertKernel + - NEThreshold + - NEThresholdKernel + - NEWarpAffine + - NEWarpAffineKernel + - NEWarpPerspective + - NEWarpPerspectiveKernel + - Deprecated GLES kernels / functions (If a kernel is used only by the function that is being deprecated, the kernel is deprecated together): + - GCAbsoluteDifference + - GCActivationLayer + - GCArithmeticAddition + - GCBatchNormalizationLayer + - GCConcatenateLayer + - GCConvolutionLayer + - GCDepthwiseConvolutionLayer + - GCDirectConvolutionLayer + - GCDropoutLayer + - GCFillBorder + - GCFullyConnectedLayer + - GCGEMM + - GCGEMMInterleave4x4 + - GCGEMMTranspose1xW + - GCNormalizationLayer + - GCNormalizePlanarYUVLayer + - GCPixelWiseMultiplication + - GCPoolingLayer + - GCScale + - GCSoftmaxLayer + - GCTensorShift + - GCTranspose + + +v20.08 Public major release + - Various bug fixes. + - Various optimisations. + - Added new data type QASYMM8_SIGNED support for: + - @ref CLArgMinMaxLayer + - @ref CLArgMinMaxLayerKernel + - Added new data type U8 support for: + - @ref NECropKernel + - CLCropKernel + - Added align_corner support for nearest neighbor interpolation in: + - NEScaleKernel + - CLScaleKernel + - New OpenCL kernels / functions: + - @ref CLMaxUnpoolingLayerKernel + - New Arm® Neon™ kernels / functions: + - NEMaxUnpoolingLayerKernel + - New graph example: + - graph_yolov3_output_detector + - GEMMTuner improvements: + - Added fp16 support + - Output json files for easier integration + - Enabled tuning for export_to_cl_image_rhs option for RHS tensors + - More robust script for running benchmarks + - Removed padding from: + - NEPixelWiseMultiplicationKernel + - NEHeightConcatenateLayerKernel + - NEThresholdKernel + - NEBatchConcatenateLayerKernel + - NETransposeKernel + - @ref NEBatchNormalizationLayerKernel + - NEArithmeticSubtractionKernel + - @ref NEBoundingBoxTransformKernel + - NELogits1DMaxKernel + - NELogits1DSoftmaxKernel + - @ref NEROIPoolingLayerKernel + - @ref NEROIAlignLayerKernel + - NEYOLOLayerKernel + - NEUpsampleLayerKernel + - NEFloorKernel + - NEWidthConcatenateLayerKernel + - NEDepthConcatenateLayerKernel + - @ref NENormalizationLayerKernel + - @ref NEL2NormalizeLayerKernel + - NEFillArrayKernel + - NEDepthConvertLayerKernel + - @ref NERangeKernel + - @ref NEPriorBoxLayer + - Removed OpenCL kernels / functions: + - CLGEMMLowpQuantizeDownInt32ToUint8Scale + - CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFloat + - Removed Arm® Neon™ kernels / functions: + - NEGEMMLowpQuantizeDownInt32ToUint8Scale + - NEGEMMMatrixAccumulateBiasesKernel + - Deprecated functions / interfaces: + - Non-descriptor based interfaces for NEThreshold, CLThreshold + - Non-descriptor based interfaces for @ref NEScale, @ref CLScale and GCScale + - In @ref NESoftmaxLayer, @ref NELogSoftmaxLayer, @ref CLSoftmaxLayer, @ref CLLogSoftmaxLayer and GCSoftmaxLayer : + The default "axis" value for @ref CLSoftmaxLayer, @ref CLLogSoftmaxLayer and GCSoftmaxLayer is changed from 1 to 0. + Only axis 0 is supported. + The default "axis" value for @ref NESoftmaxLayer, @ref NELogSoftmaxLayer is changed from 1 to 0. + Only axis 0 is supported. + - The support for quantized data types has been removed from @ref CLLogSoftmaxLayer due to implementation complexity. + - Removed padding requirement for the input (e.g. LHS of GEMM) and output in CLGEMMMatrixMultiplyNativeKernel, CLGEMMMatrixMultiplyReshapedKernel, CLGEMMMatrixMultiplyReshapedOnlyRHSKernel and CLIm2ColKernel (NHWC only) + - This change allows to use @ref CLGEMMConvolutionLayer without extra padding for the input and output. + - Only the weights/bias of @ref CLGEMMConvolutionLayer could require padding for the computation. + - Only on Arm® Mali™ Midgard GPUs, @ref CLGEMMConvolutionLayer could require padding since CLGEMMMatrixMultiplyKernel is called and currently requires padding. + - Added support for exporting the OpenCL buffer object to the OpenCL image object in CLGEMMMatrixMultiplyReshapedKernel and CLGEMMMatrixMultiplyReshapedOnlyRHSKernel. + - This support allows to export the OpenCL buffer used for the reshaped RHS matrix to the OpenCL image object. + - The padding requirement for the OpenCL image object is considered into the CLGEMMReshapeRHSMatrixKernel. + - The reshaped RHS matrix stores the weights when GEMM is used to accelerate CLGEMMConvolutionLayer. + +v20.05 Public major release + - Various bug fixes. + - Various optimisations. + - Updated recommended NDK version to r18b. + - Updated recommended gcc version to Linaro 6.3.1. + - Added Bfloat16 type support + - Added Bfloat16 support in: + - NEWeightsReshapeKernel + - NEConvolutionLayerReshapeWeights + - NEIm2ColKernel + - NEIm2Col + - NEDepthConvertLayerKernel + - @ref NEDepthConvertLayer + - @ref NEGEMMConvolutionLayer + - NEGEMMAssemblyDispatch + - Added new data type QASYMM8_SIGNED support for: + - @ref CLDirectConvolutionLayer + - @ref CLDeconvolutionLayer + - @ref CLDirectDeconvolutionLayer + - @ref CLGEMMDeconvolutionLayer + - CLGEMMLowpMatrixMultiplyReshapedKernel + - CLGEMMLowpQuantizeDownInt32ScaleKernel + - CLGEMMLowpQuantizeDownInt32ScaleByFloatKernel + - @ref CLReductionOperation + - @ref CLReduceMean + - @ref NEScale + - NEScaleKernel + - NEUpsampleLayer + - @ref NECast + - @ref NEReductionOperation + - @ref NEReduceMean + - @ref NEArgMinMaxLayer + - @ref NEDeconvolutionLayer + - NEGEMMLowpQuantizeDownInt32ScaleKernel + - @ref CPPBoxWithNonMaximaSuppressionLimit + - @ref CPPDetectionPostProcessLayer + - @ref CPPPermuteKernel + - @ref CPPPermute + - @ref CPPTopKVKernel + - @ref CPPTopKV + - @ref CPPUpsample + - @ref CPPUpsampleKernel + - New OpenCL kernels / functions: + - @ref CLQLSTMLayer + - @ref CLQLSTMLayerNormalizationKernel + - New Arm® Neon™ kernels / functions: + - @ref NEQLSTMLayer + - @ref NEQLSTMLayerNormalizationKernel + - Added HARD_SWISH support in: + - CLActivationLayerKernel + - NEActivationLayerKernel + - Deprecated OpenCL kernels / functions: + - CLGEMMLowpQuantizeDownInt32ToUint8Scale + - CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFloat + - Deprecated Arm® Neon™ kernels / functions: + - NEGEMMLowpQuantizeDownInt32ToUint8Scale + - Removed CPP kernels / functions: + - CPPFlipWeightsKernel + - Removed PoolingLayerInfo constructors without Data Layout. + - Removed CLDepthwiseConvolutionLayer3x3 + - Removed NEDepthwiseConvolutionLayerOptimized + - Added support for Winograd 3x3,4x4 on Arm® Neon™ FP16: + - @ref NEWinogradConvolutionLayer + - CpuWinogradConv2dTransformInputKernel + - CpuWinogradConv2dTransformOutputKernel + - CpuWinogradConv2dTransformWeightsKernel + - Added CLCompileContext + - Added Arm® Neon™ GEMM kernel with 2D window support + +v20.02.1 Maintenance release + - Added Android-NN build script. + +v20.02 Public major release + - Various bug fixes. + - Various optimisations. + - Added new data type QASYMM8_SIGNED support for: + - @ref CLDepthwiseConvolutionLayer + - CLDepthwiseConvolutionLayer3x3 + - @ref CLGEMMConvolutionLayer + - CLGEMMLowpMatrixMultiplyCore + - CLGEMMLowpMatrixMultiplyReshapedOnlyRHSKernel + - CLGEMMLowpMatrixMultiplyNativeKernel + - @ref NEActivationLayer + - NEComparisonOperationKernel + - @ref NEConvolutionLayer + - @ref NEDepthwiseConvolutionLayer + - NEDepthwiseConvolutionLayer3x3Kernel + - NEDirectConvolutionLayerOutputStageKernel + - @ref NEElementwiseComparison + - @ref NEElementwiseMax + - @ref NEElementwiseMin + - @ref NEElementwiseSquaredDiff + - @ref NEFullyConnectedLayer + - NEGEMMMatrixVectorMultiplyKernel + - @ref NEPixelWiseMultiplication + - @ref NEPoolingLayer + - @ref NEPReluLayer + - Added support for QSYMM8_PER_CHANNEL in: + - NEDepthwiseConvolutionLayer3x3Kernel + - Added support for split sizes in: + - @ref CLSplit + - @ref NESplit + - New OpenCL kernels / functions: + - @ref CLFill + - CLGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel / CLGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint + - New Arm® Neon™ kernels / functions: + - @ref NEFill + - NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPointKernel / NEGEMMLowpQuantizeDownInt32ToInt8ScaleByFixedPoint + - Deprecated Arm® Neon™ functions / interfaces: + - CLDepthwiseConvolutionLayer3x3 + - NEDepthwiseConvolutionLayerOptimized + - PoolingLayerInfo constructors without Data Layout. + - Added support for quantization with multiplier greater than 1 on Arm® Neon™ and CL. + - Added support for quantized inputs of type QASYMM8_SIGNED and QASYMM8 to @ref CLQuantizationLayer. + - Added the ability to build bootcode for bare metal. + - Added support for generating synthetic QASYMM8 graphs. + - Added support for F16 datatype in VGG16. + - Removed pre-built binaries for GLES. + +v19.11.1 Public maintenance release + - Fix offset calculation in NEReductionOperationKernel. + - Fix data layout in NEScaleKernel for nhwc. + - Retain configuration step data layout to avoid side-effects. + - Perform sqrt in double domain for L2 pooling. + - Fix output shape calculation for Reduce Mean + - Restrict cases where optimized NEPadLayer runs. + +v19.11 Public major release + - Various bug fixes. + - Various optimisations. + - Updated recommended NDK version to r17c. + - Deprecated OpenCL kernels / functions: + - CLDepthwiseConvolutionLayerReshapeWeightsGenericKernel + - CLDepthwiseIm2ColKernel + - CLDepthwiseSeparableConvolutionLayer + - CLDepthwiseVectorToTensorKernel + - CLDirectConvolutionLayerOutputStageKernel + - Deprecated Arm® Neon™ kernels / functions: + - NEDepthwiseWeightsReshapeKernel + - NEDepthwiseIm2ColKernel + - NEDepthwiseSeparableConvolutionLayer + - NEDepthwiseVectorToTensorKernel + - NEDepthwiseConvolutionLayer3x3 + - New OpenCL kernels / functions: + - @ref CLInstanceNormalizationLayerKernel / @ref CLInstanceNormalizationLayer + - @ref CLDepthwiseConvolutionLayerNativeKernel to replace the old generic depthwise convolution (see Deprecated + OpenCL kernels / functions) + - @ref CLLogSoftmaxLayer + - New Arm® Neon™ kernels / functions: + - @ref NEBoundingBoxTransformKernel / @ref NEBoundingBoxTransform + - @ref NEComputeAllAnchorsKernel / NEComputeAllAnchors + - @ref NEDetectionPostProcessLayer + - @ref NEGenerateProposalsLayer + - @ref NEInstanceNormalizationLayerKernel / @ref NEInstanceNormalizationLayer + - @ref NELogSoftmaxLayer + - @ref NEROIAlignLayerKernel / @ref NEROIAlignLayer + - Added QASYMM8 support for: + - @ref CLGenerateProposalsLayer + - @ref CLROIAlignLayer + - @ref CPPBoxWithNonMaximaSuppressionLimit + - Added QASYMM16 support for: + - @ref CLBoundingBoxTransform + - Added FP16 support for: + - CLGEMMMatrixMultiplyReshapedKernel + - Added new data type QASYMM8_PER_CHANNEL support for: + - CLDequantizationLayer + - @ref NEDequantizationLayer + - Added new data type QSYMM8_PER_CHANNEL support for: + - @ref CLConvolutionLayer + - @ref NEConvolutionLayer + - @ref CLDepthwiseConvolutionLayer + - @ref NEDepthwiseConvolutionLayer + - Added FP16 mixed-precision support for: + - CLGEMMMatrixMultiplyReshapedKernel + - CLPoolingLayerKernel + - Added FP32 and FP16 ELU activation for: + - @ref CLActivationLayer + - @ref NEActivationLayer + - Added asymmetric padding support for: + - @ref CLDirectDeconvolutionLayer + - @ref CLGEMMDeconvolutionLayer + - @ref NEDeconvolutionLayer + - Added SYMMETRIC and REFLECT modes for @ref CLPadLayerKernel / @ref CLPadLayer. + - Replaced the calls to NECopyKernel and NEMemsetKernel with @ref NEPadLayer in @ref NEGenerateProposalsLayer. + - Replaced the calls to CLCopyKernel and CLMemsetKernel with @ref CLPadLayer in @ref CLGenerateProposalsLayer. + - Improved performance for CL Inception V3 - FP16. + - Improved accuracy for CL Inception V3 - FP16 by enabling FP32 accumulator (mixed-precision). + - Improved Arm® Neon™ performance by enabling fusing batch normalization with convolution and depth-wise convolution layer. + - Improved Arm® Neon™ performance for MobileNet-SSD by improving the output detection performance. + - Optimized @ref CLPadLayer. + - Optimized CL generic depthwise convolution layer by introducing @ref CLDepthwiseConvolutionLayerNativeKernel. + - Reduced memory consumption by implementing weights sharing. + +v19.08.1 Public maintenance release + - Fix offset calculation in NEReductionOperationKernel. + - Fix data layout in NEScaleKernel for nhwc. + - Retain configuration step data layout to avoid side-effects. + - Perform sqrt in double domain for L2 pooling. + - Fix output shape calculation for Reduce Mean + - Fix broadcast CLPixelwiseMultiplication with 5D tensors + +v19.08 Public major release + - Various bug fixes. + - Various optimisations. + - Deprecated Arm® Neon™ functions + - NEDepthConcatenateLayer + - NEWidthConcatenateLayer + - Deprecated OpenCL kernels / functions + - CLDepthConcatenateLayer + - CLGEMMInterleave4x4Kernel / CLGEMMInterleave4x4 + - CLGEMMTranspose1xWKernel / CLGEMMTranspose1xW + - CLWidthConcatenateLayer + - New Arm® Neon™ kernels / functions: + - @ref NEAbsLayer + - @ref NECast + - @ref NEElementwisePower + - @ref NELogLayer + - @ref NELSTMLayerQuantized + - @ref NENegLayer + - @ref NEPReluLayer + - @ref NESinLayer + - NEBatchConcatenateLayerKernel + - @ref NEDepthToSpaceLayerKernel / @ref NEDepthToSpaceLayer + - NEDepthwiseConvolutionLayerNativeKernel + - NEGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel + - @ref NEMeanStdDevNormalizationKernel / @ref NEMeanStdDevNormalizationLayer + - @ref NESpaceToDepthLayerKernel / @ref NESpaceToDepthLayer + - New OpenCL kernels / functions: + - @ref CLAbsLayer + - @ref CLElementwisePower + - @ref CLLogLayer + - @ref CLLSTMLayerQuantized + - @ref CLNegLayer + - @ref CLPReluLayer + - @ref CLSinLayer + - CLBatchConcatenateLayerKernel + - @ref CLDepthToSpaceLayerKernel / @ref CLDepthToSpaceLayer + - CLGEMMLowpMatrixMultiplyNativeKernel + - CLGEMMLowpQuantizeDownInt32ToInt16ScaleByFixedPointKernel + - CLGEMMMatrixMultiplyNativeKernel + - CLMeanStdDevNormalizationKernel /CLMeanStdDevNormalizationLayer + - @ref CLSpaceToDepthLayerKernel / @ref CLSpaceToDepthLayer + - New examples: + - neon_opticalflow + - cl_cache + - neon_permute + - Added support for FP16 in @ref NEDeconvolutionLayer + - Added support for FP16 in @ref CLDeconvolutionLayer + - Added support for REDUCE_MIN and REDUCE_MAX in @ref ReductionOperation + - Enable the fusion of batch normalization with convolution and depthwise convolution layer for FP32 in the graph API (OpenCL only) + - Added support for fusing activation function and broadcast addition with the matrix multiplication for FP32 (OpenCL only) + - Re-factored the depthwise convolution layer kernel on Arm® Neon™ for generic cases + - Added an optimized depthwise convolution layer kernel for 5x5 filters (Neon™ only) + - Added support to enable OpenCL kernel cache. Added example showing how to load the prebuilt OpenCL kernels from a binary cache file + - Altered @ref QuantizationInfo interface to support per-channel quantization. + - The CLDepthwiseConvolutionLayer3x3 will be included by @ref CLDepthwiseConvolutionLayer to accommodate for future optimizations. + - The NEDepthwiseConvolutionLayerOptimized will be included by @ref NEDepthwiseConvolutionLayer to accommodate for future optimizations. + - Removed inner_border_right and inner_border_top parameters from @ref CLDeconvolutionLayer interface + - Removed inner_border_right and inner_border_top parameters from @ref NEDeconvolutionLayer interface + - Optimized the Arm® Neon™ assembly kernel for GEMMLowp. The new implementation fuses the output stage and quantization with the matrix multiplication kernel + +v19.05 Public major release + - Various bug fixes. + - Various optimisations. + - New Arm® Neon™ kernels / functions: + - @ref NEBatchToSpaceLayerKernel / @ref NEBatchToSpaceLayer + - NEComplexPixelWiseMultiplicationKernel / @ref NEComplexPixelWiseMultiplication + - @ref NECropKernel / @ref NECropResize + - NEDepthwiseConvolutionAssemblyDispatch + - @ref NEFFTDigitReverseKernel + - @ref NEFFTRadixStageKernel + - @ref NEFFTScaleKernel + - NEGEMMLowpOffsetContributionOutputStageKernel + - NEHeightConcatenateLayerKernel + - @ref NESpaceToBatchLayerKernel / @ref NESpaceToBatchLayer + - @ref NEFFT1D + - @ref NEFFT2D + - @ref NEFFTConvolutionLayer + - New OpenCL kernels / functions: + - CLComplexPixelWiseMultiplicationKernel / @ref CLComplexPixelWiseMultiplication + - CLCropKernel / @ref CLCropResize + - @ref CLDeconvolutionReshapeOutputKernel + - @ref CLFFTDigitReverseKernel + - @ref CLFFTRadixStageKernel + - @ref CLFFTScaleKernel + - CLGEMMLowpMatrixMultiplyReshapedOnlyRHSKernel + - CLGEMMMatrixMultiplyReshapedOnlyRHSKernel + - CLHeightConcatenateLayerKernel + - @ref CLDirectDeconvolutionLayer + - @ref CLFFT1D + - @ref CLFFT2D + - @ref CLFFTConvolutionLayer + - @ref CLGEMMDeconvolutionLayer + - New OpenGLES kernels / functions: + - GCConcatenateLayer + - Deprecated functions/interfaces + - GCDepthConcatenateLayer + - NEWidthConcatenateLayer + - NEDepthConcatenateLayer + - CLWidthConcatenateLayer + - CLDepthConcatenateLayer + - CLGEMMInterleave4x4 + - CLGEMMTranspose1xW + - Support different quantization info in CLConcatLayer. + - Add checks on different input/output quantization info were not supported. + - Tensors have different quantization information. + - Add FP16 support checks. + - Fix output quantization CLDeptwiseConv3x3 when activation is fused. + - New graph examples: + - graph_convolution + - graph_fully_connected + - graph_depthwise_convolution + - Deepspeech v0.4.1 + - Add support for QASYMM8 in NEArithmeticSubtractionKernel. + - Add support for QASYMM8 in NEPixelWiseMultiplicationKernel. + - Add support for QASYMM8 NEDeconvolution. + - Add support for DequantizationLayer for Neon/CL. + - Add support for dilation in CLDepthwiseConvolution. + - Fuse offset contribution with the output stage when we use NEGEMMLowpMatrixMultiplyCore. + - Optimize CLDeconvolution. + - Add StackLayer to the graph API. + - Add support for "reflect" padding mode in NEPad. + - Winograd 7x7 NHWC on OpenCL. + - Rework CL ML layers to run exclusively on CL. + - Support different quantization info in PoolingLayer. + - Implement and test import memory interfaces. + - Added new tests and removed old ones. + - Various clang-tidy fixes. + +v19.02 Public major release + - Various bug fixes. + - Various optimisations. + - New Arm® Neon™ kernels / functions: + - @ref NETileKernel / @ref NETile + - @ref NEFuseBatchNormalizationKernel / @ref NEFuseBatchNormalization + - NEElementwiseOperationKernel + - @ref NEElementwiseMax + - @ref NEElementwiseMin + - @ref NEElementwiseSquaredDiff + - @ref NESelectKernel / @ref NESelect + - @ref NESplit + - @ref NESlice + - @ref NEUnstack + - @ref NEStridedSliceKernel / @ref NEStridedSlice + - NEElementwiseUnaryKernel + - @ref NERsqrtLayer + - @ref NEExpLayer + - @ref NEReverseKernel / @ref NEReverse + - @ref NEArgMinMaxLayer + - @ref NEStackLayerKernel / @ref NEStackLayer + - @ref NERangeKernel / @ref NERange + - @ref NEPadLayer + - NEMemsetKernel + - @ref NEGatherKernel / @ref NEGather + - @ref NEElementwiseComparison + - @ref NEElementwiseComparisonStatic + - NEComparisonOperationKernel + - @ref NEElementwiseDivision + - New OpenCL kernels / functions: + - @ref CLSelectKernel / @ref CLSelect + - @ref CLTileKernel / @ref CLTile + - @ref CLComparisonKernel / @ref CLComparison + - @ref CLArgMinMaxLayer + - @ref CLElementwiseMax + - @ref CLElementwiseMin + - @ref CLElementwiseSquaredDiff + - @ref CLStackLayerKernel / @ref CLStackLayer + - @ref CLReverse / @ref CLReverseKernel + - @ref CLRsqrtLayer + - @ref CLExpLayer + - CLElementWiseUnaryLayerKernel + - CLGEMMReshapeLHSMatrixKernel + - CLGEMMReshapeRHSMatrixKernel + - CLGEMMMatrixMultiplyReshapedKernel + - @ref CLRangeKernel / @ref CLRange + - @ref CLUnstack + - @ref CLGatherKernel / @ref CLGather + - CLGEMMLowpMatrixMultiplyReshapedKernel + - New CPP kernels / functions: + - @ref CPPDetectionOutputLayer + - @ref CPPTopKV / @ref CPPTopKVKernel + - Added new examples: + - graph_ssd_mobilenet.cpp + - graph_mobilenet_v2.cpp + - graph_resnet12.cpp + - graph_srcnn955.cpp + - graph_vgg_vdsr.cpp + - graph_inception_resnet_v1.cpp + - Add 4D tensors support to + - @ref NESoftmaxLayer + - Fused activation in @ref CLWinogradConvolutionLayer + - Extended @ref NEPermute to support more cases + - Added Neon™/SVE GEMM Hybrid kernels + - Added u8 and s8 hybrid assembly kernels + - Introduced GEMM strategy name in NEGEMMAssemblyWrapper + - Improved @ref CLTuner + - Fused the bias addition within @ref CLGEMM + - Added support for QASYMM8 LOGISTIC activation in @ref NEActivationLayer + - Added NHWC data layout support to: + - @ref NEScale for F16 + - @ref CLNormalizationLayer IN_MAP_2D for FP32/FP16 + - @ref NEL2NormalizeLayer for FP32/FP16 + - @ref NENormalizationLayer IN_MAP_2D for FP32/FP16 + - @ref CLROIAlignLayer + - @ref CLGenerateProposalsLayer + - Added QASYMM8 support to the following kernels: + - NEArithmeticAdditionKernel + - @ref NEScale + - Added new tests and improved validation and benchmarking suites. + - Deprecated functions/interfaces + - Usage of inner_border_right and inner_border_top has been deprecated in @ref CLDeconvolutionLayer and @ref NEDeconvolutionLayer + +v18.11 Public major release + - Various bug fixes. + - Various optimisations. + - New Arm® Neon™ kernels / functions: + - @ref NEChannelShuffleLayer / @ref NEChannelShuffleLayerKernel + - @ref NEReduceMean + - @ref NEReorgLayer / @ref NEReorgLayerKernel + - @ref NEPriorBoxLayer / @ref NEPriorBoxLayerKernel + - NEUpsampleLayer / NEUpsampleLayerKernel + - NEYOLOLayer / NEYOLOLayerKernel + - New OpenCL kernels / functions: + - @ref CLBatchToSpaceLayer / @ref CLBatchToSpaceLayerKernel + - @ref CLBoundingBoxTransform / @ref CLBoundingBoxTransformKernel + - @ref CLComputeAllAnchorsKernel + - @ref CLGenerateProposalsLayer + - @ref CLNormalizePlanarYUVLayer / @ref CLNormalizePlanarYUVLayerKernel + - @ref CLReorgLayer / @ref CLReorgLayerKernel + - @ref CLSpaceToBatchLayer / @ref CLSpaceToBatchLayerKernel + - @ref CLPadLayer + - @ref CLReduceMean + - @ref CLPriorBoxLayer / @ref CLPriorBoxLayerKernel + - @ref CLROIAlignLayer / @ref CLROIAlignLayerKernel + - @ref CLSlice + - @ref CLSplit + - @ref CLStridedSlice / @ref CLStridedSliceKernel + - CLUpsampleLayer / CLUpsampleLayerKernel + - CLYOLOLayer / CLYOLOLayerKernel + - New CPP kernels / functions: + - @ref CPPBoxWithNonMaximaSuppressionLimit / @ref CPPBoxWithNonMaximaSuppressionLimitKernel + - Added the validate method in: + - @ref NEDepthConvertLayer + - @ref NEFloor / @ref CLFloor + - NEGEMMMatrixAdditionKernel + - @ref NEReshapeLayer / @ref CLReshapeLayer + - @ref CLScale + - Added new examples: + - graph_shufflenet.cpp + - graph_yolov3.cpp + - Added documentation for add a new function or kernel. + - Improved doxygen documentation adding a list of the existing functions. + - Add 4D tensors support to + - CLWidthConcatenateLayer + - CLFlattenLayer + - @ref CLSoftmaxLayer + - Add dot product support for CLDepthwiseConvolutionLayer3x3NHWCKernel non-unit stride + - Add SVE support + - Fused batch normalization into convolution layer weights in @ref CLFuseBatchNormalization + - Fuses activation in CLDepthwiseConvolutionLayer3x3NCHWKernel, CLDepthwiseConvolutionLayer3x3NHWCKernel and @ref NEGEMMConvolutionLayer + - Added NHWC data layout support to: + - @ref CLChannelShuffleLayer + - @ref CLDeconvolutionLayer + - @ref CLL2NormalizeLayer + - Added QASYMM8 support to the following kernels: + - CLScaleKernel + - NEDepthwiseConvolutionLayer3x3Kernel + - CLPixelWiseMultiplicationKernel + - Added FP16 support to the following kernels: + - CLDepthwiseConvolutionLayer3x3NHWCKernel + - NEDepthwiseConvolutionLayer3x3Kernel + - @ref CLNormalizePlanarYUVLayerKernel + - @ref CLWinogradConvolutionLayer (5x5 kernel) + - More tests added to both validation and benchmarking suites. + +v18.08 Public major release + - Various bug fixes. + - Various optimisations. + - Updated recommended NDK version to r17b. + - Removed support for QS8/QS16 data types. + - Added support for grouped convolution in @ref CLConvolutionLayer. + - Added NHWC data layout support to: + - NEDepthConcatenateLayer / CLDepthConcatenateLayer + - @ref NEWinogradConvolutionLayer / @ref CLWinogradConvolutionLayer + - @ref CLDepthwiseConvolutionLayer + - @ref CLDirectConvolutionLayer + - @ref CLConvolutionLayer + - @ref CLScale + - CLIm2ColKernel + - New Arm® Neon™ kernels / functions: + - @ref NERNNLayer + - New OpenCL kernels / functions: + - @ref CLArithmeticDivision + - Introduced prepare() stage support in the graph API for GLES. + - Added support for memory reusage when trying to allocate smaller CLTensors. + - Enabled NHWC execution on graph examples. + - Added JPEG accessor for validation purposes. + - Added validate methods to some kernels / functions. + +v18.05 Public major release + - Various bug fixes. + - Various optimisations. + - Major redesign in the interface for the Neon™ kernels implemented in assembly. + - Removed arm_compute::NEGEMMLowpAArch64A53Kernel / arm_compute::NEGEMMLowpAArch64Kernel / arm_compute::NEGEMMLowpAArch64V8P4Kernel / arm_compute::NEGEMMInterleavedBlockedKernel / arm_compute::NEGEMMLowpAssemblyMatrixMultiplyCore / arm_compute::NEHGEMMAArch64FP16Kernel + - Added NEGEMMAssemblyWrapper and AssemblyKernelGlue which are used to execute assembly kernels in Neon™ functions. + - Minor changes to the CPUInfo type to make it compatible with the new assembly gemm interface. + - Moved Neon™ assembly kernels to the folder src/core/Neon/kernels/arm_gemm. + - Improved doxygen documentation. + - Improved memory management for layer's transitions. + - Added support for NHWC data layout in tensors. + - Added NHWC data layout support to: + - @ref NEGEMMConvolutionLayer + - @ref NEDirectConvolutionLayer + - @ref NEPoolingLayer / @ref CLPoolingLayer + - @ref NEBatchNormalizationLayer / @ref CLBatchNormalizationLayer + - @ref NEDepthwiseConvolutionLayer + - @ref NEScale + - NEIm2Col + - Added support for dilated convolutions in @ref NEConvolutionLayer and @ref CLConvolutionLayer. + - New OpenCL kernels / functions: + - @ref CLChannelShuffleLayer / @ref CLChannelShuffleLayerKernel + - CLConvertFullyConnectedWeightsKernel / @ref CLConvertFullyConnectedWeights + - @ref CLCopy / CLCopyKernel + - @ref CLLSTMLayer + - @ref CLRNNLayer + - CLWidthConcatenateLayer / CLWidthConcatenateLayerKernel + - CLWinogradFilterTransformKernel / @ref CLWinogradConvolutionLayer + - CLWinogradInputTransformKernel / CLWinogradInputTransform + - New Arm® Neon™ kernels / functions: + - NEConvertFullyConnectedWeightsKernel / @ref NEConvertFullyConnectedWeights. + - Created the validate method in @ref CLDepthwiseConvolutionLayer. + - Beta and gamma are no longer mandatory arguments in @ref NEBatchNormalizationLayer and @ref CLBatchNormalizationLayer. + - Added depth multiplier support in @ref NEDepthwiseConvolutionLayer and @ref CLDepthwiseConvolutionLayer. + - Added broadcast multiply support in @ref NEPixelWiseMultiplication / NEPixelWiseMultiplicationKernel. + - Port mobilenet example to NHWC data layout. + - Enabled Winograd method in @ref CLConvolutionLayer. + - Renamed NEWinogradLayer to @ref NEWinogradConvolutionLayer. + - Updated @ref NEWinogradConvolutionLayer to use highly optimised assembly kernels in src/core/Neon/kernels/arm_gemm. + - Added memory manager support in GLES functions. + - Major refactoring of the graph API. + - Added GLES backend in the graph API. + - Added support for the memory manager in the graph API. + - Enabled Winograd Convolution method in the graph API. + - Added support for grouped convolutions in the graph API. + - Replaced NEDeconvolutionLayerUpsampleKernel with NEScaleKernel in @ref NEDeconvolutionLayer. + - Added fast maths flag in @ref CLConvolutionLayer. + - Added new tests and benchmarks in validation and benchmark frameworks + - Merge Activation layer with Convolution Layer (Neon™, CL, GLES) + - Added support to OpenCL 2.0 SVM + - Added support to import memory in OpenCL tensors. + - Added the prepare() method to perform any one off pre-processing before running the function. + - Added new examples: + - graph_inception_v4.cpp + - graph_resnext50.cpp + - Added memory measurement instrument for CL. + +v18.03 Public maintenance release + - Various bug fixes. + - Fixed bug in @ref NEActivationLayer + - Fix in @ref CLTuner when using batches. + - Updated recommended NDK version to r16b (And fixed warnings). + - Fixed bug in validation code. + - Added Inception v4 graph example. + - Renamed NEWinogradLayer.cpp to @ref NEWinogradConvolutionLayer + +v18.02 Public major release + - Various Arm® Neon™ / OpenCL / GLES optimisations. + - Various bug fixes. + - Changed default number of threads on big LITTLE systems. + - Refactored examples and added: + - graph_mobilenet_qassym8 + - graph_resnet + - graph_squeezenet_v1_1 + - Renamed @ref CLConvolutionLayer into @ref CLGEMMConvolutionLayer and created a new @ref CLConvolutionLayer to select the fastest convolution method. + - Renamed @ref NEConvolutionLayer into @ref NEGEMMConvolutionLayer and created a new @ref NEConvolutionLayer to select the fastest convolution method. + - Added in place support to: + - @ref CLActivationLayer + - @ref CLBatchNormalizationLayer + - Added QASYMM8 support to: + - @ref CLActivationLayer + - @ref CLDepthwiseConvolutionLayer + - @ref NEDepthwiseConvolutionLayer + - @ref NESoftmaxLayer + - Added FP16 support to: + - CLDepthwiseConvolutionLayer3x3 + - @ref CLDepthwiseConvolutionLayer + - Added broadcasting support to NEArithmeticAddition / @ref CLArithmeticAddition / @ref CLPixelWiseMultiplication + - Added fused batched normalization and activation to @ref CLBatchNormalizationLayer and @ref NEBatchNormalizationLayer + - Added support for non-square pooling to @ref NEPoolingLayer and @ref CLPoolingLayer + - New OpenCL kernels / functions: + - CLDirectConvolutionLayerOutputStageKernel + - New Arm® Neon™ kernels / functions + - Added name() method to all kernels. + - Added support for Winograd 5x5. + - NEPermuteKernel / @ref NEPermute + - CpuWinogradConv2dTransformInputKernel / NEWinogradLayer + - CpuWinogradConv2dTransformOutputKernel / NEWinogradLayer + - CpuWinogradConv2dTransformWeightsKernel / NEWinogradLayer + - Renamed NEWinogradLayerKernel into NEWinogradLayerBatchedGEMMKernel + - New GLES kernels / functions: + - GCTensorShiftKernel / GCTensorShift + +v18.01 Public maintenance release + - Various bug fixes + - Added some of the missing validate() methods + - Added @ref CLDeconvolutionLayerUpsampleKernel / @ref CLDeconvolutionLayer @ref CLDeconvolutionLayerUpsample + - Added CLPermuteKernel / @ref CLPermute + - Added method to clean the programs cache in the CL Kernel library. + - Added GCArithmeticAdditionKernel / GCArithmeticAddition + - Added GCDepthwiseConvolutionLayer3x3Kernel / GCDepthwiseConvolutionLayer3x3 + - Added GCNormalizePlanarYUVLayerKernel / GCNormalizePlanarYUVLayer + - Added GCScaleKernel / GCScale + - Added GCWeightsReshapeKernel / GCConvolutionLayer + - Added FP16 support to the following GLES compute kernels: + - GCCol2ImKernel + - GCGEMMInterleave4x4Kernel + - GCGEMMTranspose1xWKernel + - GCIm2ColKernel + - Refactored Arm® Neon™ Winograd (NEWinogradLayerKernel) + - Added NEDirectConvolutionLayerOutputStageKernel + - Added QASYMM8 support to the following Arm® Neon™ kernels: + - NEDepthwiseConvolutionLayer3x3Kernel + - @ref NEFillBorderKernel + - NEPoolingLayerKernel + - Added new examples: + - graph_cl_mobilenet_qasymm8.cpp + - graph_inception_v3.cpp + - gc_dc.cpp + - More tests added to both validation and benchmarking suites. + +v17.12 Public major release + - Most machine learning functions on OpenCL support the new data type QASYMM8 + - Introduced logging interface + - Introduced opencl timer + - Reworked GEMMLowp interface + - Added new Arm® Neon™ assembly kernels for GEMMLowp, SGEMM and HGEMM + - Added validation method for most Machine Learning kernels / functions + - Added new graph examples such as googlenet, mobilenet, squeezenet, vgg16 and vgg19 + - Added sgemm example for OpenCL + - Added absolute difference example for GLES compute + - Added new tests and benchmarks in validation and benchmark frameworks + - Added new kernels / functions for GLES compute + + - New OpenGL ES kernels / functions + - GCAbsoluteDifferenceKernel / GCAbsoluteDifference + - GCActivationLayerKernel / GCActivationLayer + - GCBatchNormalizationLayerKernel / GCBatchNormalizationLayer + - GCCol2ImKernel + - GCDepthConcatenateLayerKernel / GCDepthConcatenateLayer + - GCDirectConvolutionLayerKernel / GCDirectConvolutionLayer + - GCDropoutLayerKernel / GCDropoutLayer + - GCFillBorderKernel / GCFillBorder + - GCGEMMInterleave4x4Kernel / GCGEMMInterleave4x4 + - GCGEMMMatrixAccumulateBiasesKernel / GCGEMMMatrixAdditionKernel / GCGEMMMatrixMultiplyKernel / GCGEMM + - GCGEMMTranspose1xWKernel / GCGEMMTranspose1xW + - GCIm2ColKernel + - GCNormalizationLayerKernel / GCNormalizationLayer + - GCPixelWiseMultiplicationKernel / GCPixelWiseMultiplication + - GCPoolingLayerKernel / GCPoolingLayer + - GCLogits1DMaxKernel / GCLogits1DShiftExpSumKernel / GCLogits1DNormKernel / GCSoftmaxLayer + - GCTransposeKernel / GCTranspose + + - New Arm® Neon™ kernels / functions + - arm_compute::NEGEMMLowpAArch64A53Kernel / arm_compute::NEGEMMLowpAArch64Kernel / arm_compute::NEGEMMLowpAArch64V8P4Kernel / arm_compute::NEGEMMInterleavedBlockedKernel / arm_compute::NEGEMMLowpAssemblyMatrixMultiplyCore + - arm_compute::NEHGEMMAArch64FP16Kernel + - NEDepthwiseConvolutionLayer3x3Kernel / NEDepthwiseIm2ColKernel / NEGEMMMatrixVectorMultiplyKernel / NEDepthwiseVectorToTensorKernel / @ref NEDepthwiseConvolutionLayer + - NEGEMMLowpOffsetContributionKernel / NEGEMMLowpMatrixAReductionKernel / NEGEMMLowpMatrixBReductionKernel / NEGEMMLowpMatrixMultiplyCore + - NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel / NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint + - NEWinogradLayer / NEWinogradLayerKernel + + - New OpenCL kernels / functions + - CLGEMMLowpOffsetContributionKernel / CLGEMMLowpMatrixAReductionKernel / CLGEMMLowpMatrixBReductionKernel / CLGEMMLowpMatrixMultiplyCore + - CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPointKernel / CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint + + - New graph nodes for Arm® Neon™ and OpenCL + - graph::BranchLayer + - graph::DepthConvertLayer + - graph::DepthwiseConvolutionLayer + - graph::DequantizationLayer + - graph::FlattenLayer + - graph::QuantizationLayer + - graph::ReshapeLayer + +v17.10 Public maintenance release + - Bug fixes: + - Check the maximum local workgroup size supported by OpenCL devices + - Minor documentation updates (Fixed instructions to build the examples) + - Introduced a graph::GraphContext + - Added a few new Graph nodes, support for branches and grouping. + - Automatically enable cl_printf in debug builds + - Fixed bare metal builds for armv7a + - Added AlexNet and cartoon effect examples + - Fixed library builds: libraries are no longer built as supersets of each other.(It means application using the Runtime part of the library now need to link against both libarm_compute_core and libarm_compute) + +v17.09 Public major release + - Experimental Graph support: initial implementation of a simple stream API to easily chain machine learning layers. + - Memory Manager (@ref BlobLifetimeManager, @ref BlobMemoryPool, @ref ILifetimeManager, @ref IMemoryGroup, @ref IMemoryManager, @ref IMemoryPool, @ref IPoolManager, @ref MemoryManagerOnDemand, @ref PoolManager) + - New validation and benchmark frameworks (Boost and Google frameworks replaced by homemade framework). + - Most machine learning functions support both fixed point 8 and 16 bit (QS8, QS16) for both Arm® Neon™ and OpenCL. + - New Arm® Neon™ kernels / functions: + - arm_compute::NEGEMMAssemblyBaseKernel arm_compute::NEGEMMAArch64Kernel + - NEDequantizationLayerKernel / @ref NEDequantizationLayer + - NEFloorKernel / @ref NEFloor + - @ref NEL2NormalizeLayerKernel / @ref NEL2NormalizeLayer + - NEQuantizationLayerKernel NEMinMaxLayerKernel / @ref NEQuantizationLayer + - @ref NEROIPoolingLayerKernel / @ref NEROIPoolingLayer + - @ref NEReductionOperationKernel / @ref NEReductionOperation + - NEReshapeLayerKernel / @ref NEReshapeLayer + + - New OpenCL kernels / functions: + - CLDepthwiseConvolutionLayer3x3NCHWKernel CLDepthwiseConvolutionLayer3x3NHWCKernel CLDepthwiseIm2ColKernel CLDepthwiseVectorToTensorKernel CLDepthwiseWeightsReshapeKernel / CLDepthwiseConvolutionLayer3x3 @ref CLDepthwiseConvolutionLayer CLDepthwiseSeparableConvolutionLayer + - CLDequantizationLayerKernel / CLDequantizationLayer + - CLDirectConvolutionLayerKernel / @ref CLDirectConvolutionLayer + - CLFlattenLayer + - CLFloorKernel / @ref CLFloor + - CLGEMMTranspose1xW + - CLGEMMMatrixVectorMultiplyKernel + - @ref CLL2NormalizeLayerKernel / @ref CLL2NormalizeLayer + - CLQuantizationLayerKernel CLMinMaxLayerKernel / @ref CLQuantizationLayer + - @ref CLROIPoolingLayerKernel / @ref CLROIPoolingLayer + - @ref CLReductionOperationKernel / @ref CLReductionOperation + - CLReshapeLayerKernel / @ref CLReshapeLayer + +v17.06 Public major release + - Various bug fixes + - Added support for fixed point 8 bit (QS8) to the various Arm® Neon™ machine learning kernels. + - Added unit tests and benchmarks (AlexNet, LeNet) + - Added support for sub tensors. + - Added infrastructure to provide GPU specific optimisation for some OpenCL kernels. + - Added @ref OMPScheduler (OpenMP) scheduler for Neon + - Added @ref SingleThreadScheduler scheduler for Arm® Neon™ (For bare metal) + - User can specify their own scheduler by implementing the @ref IScheduler interface. + - New OpenCL kernels / functions: + - @ref CLBatchNormalizationLayerKernel / @ref CLBatchNormalizationLayer + - CLDepthConcatenateLayerKernel / CLDepthConcatenateLayer + - CLHOGOrientationBinningKernel CLHOGBlockNormalizationKernel, CLHOGDetectorKernel / CLHOGDescriptor CLHOGDetector CLHOGGradient CLHOGMultiDetection + - CLLocallyConnectedMatrixMultiplyKernel / CLLocallyConnectedLayer + - CLWeightsReshapeKernel / CLConvolutionLayerReshapeWeights + - New C++ kernels: + - CPPDetectionWindowNonMaximaSuppressionKernel + - New Arm® Neon™ kernels / functions: + - @ref NEBatchNormalizationLayerKernel / @ref NEBatchNormalizationLayer + - NEDepthConcatenateLayerKernel / NEDepthConcatenateLayer + - NEDirectConvolutionLayerKernel / @ref NEDirectConvolutionLayer + - NELocallyConnectedMatrixMultiplyKernel / NELocallyConnectedLayer + - NEWeightsReshapeKernel / NEConvolutionLayerReshapeWeights + +v17.05 Public bug fixes release + - Various bug fixes + - Remaining of the functions ported to use accurate padding. + - Library does not link against OpenCL anymore (It uses dlopen / dlsym at runtime instead to determine whether or not OpenCL is available). + - Added "free" method to allocator. + - Minimum version of g++ required for armv7 Linux changed from 4.8 to 4.9 + +v17.04 Public bug fixes release + + The following functions have been ported to use the new accurate padding: + - CLColorConvertKernel + - CLEdgeNonMaxSuppressionKernel + - CLEdgeTraceKernel + - CLGaussianPyramidHorKernel + - CLGaussianPyramidVertKernel + - CLGradientKernel + - NEChannelCombineKernel + - NEFillArrayKernel + - NEGaussianPyramidHorKernel + - NEGaussianPyramidVertKernel + - NEHarrisScoreFP16Kernel + - NEHarrisScoreKernel + - NEHOGDetectorKernel + - NELogits1DMaxKernel + - NELogits1DShiftExpSumKernel + - NELogits1DNormKernel + - NENonMaximaSuppression3x3FP16Kernel + - NENonMaximaSuppression3x3Kernel + +v17.03.1 First Major public release of the sources + - Renamed the library to arm_compute + - New CPP target introduced for C++ kernels shared between Arm® Neon™ and CL functions. + - New padding calculation interface introduced and ported most kernels / functions to use it. + - New OpenCL kernels / functions: + - CLGEMMLowpMatrixMultiplyKernel / CLGEMMLowp + - New Arm® Neon™ kernels / functions: + - @ref NENormalizationLayerKernel / @ref NENormalizationLayer + - NETransposeKernel / @ref NETranspose + - NELogits1DMaxKernel, NELogits1DShiftExpSumKernel, NELogits1DNormKernel / @ref NESoftmaxLayer + - NEIm2ColKernel, NECol2ImKernel, NEConvolutionLayerWeightsReshapeKernel / @ref NEConvolutionLayer + - NEGEMMMatrixAccumulateBiasesKernel / @ref NEFullyConnectedLayer + - NEGEMMLowpMatrixMultiplyKernel / NEGEMMLowp + +v17.03 Sources preview + - New OpenCL kernels / functions: + - CLGradientKernel, CLEdgeNonMaxSuppressionKernel, CLEdgeTraceKernel / CLCannyEdge + - GEMM refactoring + FP16 support: CLGEMMInterleave4x4Kernel, CLGEMMTranspose1xWKernel, CLGEMMMatrixMultiplyKernel, CLGEMMMatrixAdditionKernel / @ref CLGEMM + - CLGEMMMatrixAccumulateBiasesKernel / @ref CLFullyConnectedLayer + - CLTransposeKernel / @ref CLTranspose + - CLLKTrackerInitKernel, CLLKTrackerStage0Kernel, CLLKTrackerStage1Kernel, CLLKTrackerFinalizeKernel / CLOpticalFlow + - @ref CLNormalizationLayerKernel / @ref CLNormalizationLayer + - CLLaplacianPyramid, CLLaplacianReconstruct + - New Arm® Neon™ kernels / functions: + - NEActivationLayerKernel / @ref NEActivationLayer + - GEMM refactoring + FP16 support (Requires armv8.2 CPU): NEGEMMInterleave4x4Kernel, NEGEMMTranspose1xWKernel, NEGEMMMatrixMultiplyKernel, NEGEMMMatrixAdditionKernel / @ref NEGEMM + - NEPoolingLayerKernel / @ref NEPoolingLayer + +v17.02.1 Sources preview + - New OpenCL kernels / functions: + - CLLogits1DMaxKernel, CLLogits1DShiftExpSumKernel, CLLogits1DNormKernel / @ref CLSoftmaxLayer + - CLPoolingLayerKernel / @ref CLPoolingLayer + - CLIm2ColKernel, CLCol2ImKernel, CLConvolutionLayerWeightsReshapeKernel / CLConvolutionLayer + - CLRemapKernel / CLRemap + - CLGaussianPyramidHorKernel, CLGaussianPyramidVertKernel / CLGaussianPyramid, CLGaussianPyramidHalf, CLGaussianPyramidOrb + - CLMinMaxKernel, CLMinMaxLocationKernel / CLMinMaxLocation + - CLNonLinearFilterKernel / CLNonLinearFilter + - New Arm® Neon™ FP16 kernels (Requires armv8.2 CPU) + - NEAccumulateWeightedFP16Kernel + - NEBox3x3FP16Kernel + - NENonMaximaSuppression3x3FP16Kernel + +v17.02 Sources preview + - New OpenCL kernels / functions: + - CLActivationLayerKernel / @ref CLActivationLayer + - CLChannelCombineKernel / CLChannelCombine + - CLDerivativeKernel / CLChannelExtract + - CLFastCornersKernel / CLFastCorners + - CLMeanStdDevKernel / CLMeanStdDev + - New Arm® Neon™ kernels / functions: + - HOG / SVM: NEHOGOrientationBinningKernel, NEHOGBlockNormalizationKernel, NEHOGDetectorKernel, NEHOGNonMaximaSuppressionKernel / NEHOGDescriptor, NEHOGDetector, NEHOGGradient, NEHOGMultiDetection + - NENonLinearFilterKernel / NENonLinearFilter + - Introduced a CLScheduler to manage the default context and command queue used by the runtime library and create synchronisation events. + - Switched all the kernels / functions to use tensors instead of images. + - Updated documentation to include instructions to build the library from sources. + +v16.12 Binary preview release + - Original release + + */ +} // namespace arm_compute diff --git a/docs/user_guide/tests.dox b/docs/user_guide/tests.dox new file mode 100644 index 0000000000..510a1967ae --- /dev/null +++ b/docs/user_guide/tests.dox @@ -0,0 +1,385 @@ +/// +/// Copyright (c) 2017-2021 Arm Limited. +/// +/// SPDX-License-Identifier: MIT +/// +/// Permission is hereby granted, free of charge, to any person obtaining a copy +/// of this software and associated documentation files (the "Software"), to +/// deal in the Software without restriction, including without limitation the +/// rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +/// sell copies of the Software, and to permit persons to whom the Software is +/// furnished to do so, subject to the following conditions: +/// +/// The above copyright notice and this permission notice shall be included in all +/// copies or substantial portions of the Software. +/// +/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +/// SOFTWARE. +/// +namespace arm_compute +{ +namespace test +{ +/** +@page tests Validation and Benchmarks + +@tableofcontents + +@section tests_overview Overview + +Benchmark and validation tests are based on the same framework to setup and run +the tests. In addition to running simple, self-contained test functions the +framework supports fixtures and data test cases. The former allows to share +common setup routines between various backends thus reducing the amount of +duplicated code. The latter can be used to parameterize tests or fixtures with +different inputs, e.g. different tensor shapes. One limitation is that +tests/fixtures cannot be parameterized based on the data type if static type +information is needed within the test (e.g. to validate the results). + +@note By default tests are not built. To enable them you need to add validation_tests=1 and / or benchmark_tests=1 to your SCons line. + +@note Tests are not included in the pre-built binary archive, you have to build them from sources. + +@subsection tests_overview_fixtures Fixtures + +Fixtures can be used to share common setup, teardown or even run tasks among +multiple test cases. For that purpose a fixture can define a `setup`, +`teardown` and `run` method. Additionally the constructor and destructor might +also be customized. + +An instance of the fixture is created immediately before the actual test is +executed. After construction the @ref framework::Fixture::setup method is called. Then the test +function or the fixtures `run` method is invoked. After test execution the +@ref framework::Fixture::teardown method is called and lastly the fixture is destructed. + +@subsubsection tests_overview_fixtures_fixture Fixture + +Fixtures for non-parameterized test are straightforward. The custom fixture +class has to inherit from @ref framework::Fixture and choose to implement any of the +`setup`, `teardown` or `run` methods. None of the methods takes any arguments +or returns anything. + + class CustomFixture : public framework::Fixture + { + void setup() + { + _ptr = malloc(4000); + } + + void run() + { + ARM_COMPUTE_ASSERT(_ptr != nullptr); + } + + void teardown() + { + free(_ptr); + } + + void *_ptr; + }; + +@subsubsection tests_overview_fixtures_data_fixture Data fixture + +The advantage of a parameterized fixture is that arguments can be passed to the setup method at runtime. To make this possible the setup method has to be a template with a type parameter for every argument (though the template parameter doesn't have to be used). All other methods remain the same. + + class CustomFixture : public framework::Fixture + { + #ifdef ALTERNATIVE_DECLARATION + template <typename ...> + void setup(size_t size) + { + _ptr = malloc(size); + } + #else + template <typename T> + void setup(T size) + { + _ptr = malloc(size); + } + #endif + + void run() + { + ARM_COMPUTE_ASSERT(_ptr != nullptr); + } + + void teardown() + { + free(_ptr); + } + + void *_ptr; + }; + +@subsection tests_overview_test_cases Test cases + +All following commands can be optionally prefixed with `EXPECTED_FAILURE_` or +`DISABLED_`. + +@subsubsection tests_overview_test_cases_test_case Test case + +A simple test case function taking no inputs and having no (shared) state. + +- First argument is the name of the test case (has to be unique within the + enclosing test suite). +- Second argument is the dataset mode in which the test will be active. + + + TEST_CASE(TestCaseName, DatasetMode::PRECOMMIT) + { + ARM_COMPUTE_ASSERT_EQUAL(1 + 1, 2); + } + +@subsubsection tests_overview_test_cases_fixture_fixture_test_case Fixture test case + +A simple test case function taking no inputs that inherits from a fixture. The +test case will have access to all public and protected members of the fixture. +Only the setup and teardown methods of the fixture will be used. The body of +this function will be used as test function. + +- First argument is the name of the test case (has to be unique within the + enclosing test suite). +- Second argument is the class name of the fixture. +- Third argument is the dataset mode in which the test will be active. + + + class FixtureName : public framework::Fixture + { + public: + void setup() override + { + _one = 1; + } + + protected: + int _one; + }; + + FIXTURE_TEST_CASE(TestCaseName, FixtureName, DatasetMode::PRECOMMIT) + { + ARM_COMPUTE_ASSERT_EQUAL(_one + 1, 2); + } + +@subsubsection tests_overview_test_cases_fixture_register_fixture_test_case Registering a fixture as test case + +Allows to use a fixture directly as test case. Instead of defining a new test +function the run method of the fixture will be executed. + +- First argument is the name of the test case (has to be unique within the + enclosing test suite). +- Second argument is the class name of the fixture. +- Third argument is the dataset mode in which the test will be active. + + + class FixtureName : public framework::Fixture + { + public: + void setup() override + { + _one = 1; + } + + void run() override + { + ARM_COMPUTE_ASSERT_EQUAL(_one + 1, 2); + } + + protected: + int _one; + }; + + REGISTER_FIXTURE_TEST_CASE(TestCaseName, FixtureName, DatasetMode::PRECOMMIT); + + +@subsubsection tests_overview_test_cases_data_test_case Data test case + +A parameterized test case function that has no (shared) state. The dataset will +be used to generate versions of the test case with different inputs. + +- First argument is the name of the test case (has to be unique within the + enclosing test suite). +- Second argument is the dataset mode in which the test will be active. +- Third argument is the dataset. +- Further arguments specify names of the arguments to the test function. The + number must match the arity of the dataset. + + + DATA_TEST_CASE(TestCaseName, DatasetMode::PRECOMMIT, framework::make("Numbers", {1, 2, 3}), num) + { + ARM_COMPUTE_ASSERT(num < 4); + } + +@subsubsection tests_overview_test_cases_fixture_data_test_case Fixture data test case + +A parameterized test case that inherits from a fixture. The test case will have +access to all public and protected members of the fixture. Only the setup and +teardown methods of the fixture will be used. The setup method of the fixture +needs to be a template and has to accept inputs from the dataset as arguments. +The body of this function will be used as test function. The dataset will be +used to generate versions of the test case with different inputs. + +- First argument is the name of the test case (has to be unique within the + enclosing test suite). +- Second argument is the class name of the fixture. +- Third argument is the dataset mode in which the test will be active. +- Fourth argument is the dataset. + + + class FixtureName : public framework::Fixture + { + public: + template <typename T> + void setup(T num) + { + _num = num; + } + + protected: + int _num; + }; + + FIXTURE_DATA_TEST_CASE(TestCaseName, FixtureName, DatasetMode::PRECOMMIT, framework::make("Numbers", {1, 2, 3})) + { + ARM_COMPUTE_ASSERT(_num < 4); + } + +@subsubsection tests_overview_test_cases_register_fixture_data_test_case Registering a fixture as data test case + +Allows to use a fixture directly as parameterized test case. Instead of +defining a new test function the run method of the fixture will be executed. +The setup method of the fixture needs to be a template and has to accept inputs +from the dataset as arguments. The dataset will be used to generate versions of +the test case with different inputs. + +- First argument is the name of the test case (has to be unique within the + enclosing test suite). +- Second argument is the class name of the fixture. +- Third argument is the dataset mode in which the test will be active. +- Fourth argument is the dataset. + + + class FixtureName : public framework::Fixture + { + public: + template <typename T> + void setup(T num) + { + _num = num; + } + + void run() override + { + ARM_COMPUTE_ASSERT(_num < 4); + } + + protected: + int _num; + }; + + REGISTER_FIXTURE_DATA_TEST_CASE(TestCaseName, FixtureName, DatasetMode::PRECOMMIT, framework::make("Numbers", {1, 2, 3})); + +@section writing_tests Writing validation tests + +Before starting a new test case have a look at the existing ones. They should +provide a good overview how test cases are structured. + +- The C++ reference needs to be added to `tests/validation/CPP/`. The + reference function is typically a template parameterized by the underlying + value type of the `SimpleTensor`. This makes it easy to specialise for + different data types. +- If all backends have a common interface it makes sense to share the setup + code. This can be done by adding a fixture in + `tests/validation/fixtures/`. Inside of the `setup` method of a fixture + the tensors can be created and initialised and the function can be configured + and run. The actual test will only have to validate the results. To be shared + among multiple backends the fixture class is usually a template that accepts + the specific types (data, tensor class, function class etc.) as parameters. +- The actual test cases need to be added for each backend individually. + Typically the will be multiple tests for different data types and for + different execution modes, e.g. precommit and nightly. + +@section tests_running_tests Running tests +@subsection tests_running_tests_benchmark_and_validation Benchmarking and validation suites +@subsubsection tests_running_tests_benchmarking_filter Filter tests +All tests can be run by invoking + + ./arm_compute_benchmark ./data + +where `./data` contains the assets needed by the tests. + +If only a subset of the tests has to be executed the `--filter` option takes a +regular expression to select matching tests. + + ./arm_compute_benchmark --filter='^NEON/.*AlexNet' ./data + +@note Filtering will be much faster if the regular expression starts from the start ("^") or end ("$") of the line. + +Additionally each test has a test id which can be used as a filter, too. +However, the test id is not guaranteed to be stable when new tests are added. +Only for a specific build the same the test will keep its id. + + ./arm_compute_benchmark --filter-id=10 ./data + +All available tests can be displayed with the `--list-tests` switch. + + ./arm_compute_benchmark --list-tests + +More options can be found in the `--help` message. + +@subsubsection tests_running_tests_benchmarking_runtime Runtime +By default every test is run once on a single thread. The number of iterations +can be controlled via the `--iterations` option and the number of threads via +`--threads`. + +@subsubsection tests_running_tests_benchmarking_output Output +By default the benchmarking results are printed in a human readable format on +the command line. The colored output can be disabled via `--no-color-output`. +As an alternative output format JSON is supported and can be selected via +`--log-format=json`. To write the output to a file instead of stdout the +`--log-file` option can be used. + +@subsubsection tests_running_tests_benchmarking_mode Mode +Tests contain different datasets of different sizes, some of which will take several hours to run. +You can select which datasets to use by using the `--mode` option, we recommed you use `--mode=precommit` to start with. + +@subsubsection tests_running_tests_benchmarking_instruments Instruments +You can use the `--instruments` option to select one or more instruments to measure the execution time of the benchmark tests. + +`PMU` will try to read the CPU PMU events from the kernel (They need to be enabled on your platform) + +`MALI` will try to collect Arm® Mali™ hardware performance counters. (You need to have a recent enough Arm® Mali™ driver) + +`WALL_CLOCK_TIMER` will measure time using `gettimeofday`: this should work on all platforms. + +You can pass a combinations of these instruments: `--instruments=PMU,MALI,WALL_CLOCK_TIMER` + +@note You need to make sure the instruments have been selected at compile time using the `pmu=1` or `mali=1` scons options. + +@subsubsection tests_running_examples Examples + +To run all the precommit validation tests: + + LD_LIBRARY_PATH=. ./arm_compute_validation --mode=precommit + +To run the OpenCL precommit validation tests: + + LD_LIBRARY_PATH=. ./arm_compute_validation --mode=precommit --filter="^CL.*" + +To run the Arm® Neon™ precommit benchmark tests with PMU and Wall Clock timer in miliseconds instruments enabled: + + LD_LIBRARY_PATH=. ./arm_compute_benchmark --mode=precommit --filter="^NEON.*" --instruments="pmu,wall_clock_timer_ms" --iterations=10 + +To run the OpenCL precommit benchmark tests with OpenCL kernel timers in miliseconds enabled: + + LD_LIBRARY_PATH=. ./arm_compute_benchmark --mode=precommit --filter="^CL.*" --instruments="opencl_timer_ms" --iterations=10 + +@note You might need to export the path to OpenCL library as well in your LD_LIBRARY_PATH if Compute Library was built with OpenCL enabled. +*/ +} // namespace test +} // namespace arm_compute |