diff options
Diffstat (limited to 'docs/user_guide')
| -rw-r--r-- | docs/user_guide/errata.dox | 10 | ||||
| -rw-r--r-- | docs/user_guide/operator_list.dox | 3 | ||||
| -rw-r--r-- | docs/user_guide/release_version_and_change_log.dox | 15 |
3 files changed, 26 insertions, 2 deletions
diff --git a/docs/user_guide/errata.dox b/docs/user_guide/errata.dox index 056e45a432..c195dc7851 100644 --- a/docs/user_guide/errata.dox +++ b/docs/user_guide/errata.dox @@ -1,5 +1,5 @@ /// -/// Copyright (c) 2019-2023 Arm Limited. +/// Copyright (c) 2019-2024 Arm Limited. /// /// SPDX-License-Identifier: MIT /// @@ -30,6 +30,14 @@ namespace arm_compute @section S7_1_errata Errata +- (COMPMID-6904) Fix out-of-bound memory write for non-optimized FP16 GeMM kernel. + - Versions: >= v17.09 && < v24.06 + - Oses: Linux, Android, MacOS, Windows. + - Conditions: + - Compile the latest Arm Compute Library for armv8.2-a or multi_isa + - Device with FP16 support + - GeMM with beta coefficient != 0 or 1 + - (COMPMID-6493) Crash when running Arm Compute Library compiled for SVE2 on a computer that support SVE only. - Versions: >= v21.02 && <=v23.08 - OSs: Linux, Android. diff --git a/docs/user_guide/operator_list.dox b/docs/user_guide/operator_list.dox index e7f1823f8b..8e828e88a4 100644 --- a/docs/user_guide/operator_list.dox +++ b/docs/user_guide/operator_list.dox @@ -602,6 +602,7 @@ where N = batches, C = channels, H = height, W = width, D = depth <tr><td>F16<td>F16<td>F16<td>F16 <tr><td>F32<td>F32<td>F32<td>F32 <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QASYMM8_SIGNED<td>S32<td>QASYMM8 <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED @@ -1762,11 +1763,13 @@ where N = batches, C = channels, H = height, W = width, D = depth <table> <tr><th>src0<th>src1<th>src2<th>dst <tr><td>QASYMM8<td>QASYMM8<td>S32<td>QASYMM8 + <tr><td>QASYMM8<td>QASYMM8_SIGNED<td>S32<td>QASYMM8 <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8 <tr><td>QASYMM8<td>QSYMM8<td>S32<td>QASYMM8 <tr><td>QASYMM8<td>QASYMM8<td>S32<td>S32 <tr><td>QASYMM8<td>QSYMM8_PER_CHANNEL<td>S32<td>S32 <tr><td>QASYMM8<td>QSYMM8<td>S32<td>S32 + <tr><td>QASYMM8<td>QASYMM8_SIGNED<td>F32<td>F32 <tr><td>QASYMM8_SIGNED<td>QASYMM8_SIGNED<td>S32<td>QASYMM8_SIGNED <tr><td>QASYMM8_SIGNED<td>QSYMM8_PER_CHANNEL<td>S32<td>QASYMM8_SIGNED <tr><td>QASYMM8_SIGNED<td>QSYMM8<td>S32<td>QASYMM8_SIGNED diff --git a/docs/user_guide/release_version_and_change_log.dox b/docs/user_guide/release_version_and_change_log.dox index d9c2c8476d..5968ec8e3c 100644 --- a/docs/user_guide/release_version_and_change_log.dox +++ b/docs/user_guide/release_version_and_change_log.dox @@ -41,7 +41,20 @@ If there is more than one release in a month then an extra sequential number is @section S2_2_changelog Changelog -v24.08 Public major release +v24.07 Public major release + - Add support for mixed sign quantized convolution. + - Add support for mixed sign dequantized GEMM. + - Add SME FP16 GEMV kernel. + - Change SME vector length function to use RDSVL instead of static variable. + - Remove unused "get_default_activation_values" functions. + - Add SVE fixed format interleaved BF16 DOT kernel. + - Updates and optimizations to assembly kernels. + - Expose CpuGemm functionality using the experimental operators api + - Optimize CPU operator memory management. + +v24.06 Public minor release + - Enable FP16 in multiple Neon™ kernels for multi_isa + v8a + - Fix OpenMP® thread scheduling for large machine - Optimize CPU activation functions using LUT-based implementation: - Tanh function for FP16. |