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| author | Adnan AlSinan <adnan.alsinan@arm.com> | 2023-02-22 12:15:14 +0000 |
|---|---|---|
| committer | Adnan AlSinan <adnan.alsinan@arm.com> | 2023-03-01 11:48:22 +0000 |
| commit | bbf2e7477be984702e1a51f2a23910ee8349b867 (patch) | |
| tree | d5ce7a16e7f6e977bba2f88c8a913d071b4e04ed /src/cpu/operators/CpuPool2d.cpp | |
| parent | 227db8db83cd85d8704a8edbd4e8c88af0dd1f84 (diff) | |
| download | ComputeLibrary-bbf2e7477be984702e1a51f2a23910ee8349b867.tar.gz | |
Add support for kernel indices in Maxpool
- Add a max pooling implementation that returns kernel indices.
- Add a parameter in pooling info object to pick kernel indices impl.
- Add validation tests.
Resolves: [ONCPUML-1187]
Signed-off-by: Adnan AlSinan <adnan.alsinan@arm.com>
Change-Id: I485ef1604f676ee14d5f7f62d33699e49c38e4d3
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9192
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/operators/CpuPool2d.cpp')
| -rw-r--r-- | src/cpu/operators/CpuPool2d.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/cpu/operators/CpuPool2d.cpp b/src/cpu/operators/CpuPool2d.cpp index eabbd5e0cc..722cd36ee5 100644 --- a/src/cpu/operators/CpuPool2d.cpp +++ b/src/cpu/operators/CpuPool2d.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021, 2023 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -27,7 +27,6 @@ #include "arm_compute/core/TensorInfo.h" #include "arm_compute/runtime/NEON/NEScheduler.h" #include "src/common/utils/Log.h" -#include "src/core/NEON/kernels/NEFillBorderKernel.h" #include "src/cpu/kernels/CpuPool2dKernel.h" #include "src/cpu/kernels/internal/CpuPool2dAssemblyWrapperKernel.h" @@ -41,6 +40,7 @@ CpuPool2d::CpuPool2d() : _pooling_layer_kernel(), _asm_glue(), _is_global_pooling_layer(false), + _use_kernel_indices(false), _data_layout(DataLayout::NCHW), _aux_mem(1) { @@ -62,6 +62,7 @@ void CpuPool2d::configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayer const unsigned int idx_width = get_data_layout_dimension_index(_data_layout, DataLayoutDimension::WIDTH); const unsigned int idx_height = get_data_layout_dimension_index(_data_layout, DataLayoutDimension::HEIGHT); _is_global_pooling_layer = (src->dimension(idx_width) == pool_info.pool_size.width) && (src->dimension(idx_height) == pool_info.pool_size.height); + _use_kernel_indices = pool_info.use_kernel_indices; if(run_optimised) { @@ -117,7 +118,7 @@ void CpuPool2d::run(ITensorPack &tensors) NEScheduler::get().schedule_op(_pooling_layer_kernel.get(), _is_global_pooling_layer ? Window::DimZ : Window::DimY, _pooling_layer_kernel->window(), tensors); break; case DataLayout::NHWC: - NEScheduler::get().schedule_op(_pooling_layer_kernel.get(), Window::DimX, _pooling_layer_kernel->window(), tensors); + NEScheduler::get().schedule_op(_pooling_layer_kernel.get(), (_use_kernel_indices ? Window::DimY : Window::DimX), _pooling_layer_kernel->window(), tensors); break; default: ARM_COMPUTE_ERROR("Data layout not supported"); |