Improve selection speed of CPU implementations

CPU micro-kernel to be used was picked during kernel execution.
Move selection during configuration to reduce runtime overhead.

Standardize kernel names as follows:
<simd_tech>_<data_type>_<data_layout>_<kernel_name>
e.g. sve_fp32_nhwc_scale

Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: I544f1c08c8fef0f130a3bde61882ccb9a1f47f21
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5855
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>

1 files changed, 20 insertions, 16 deletions

diff --git a/src/core/cpu/kernels/CpuSubKernel.cpp b/src/core/cpu/kernels/CpuSubKernel.cpp
index d7057bbe2b..098a324377 100644
--- a/src/core/cpu/kernels/CpuSubKernel.cpp
+++ b/src/core/cpu/kernels/CpuSubKernel.cpp
@@ -59,59 +59,59 @@ struct SubKernel
 static const SubKernel available_kernels[] =
 {
     {
-        "sub_same_neon",
+        "neon_fp32_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == DataType::F32)); },
         REGISTER_FP32_NEON(arm_compute::cpu::sub_same_neon<float>)
     },
 #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
     {
-        "sub_same_neon",
+        "neon_fp16_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == DataType::F16)); },
         REGISTER_FP16_NEON(arm_compute::cpu::sub_same_neon<float16_t>)
     },
 #endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */
     {
-        "sub_same_neon",
+        "neon_u8_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == data.dt3) && (data.dt1 == DataType::U8)); },
         REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<uint8_t>)
     },
     {
-        "sub_same_neon",
+        "neon_s16_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == data.dt3) && (data.dt1 == DataType::S16)); },
         REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<int16_t>)
     },
     {
-        "sub_same_neon",
+        "neon_s32_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == data.dt3) && (data.dt1 == DataType::S32)); },
         REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<int32_t>)
     },
     {
-        "sub_u8_s16_s16_neon",
+        "neon_u8_s16_s16_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == DataType::U8) && (data.dt2 == DataType::S16)); },
         REGISTER_INTEGER_NEON(arm_compute::cpu::sub_u8_s16_s16_neon)
     },
     {
-        "sub_s16_u8_s16_neon",
+        "neon_s16_u8_s16_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == DataType::S16) && (data.dt2 == DataType::U8)); },
         REGISTER_INTEGER_NEON(arm_compute::cpu::sub_s16_u8_s16_neon)
     },
     {
-        "sub_u8_u8_s16_neon",
+        "neon_u8_u8_s16_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt3 == DataType::S16)); },
         REGISTER_INTEGER_NEON(arm_compute::cpu::sub_u8_u8_s16_neon)
     },
     {
-        "sub_qasymm8_neon",
+        "neon_qu8_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == DataType::QASYMM8)); },
         REGISTER_QASYMM8_NEON(arm_compute::cpu::sub_qasymm8_neon)
     },
     {
-        "sub_qasymm8_signed_neon",
+        "neon_qs8_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == DataType::QASYMM8_SIGNED)); },
         REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::sub_qasymm8_signed_neon)
     },
     {
-        "sub_qsymm16_neon",
+        "neon_s16_sub",
         [](const SubSelectorData & data) { return ((data.dt1 == data.dt2) && (data.dt1 == DataType::QSYMM16)); },
         REGISTER_QSYMM16_NEON(arm_compute::cpu::sub_qsymm16_neon)
     },
@@ -206,7 +206,12 @@ void CpuSubKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, I
     // Auto initialize dst if not initialized
     set_shape_if_empty(*dst, out_shape);
 
-    _policy = policy;
+    const auto *uk = get_implementation(src0->data_type(), src1->data_type(), dst->data_type());
+    ARM_COMPUTE_ERROR_ON_NULLPTR(uk);
+
+    _policy     = policy;
+    _run_method = uk->ukernel;
+    _name       = std::string("CpuSubKernel").append("/").append(uk->name);
 
     // CpuSubKernel doesn't need padding so update_window_and_padding() can be skipped
     Window win = calculate_max_window(out_shape, Steps());
@@ -227,19 +232,18 @@ void CpuSubKernel::run_op(ITensorPack &tensors, const Window &window, const Thre
     ARM_COMPUTE_UNUSED(info);
     ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);
     ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
+    ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
 
     const ITensor *src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
     const ITensor *src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
     ITensor       *dst  = tensors.get_tensor(TensorType::ACL_DST);
 
-    // Dispatch kernel
-    const auto *uk = get_implementation(src0->info()->data_type(), src1->info()->data_type(), dst->info()->data_type());
-    uk->ukernel(src0, src1, dst, _policy, window);
+    _run_method(src0, src1, dst, _policy, window);
 }
 
 const char *CpuSubKernel::name() const
 {
-    return "CpuSubKernel";
+    return _name.c_str();
 }
 } // namespace kernels
 } // namespace cpu