diff options
| author | David Mansell <David.Mansell@arm.com> | 2023-03-30 19:10:52 +0100 |
|---|---|---|
| committer | Viet-Hoa Do <viet-hoa.do@arm.com> | 2023-04-26 11:05:03 +0000 |
| commit | b2758f35da97319fd15722485e9b4ba7b35c8cfa (patch) | |
| tree | edec5ead897c52b027f95e470fe23e09c6b1291e /src/core/NEON/kernels | |
| parent | af15076bf8148870aa41d414b73e81f3b7e86436 (diff) | |
| download | ComputeLibrary-b2758f35da97319fd15722485e9b4ba7b35c8cfa.tar.gz | |
Add FP16 depthwise kernels for SME2
Resolves: COMPMID-5988
Change-Id: I93e78edf31c9eec8242ccbb8c3c768f46a7c7c38
Signed-off-by: David Mansell <David.Mansell@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9456
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels')
16 files changed, 5084 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp index 6b100d9d61..350e93b874 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_fp16.cpp @@ -36,6 +36,13 @@ #if defined(__aarch64__) #if defined(ARM_COMPUTE_ENABLE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME2) +#include "kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp" +#include "kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp" +#include "kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp" +#include "kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp" +#include "kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp" +#endif // defined(ARM_COMPUTE_ENABLE_SME2) #include "kernels/sve_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp" #include "kernels/sve_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp" #include "kernels/sve_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp" @@ -82,6 +89,68 @@ namespace static const DepthwiseImplementation<__fp16, __fp16> depthwise_fp16_methods[] = { #if defined(__aarch64__) #if defined(ARM_COMPUTE_ENABLE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME2) + { + DepthwiseMethod::DEPTHFIRST, + "sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst", + constraint(is_supported<sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst>, + has_no_channel_multiplier, + cpu_has_sme2), + cycle_estimate<sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst>, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + auto strat = new sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst(args.cpu_info); + return new DepthwiseDepthfirst<__fp16>(strat, args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst", + constraint(is_supported<sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst>, + has_no_channel_multiplier, + cpu_has_sme2), + cycle_estimate<sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst>, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + auto strat = new sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst(args.cpu_info); + return new DepthwiseDepthfirst<__fp16>(strat, args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst", + constraint(is_supported<sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst>, + has_no_channel_multiplier, + cpu_has_sme2), + cycle_estimate<sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst>, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + auto strat = new sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst(args.cpu_info); + return new DepthwiseDepthfirst<__fp16>(strat, args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst", + constraint(is_supported<sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst>, + has_no_channel_multiplier, + cpu_has_sme2), + cycle_estimate<sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst>, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + auto strat = new sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst(args.cpu_info); + return new DepthwiseDepthfirst<__fp16>(strat, args); + }, + }, + { + DepthwiseMethod::DEPTHFIRST, + "sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst", + constraint(is_supported<sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst>, + has_no_channel_multiplier, + cpu_has_sme2), + cycle_estimate<sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst>, + [] (const DepthwiseArgs &args, const Nothing &) -> DepthwiseCommon<__fp16, __fp16, __fp16> * { + auto strat = new sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst(args.cpu_info); + return new DepthwiseDepthfirst<__fp16>(strat, args); + }, + }, +#endif // defined(ARM_COMPUTE_ENABLE_SME2) { DepthwiseMethod::DEPTHFIRST, "sve_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst", diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp new file mode 100644 index 0000000000..2b6f70c089 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst.hpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/core/NEON/kernels/arm_gemm/utils.hpp" + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl(const __fp16 *const *const input_ptrs, __fp16 *const *const outptrs, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); +void sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl(const unsigned int n_tile_rows, const unsigned int n_tile_cols, const __fp16 *inptr, int64_t ld_input_row, int64_t ld_input_col, __fp16 *outptr, int64_t ld_output_row, int64_t ld_output_col, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); + +class sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16> +{ + private: + using Parent = DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16>; + Parent::IndirectKernelType m_indirect_kernel = sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl; + Parent::DirectKernelType m_direct_kernel = sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl; + + public: + using return_type = __fp16; + constexpr static auto vl_type = arm_gemm::VLType::SME; + + constexpr static unsigned int kernel_rows = 3; + constexpr static unsigned int kernel_cols = 3; + + constexpr static unsigned int stride_rows = 1; + constexpr static unsigned int stride_cols = 1; + + constexpr static unsigned int output_rows = 2; + constexpr static unsigned int output_cols = 2; + + sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst(const CPUInfo *) + : Parent(output_rows, output_cols, kernel_rows, kernel_cols, stride_rows, stride_cols) {} + + arm_gemm::VLType get_vl_type(void) const override { return vl_type; } + + Parent::IndirectKernelType get_indirect_kernel() const override { return m_indirect_kernel; } + Parent::DirectKernelType get_direct_kernel() const override { return m_direct_kernel; } +}; + +} // namespace depthwise +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp new file mode 100644 index 0000000000..2d558ade3f --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_direct.cpp @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_direct_impl( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + const uint64_t n_tile_rows, n_tile_cols; + const __fp16 *inptr; + const uint64_t ld_input_row; + const uint64_t ld_input_col; + __fp16 *outptr; + const uint64_t ld_output_row; + const uint64_t ld_output_col; + const void *params; + const __fp16 min, max; + + uint64_t tile_i = 0, tile_j = 0; + + Args( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + const float activation_min, + const float activation_max + ) : n_tile_rows(n_tile_rows), n_tile_cols(n_tile_cols), inptr(inptr), + ld_input_row(ld_input_row), ld_input_col(ld_input_col), outptr(outptr), + ld_output_row(ld_output_row), ld_output_col(ld_output_col), + params(params), min(activation_min), max(activation_max) + { + } + }; + + Args params_struct( + n_tile_rows, n_tile_cols, + inptr, ld_input_row, ld_input_col, + outptr, ld_output_row, ld_output_col, + params, activation_min, activation_max + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x4, #0x0\n" + "mov x5, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "1:" // Tile loop + "str x4, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "mov x22, #0x2\n" + "str x5, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" + "ldr x6, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" + "ldr x7, [%x[params_struct], %[offsetof_args_inptr]]\n" + "mul x20, x4, x21\n" // offset = tile_i * ld_input_row + "ldr x8, [%x[params_struct], %[offsetof_args_params]]\n" + "madd x20, x5, x6, x20\n" // offset += tile_j * ld_input_col + "mul x20, x20, x22\n" // offset *= kernel_stride * output_size + "add x17, x6, x6\n" + "add x7, x7, x20, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) + "add x16, x7, x21, LSL #1\n" + "add x15, x17, x6\n" + "add x14, x16, x21, LSL #1\n" + "add x13, x14, x21, LSL #1\n" + "cbnz x5, 2f\n" + "ldr x24, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "lsl x12, %x[n_channels], #0x1\n" + "mov x21, #0x4\n" + "mul x21, x21, x6\n" + "add x11, x16, x6, LSL #1\n" + "add x10, x7, x15, LSL #1\n" + "add x9, x16, x17, LSL #1\n" + "sub x20, x24, x5\n" + "add x28, x14, x6, LSL #1\n" + "sub x20, x20, #0x1\n" + "add x27, x13, x15, LSL #1\n" + "and x20, x20, #0x3fffff\n" + "add x26, x7, x6, LSL #1\n" + "orr x12, x12, x20, LSL #22\n" + "add x25, x7, x17, LSL #1\n" + "orr x12, x12, x21, LSL #38\n" + "add x24, x14, x17, LSL #1\n" + "add x23, x16, x15, LSL #1\n" + "add x22, x14, x15, LSL #1\n" + "add x21, x13, x6, LSL #1\n" + "add x20, x13, x17, LSL #1\n" + ".inst 0xf8ac497a // rprfm pldonce, x12, [x11]\n" + ".inst 0xf8ac48fa // rprfm pldonce, x12, [x7]\n" + ".inst 0xf8ac495a // rprfm pldonce, x12, [x10]\n" + ".inst 0xf8ac493a // rprfm pldonce, x12, [x9]\n" + ".inst 0xf8ac4b9a // rprfm pldonce, x12, [x28]\n" + ".inst 0xf8ac49ba // rprfm pldonce, x12, [x13]\n" + ".inst 0xf8ac4b7a // rprfm pldonce, x12, [x27]\n" + ".inst 0xf8ac4b5a // rprfm pldonce, x12, [x26]\n" + ".inst 0xf8ac4b3a // rprfm pldonce, x12, [x25]\n" + ".inst 0xf8ac4b1a // rprfm pldonce, x12, [x24]\n" + ".inst 0xf8ac4a1a // rprfm pldonce, x12, [x16]\n" + ".inst 0xf8ac4afa // rprfm pldonce, x12, [x23]\n" + ".inst 0xf8ac49da // rprfm pldonce, x12, [x14]\n" + ".inst 0xf8ac4ada // rprfm pldonce, x12, [x22]\n" + ".inst 0xf8ac4aba // rprfm pldonce, x12, [x21]\n" + ".inst 0xf8ac4a9a // rprfm pldonce, x12, [x20]\n" + "2:" // Tile loop: Prefetch input rows: End + "ldr x26, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" + "mov x20, #0x2\n" + "ld1h { z18.h }, p3/Z, [x8]\n" + "addvl x8, x8, #1\n" + "ldr x25, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" + "cnth x24\n" + ".inst 0xa040a100 // ld1h { z0.h-z3.h }, pn8.b/Z, [x8]\n" + "addvl x8, x8, #4\n" + "ldr x23, [%x[params_struct], %[offsetof_args_outptr]]\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + ".inst 0xa040a104 // ld1h { z4.h-z7.h }, pn8.b/Z, [x8]\n" + "addvl x8, x8, #4\n" + "mul x22, x4, x26\n" // offset = tile_i * ld_output_row + "cmp x24, %x[n_channels]\n" + "ld1rh { z17.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "madd x22, x5, x25, x22\n" // offset += tile_j * ld_output_col + "ld1rh { z16.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "mov x21, #0x0\n" + "mul x22, x22, x20\n" // offset *= output_tile_size + "sub x20, XZR, x24\n" + "ld1h { z8.h }, p3/Z, [x8]\n" + "add x23, x23, x22, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) + "ld1h { z9.h }, p2/Z, [x16, x6, LSL #1]\n" + "addvl x8, x8, #1\n" + "add x22, x23, x26, LSL #1\n" + "ld1h { z10.h }, p2/Z, [x7]\n" + "ld1h { z11.h }, p2/Z, [x7, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x16, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x14, x6, LSL #1]\n" + "bge 4f\n" + "3:" // Tile loop: Channel loop + "movprfx z28, z18\n fmla z28.h, p3/M, z4.h, z9.h\n" + "movprfx z29, z18\n fmla z29.h, p3/M, z3.h, z9.h\n" + "whilelt p1.h, x24, %x[n_channels]\n" + "inch x21\n" + "movprfx z30, z18\n fmla z30.h, p3/M, z1.h, z9.h\n" + "movprfx z31, z18\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x13]\n" + "inch x24\n" + "ld1h { z18.h }, p3/Z, [x8]\n" + "addvl x8, x8, #1\n" + "mov p0.b, p2.b\n" + "inch x20\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z30.h, p3/M, z2.h, z12.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "fmla z28.h, p3/M, z5.h, z12.h\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x7, x6, LSL #1]\n" + "fmla z30.h, p3/M, z6.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x7, x17, LSL #1]\n" + "addvl x7, x7, #1\n" + "fmla z31.h, p3/M, z3.h, z13.h\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z29.h, p3/M, z6.h, z13.h\n" + "fmla z30.h, p3/M, z4.h, z13.h\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16]\n" + "fmla z28.h, p3/M, z1.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x16, x15, LSL #1]\n" + "addvl x16, x16, #1\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z29.h, p3/M, z1.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x14]\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x15, LSL #1]\n" + "addvl x14, x14, #1\n" + "ld1h { z13.h }, p1/Z, [x14, x6, LSL #1]\n" + "fmla z30.h, p3/M, z3.h, z9.h\n" + "fmla z31.h, p3/M, z5.h, z10.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x6, LSL #1]\n" + ".inst 0xa040a100 // ld1h { z0.h-z3.h }, pn8.b/Z, [x8]\n" + "addvl x8, x8, #4\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x17, LSL #1]\n" + "whilelt p2.h, x21, %x[n_channels]\n" + "cmp x24, %x[n_channels]\n" + "fmla z30.h, p3/M, z7.h, z11.h\n" + "fmla z31.h, p3/M, z6.h, z11.h\n" + "addvl x13, x13, #1\n" + "ld1h { z11.h }, p1/Z, [x7, x15, LSL #1]\n" + "fmla z28.h, p3/M, z6.h, z9.h\n" + "ld1h { z9.h }, p1/Z, [x16, x6, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p1/Z, [x7]\n" + "fmla z30.h, p3/M, z8.h, z12.h\n" + "fmla z31.h, p3/M, z7.h, z12.h\n" + ".inst 0xa040a104 // ld1h { z4.h-z7.h }, pn8.b/Z, [x8]\n" + "addvl x8, x8, #4\n" + "ld1h { z12.h }, p1/Z, [x16, x17, LSL #1]\n" + "ld1h { z8.h }, p3/Z, [x8]\n" + "addvl x8, x8, #1\n" + ".inst 0xc170ca3c // fclamp { z28.h-z31.h }, z17.h, z16.h\n" + "st1h { z28.h }, p0, [x23]\n" + "st1h { z29.h }, p0, [x23, x25, LSL #1]\n" + "addvl x23, x23, #1\n" + "st1h { z30.h }, p0, [x22]\n" + "st1h { z31.h }, p0, [x22, x25, LSL #1]\n" + "addvl x22, x22, #1\n" + "blt 3b\n" + "4:" // Tile loop: Channel tail + "movprfx z28, z18\n fmla z28.h, p3/M, z4.h, z9.h\n" + "movprfx z29, z18\n fmla z29.h, p3/M, z3.h, z9.h\n" + "ldr x5, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "mov p0.b, p2.b\n" + "movprfx z30, z18\n fmla z30.h, p3/M, z1.h, z9.h\n" + "movprfx z31, z18\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x13]\n" + "ldr x4, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "ldr x24, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" + "add x5, x5, #0x1\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "add x20, x4, #0x1\n" + "fmla z30.h, p3/M, z2.h, z12.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "cmp x5, x24\n" + "csel x4, x4, x20, LT\n" + "csel x5, x5, XZR, LT\n" + "cmp x4, x21\n" + "fmla z28.h, p3/M, z5.h, z12.h\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x7, x6, LSL #1]\n" + "fmla z30.h, p3/M, z6.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x7, x17, LSL #1]\n" + "fmla z31.h, p3/M, z3.h, z13.h\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z29.h, p3/M, z6.h, z13.h\n" + "fmla z30.h, p3/M, z4.h, z13.h\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16]\n" + "fmla z28.h, p3/M, z1.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x16, x15, LSL #1]\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z29.h, p3/M, z1.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x14]\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z30.h, p3/M, z3.h, z9.h\n" + "fmla z31.h, p3/M, z5.h, z10.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x6, LSL #1]\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x17, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z11.h\n" + "fmla z31.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z6.h, z9.h\n" + "fmla z29.h, p3/M, z8.h, z10.h\n" + "fmla z30.h, p3/M, z8.h, z12.h\n" + "fmla z31.h, p3/M, z7.h, z12.h\n" + ".inst 0xc170ca3c // fclamp { z28.h-z31.h }, z17.h, z16.h\n" + "st1h { z28.h }, p0, [x23]\n" + "st1h { z29.h }, p0, [x23, x25, LSL #1]\n" + "st1h { z30.h }, p0, [x22]\n" + "st1h { z31.h }, p0, [x22, x25, LSL #1]\n" + "blt 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp new file mode 100644 index 0000000000..415e344832 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst/generic_indirect.cpp @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output2x2_mla_depthfirst_indirect_impl( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + __fp16 *const *outptrs; + const void *params; + const __fp16 min, max; + const __fp16 *inptrs[16]; + + Args( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *const params, + const __fp16 min, + const __fp16 max + ) : outptrs(outptrs), params(params), min(min), max(max) + { + inptrs[0] = input_ptrs[5]; + inptrs[1] = input_ptrs[0]; + inptrs[2] = input_ptrs[3]; + inptrs[3] = input_ptrs[6]; + inptrs[4] = input_ptrs[9]; + inptrs[5] = input_ptrs[12]; + inptrs[6] = input_ptrs[15]; + inptrs[7] = input_ptrs[1]; + inptrs[8] = input_ptrs[2]; + inptrs[9] = input_ptrs[10]; + inptrs[10] = input_ptrs[4]; + inptrs[11] = input_ptrs[7]; + inptrs[12] = input_ptrs[8]; + inptrs[13] = input_ptrs[11]; + inptrs[14] = input_ptrs[13]; + inptrs[15] = input_ptrs[14]; + + } + }; + + Args params_struct(input_ptrs, outptrs, params, + activation_min, activation_max); + + __asm__ __volatile__( + "ldr x20, [%x[params_struct], %[offsetof_args_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "add x16, %x[params_struct], %[offsetof_Args_inptrs]\n" + "mov x15, #0x0\n" + "ldr x14, [%x[params_struct], %[offsetof_args_params]]\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "ldr x13, [x16, #0x20]\n" + "cnth x12\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + "ld1rh { z18.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "ldp x11, x10, [x20, #0x0]\n" + "cmp x12, %x[n_channels]\n" + "ld1rh { z17.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "sub x9, XZR, x12\n" + "ldp x28, x27, [x20, #0x10]\n" + "ld1h { z16.h }, p3/Z, [x14]\n" + "addvl x14, x14, #1\n" + "ldp x26, x25, [x16, #0x0]\n" + ".inst 0xa040a1c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "ldp x24, x23, [x16, #0x10]\n" + ".inst 0xa040a1c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "ld1h { z8.h }, p3/Z, [x14]\n" + "addvl x14, x14, #1\n" + "ld1h { z9.h }, p2/Z, [x26, x15, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x24, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x23, x15, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x13, x15, LSL #1]\n" + "bge 2f\n" + "1:" // Channel loop + "movprfx z28, z16\n fmla z28.h, p3/M, z4.h, z9.h\n" + "movprfx z29, z16\n fmla z29.h, p3/M, z3.h, z9.h\n" + "ldr x22, [x16, #0x28]\n" + "whilelt p1.h, x12, %x[n_channels]\n" + "movprfx z30, z16\n fmla z30.h, p3/M, z1.h, z9.h\n" + "movprfx z31, z16\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ldr x21, [x16, #0x30]\n" + "ld1h { z16.h }, p3/Z, [x14]\n" + "ldr x20, [x16, #0x38]\n" + "addvl x14, x14, #1\n" + "inch x9\n" + "ld1h { z9.h }, p2/Z, [x22, x15, LSL #1]\n" + "ldr x25, [x16, #0x48]\n" + "mov p0.b, p2.b\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x21, x15, LSL #1]\n" + "ldr x26, [x16, #0x40]\n" + "fmla z30.h, p3/M, z2.h, z12.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "ldr x24, [x16, #0x50]\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x23, [x16, #0x58]\n" + "fmla z28.h, p3/M, z5.h, z12.h\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x20, x15, LSL #1]\n" + "ldr x13, [x16, #0x60]\n" + "fmla z30.h, p3/M, z6.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z31.h, p3/M, z3.h, z13.h\n" + "ldr x22, [x16, #0x68]\n" + "ldr x21, [x16, #0x70]\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z29.h, p3/M, z6.h, z13.h\n" + "ldr x20, [x16, #0x78]\n" + "fmla z30.h, p3/M, z4.h, z13.h\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldp x26, x25, [x16, #0x0]\n" + "fmla z28.h, p3/M, z1.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x23, x15, LSL #1]\n" + "ldp x24, x23, [x16, #0x10]\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z29.h, p3/M, z1.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x13, [x16, #0x20]\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "ld1h { z13.h }, p1/Z, [x13, x12, LSL #1]\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x22, x15, LSL #1]\n" + "fmla z30.h, p3/M, z3.h, z9.h\n" + "fmla z31.h, p3/M, z5.h, z10.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x21, x15, LSL #1]\n" + ".inst 0xa040a1c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x20, x15, LSL #1]\n" + "inch x15\n" + "fmla z30.h, p3/M, z7.h, z11.h\n" + "fmla z31.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p1/Z, [x24, x12, LSL #1]\n" + "whilelt p2.h, x15, %x[n_channels]\n" + "fmla z28.h, p3/M, z6.h, z9.h\n" + "ld1h { z9.h }, p1/Z, [x26, x12, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p1/Z, [x25, x12, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z12.h\n" + "fmla z31.h, p3/M, z7.h, z12.h\n" + "ld1h { z12.h }, p1/Z, [x23, x12, LSL #1]\n" + "inch x12\n" + ".inst 0xa040a1c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "cmp x12, %x[n_channels]\n" + "ld1h { z8.h }, p3/Z, [x14]\n" + "addvl x14, x14, #1\n" + ".inst 0xc171ca5c // fclamp { z28.h-z31.h }, z18.h, z17.h\n" + "st1h { z28.h }, p0, [x11, x9, LSL #1]\n" + "st1h { z29.h }, p0, [x10, x9, LSL #1]\n" + "st1h { z30.h }, p0, [x28, x9, LSL #1]\n" + "st1h { z31.h }, p0, [x27, x9, LSL #1]\n" + "blt 1b\n" + "2:" // Channel tail + "movprfx z28, z16\n fmla z28.h, p3/M, z4.h, z9.h\n" + "movprfx z29, z16\n fmla z29.h, p3/M, z3.h, z9.h\n" + "ldr x22, [x16, #0x28]\n" + "inch x9\n" + "movprfx z30, z16\n fmla z30.h, p3/M, z1.h, z9.h\n" + "movprfx z31, z16\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ldr x21, [x16, #0x30]\n" + "mov p0.b, p2.b\n" + "ldr x20, [x16, #0x38]\n" + "ld1h { z9.h }, p2/Z, [x22, x15, LSL #1]\n" + "ldr x25, [x16, #0x48]\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x21, x15, LSL #1]\n" + "ldr x26, [x16, #0x40]\n" + "fmla z30.h, p3/M, z2.h, z12.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "ldr x24, [x16, #0x50]\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x23, [x16, #0x58]\n" + "fmla z28.h, p3/M, z5.h, z12.h\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x20, x15, LSL #1]\n" + "ldr x13, [x16, #0x60]\n" + "fmla z30.h, p3/M, z6.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z31.h, p3/M, z3.h, z13.h\n" + "ldr x22, [x16, #0x68]\n" + "ldr x21, [x16, #0x70]\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z29.h, p3/M, z6.h, z13.h\n" + "ldr x20, [x16, #0x78]\n" + "fmla z30.h, p3/M, z4.h, z13.h\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z28.h, p3/M, z1.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x23, x15, LSL #1]\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z29.h, p3/M, z1.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x22, x15, LSL #1]\n" + "fmla z30.h, p3/M, z3.h, z9.h\n" + "fmla z31.h, p3/M, z5.h, z10.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x21, x15, LSL #1]\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x20, x15, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z11.h\n" + "fmla z31.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z6.h, z9.h\n" + "fmla z29.h, p3/M, z8.h, z10.h\n" + "fmla z30.h, p3/M, z8.h, z12.h\n" + "fmla z31.h, p3/M, z7.h, z12.h\n" + ".inst 0xc171ca5c // fclamp { z28.h-z31.h }, z18.h, z17.h\n" + "st1h { z28.h }, p0, [x11, x9, LSL #1]\n" + "st1h { z29.h }, p0, [x10, x9, LSL #1]\n" + "st1h { z30.h }, p0, [x28, x9, LSL #1]\n" + "st1h { z31.h }, p0, [x27, x9, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp new file mode 100644 index 0000000000..f90fbc3906 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst.hpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/core/NEON/kernels/arm_gemm/utils.hpp" + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl(const __fp16 *const *const input_ptrs, __fp16 *const *const outptrs, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); +void sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_direct_impl(const unsigned int n_tile_rows, const unsigned int n_tile_cols, const __fp16 *inptr, int64_t ld_input_row, int64_t ld_input_col, __fp16 *outptr, int64_t ld_output_row, int64_t ld_output_col, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); + +class sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst : public DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16> +{ + private: + using Parent = DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16>; + Parent::IndirectKernelType m_indirect_kernel = sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl; + Parent::DirectKernelType m_direct_kernel = sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_direct_impl; + + public: + using return_type = __fp16; + constexpr static auto vl_type = arm_gemm::VLType::SME; + + constexpr static unsigned int kernel_rows = 3; + constexpr static unsigned int kernel_cols = 3; + + constexpr static unsigned int stride_rows = 1; + constexpr static unsigned int stride_cols = 1; + + constexpr static unsigned int output_rows = 3; + constexpr static unsigned int output_cols = 3; + + sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst(const CPUInfo *) + : Parent(output_rows, output_cols, kernel_rows, kernel_cols, stride_rows, stride_cols) {} + + arm_gemm::VLType get_vl_type(void) const override { return vl_type; } + + Parent::IndirectKernelType get_indirect_kernel() const override { return m_indirect_kernel; } + Parent::DirectKernelType get_direct_kernel() const override { return m_direct_kernel; } +}; + +} // namespace depthwise +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_direct.cpp new file mode 100644 index 0000000000..3a7d1cb0b4 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_direct.cpp @@ -0,0 +1,483 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_direct_impl( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + const uint64_t n_tile_rows, n_tile_cols; + const __fp16 *inptr; + const uint64_t ld_input_row; + const uint64_t ld_input_col; + __fp16 *outptr; + const uint64_t ld_output_row; + const uint64_t ld_output_col; + const void *params; + const __fp16 min, max; + + uint64_t tile_i = 0, tile_j = 0; + + Args( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + const float activation_min, + const float activation_max + ) : n_tile_rows(n_tile_rows), n_tile_cols(n_tile_cols), inptr(inptr), + ld_input_row(ld_input_row), ld_input_col(ld_input_col), outptr(outptr), + ld_output_row(ld_output_row), ld_output_col(ld_output_col), + params(params), min(activation_min), max(activation_max) + { + } + }; + + Args params_struct( + n_tile_rows, n_tile_cols, + inptr, ld_input_row, ld_input_col, + outptr, ld_output_row, ld_output_col, + params, activation_min, activation_max + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x2, #0x0\n" + "mov x3, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "1:" // Tile loop + "str x2, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "mov x22, #0x3\n" + "str x3, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" + "ldr x4, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" + "ldr x5, [%x[params_struct], %[offsetof_args_inptr]]\n" + "mul x20, x2, x21\n" // offset = tile_i * ld_input_row + "ldr x6, [%x[params_struct], %[offsetof_args_params]]\n" + "madd x20, x3, x4, x20\n" // offset += tile_j * ld_input_col + "mul x20, x20, x22\n" // offset *= kernel_stride * output_size + "add x7, x4, x4\n" + "add x5, x5, x20, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) + "add x8, x5, x21, LSL #1\n" + "add x17, x7, x4\n" + "add x16, x8, x21, LSL #1\n" + "add x15, x17, x4\n" + "add x14, x16, x21, LSL #1\n" + "add x13, x14, x21, LSL #1\n" + "cbnz x3, 2f\n" + "ldr x9, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "lsl x12, %x[n_channels], #0x1\n" + "mov x28, #0x6\n" + "mul x28, x28, x4\n" + "add x27, x16, x7, LSL #1\n" + "add x26, x5, x15, LSL #1\n" + "add x25, x8, x7, LSL #1\n" + "sub x20, x9, x3\n" + "add x24, x13, x15, LSL #1\n" + "sub x20, x20, #0x1\n" + "add x23, x16, x4, LSL #1\n" + "and x20, x20, #0x3fffff\n" + "add x22, x5, x4, LSL #1\n" + "orr x12, x12, x20, LSL #22\n" + "add x21, x5, x17, LSL #1\n" + "orr x12, x12, x28, LSL #38\n" + "add x20, x16, x17, LSL #1\n" + "add x11, x8, x15, LSL #1\n" + "add x10, x14, x7, LSL #1\n" + "add x9, x14, x15, LSL #1\n" + "add x28, x13, x4, LSL #1\n" + ".inst 0xf8ac4b7a // rprfm pldonce, x12, [x27]\n" + "add x27, x8, x4, LSL #1\n" + ".inst 0xf8ac48ba // rprfm pldonce, x12, [x5]\n" + ".inst 0xf8ac4b5a // rprfm pldonce, x12, [x26]\n" + "add x26, x8, x17, LSL #1\n" + ".inst 0xf8ac49ba // rprfm pldonce, x12, [x13]\n" + ".inst 0xf8ac4b3a // rprfm pldonce, x12, [x25]\n" + "add x25, x13, x17, LSL #1\n" + ".inst 0xf8ac4b1a // rprfm pldonce, x12, [x24]\n" + "add x24, x14, x4, LSL #1\n" + ".inst 0xf8ac4afa // rprfm pldonce, x12, [x23]\n" + "add x23, x5, x7, LSL #1\n" + ".inst 0xf8ac4ada // rprfm pldonce, x12, [x22]\n" + "add x22, x14, x17, LSL #1\n" + ".inst 0xf8ac4aba // rprfm pldonce, x12, [x21]\n" + "add x21, x16, x15, LSL #1\n" + ".inst 0xf8ac4a9a // rprfm pldonce, x12, [x20]\n" + "add x20, x13, x7, LSL #1\n" + ".inst 0xf8ac491a // rprfm pldonce, x12, [x8]\n" + ".inst 0xf8ac497a // rprfm pldonce, x12, [x11]\n" + ".inst 0xf8ac49da // rprfm pldonce, x12, [x14]\n" + ".inst 0xf8ac495a // rprfm pldonce, x12, [x10]\n" + ".inst 0xf8ac493a // rprfm pldonce, x12, [x9]\n" + ".inst 0xf8ac4b9a // rprfm pldonce, x12, [x28]\n" + ".inst 0xf8ac4b7a // rprfm pldonce, x12, [x27]\n" + ".inst 0xf8ac4b5a // rprfm pldonce, x12, [x26]\n" + ".inst 0xf8ac4b3a // rprfm pldonce, x12, [x25]\n" + ".inst 0xf8ac4b1a // rprfm pldonce, x12, [x24]\n" + ".inst 0xf8ac4afa // rprfm pldonce, x12, [x23]\n" + ".inst 0xf8ac4ada // rprfm pldonce, x12, [x22]\n" + ".inst 0xf8ac4a1a // rprfm pldonce, x12, [x16]\n" + ".inst 0xf8ac4aba // rprfm pldonce, x12, [x21]\n" + ".inst 0xf8ac4a9a // rprfm pldonce, x12, [x20]\n" + "2:" // Tile loop: Prefetch input rows: End + "ldr x22, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" + "mov x21, #0x3\n" + "ld1h { z18.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + "ldr x27, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" + "cnth x26\n" + ".inst 0xa040a0c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "ldr x25, [%x[params_struct], %[offsetof_args_outptr]]\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + ".inst 0xa040a0c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "mul x20, x2, x22\n" // offset = tile_i * ld_output_row + "cmp x26, %x[n_channels]\n" + "ld1rh { z17.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "madd x20, x3, x27, x20\n" // offset += tile_j * ld_output_col + "add x24, x27, x27\n" + "ld1rh { z16.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "mul x20, x20, x21\n" // offset *= output_tile_size + "mov x21, #0x0\n" + "ld1h { z8.h }, p3/Z, [x6]\n" + "add x25, x25, x20, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) + "sub x20, XZR, x26\n" + "ld1h { z9.h }, p2/Z, [x16, x7, LSL #1]\n" + "add x23, x25, x22, LSL #1\n" + "ld1h { z10.h }, p2/Z, [x5]\n" + "addvl x6, x6, #1\n" + "add x22, x23, x22, LSL #1\n" + "ld1h { z11.h }, p2/Z, [x5, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x13]\n" + "ld1h { z13.h }, p2/Z, [x8, x7, LSL #1]\n" + "bge 4f\n" + "3:" // Tile loop: Channel loop + "movprfx z24, z18\n fmla z24.h, p3/M, z7.h, z9.h\n" + "movprfx z23, z18\n fmla z23.h, p3/M, z8.h, z9.h\n" + "whilelt p1.h, x26, %x[n_channels]\n" + "inch x21\n" + "movprfx z25, z18\n fmla z25.h, p3/M, z6.h, z9.h\n" + "movprfx z26, z18\n fmla z26.h, p3/M, z5.h, z9.h\n" + "inch x26\n" + "mov p0.b, p2.b\n" + "movprfx z27, z18\n fmla z27.h, p3/M, z4.h, z9.h\n" + "movprfx z28, z18\n fmla z28.h, p3/M, z3.h, z9.h\n" + "inch x20\n" + "movprfx z29, z18\n fmla z29.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z18\n fmla z31.h, p3/M, z0.h, z9.h\n" + "fmla z24.h, p3/M, z4.h, z13.h\n" + "fmla z23.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x16, x17, LSL #1]\n" + "fmla z25.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16, x4, LSL #1]\n" + "fmla z26.h, p3/M, z2.h, z13.h\n" + "fmla z27.h, p3/M, z1.h, z13.h\n" + "fmla z28.h, p3/M, z0.h, z13.h\n" + "fmla z29.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x15, LSL #1]\n" + "movprfx z30, z18\n fmla z30.h, p3/M, z1.h, z9.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "fmla z23.h, p3/M, z5.h, z13.h\n" + "ld1h { z18.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + "fmla z25.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x5, x4, LSL #1]\n" + "fmla z26.h, p3/M, z4.h, z11.h\n" + "fmla z31.h, p3/M, z8.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x5, x17, LSL #1]\n" + "fmla z27.h, p3/M, z3.h, z11.h\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z29.h, p3/M, z1.h, z11.h\n" + "fmla z24.h, p3/M, z0.h, z13.h\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x8]\n" + "fmla z25.h, p3/M, z1.h, z12.h\n" + "fmla z28.h, p3/M, z4.h, z10.h\n" + "fmla z31.h, p3/M, z1.h, z10.h\n" + "fmla z27.h, p3/M, z5.h, z10.h\n" + "fmla z30.h, p3/M, z2.h, z10.h\n" + "fmla z26.h, p3/M, z0.h, z11.h\n" + "fmla z24.h, p3/M, z2.h, z12.h\n" + "fmla z23.h, p3/M, z1.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x8, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x14]\n" + "fmla z25.h, p3/M, z7.h, z10.h\n" + "fmla z28.h, p3/M, z2.h, z13.h\n" + "fmla z24.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x7, LSL #1]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z23.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z26.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x8, x4, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z10.h\n" + "fmla z31.h, p3/M, z3.h, z10.h\n" + "fmla z25.h, p3/M, z5.h, z13.h\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "ld1h { z13.h }, p2/Z, [x13, x4, LSL #1]\n" + "fmla z28.h, p3/M, z6.h, z10.h\n" + "fmla z29.h, p3/M, z5.h, z10.h\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "fmla z24.h, p3/M, z3.h, z12.h\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "fmla z30.h, p3/M, z6.h, z13.h\n" + "fmla z27.h, p3/M, z0.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z11.h\n" + "fmla z29.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x13, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x8, x17, LSL #1]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "addvl x8, x8, #1\n" + "ld1h { z12.h }, p2/Z, [x14, x4, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z13.h\n" + "fmla z31.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x14, x17, LSL #1]\n" + "addvl x14, x14, #1\n" + "fmla z24.h, p3/M, z5.h, z11.h\n" + "fmla z25.h, p3/M, z4.h, z11.h\n" + "fmla z27.h, p3/M, z2.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x5, x7, LSL #1]\n" + "addvl x5, x5, #1\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "fmla z26.h, p3/M, z7.h, z12.h\n" + "ld1h { z10.h }, p1/Z, [x5]\n" + "fmla z30.h, p3/M, z3.h, z12.h\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "fmla z23.h, p3/M, z2.h, z11.h\n" + "fmla z24.h, p3/M, z1.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z12.h\n" + "fmla z25.h, p3/M, z0.h, z11.h\n" + "ld1h { z12.h }, p2/Z, [x16]\n" + "ld1h { z11.h }, p2/Z, [x16, x15, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "addvl x16, x16, #1\n" + "fmla z30.h, p3/M, z5.h, z13.h\n" + "ld1h { z9.h }, p1/Z, [x16, x7, LSL #1]\n" + "fmla z23.h, p3/M, z6.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "fmla z26.h, p3/M, z3.h, z12.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + ".inst 0xa040a0c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "fmla z27.h, p3/M, z8.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x13, x7, LSL #1]\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "whilelt p2.h, x21, %x[n_channels]\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "addvl x13, x13, #1\n" + "cmp x26, %x[n_channels]\n" + "ld1h { z11.h }, p1/Z, [x5, x15, LSL #1]\n" + "fmax z23.h, p3/M, z23.h, z17.h\n" + "ld1h { z12.h }, p1/Z, [x13]\n" + "fmla z29.h, p3/M, z8.h, z13.h\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z6.h, z13.h\n" + ".inst 0xa040a0c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + ".inst 0xc170ca38 // fclamp { z24.h-z27.h }, z17.h, z16.h\n" + "ld1h { z13.h }, p1/Z, [x8, x7, LSL #1]\n" + "ld1h { z8.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + "fmin z23.h, p3/M, z23.h, z16.h\n" + ".inst 0xc170ca3c // fclamp { z28.h-z31.h }, z17.h, z16.h\n" + "st1h { z26.h }, p0, [x23]\n" + "st1h { z27.h }, p0, [x23, x27, LSL #1]\n" + "st1h { z23.h }, p0, [x25]\n" + "st1h { z24.h }, p0, [x25, x27, LSL #1]\n" + "st1h { z25.h }, p0, [x25, x24, LSL #1]\n" + "addvl x25, x25, #1\n" + "st1h { z28.h }, p0, [x23, x24, LSL #1]\n" + "addvl x23, x23, #1\n" + "st1h { z29.h }, p0, [x22]\n" + "st1h { z30.h }, p0, [x22, x27, LSL #1]\n" + "st1h { z31.h }, p0, [x22, x24, LSL #1]\n" + "addvl x22, x22, #1\n" + "blt 3b\n" + "4:" // Tile loop: Channel tail + "movprfx z24, z18\n fmla z24.h, p3/M, z7.h, z9.h\n" + "movprfx z23, z18\n fmla z23.h, p3/M, z8.h, z9.h\n" + "ldr x3, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "mov p0.b, p2.b\n" + "movprfx z25, z18\n fmla z25.h, p3/M, z6.h, z9.h\n" + "movprfx z26, z18\n fmla z26.h, p3/M, z5.h, z9.h\n" + "ldr x2, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "movprfx z27, z18\n fmla z27.h, p3/M, z4.h, z9.h\n" + "movprfx z28, z18\n fmla z28.h, p3/M, z3.h, z9.h\n" + "ldr x9, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "movprfx z29, z18\n fmla z29.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z18\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ldr x21, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" + "add x3, x3, #0x1\n" + "fmla z24.h, p3/M, z4.h, z13.h\n" + "fmla z23.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x16, x17, LSL #1]\n" + "add x20, x2, #0x1\n" + "fmla z25.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16, x4, LSL #1]\n" + "fmla z26.h, p3/M, z2.h, z13.h\n" + "cmp x3, x9\n" + "fmla z27.h, p3/M, z1.h, z13.h\n" + "fmla z28.h, p3/M, z0.h, z13.h\n" + "csel x2, x2, x20, LT\n" + "csel x3, x3, XZR, LT\n" + "fmla z29.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x15, LSL #1]\n" + "movprfx z30, z18\n fmla z30.h, p3/M, z1.h, z9.h\n" + "cmp x2, x21\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "fmla z23.h, p3/M, z5.h, z13.h\n" + "fmla z25.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x5, x4, LSL #1]\n" + "fmla z26.h, p3/M, z4.h, z11.h\n" + "fmla z31.h, p3/M, z8.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x5, x17, LSL #1]\n" + "fmla z27.h, p3/M, z3.h, z11.h\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z29.h, p3/M, z1.h, z11.h\n" + "fmla z24.h, p3/M, z0.h, z13.h\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x8]\n" + "fmla z25.h, p3/M, z1.h, z12.h\n" + "fmla z28.h, p3/M, z4.h, z10.h\n" + "fmla z31.h, p3/M, z1.h, z10.h\n" + "fmla z27.h, p3/M, z5.h, z10.h\n" + "fmla z30.h, p3/M, z2.h, z10.h\n" + "fmla z26.h, p3/M, z0.h, z11.h\n" + "fmla z24.h, p3/M, z2.h, z12.h\n" + "fmla z23.h, p3/M, z1.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x8, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x14]\n" + "fmla z25.h, p3/M, z7.h, z10.h\n" + "fmla z28.h, p3/M, z2.h, z13.h\n" + "fmla z24.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x7, LSL #1]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z23.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z26.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x8, x4, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z10.h\n" + "fmla z31.h, p3/M, z3.h, z10.h\n" + "fmla z25.h, p3/M, z5.h, z13.h\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "ld1h { z13.h }, p2/Z, [x13, x4, LSL #1]\n" + "fmla z28.h, p3/M, z6.h, z10.h\n" + "fmla z29.h, p3/M, z5.h, z10.h\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "fmla z24.h, p3/M, z3.h, z12.h\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "fmla z30.h, p3/M, z6.h, z13.h\n" + "fmla z27.h, p3/M, z0.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z11.h\n" + "fmla z29.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x13, x17, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x8, x17, LSL #1]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x4, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z13.h\n" + "fmla z31.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z24.h, p3/M, z5.h, z11.h\n" + "fmla z25.h, p3/M, z4.h, z11.h\n" + "fmla z27.h, p3/M, z2.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x5, x7, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "fmla z26.h, p3/M, z7.h, z12.h\n" + "fmla z30.h, p3/M, z3.h, z12.h\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "fmla z23.h, p3/M, z2.h, z11.h\n" + "fmla z24.h, p3/M, z1.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z12.h\n" + "fmla z25.h, p3/M, z0.h, z11.h\n" + "ld1h { z12.h }, p2/Z, [x16]\n" + "ld1h { z11.h }, p2/Z, [x16, x15, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z30.h, p3/M, z5.h, z13.h\n" + "fmla z23.h, p3/M, z6.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "fmla z26.h, p3/M, z3.h, z12.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "fmla z27.h, p3/M, z8.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x13, x7, LSL #1]\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "fmax z23.h, p3/M, z23.h, z17.h\n" + "fmla z29.h, p3/M, z8.h, z13.h\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z6.h, z13.h\n" + ".inst 0xc170ca38 // fclamp { z24.h-z27.h }, z17.h, z16.h\n" + "fmin z23.h, p3/M, z23.h, z16.h\n" + ".inst 0xc170ca3c // fclamp { z28.h-z31.h }, z17.h, z16.h\n" + "st1h { z26.h }, p0, [x23]\n" + "st1h { z27.h }, p0, [x23, x27, LSL #1]\n" + "st1h { z23.h }, p0, [x25]\n" + "st1h { z24.h }, p0, [x25, x27, LSL #1]\n" + "st1h { z25.h }, p0, [x25, x24, LSL #1]\n" + "st1h { z28.h }, p0, [x23, x24, LSL #1]\n" + "st1h { z29.h }, p0, [x22]\n" + "st1h { z30.h }, p0, [x22, x27, LSL #1]\n" + "st1h { z31.h }, p0, [x22, x24, LSL #1]\n" + "blt 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp new file mode 100644 index 0000000000..e85cb9e017 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst/generic_indirect.cpp @@ -0,0 +1,444 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output3x3_mla_depthfirst_indirect_impl( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + __fp16 *const *outptrs; + const void *params; + const __fp16 min, max; + const __fp16 *inptrs[25]; + + Args( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *const params, + const __fp16 min, + const __fp16 max + ) : outptrs(outptrs), params(params), min(min), max(max) + { + inptrs[0] = input_ptrs[12]; + inptrs[1] = input_ptrs[0]; + inptrs[2] = input_ptrs[4]; + inptrs[3] = input_ptrs[20]; + inptrs[4] = input_ptrs[7]; + inptrs[5] = input_ptrs[24]; + inptrs[6] = input_ptrs[11]; + inptrs[7] = input_ptrs[1]; + inptrs[8] = input_ptrs[3]; + inptrs[9] = input_ptrs[13]; + inptrs[10] = input_ptrs[5]; + inptrs[11] = input_ptrs[9]; + inptrs[12] = input_ptrs[15]; + inptrs[13] = input_ptrs[17]; + inptrs[14] = input_ptrs[19]; + inptrs[15] = input_ptrs[21]; + inptrs[16] = input_ptrs[6]; + inptrs[17] = input_ptrs[8]; + inptrs[18] = input_ptrs[23]; + inptrs[19] = input_ptrs[16]; + inptrs[20] = input_ptrs[2]; + inptrs[21] = input_ptrs[18]; + inptrs[22] = input_ptrs[10]; + inptrs[23] = input_ptrs[14]; + inptrs[24] = input_ptrs[22]; + + } + }; + + Args params_struct(input_ptrs, outptrs, params, + activation_min, activation_max); + + __asm__ __volatile__( + "ldr x17, [%x[params_struct], %[offsetof_args_params]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "add x16, %x[params_struct], %[offsetof_Args_inptrs]\n" + "mov x15, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "ldp x14, x13, [x16, #0x0]\n" + "ldp x12, x11, [x16, #0x10]\n" + "cnth x10\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + "ld1rh { z18.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "ld1h { z17.h }, p3/Z, [x17]\n" + "addvl x17, x17, #1\n" + "ldr x9, [x16, #0x20]\n" + "cmp x10, %x[n_channels]\n" + ".inst 0xa040a220 // ld1h { z0.h-z3.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "ldr x28, [%x[params_struct], %[offsetof_args_outptrs]]\n" + "sub x27, XZR, x10\n" + ".inst 0xa040a224 // ld1h { z4.h-z7.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "ld1rh { z16.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "ld1h { z8.h }, p3/Z, [x17]\n" + "addvl x17, x17, #1\n" + "ld1h { z9.h }, p2/Z, [x14, x15, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x12, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x9, x15, LSL #1]\n" + "bge 2f\n" + "1:" // Channel loop + "movprfx z23, z17\n fmla z23.h, p3/M, z8.h, z9.h\n" + "movprfx z24, z17\n fmla z24.h, p3/M, z7.h, z9.h\n" + "ldr x26, [x16, #0x30]\n" + "inch x27\n" + "movprfx z25, z17\n fmla z25.h, p3/M, z6.h, z9.h\n" + "movprfx z26, z17\n fmla z26.h, p3/M, z5.h, z9.h\n" + "ldr x25, [x16, #0x38]\n" + "mov p1.b, p2.b\n" + "movprfx z27, z17\n fmla z27.h, p3/M, z4.h, z9.h\n" + "movprfx z28, z17\n fmla z28.h, p3/M, z3.h, z9.h\n" + "ldr x24, [x16, #0x28]\n" + "whilelt p0.h, x10, %x[n_channels]\n" + "movprfx z29, z17\n fmla z29.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z17\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ldr x13, [x16, #0x48]\n" + "fmla z23.h, p3/M, z0.h, z10.h\n" + "fmla z24.h, p3/M, z4.h, z13.h\n" + "ldr x14, [x16, #0x40]\n" + "fmla z25.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z26.h, p3/M, z2.h, z13.h\n" + "ldr x12, [x16, #0x50]\n" + "fmla z27.h, p3/M, z1.h, z13.h\n" + "fmla z28.h, p3/M, z0.h, z13.h\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x11, [x16, #0x58]\n" + "fmla z29.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "movprfx z30, z17\n fmla z30.h, p3/M, z1.h, z9.h\n" + "ldr x9, [x16, #0x60]\n" + "fmla z23.h, p3/M, z5.h, z13.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "ldr x24, [x16, #0x68]\n" + "ld1h { z17.h }, p3/Z, [x17]\n" + "fmla z25.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z26.h, p3/M, z4.h, z11.h\n" + "ldr x26, [x16, #0x70]\n" + "fmla z31.h, p3/M, z8.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z27.h, p3/M, z3.h, z11.h\n" + "ldr x25, [x16, #0x78]\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z28.h, p3/M, z4.h, z10.h\n" + "ldr x14, [x16, #0x80]\n" + "addvl x17, x17, #1\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "fmla z24.h, p3/M, z0.h, z13.h\n" + "ldr x13, [x16, #0x88]\n" + "fmla z29.h, p3/M, z1.h, z11.h\n" + "fmla z25.h, p3/M, z1.h, z12.h\n" + "ld1h { z11.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0x90]\n" + "fmla z27.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z1.h, z10.h\n" + "ldr x23, [x28, #0x0]\n" + "fmla z30.h, p3/M, z2.h, z10.h\n" + "ldr x22, [x28, #0x8]\n" + "fmla z23.h, p3/M, z1.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z24.h, p3/M, z2.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x9, x15, LSL #1]\n" + "fmla z26.h, p3/M, z0.h, z11.h\n" + "ldr x9, [x16, #0xa0]\n" + "fmla z25.h, p3/M, z7.h, z10.h\n" + "ldr x11, [x16, #0x98]\n" + "fmla z28.h, p3/M, z2.h, z13.h\n" + "ldr x21, [x28, #0x10]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z23.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xb0]\n" + "fmla z24.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z26.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldr x24, [x16, #0xa8]\n" + "fmla z25.h, p3/M, z5.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0xb8]\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "fmla z28.h, p3/M, z6.h, z10.h\n" + "fmla z30.h, p3/M, z4.h, z10.h\n" + "fmla z29.h, p3/M, z5.h, z10.h\n" + "ldr x14, [x16, #0xc0]\n" + "fmla z31.h, p3/M, z3.h, z10.h\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "ldr x20, [x28, #0x18]\n" + "fmla z24.h, p3/M, z3.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z11.h\n" + "fmla z27.h, p3/M, z0.h, z12.h\n" + "fmla z30.h, p3/M, z6.h, z13.h\n" + "fmla z29.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x12, x15, LSL #1]\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z24.h, p3/M, z5.h, z11.h\n" + "fmla z25.h, p3/M, z4.h, z11.h\n" + "fmla z27.h, p3/M, z2.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x9, x15, LSL #1]\n" + "ldr x9, [x16, #0x20]\n" + "fmla z30.h, p3/M, z8.h, z13.h\n" + "fmla z26.h, p3/M, z7.h, z12.h\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "fmla z31.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z23.h, p3/M, z2.h, z11.h\n" + "fmla z24.h, p3/M, z1.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z12.h\n" + "fmla z25.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z30.h, p3/M, z3.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "fmla z23.h, p3/M, z6.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "fmla z27.h, p3/M, z8.h, z13.h\n" + "fmla z26.h, p3/M, z3.h, z12.h\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "fmla z30.h, p3/M, z5.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldp x14, x13, [x16, #0x0]\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "fmax z23.h, p3/M, z23.h, z18.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ldp x12, x11, [x16, #0x10]\n" + "inch x15\n" + ".inst 0xa040a220 // ld1h { z0.h-z3.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "whilelt p2.h, x15, %x[n_channels]\n" + "fmla z29.h, p3/M, z8.h, z13.h\n" + ".inst 0xc170ca58 // fclamp { z24.h-z27.h }, z18.h, z16.h\n" + "ld1h { z9.h }, p0/Z, [x14, x10, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "ld1h { z10.h }, p0/Z, [x13, x10, LSL #1]\n" + "fmin z23.h, p3/M, z23.h, z16.h\n" + "fmla z31.h, p3/M, z6.h, z13.h\n" + "ld1h { z11.h }, p0/Z, [x12, x10, LSL #1]\n" + "ld1h { z12.h }, p0/Z, [x11, x10, LSL #1]\n" + "st1h { z24.h }, p1, [x22, x27, LSL #1]\n" + "ldr x22, [x28, #0x28]\n" + "st1h { z25.h }, p1, [x21, x27, LSL #1]\n" + "ldr x21, [x28, #0x30]\n" + "ld1h { z13.h }, p0/Z, [x9, x10, LSL #1]\n" + "inch x10\n" + "st1h { z23.h }, p1, [x23, x27, LSL #1]\n" + "ldr x23, [x28, #0x20]\n" + ".inst 0xa040a224 // ld1h { z4.h-z7.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "st1h { z26.h }, p1, [x20, x27, LSL #1]\n" + "ldr x20, [x28, #0x38]\n" + "cmp x10, %x[n_channels]\n" + ".inst 0xc170ca5c // fclamp { z28.h-z31.h }, z18.h, z16.h\n" + "ld1h { z8.h }, p3/Z, [x17]\n" + "addvl x17, x17, #1\n" + "st1h { z27.h }, p1, [x23, x27, LSL #1]\n" + "ldr x23, [x28, #0x40]\n" + "st1h { z28.h }, p1, [x22, x27, LSL #1]\n" + "st1h { z29.h }, p1, [x21, x27, LSL #1]\n" + "st1h { z30.h }, p1, [x20, x27, LSL #1]\n" + "st1h { z31.h }, p1, [x23, x27, LSL #1]\n" + "blt 1b\n" + "2:" // Channel tail + "movprfx z23, z17\n fmla z23.h, p3/M, z8.h, z9.h\n" + "movprfx z24, z17\n fmla z24.h, p3/M, z7.h, z9.h\n" + "ldr x26, [x16, #0x30]\n" + "inch x27\n" + "movprfx z25, z17\n fmla z25.h, p3/M, z6.h, z9.h\n" + "movprfx z26, z17\n fmla z26.h, p3/M, z5.h, z9.h\n" + "ldr x25, [x16, #0x38]\n" + "mov p1.b, p2.b\n" + "movprfx z27, z17\n fmla z27.h, p3/M, z4.h, z9.h\n" + "movprfx z28, z17\n fmla z28.h, p3/M, z3.h, z9.h\n" + "ldr x24, [x16, #0x28]\n" + "movprfx z29, z17\n fmla z29.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z17\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ldr x13, [x16, #0x48]\n" + "fmla z23.h, p3/M, z0.h, z10.h\n" + "fmla z24.h, p3/M, z4.h, z13.h\n" + "ldr x14, [x16, #0x40]\n" + "fmla z25.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z26.h, p3/M, z2.h, z13.h\n" + "ldr x12, [x16, #0x50]\n" + "fmla z27.h, p3/M, z1.h, z13.h\n" + "fmla z28.h, p3/M, z0.h, z13.h\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x11, [x16, #0x58]\n" + "fmla z29.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "movprfx z30, z17\n fmla z30.h, p3/M, z1.h, z9.h\n" + "ldr x9, [x16, #0x60]\n" + "fmla z23.h, p3/M, z5.h, z13.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "ldr x24, [x16, #0x68]\n" + "fmla z25.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z26.h, p3/M, z4.h, z11.h\n" + "ldr x26, [x16, #0x70]\n" + "fmla z31.h, p3/M, z8.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z27.h, p3/M, z3.h, z11.h\n" + "ldr x25, [x16, #0x78]\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "fmla z28.h, p3/M, z4.h, z10.h\n" + "ldr x14, [x16, #0x80]\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "fmla z24.h, p3/M, z0.h, z13.h\n" + "ldr x13, [x16, #0x88]\n" + "fmla z29.h, p3/M, z1.h, z11.h\n" + "fmla z25.h, p3/M, z1.h, z12.h\n" + "ld1h { z11.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0x90]\n" + "fmla z27.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z1.h, z10.h\n" + "ldr x23, [x28, #0x0]\n" + "fmla z30.h, p3/M, z2.h, z10.h\n" + "ldr x22, [x28, #0x8]\n" + "fmla z23.h, p3/M, z1.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z24.h, p3/M, z2.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x9, x15, LSL #1]\n" + "fmla z26.h, p3/M, z0.h, z11.h\n" + "ldr x9, [x16, #0xa0]\n" + "fmla z25.h, p3/M, z7.h, z10.h\n" + "ldr x11, [x16, #0x98]\n" + "fmla z28.h, p3/M, z2.h, z13.h\n" + "ldr x21, [x28, #0x10]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z23.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xb0]\n" + "fmla z24.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z26.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldr x24, [x16, #0xa8]\n" + "fmla z25.h, p3/M, z5.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0xb8]\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "fmla z28.h, p3/M, z6.h, z10.h\n" + "fmla z30.h, p3/M, z4.h, z10.h\n" + "fmla z29.h, p3/M, z5.h, z10.h\n" + "ldr x14, [x16, #0xc0]\n" + "fmla z31.h, p3/M, z3.h, z10.h\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "ldr x20, [x28, #0x18]\n" + "fmla z24.h, p3/M, z3.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z28.h, p3/M, z8.h, z11.h\n" + "fmla z27.h, p3/M, z0.h, z12.h\n" + "fmla z30.h, p3/M, z6.h, z13.h\n" + "fmla z29.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x12, x15, LSL #1]\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z24.h, p3/M, z5.h, z11.h\n" + "fmla z25.h, p3/M, z4.h, z11.h\n" + "fmla z27.h, p3/M, z2.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x9, x15, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z13.h\n" + "fmla z26.h, p3/M, z7.h, z12.h\n" + "fmla z29.h, p3/M, z4.h, z12.h\n" + "fmla z31.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z23.h, p3/M, z2.h, z11.h\n" + "fmla z24.h, p3/M, z1.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z12.h\n" + "fmla z25.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z30.h, p3/M, z3.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "fmla z23.h, p3/M, z6.h, z12.h\n" + "fmla z29.h, p3/M, z0.h, z12.h\n" + "fmla z27.h, p3/M, z8.h, z13.h\n" + "fmla z26.h, p3/M, z3.h, z12.h\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "fmla z30.h, p3/M, z5.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "fmax z23.h, p3/M, z23.h, z18.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "fmla z29.h, p3/M, z8.h, z13.h\n" + ".inst 0xc170ca58 // fclamp { z24.h-z27.h }, z18.h, z16.h\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "fmin z23.h, p3/M, z23.h, z16.h\n" + "fmla z31.h, p3/M, z6.h, z13.h\n" + "st1h { z24.h }, p1, [x22, x27, LSL #1]\n" + "ldr x22, [x28, #0x28]\n" + "st1h { z25.h }, p1, [x21, x27, LSL #1]\n" + "ldr x21, [x28, #0x30]\n" + "st1h { z26.h }, p1, [x20, x27, LSL #1]\n" + "ldr x20, [x28, #0x38]\n" + "st1h { z23.h }, p1, [x23, x27, LSL #1]\n" + "ldr x23, [x28, #0x20]\n" + ".inst 0xc170ca5c // fclamp { z28.h-z31.h }, z18.h, z16.h\n" + "st1h { z27.h }, p1, [x23, x27, LSL #1]\n" + "ldr x23, [x28, #0x40]\n" + "st1h { z28.h }, p1, [x22, x27, LSL #1]\n" + "st1h { z29.h }, p1, [x21, x27, LSL #1]\n" + "st1h { z30.h }, p1, [x20, x27, LSL #1]\n" + "st1h { z31.h }, p1, [x23, x27, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp new file mode 100644 index 0000000000..6b75d12295 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst.hpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/core/NEON/kernels/arm_gemm/utils.hpp" + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst_indirect_impl(const __fp16 *const *const input_ptrs, __fp16 *const *const outptrs, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); +void sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst_direct_impl(const unsigned int n_tile_rows, const unsigned int n_tile_cols, const __fp16 *inptr, int64_t ld_input_row, int64_t ld_input_col, __fp16 *outptr, int64_t ld_output_row, int64_t ld_output_col, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); + +class sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst : public DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16> +{ + private: + using Parent = DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16>; + Parent::IndirectKernelType m_indirect_kernel = sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst_indirect_impl; + Parent::DirectKernelType m_direct_kernel = sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst_direct_impl; + + public: + using return_type = __fp16; + constexpr static auto vl_type = arm_gemm::VLType::SME; + + constexpr static unsigned int kernel_rows = 3; + constexpr static unsigned int kernel_cols = 3; + + constexpr static unsigned int stride_rows = 1; + constexpr static unsigned int stride_cols = 1; + + constexpr static unsigned int output_rows = 4; + constexpr static unsigned int output_cols = 4; + + sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst(const CPUInfo *) + : Parent(output_rows, output_cols, kernel_rows, kernel_cols, stride_rows, stride_cols) {} + + arm_gemm::VLType get_vl_type(void) const override { return vl_type; } + + Parent::IndirectKernelType get_indirect_kernel() const override { return m_indirect_kernel; } + Parent::DirectKernelType get_direct_kernel() const override { return m_direct_kernel; } +}; + +} // namespace depthwise +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_direct.cpp new file mode 100644 index 0000000000..37a9febf47 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_direct.cpp @@ -0,0 +1,672 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst_direct_impl( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + const uint64_t n_tile_rows, n_tile_cols; + const __fp16 *inptr; + const uint64_t ld_input_row; + const uint64_t ld_input_col; + __fp16 *outptr; + const uint64_t ld_output_row; + const uint64_t ld_output_col; + const void *params; + const __fp16 min, max; + + uint64_t tile_i = 0, tile_j = 0; + + Args( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + const float activation_min, + const float activation_max + ) : n_tile_rows(n_tile_rows), n_tile_cols(n_tile_cols), inptr(inptr), + ld_input_row(ld_input_row), ld_input_col(ld_input_col), outptr(outptr), + ld_output_row(ld_output_row), ld_output_col(ld_output_col), + params(params), min(activation_min), max(activation_max) + { + } + }; + + Args params_struct( + n_tile_rows, n_tile_cols, + inptr, ld_input_row, ld_input_col, + outptr, ld_output_row, ld_output_col, + params, activation_min, activation_max + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x1, #0x0\n" + "mov x2, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "1:" // Tile loop + "str x1, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "mov x22, #0x4\n" + "str x2, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" + "ldr x3, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" + "ldr x4, [%x[params_struct], %[offsetof_args_inptr]]\n" + "mul x20, x1, x21\n" // offset = tile_i * ld_input_row + "ldr x5, [%x[params_struct], %[offsetof_args_params]]\n" + "madd x20, x2, x3, x20\n" // offset += tile_j * ld_input_col + "mul x20, x20, x22\n" // offset *= kernel_stride * output_size + "add x6, x3, x3\n" + "add x4, x4, x20, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) + "add x7, x4, x21, LSL #1\n" + "add x8, x6, x3\n" + "add x17, x7, x21, LSL #1\n" + "add x16, x8, x3\n" + "add x15, x17, x21, LSL #1\n" + "add x14, x16, x3\n" + "add x13, x15, x21, LSL #1\n" + "add x12, x13, x21, LSL #1\n" + "cbnz x2, 2f\n" + "ldr x11, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "lsl x10, %x[n_channels], #0x1\n" + "mov x21, #0x8\n" + "mul x21, x21, x3\n" + "add x9, x17, x6, LSL #1\n" + "add x28, x4, x14, LSL #1\n" + "add x27, x17, x8, LSL #1\n" + "sub x20, x11, x2\n" + "add x26, x12, x14, LSL #1\n" + "sub x20, x20, #0x1\n" + "add x25, x15, x6, LSL #1\n" + "and x20, x20, #0x3fffff\n" + "add x24, x4, x3, LSL #1\n" + "orr x10, x10, x20, LSL #22\n" + "add x23, x4, x16, LSL #1\n" + "orr x10, x10, x21, LSL #38\n" + "add x22, x15, x8, LSL #1\n" + "add x21, x7, x14, LSL #1\n" + "add x20, x7, x6, LSL #1\n" + ".inst 0xf8aa493a // rprfm pldonce, x10, [x9]\n" + "add x9, x13, x14, LSL #1\n" + ".inst 0xf8aa489a // rprfm pldonce, x10, [x4]\n" + ".inst 0xf8aa4b9a // rprfm pldonce, x10, [x28]\n" + "add x28, x7, x8, LSL #1\n" + ".inst 0xf8aa4b7a // rprfm pldonce, x10, [x27]\n" + "add x27, x12, x3, LSL #1\n" + ".inst 0xf8aa499a // rprfm pldonce, x10, [x12]\n" + ".inst 0xf8aa4b5a // rprfm pldonce, x10, [x26]\n" + "add x26, x17, x3, LSL #1\n" + ".inst 0xf8aa4b3a // rprfm pldonce, x10, [x25]\n" + "add x25, x12, x16, LSL #1\n" + ".inst 0xf8aa4b1a // rprfm pldonce, x10, [x24]\n" + "add x24, x17, x16, LSL #1\n" + ".inst 0xf8aa4afa // rprfm pldonce, x10, [x23]\n" + "add x23, x4, x6, LSL #1\n" + ".inst 0xf8aa4ada // rprfm pldonce, x10, [x22]\n" + "add x22, x15, x3, LSL #1\n" + ".inst 0xf8aa48fa // rprfm pldonce, x10, [x7]\n" + ".inst 0xf8aa4aba // rprfm pldonce, x10, [x21]\n" + "add x21, x4, x8, LSL #1\n" + ".inst 0xf8aa49ba // rprfm pldonce, x10, [x13]\n" + ".inst 0xf8aa4a9a // rprfm pldonce, x10, [x20]\n" + "add x20, x15, x16, LSL #1\n" + ".inst 0xf8aa493a // rprfm pldonce, x10, [x9]\n" + "add x9, x17, x14, LSL #1\n" + ".inst 0xf8aa4b9a // rprfm pldonce, x10, [x28]\n" + "add x28, x13, x6, LSL #1\n" + ".inst 0xf8aa4b7a // rprfm pldonce, x10, [x27]\n" + "add x27, x15, x14, LSL #1\n" + ".inst 0xf8aa4b5a // rprfm pldonce, x10, [x26]\n" + "add x26, x12, x6, LSL #1\n" + ".inst 0xf8aa4b3a // rprfm pldonce, x10, [x25]\n" + "add x25, x13, x8, LSL #1\n" + ".inst 0xf8aa4b1a // rprfm pldonce, x10, [x24]\n" + "add x24, x12, x8, LSL #1\n" + ".inst 0xf8aa4afa // rprfm pldonce, x10, [x23]\n" + "add x23, x7, x3, LSL #1\n" + ".inst 0xf8aa4ada // rprfm pldonce, x10, [x22]\n" + "add x22, x7, x16, LSL #1\n" + ".inst 0xf8aa4aba // rprfm pldonce, x10, [x21]\n" + "add x21, x13, x3, LSL #1\n" + ".inst 0xf8aa4a3a // rprfm pldonce, x10, [x17]\n" + ".inst 0xf8aa4a9a // rprfm pldonce, x10, [x20]\n" + "add x20, x13, x16, LSL #1\n" + ".inst 0xf8aa493a // rprfm pldonce, x10, [x9]\n" + ".inst 0xf8aa49fa // rprfm pldonce, x10, [x15]\n" + ".inst 0xf8aa4b9a // rprfm pldonce, x10, [x28]\n" + ".inst 0xf8aa4b7a // rprfm pldonce, x10, [x27]\n" + ".inst 0xf8aa4b5a // rprfm pldonce, x10, [x26]\n" + ".inst 0xf8aa4b3a // rprfm pldonce, x10, [x25]\n" + ".inst 0xf8aa4b1a // rprfm pldonce, x10, [x24]\n" + ".inst 0xf8aa4afa // rprfm pldonce, x10, [x23]\n" + ".inst 0xf8aa4ada // rprfm pldonce, x10, [x22]\n" + ".inst 0xf8aa4aba // rprfm pldonce, x10, [x21]\n" + ".inst 0xf8aa4a9a // rprfm pldonce, x10, [x20]\n" + "2:" // Tile loop: Prefetch input rows: End + "ldr x22, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" + "mov x21, #0x4\n" + "ld1h { z15.h }, p3/Z, [x5]\n" + "addvl x5, x5, #1\n" + "ldr x9, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" + "cnth x28\n" + ".inst 0xa040a0a0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x5]\n" + "addvl x5, x5, #4\n" + "ldr x27, [%x[params_struct], %[offsetof_args_outptr]]\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + ".inst 0xa040a0a4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x5]\n" + "addvl x5, x5, #4\n" + "mul x20, x1, x22\n" // offset = tile_i * ld_output_row + "cmp x28, %x[n_channels]\n" + "ld1rh { z14.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "madd x20, x2, x9, x20\n" // offset += tile_j * ld_output_col + "add x26, x9, x9\n" + "ld1rh { z13.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "mul x20, x20, x21\n" // offset *= output_tile_size + "add x25, x26, x9\n" + "ld1h { z8.h }, p3/Z, [x5]\n" + "add x27, x27, x20, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) + "mov x21, #0x0\n" + "ld1h { z9.h }, p2/Z, [x17, x6, LSL #1]\n" + "add x24, x27, x22, LSL #1\n" + "sub x20, XZR, x28\n" + "ld1h { z10.h }, p2/Z, [x4]\n" + "add x23, x24, x22, LSL #1\n" + "ld1h { z11.h }, p2/Z, [x4, x14, LSL #1]\n" + "addvl x5, x5, #1\n" + "add x22, x23, x22, LSL #1\n" + "ld1h { z12.h }, p2/Z, [x17, x8, LSL #1]\n" + "bge 4f\n" + "3:" // Tile loop: Channel loop + "movprfx z21, z15\n fmla z21.h, p3/M, z4.h, z9.h\n" + "movprfx z16, z15\n fmla z16.h, p3/M, z8.h, z9.h\n" + "whilelt p1.h, x28, %x[n_channels]\n" + "inch x21\n" + "movprfx z22, z15\n fmla z22.h, p3/M, z3.h, z9.h\n" + "movprfx z25, z15\n fmla z25.h, p3/M, z1.h, z9.h\n" + "inch x28\n" + "mov p0.b, p2.b\n" + "movprfx z26, z15\n fmla z26.h, p3/M, z0.h, z9.h\n" + "movprfx z17, z15\n fmla z17.h, p3/M, z7.h, z9.h\n" + "inch x20\n" + "movprfx z18, z15\n fmla z18.h, p3/M, z6.h, z9.h\n" + "movprfx z20, z15\n fmla z20.h, p3/M, z5.h, z9.h\n" + "fmla z21.h, p3/M, z5.h, z12.h\n" + "movprfx z24, z15\n fmla z24.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x15, x6, LSL #1]\n" + "fmla z16.h, p3/M, z0.h, z10.h\n" + "movprfx z19, z15\n fmla z19.h, p3/M, z2.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x12]\n" + "fmla z22.h, p3/M, z4.h, z12.h\n" + "fmla z25.h, p3/M, z2.h, z12.h\n" + "ld1h { z11.h }, p2/Z, [x12, x14, LSL #1]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "fmla z17.h, p3/M, z8.h, z12.h\n" + "movprfx z28, z15\n fmla z28.h, p3/M, z6.h, z10.h\n" + "fmla z21.h, p3/M, z7.h, z9.h\n" + "ld1h { z10.h }, p2/Z, [x15, x8, LSL #1]\n" + "fmla z18.h, p3/M, z7.h, z12.h\n" + "fmla z19.h, p3/M, z6.h, z12.h\n" + "movprfx z23, z15\n fmla z23.h, p3/M, z3.h, z12.h\n" + "movprfx z27, z15\n fmla z27.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x4, x3, LSL #1]\n" + "movprfx z31, z15\n fmla z31.h, p3/M, z8.h, z11.h\n" + "fmla z22.h, p3/M, z6.h, z9.h\n" + "ld1h { z11.h }, p2/Z, [x4, x16, LSL #1]\n" + "fmla z25.h, p3/M, z4.h, z9.h\n" + "fmla z26.h, p3/M, z3.h, z9.h\n" + "movprfx z29, z15\n fmla z29.h, p3/M, z1.h, z9.h\n" + "movprfx z30, z15\n fmla z30.h, p3/M, z0.h, z9.h\n" + "ld1h { z15.h }, p3/Z, [x5]\n" + "addvl x5, x5, #1\n" + "fmla z20.h, p3/M, z8.h, z9.h\n" + "fmla z24.h, p3/M, z5.h, z9.h\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z21.h, p3/M, z8.h, z10.h\n" + "ld1h { z9.h }, p2/Z, [x7]\n" + "fmla z16.h, p3/M, z1.h, z12.h\n" + "fmla z17.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x7, x14, LSL #1]\n" + "fmla z18.h, p3/M, z2.h, z11.h\n" + "fmla z19.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13]\n" + "fmla z22.h, p3/M, z7.h, z10.h\n" + "fmla z23.h, p3/M, z6.h, z10.h\n" + "fmla z25.h, p3/M, z5.h, z10.h\n" + "fmla z26.h, p3/M, z4.h, z10.h\n" + "fmla z27.h, p3/M, z3.h, z10.h\n" + "fmla z29.h, p3/M, z2.h, z10.h\n" + "fmla z30.h, p3/M, z1.h, z10.h\n" + "fmla z31.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x7, x6, LSL #1]\n" + "fmla z20.h, p3/M, z0.h, z9.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x14, LSL #1]\n" + "fmla z16.h, p3/M, z3.h, z9.h\n" + "fmla z21.h, p3/M, z1.h, z10.h\n" + "fmla z19.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z2.h, z12.h\n" + "fmla z17.h, p3/M, z4.h, z10.h\n" + "ld1h { z12.h }, p2/Z, [x7, x8, LSL #1]\n" + "fmla z18.h, p3/M, z3.h, z10.h\n" + "fmla z22.h, p3/M, z0.h, z10.h\n" + "fmla z27.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x12, x3, LSL #1]\n" + "fmla z20.h, p3/M, z2.h, z10.h\n" + "fmla z21.h, p3/M, z2.h, z12.h\n" + "fmla z16.h, p3/M, z5.h, z10.h\n" + "fmla z17.h, p3/M, z5.h, z12.h\n" + "ld1h { z10.h }, p2/Z, [x17, x3, LSL #1]\n" + "fmla z18.h, p3/M, z4.h, z12.h\n" + "fmla z19.h, p3/M, z3.h, z12.h\n" + "fmla z22.h, p3/M, z1.h, z12.h\n" + "fmla z23.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x17, x16, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z11.h\n" + "fmla z29.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x12, x16, LSL #1]\n" + "fmla z20.h, p3/M, z4.h, z10.h\n" + "fmla z21.h, p3/M, z3.h, z10.h\n" + "fmla z24.h, p3/M, z1.h, z10.h\n" + "fmla z25.h, p3/M, z0.h, z10.h\n" + "fmla z16.h, p3/M, z7.h, z10.h\n" + "fmla z17.h, p3/M, z6.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x4, x6, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z7.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x15, x3, LSL #1]\n" + "fmla z18.h, p3/M, z8.h, z12.h\n" + "fmla z19.h, p3/M, z7.h, z12.h\n" + "fmla z22.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z26.h, p3/M, z2.h, z12.h\n" + "fmla z27.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x4, x8, LSL #1]\n" + "addvl x4, x4, #1\n" + "fmla z20.h, p3/M, z7.h, z11.h\n" + "fmla z21.h, p3/M, z6.h, z11.h\n" + "fmla z24.h, p3/M, z4.h, z11.h\n" + "fmla z25.h, p3/M, z3.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "fmla z29.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x15, x16, LSL #1]\n" + "fmla z16.h, p3/M, z2.h, z10.h\n" + "fmla z17.h, p3/M, z1.h, z10.h\n" + "fmla z18.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x17]\n" + "fmla z19.h, p3/M, z0.h, z12.h\n" + "fmla z30.h, p3/M, z2.h, z11.h\n" + "fmla z22.h, p3/M, z8.h, z11.h\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "fmla z26.h, p3/M, z5.h, z11.h\n" + "fmla z20.h, p3/M, z3.h, z10.h\n" + "fmla z24.h, p3/M, z0.h, z10.h\n" + "fmla z27.h, p3/M, z4.h, z11.h\n" + "fmla z31.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x6, LSL #1]\n" + "fmla z17.h, p3/M, z2.h, z12.h\n" + "fmla z18.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x17, x14, LSL #1]\n" + "addvl x17, x17, #1\n" + "fmla z16.h, p3/M, z6.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x15]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z25.h, p3/M, z7.h, z11.h\n" + "ld1h { z9.h }, p1/Z, [x17, x6, LSL #1]\n" + "fmla z19.h, p3/M, z8.h, z12.h\n" + "fmla z23.h, p3/M, z5.h, z12.h\n" + "fmla z27.h, p3/M, z2.h, z12.h\n" + "fmla z20.h, p3/M, z6.h, z10.h\n" + "ld1h { z12.h }, p2/Z, [x15, x14, LSL #1]\n" + "addvl x15, x15, #1\n" + "fmla z24.h, p3/M, z3.h, z10.h\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x12, x6, LSL #1]\n" + "fmla z26.h, p3/M, z6.h, z11.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z23.h, p3/M, z8.h, z12.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "fmla z30.h, p3/M, z6.h, z10.h\n" + "fmla z27.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x12, x8, LSL #1]\n" + "addvl x12, x12, #1\n" + "fmla z24.h, p3/M, z8.h, z11.h\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x8, LSL #1]\n" + "fmla z29.h, p3/M, z5.h, z11.h\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z11.h\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "fmla z26.h, p3/M, z7.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x7, x16, LSL #1]\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x7, x3, LSL #1]\n" + "addvl x7, x7, #1\n" + "fmla z29.h, p3/M, z8.h, z12.h\n" + "fmla z30.h, p3/M, z7.h, z12.h\n" + "fmla z31.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x3, LSL #1]\n" + "fmla z18.h, p3/M, z5.h, z11.h\n" + "fmla z19.h, p3/M, z4.h, z11.h\n" + "fmla z16.h, p3/M, z4.h, z10.h\n" + "fmla z17.h, p3/M, z3.h, z10.h\n" + "fmla z20.h, p3/M, z1.h, z10.h\n" + "fmla z21.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x13, x16, LSL #1]\n" + "whilelt p2.h, x21, %x[n_channels]\n" + "fmla z22.h, p3/M, z2.h, z11.h\n" + "fmla z23.h, p3/M, z1.h, z11.h\n" + "cmp x28, %x[n_channels]\n" + "addvl x13, x13, #1\n" + "fmla z24.h, p3/M, z7.h, z12.h\n" + "fmla z25.h, p3/M, z6.h, z12.h\n" + "ld1h { z11.h }, p1/Z, [x4, x14, LSL #1]\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + ".inst 0xa040a0a0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x5]\n" + "addvl x5, x5, #4\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "ld1h { z12.h }, p1/Z, [x17, x8, LSL #1]\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + ".inst 0xa040a0a4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x5]\n" + "addvl x5, x5, #4\n" + ".inst 0xc16dc9d0 // fclamp { z16.h-z19.h }, z14.h, z13.h\n" + ".inst 0xc16dc9d4 // fclamp { z20.h-z23.h }, z14.h, z13.h\n" + "ld1h { z10.h }, p1/Z, [x4]\n" + "ld1h { z8.h }, p3/Z, [x5]\n" + "addvl x5, x5, #1\n" + ".inst 0xc16dc9d8 // fclamp { z24.h-z27.h }, z14.h, z13.h\n" + ".inst 0xc16dc9dc // fclamp { z28.h-z31.h }, z14.h, z13.h\n" + "st1h { z16.h }, p0, [x27]\n" + "st1h { z17.h }, p0, [x27, x9, LSL #1]\n" + "st1h { z18.h }, p0, [x27, x26, LSL #1]\n" + "st1h { z19.h }, p0, [x27, x25, LSL #1]\n" + "addvl x27, x27, #1\n" + "st1h { z20.h }, p0, [x24]\n" + "st1h { z21.h }, p0, [x24, x9, LSL #1]\n" + "st1h { z22.h }, p0, [x24, x26, LSL #1]\n" + "st1h { z23.h }, p0, [x24, x25, LSL #1]\n" + "addvl x24, x24, #1\n" + "st1h { z24.h }, p0, [x23]\n" + "st1h { z25.h }, p0, [x23, x9, LSL #1]\n" + "st1h { z26.h }, p0, [x23, x26, LSL #1]\n" + "st1h { z27.h }, p0, [x23, x25, LSL #1]\n" + "addvl x23, x23, #1\n" + "st1h { z28.h }, p0, [x22]\n" + "st1h { z29.h }, p0, [x22, x9, LSL #1]\n" + "st1h { z30.h }, p0, [x22, x26, LSL #1]\n" + "st1h { z31.h }, p0, [x22, x25, LSL #1]\n" + "addvl x22, x22, #1\n" + "blt 3b\n" + "4:" // Tile loop: Channel tail + "movprfx z21, z15\n fmla z21.h, p3/M, z4.h, z9.h\n" + "movprfx z16, z15\n fmla z16.h, p3/M, z8.h, z9.h\n" + "ldr x2, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "mov p0.b, p2.b\n" + "movprfx z22, z15\n fmla z22.h, p3/M, z3.h, z9.h\n" + "movprfx z25, z15\n fmla z25.h, p3/M, z1.h, z9.h\n" + "ldr x1, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "movprfx z26, z15\n fmla z26.h, p3/M, z0.h, z9.h\n" + "movprfx z17, z15\n fmla z17.h, p3/M, z7.h, z9.h\n" + "ldr x11, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "movprfx z18, z15\n fmla z18.h, p3/M, z6.h, z9.h\n" + "movprfx z20, z15\n fmla z20.h, p3/M, z5.h, z9.h\n" + "ldr x21, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" + "add x2, x2, #0x1\n" + "fmla z21.h, p3/M, z5.h, z12.h\n" + "movprfx z24, z15\n fmla z24.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x15, x6, LSL #1]\n" + "add x20, x1, #0x1\n" + "fmla z16.h, p3/M, z0.h, z10.h\n" + "movprfx z19, z15\n fmla z19.h, p3/M, z2.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x12]\n" + "cmp x2, x11\n" + "fmla z22.h, p3/M, z4.h, z12.h\n" + "fmla z25.h, p3/M, z2.h, z12.h\n" + "ld1h { z11.h }, p2/Z, [x12, x14, LSL #1]\n" + "csel x1, x1, x20, LT\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "fmla z17.h, p3/M, z8.h, z12.h\n" + "csel x2, x2, XZR, LT\n" + "cmp x1, x21\n" + "movprfx z28, z15\n fmla z28.h, p3/M, z6.h, z10.h\n" + "fmla z21.h, p3/M, z7.h, z9.h\n" + "ld1h { z10.h }, p2/Z, [x15, x8, LSL #1]\n" + "fmla z18.h, p3/M, z7.h, z12.h\n" + "fmla z19.h, p3/M, z6.h, z12.h\n" + "movprfx z23, z15\n fmla z23.h, p3/M, z3.h, z12.h\n" + "movprfx z27, z15\n fmla z27.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x4, x3, LSL #1]\n" + "movprfx z31, z15\n fmla z31.h, p3/M, z8.h, z11.h\n" + "fmla z22.h, p3/M, z6.h, z9.h\n" + "ld1h { z11.h }, p2/Z, [x4, x16, LSL #1]\n" + "fmla z25.h, p3/M, z4.h, z9.h\n" + "fmla z26.h, p3/M, z3.h, z9.h\n" + "movprfx z29, z15\n fmla z29.h, p3/M, z1.h, z9.h\n" + "movprfx z30, z15\n fmla z30.h, p3/M, z0.h, z9.h\n" + "fmla z20.h, p3/M, z8.h, z9.h\n" + "fmla z24.h, p3/M, z5.h, z9.h\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z21.h, p3/M, z8.h, z10.h\n" + "ld1h { z9.h }, p2/Z, [x7]\n" + "fmla z16.h, p3/M, z1.h, z12.h\n" + "fmla z17.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x7, x14, LSL #1]\n" + "fmla z18.h, p3/M, z2.h, z11.h\n" + "fmla z19.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13]\n" + "fmla z22.h, p3/M, z7.h, z10.h\n" + "fmla z23.h, p3/M, z6.h, z10.h\n" + "fmla z25.h, p3/M, z5.h, z10.h\n" + "fmla z26.h, p3/M, z4.h, z10.h\n" + "fmla z27.h, p3/M, z3.h, z10.h\n" + "fmla z29.h, p3/M, z2.h, z10.h\n" + "fmla z30.h, p3/M, z1.h, z10.h\n" + "fmla z31.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x7, x6, LSL #1]\n" + "fmla z20.h, p3/M, z0.h, z9.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x14, LSL #1]\n" + "fmla z16.h, p3/M, z3.h, z9.h\n" + "fmla z21.h, p3/M, z1.h, z10.h\n" + "fmla z19.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z2.h, z12.h\n" + "fmla z17.h, p3/M, z4.h, z10.h\n" + "ld1h { z12.h }, p2/Z, [x7, x8, LSL #1]\n" + "fmla z18.h, p3/M, z3.h, z10.h\n" + "fmla z22.h, p3/M, z0.h, z10.h\n" + "fmla z27.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x12, x3, LSL #1]\n" + "fmla z20.h, p3/M, z2.h, z10.h\n" + "fmla z21.h, p3/M, z2.h, z12.h\n" + "fmla z16.h, p3/M, z5.h, z10.h\n" + "fmla z17.h, p3/M, z5.h, z12.h\n" + "ld1h { z10.h }, p2/Z, [x17, x3, LSL #1]\n" + "fmla z18.h, p3/M, z4.h, z12.h\n" + "fmla z19.h, p3/M, z3.h, z12.h\n" + "fmla z22.h, p3/M, z1.h, z12.h\n" + "fmla z23.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x17, x16, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z11.h\n" + "fmla z29.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x12, x16, LSL #1]\n" + "fmla z20.h, p3/M, z4.h, z10.h\n" + "fmla z21.h, p3/M, z3.h, z10.h\n" + "fmla z24.h, p3/M, z1.h, z10.h\n" + "fmla z25.h, p3/M, z0.h, z10.h\n" + "fmla z16.h, p3/M, z7.h, z10.h\n" + "fmla z17.h, p3/M, z6.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x4, x6, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z7.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x15, x3, LSL #1]\n" + "fmla z18.h, p3/M, z8.h, z12.h\n" + "fmla z19.h, p3/M, z7.h, z12.h\n" + "fmla z22.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z26.h, p3/M, z2.h, z12.h\n" + "fmla z27.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x4, x8, LSL #1]\n" + "fmla z20.h, p3/M, z7.h, z11.h\n" + "fmla z21.h, p3/M, z6.h, z11.h\n" + "fmla z24.h, p3/M, z4.h, z11.h\n" + "fmla z25.h, p3/M, z3.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "fmla z29.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x15, x16, LSL #1]\n" + "fmla z16.h, p3/M, z2.h, z10.h\n" + "fmla z17.h, p3/M, z1.h, z10.h\n" + "fmla z18.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x17]\n" + "fmla z19.h, p3/M, z0.h, z12.h\n" + "fmla z30.h, p3/M, z2.h, z11.h\n" + "fmla z22.h, p3/M, z8.h, z11.h\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "fmla z26.h, p3/M, z5.h, z11.h\n" + "fmla z20.h, p3/M, z3.h, z10.h\n" + "fmla z24.h, p3/M, z0.h, z10.h\n" + "fmla z27.h, p3/M, z4.h, z11.h\n" + "fmla z31.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x6, LSL #1]\n" + "fmla z17.h, p3/M, z2.h, z12.h\n" + "fmla z18.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x17, x14, LSL #1]\n" + "fmla z16.h, p3/M, z6.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x15]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z25.h, p3/M, z7.h, z11.h\n" + "fmla z19.h, p3/M, z8.h, z12.h\n" + "fmla z23.h, p3/M, z5.h, z12.h\n" + "fmla z27.h, p3/M, z2.h, z12.h\n" + "fmla z20.h, p3/M, z6.h, z10.h\n" + "ld1h { z12.h }, p2/Z, [x15, x14, LSL #1]\n" + "fmla z24.h, p3/M, z3.h, z10.h\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x12, x6, LSL #1]\n" + "fmla z26.h, p3/M, z6.h, z11.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z23.h, p3/M, z8.h, z12.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "fmla z30.h, p3/M, z6.h, z10.h\n" + "fmla z27.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x12, x8, LSL #1]\n" + "fmla z24.h, p3/M, z8.h, z11.h\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x8, LSL #1]\n" + "fmla z29.h, p3/M, z5.h, z11.h\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z11.h\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "fmla z26.h, p3/M, z7.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x7, x16, LSL #1]\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x7, x3, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z12.h\n" + "fmla z30.h, p3/M, z7.h, z12.h\n" + "fmla z31.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x3, LSL #1]\n" + "fmla z18.h, p3/M, z5.h, z11.h\n" + "fmla z19.h, p3/M, z4.h, z11.h\n" + "fmla z16.h, p3/M, z4.h, z10.h\n" + "fmla z17.h, p3/M, z3.h, z10.h\n" + "fmla z20.h, p3/M, z1.h, z10.h\n" + "fmla z21.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x13, x16, LSL #1]\n" + "fmla z22.h, p3/M, z2.h, z11.h\n" + "fmla z23.h, p3/M, z1.h, z11.h\n" + "fmla z24.h, p3/M, z7.h, z12.h\n" + "fmla z25.h, p3/M, z6.h, z12.h\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + ".inst 0xc16dc9d0 // fclamp { z16.h-z19.h }, z14.h, z13.h\n" + ".inst 0xc16dc9d4 // fclamp { z20.h-z23.h }, z14.h, z13.h\n" + ".inst 0xc16dc9d8 // fclamp { z24.h-z27.h }, z14.h, z13.h\n" + ".inst 0xc16dc9dc // fclamp { z28.h-z31.h }, z14.h, z13.h\n" + "st1h { z16.h }, p0, [x27]\n" + "st1h { z17.h }, p0, [x27, x9, LSL #1]\n" + "st1h { z18.h }, p0, [x27, x26, LSL #1]\n" + "st1h { z19.h }, p0, [x27, x25, LSL #1]\n" + "st1h { z20.h }, p0, [x24]\n" + "st1h { z21.h }, p0, [x24, x9, LSL #1]\n" + "st1h { z22.h }, p0, [x24, x26, LSL #1]\n" + "st1h { z23.h }, p0, [x24, x25, LSL #1]\n" + "st1h { z24.h }, p0, [x23]\n" + "st1h { z25.h }, p0, [x23, x9, LSL #1]\n" + "st1h { z26.h }, p0, [x23, x26, LSL #1]\n" + "st1h { z27.h }, p0, [x23, x25, LSL #1]\n" + "st1h { z28.h }, p0, [x22]\n" + "st1h { z29.h }, p0, [x22, x9, LSL #1]\n" + "st1h { z30.h }, p0, [x22, x26, LSL #1]\n" + "st1h { z31.h }, p0, [x22, x25, LSL #1]\n" + "blt 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp new file mode 100644 index 0000000000..2e6f1123a4 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst/generic_indirect.cpp @@ -0,0 +1,653 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s1_output4x4_mla_depthfirst_indirect_impl( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + __fp16 *const *outptrs; + const void *params; + const __fp16 min, max; + const __fp16 *inptrs[36]; + + Args( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *const params, + const __fp16 min, + const __fp16 max + ) : outptrs(outptrs), params(params), min(min), max(max) + { + inptrs[0] = input_ptrs[14]; + inptrs[1] = input_ptrs[0]; + inptrs[2] = input_ptrs[5]; + inptrs[3] = input_ptrs[15]; + inptrs[4] = input_ptrs[30]; + inptrs[5] = input_ptrs[35]; + inptrs[6] = input_ptrs[20]; + inptrs[7] = input_ptrs[1]; + inptrs[8] = input_ptrs[4]; + inptrs[9] = input_ptrs[21]; + inptrs[10] = input_ptrs[6]; + inptrs[11] = input_ptrs[11]; + inptrs[12] = input_ptrs[24]; + inptrs[13] = input_ptrs[8]; + inptrs[14] = input_ptrs[29]; + inptrs[15] = input_ptrs[9]; + inptrs[16] = input_ptrs[31]; + inptrs[17] = input_ptrs[13]; + inptrs[18] = input_ptrs[34]; + inptrs[19] = input_ptrs[16]; + inptrs[20] = input_ptrs[2]; + inptrs[21] = input_ptrs[19]; + inptrs[22] = input_ptrs[3]; + inptrs[23] = input_ptrs[12]; + inptrs[24] = input_ptrs[22]; + inptrs[25] = input_ptrs[17]; + inptrs[26] = input_ptrs[18]; + inptrs[27] = input_ptrs[26]; + inptrs[28] = input_ptrs[23]; + inptrs[29] = input_ptrs[32]; + inptrs[30] = input_ptrs[27]; + inptrs[31] = input_ptrs[33]; + inptrs[32] = input_ptrs[7]; + inptrs[33] = input_ptrs[10]; + inptrs[34] = input_ptrs[25]; + inptrs[35] = input_ptrs[28]; + + } + }; + + Args params_struct(input_ptrs, outptrs, params, + activation_min, activation_max); + + __asm__ __volatile__( + "ldr x17, [%x[params_struct], %[offsetof_args_params]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "add x16, %x[params_struct], %[offsetof_Args_inptrs]\n" + "mov x15, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "ldp x14, x13, [x16, #0x0]\n" + "ldp x12, x11, [x16, #0x10]\n" + "cnth x10\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + "ld1rh { z15.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "ld1h { z14.h }, p3/Z, [x17]\n" + "addvl x17, x17, #1\n" + "cmp x10, %x[n_channels]\n" + "ldr x9, [%x[params_struct], %[offsetof_args_outptrs]]\n" + ".inst 0xa040a220 // ld1h { z0.h-z3.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "sub x28, XZR, x10\n" + ".inst 0xa040a224 // ld1h { z4.h-z7.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "ld1rh { z13.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "ld1h { z8.h }, p3/Z, [x17]\n" + "addvl x17, x17, #1\n" + "ld1h { z9.h }, p2/Z, [x14, x15, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x12, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "bge 2f\n" + "1:" // Channel loop + "movprfx z21, z14\n fmla z21.h, p3/M, z4.h, z9.h\n" + "movprfx z16, z14\n fmla z16.h, p3/M, z8.h, z9.h\n" + "ldr x27, [x16, #0x20]\n" + "inch x28\n" + "movprfx z22, z14\n fmla z22.h, p3/M, z3.h, z9.h\n" + "movprfx z25, z14\n fmla z25.h, p3/M, z1.h, z9.h\n" + "ldr x26, [x16, #0x30]\n" + "mov p1.b, p2.b\n" + "movprfx z26, z14\n fmla z26.h, p3/M, z0.h, z9.h\n" + "ldr x25, [x16, #0x28]\n" + "movprfx z17, z14\n fmla z17.h, p3/M, z7.h, z9.h\n" + "whilelt p0.h, x10, %x[n_channels]\n" + "movprfx z18, z14\n fmla z18.h, p3/M, z6.h, z9.h\n" + "movprfx z20, z14\n fmla z20.h, p3/M, z5.h, z9.h\n" + "ldr x24, [x16, #0x38]\n" + "fmla z21.h, p3/M, z5.h, z12.h\n" + "movprfx z24, z14\n fmla z24.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x14, [x16, #0x40]\n" + "fmla z16.h, p3/M, z0.h, z10.h\n" + "movprfx z19, z14\n fmla z19.h, p3/M, z2.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x13, [x16, #0x48]\n" + "fmla z22.h, p3/M, z4.h, z12.h\n" + "fmla z25.h, p3/M, z2.h, z12.h\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x12, [x16, #0x50]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "fmla z17.h, p3/M, z8.h, z12.h\n" + "ldr x27, [x16, #0x60]\n" + "fmla z18.h, p3/M, z7.h, z12.h\n" + "movprfx z28, z14\n fmla z28.h, p3/M, z6.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x25, [x16, #0x68]\n" + "fmla z21.h, p3/M, z7.h, z9.h\n" + "fmla z19.h, p3/M, z6.h, z12.h\n" + "ldr x11, [x16, #0x58]\n" + "movprfx z23, z14\n fmla z23.h, p3/M, z3.h, z12.h\n" + "movprfx z27, z14\n fmla z27.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldr x26, [x16, #0x70]\n" + "movprfx z31, z14\n fmla z31.h, p3/M, z8.h, z11.h\n" + "fmla z22.h, p3/M, z6.h, z9.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldr x24, [x16, #0x78]\n" + "fmla z25.h, p3/M, z4.h, z9.h\n" + "fmla z26.h, p3/M, z3.h, z9.h\n" + "ldr x14, [x16, #0x80]\n" + "movprfx z29, z14\n fmla z29.h, p3/M, z1.h, z9.h\n" + "movprfx z30, z14\n fmla z30.h, p3/M, z0.h, z9.h\n" + "ldr x13, [x16, #0x88]\n" + "ld1h { z14.h }, p3/Z, [x17]\n" + "fmla z20.h, p3/M, z8.h, z9.h\n" + "fmla z24.h, p3/M, z5.h, z9.h\n" + "ldr x23, [x9, #0x0]\n" + "addvl x17, x17, #1\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z16.h, p3/M, z1.h, z12.h\n" + "ld1h { z9.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0x90]\n" + "fmla z17.h, p3/M, z0.h, z12.h\n" + "fmla z18.h, p3/M, z2.h, z11.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "ldr x11, [x16, #0x98]\n" + "fmla z21.h, p3/M, z8.h, z10.h\n" + "fmla z19.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xa0]\n" + "fmla z22.h, p3/M, z7.h, z10.h\n" + "fmla z23.h, p3/M, z6.h, z10.h\n" + "ldr x22, [x9, #0x8]\n" + "fmla z25.h, p3/M, z5.h, z10.h\n" + "fmla z26.h, p3/M, z4.h, z10.h\n" + "ldr x21, [x9, #0x10]\n" + "fmla z27.h, p3/M, z3.h, z10.h\n" + "fmla z29.h, p3/M, z2.h, z10.h\n" + "ldr x20, [x9, #0x18]\n" + "fmla z30.h, p3/M, z1.h, z10.h\n" + "fmla z31.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0xa8]\n" + "fmla z16.h, p3/M, z3.h, z9.h\n" + "fmla z20.h, p3/M, z0.h, z9.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xb0]\n" + "fmla z17.h, p3/M, z4.h, z10.h\n" + "fmla z18.h, p3/M, z3.h, z10.h\n" + "fmla z21.h, p3/M, z1.h, z10.h\n" + "fmla z19.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z2.h, z12.h\n" + "fmla z22.h, p3/M, z0.h, z10.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0xb8]\n" + "fmla z27.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldr x14, [x16, #0xc0]\n" + "fmla z16.h, p3/M, z5.h, z10.h\n" + "fmla z20.h, p3/M, z2.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x13, [x16, #0xc8]\n" + "fmla z17.h, p3/M, z5.h, z12.h\n" + "fmla z18.h, p3/M, z4.h, z12.h\n" + "fmla z21.h, p3/M, z2.h, z12.h\n" + "fmla z19.h, p3/M, z3.h, z12.h\n" + "fmla z22.h, p3/M, z1.h, z12.h\n" + "fmla z23.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "ldr x11, [x16, #0xd8]\n" + "fmla z28.h, p3/M, z7.h, z11.h\n" + "fmla z29.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0xd0]\n" + "fmla z16.h, p3/M, z7.h, z10.h\n" + "fmla z17.h, p3/M, z6.h, z10.h\n" + "fmla z20.h, p3/M, z4.h, z10.h\n" + "fmla z21.h, p3/M, z3.h, z10.h\n" + "fmla z24.h, p3/M, z1.h, z10.h\n" + "fmla z25.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xe0]\n" + "fmla z18.h, p3/M, z8.h, z12.h\n" + "fmla z30.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z7.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z27.h, p3/M, z1.h, z12.h\n" + "ldr x25, [x16, #0xe8]\n" + "fmla z19.h, p3/M, z7.h, z12.h\n" + "fmla z22.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z26.h, p3/M, z2.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xf0]\n" + "fmla z16.h, p3/M, z2.h, z10.h\n" + "fmla z17.h, p3/M, z1.h, z10.h\n" + "fmla z18.h, p3/M, z0.h, z10.h\n" + "fmla z20.h, p3/M, z7.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0xf8]\n" + "fmla z21.h, p3/M, z6.h, z11.h\n" + "fmla z24.h, p3/M, z4.h, z11.h\n" + "fmla z25.h, p3/M, z3.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "fmla z29.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z17.h, p3/M, z2.h, z12.h\n" + "ldr x14, [x16, #0x100]\n" + "fmla z18.h, p3/M, z1.h, z12.h\n" + "fmla z19.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x13, [x16, #0x108]\n" + "fmla z16.h, p3/M, z6.h, z10.h\n" + "fmla z20.h, p3/M, z3.h, z10.h\n" + "fmla z27.h, p3/M, z4.h, z11.h\n" + "fmla z30.h, p3/M, z2.h, z11.h\n" + "fmla z24.h, p3/M, z0.h, z10.h\n" + "fmla z22.h, p3/M, z8.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0x110]\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "fmla z26.h, p3/M, z5.h, z11.h\n" + "fmla z31.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z19.h, p3/M, z8.h, z12.h\n" + "ldr x11, [x16, #0x118]\n" + "fmla z27.h, p3/M, z2.h, z12.h\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z20.h, p3/M, z6.h, z10.h\n" + "fmla z24.h, p3/M, z3.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z23.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x27, x15, LSL #1]\n" + "fmla z25.h, p3/M, z7.h, z11.h\n" + "fmla z26.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "fmla z24.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z27.h, p3/M, z5.h, z12.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "fmla z30.h, p3/M, z6.h, z10.h\n" + "fmla z23.h, p3/M, z8.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z26.h, p3/M, z7.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z11.h\n" + "fmla z29.h, p3/M, z5.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z11.h\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z16.h, p3/M, z4.h, z10.h\n" + "ldp x14, x13, [x16, #0x0]\n" + "fmla z17.h, p3/M, z3.h, z10.h\n" + "fmla z20.h, p3/M, z1.h, z10.h\n" + "fmla z21.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z18.h, p3/M, z5.h, z11.h\n" + "fmla z19.h, p3/M, z4.h, z11.h\n" + "fmla z29.h, p3/M, z8.h, z12.h\n" + "ld1h { z9.h }, p0/Z, [x14, x10, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z12.h\n" + "fmla z31.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldp x12, x11, [x16, #0x10]\n" + "fmla z22.h, p3/M, z2.h, z11.h\n" + "fmla z23.h, p3/M, z1.h, z11.h\n" + "inch x15\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + "whilelt p2.h, x15, %x[n_channels]\n" + ".inst 0xc16dc9f0 // fclamp { z16.h-z19.h }, z15.h, z13.h\n" + "fmla z24.h, p3/M, z7.h, z12.h\n" + "ld1h { z11.h }, p0/Z, [x12, x10, LSL #1]\n" + "fmla z25.h, p3/M, z6.h, z12.h\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + ".inst 0xc16dc9f4 // fclamp { z20.h-z23.h }, z15.h, z13.h\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "ld1h { z12.h }, p0/Z, [x11, x10, LSL #1]\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "ld1h { z10.h }, p0/Z, [x13, x10, LSL #1]\n" + "inch x10\n" + "st1h { z16.h }, p1, [x23, x28, LSL #1]\n" + "ldr x23, [x9, #0x20]\n" + ".inst 0xa040a220 // ld1h { z0.h-z3.h }, pn8.b/Z, [x17]\n" + "addvl x17, x17, #4\n" + "st1h { z17.h }, p1, [x22, x28, LSL #1]\n" + "ldr x22, [x9, #0x28]\n" + ".inst 0xc16dc9f8 // fclamp { z24.h-z27.h }, z15.h, z13.h\n" + ".inst 0xa040a224 // ld1h { z4.h-z7.h }, pn8.b/Z, [x17]\n" + "st1h { z18.h }, p1, [x21, x28, LSL #1]\n" + "ldr x21, [x9, #0x30]\n" + "addvl x17, x17, #4\n" + "cmp x10, %x[n_channels]\n" + "st1h { z19.h }, p1, [x20, x28, LSL #1]\n" + "ldr x20, [x9, #0x38]\n" + ".inst 0xc16dc9fc // fclamp { z28.h-z31.h }, z15.h, z13.h\n" + "ld1h { z8.h }, p3/Z, [x17]\n" + "st1h { z20.h }, p1, [x23, x28, LSL #1]\n" + "ldr x23, [x9, #0x40]\n" + "addvl x17, x17, #1\n" + "st1h { z21.h }, p1, [x22, x28, LSL #1]\n" + "ldr x22, [x9, #0x48]\n" + "st1h { z22.h }, p1, [x21, x28, LSL #1]\n" + "ldr x21, [x9, #0x50]\n" + "st1h { z23.h }, p1, [x20, x28, LSL #1]\n" + "ldr x20, [x9, #0x58]\n" + "st1h { z24.h }, p1, [x23, x28, LSL #1]\n" + "ldr x23, [x9, #0x60]\n" + "st1h { z25.h }, p1, [x22, x28, LSL #1]\n" + "ldr x22, [x9, #0x68]\n" + "st1h { z26.h }, p1, [x21, x28, LSL #1]\n" + "ldr x21, [x9, #0x70]\n" + "st1h { z27.h }, p1, [x20, x28, LSL #1]\n" + "ldr x20, [x9, #0x78]\n" + "st1h { z28.h }, p1, [x23, x28, LSL #1]\n" + "st1h { z29.h }, p1, [x22, x28, LSL #1]\n" + "st1h { z30.h }, p1, [x21, x28, LSL #1]\n" + "st1h { z31.h }, p1, [x20, x28, LSL #1]\n" + "blt 1b\n" + "2:" // Channel tail + "movprfx z21, z14\n fmla z21.h, p3/M, z4.h, z9.h\n" + "movprfx z16, z14\n fmla z16.h, p3/M, z8.h, z9.h\n" + "ldr x27, [x16, #0x20]\n" + "inch x28\n" + "movprfx z22, z14\n fmla z22.h, p3/M, z3.h, z9.h\n" + "movprfx z25, z14\n fmla z25.h, p3/M, z1.h, z9.h\n" + "ldr x26, [x16, #0x30]\n" + "mov p1.b, p2.b\n" + "movprfx z26, z14\n fmla z26.h, p3/M, z0.h, z9.h\n" + "ldr x25, [x16, #0x28]\n" + "movprfx z17, z14\n fmla z17.h, p3/M, z7.h, z9.h\n" + "movprfx z18, z14\n fmla z18.h, p3/M, z6.h, z9.h\n" + "movprfx z20, z14\n fmla z20.h, p3/M, z5.h, z9.h\n" + "ldr x24, [x16, #0x38]\n" + "fmla z21.h, p3/M, z5.h, z12.h\n" + "movprfx z24, z14\n fmla z24.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x14, [x16, #0x40]\n" + "fmla z16.h, p3/M, z0.h, z10.h\n" + "movprfx z19, z14\n fmla z19.h, p3/M, z2.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x13, [x16, #0x48]\n" + "fmla z22.h, p3/M, z4.h, z12.h\n" + "fmla z25.h, p3/M, z2.h, z12.h\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x12, [x16, #0x50]\n" + "fmla z26.h, p3/M, z1.h, z12.h\n" + "fmla z17.h, p3/M, z8.h, z12.h\n" + "ldr x27, [x16, #0x60]\n" + "fmla z18.h, p3/M, z7.h, z12.h\n" + "movprfx z28, z14\n fmla z28.h, p3/M, z6.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x25, [x16, #0x68]\n" + "fmla z21.h, p3/M, z7.h, z9.h\n" + "fmla z19.h, p3/M, z6.h, z12.h\n" + "ldr x11, [x16, #0x58]\n" + "movprfx z23, z14\n fmla z23.h, p3/M, z3.h, z12.h\n" + "movprfx z27, z14\n fmla z27.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldr x26, [x16, #0x70]\n" + "movprfx z31, z14\n fmla z31.h, p3/M, z8.h, z11.h\n" + "fmla z22.h, p3/M, z6.h, z9.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldr x24, [x16, #0x78]\n" + "fmla z25.h, p3/M, z4.h, z9.h\n" + "fmla z26.h, p3/M, z3.h, z9.h\n" + "ldr x14, [x16, #0x80]\n" + "movprfx z29, z14\n fmla z29.h, p3/M, z1.h, z9.h\n" + "movprfx z30, z14\n fmla z30.h, p3/M, z0.h, z9.h\n" + "ldr x13, [x16, #0x88]\n" + "fmla z20.h, p3/M, z8.h, z9.h\n" + "fmla z24.h, p3/M, z5.h, z9.h\n" + "ldr x23, [x9, #0x0]\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "fmla z16.h, p3/M, z1.h, z12.h\n" + "ld1h { z9.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0x90]\n" + "fmla z17.h, p3/M, z0.h, z12.h\n" + "fmla z18.h, p3/M, z2.h, z11.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "ldr x11, [x16, #0x98]\n" + "fmla z21.h, p3/M, z8.h, z10.h\n" + "fmla z19.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xa0]\n" + "fmla z22.h, p3/M, z7.h, z10.h\n" + "fmla z23.h, p3/M, z6.h, z10.h\n" + "ldr x22, [x9, #0x8]\n" + "fmla z25.h, p3/M, z5.h, z10.h\n" + "fmla z26.h, p3/M, z4.h, z10.h\n" + "ldr x21, [x9, #0x10]\n" + "fmla z27.h, p3/M, z3.h, z10.h\n" + "fmla z29.h, p3/M, z2.h, z10.h\n" + "ldr x20, [x9, #0x18]\n" + "fmla z30.h, p3/M, z1.h, z10.h\n" + "fmla z31.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0xa8]\n" + "fmla z16.h, p3/M, z3.h, z9.h\n" + "fmla z20.h, p3/M, z0.h, z9.h\n" + "fmla z24.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xb0]\n" + "fmla z17.h, p3/M, z4.h, z10.h\n" + "fmla z18.h, p3/M, z3.h, z10.h\n" + "fmla z21.h, p3/M, z1.h, z10.h\n" + "fmla z19.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z2.h, z12.h\n" + "fmla z22.h, p3/M, z0.h, z10.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0xb8]\n" + "fmla z27.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "ldr x14, [x16, #0xc0]\n" + "fmla z16.h, p3/M, z5.h, z10.h\n" + "fmla z20.h, p3/M, z2.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x13, [x16, #0xc8]\n" + "fmla z17.h, p3/M, z5.h, z12.h\n" + "fmla z18.h, p3/M, z4.h, z12.h\n" + "fmla z21.h, p3/M, z2.h, z12.h\n" + "fmla z19.h, p3/M, z3.h, z12.h\n" + "fmla z22.h, p3/M, z1.h, z12.h\n" + "fmla z23.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "ldr x11, [x16, #0xd8]\n" + "fmla z28.h, p3/M, z7.h, z11.h\n" + "fmla z29.h, p3/M, z6.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0xd0]\n" + "fmla z16.h, p3/M, z7.h, z10.h\n" + "fmla z17.h, p3/M, z6.h, z10.h\n" + "fmla z20.h, p3/M, z4.h, z10.h\n" + "fmla z21.h, p3/M, z3.h, z10.h\n" + "fmla z24.h, p3/M, z1.h, z10.h\n" + "fmla z25.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xe0]\n" + "fmla z18.h, p3/M, z8.h, z12.h\n" + "fmla z30.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z7.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z27.h, p3/M, z1.h, z12.h\n" + "ldr x25, [x16, #0xe8]\n" + "fmla z19.h, p3/M, z7.h, z12.h\n" + "fmla z22.h, p3/M, z5.h, z12.h\n" + "fmla z23.h, p3/M, z4.h, z12.h\n" + "fmla z26.h, p3/M, z2.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xf0]\n" + "fmla z16.h, p3/M, z2.h, z10.h\n" + "fmla z17.h, p3/M, z1.h, z10.h\n" + "fmla z18.h, p3/M, z0.h, z10.h\n" + "fmla z20.h, p3/M, z7.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0xf8]\n" + "fmla z21.h, p3/M, z6.h, z11.h\n" + "fmla z24.h, p3/M, z4.h, z11.h\n" + "fmla z25.h, p3/M, z3.h, z11.h\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "fmla z29.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z17.h, p3/M, z2.h, z12.h\n" + "ldr x14, [x16, #0x100]\n" + "fmla z18.h, p3/M, z1.h, z12.h\n" + "fmla z19.h, p3/M, z0.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x13, x15, LSL #1]\n" + "ldr x13, [x16, #0x108]\n" + "fmla z16.h, p3/M, z6.h, z10.h\n" + "fmla z20.h, p3/M, z3.h, z10.h\n" + "fmla z27.h, p3/M, z4.h, z11.h\n" + "fmla z30.h, p3/M, z2.h, z11.h\n" + "fmla z24.h, p3/M, z0.h, z10.h\n" + "fmla z22.h, p3/M, z8.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x12, x15, LSL #1]\n" + "ldr x12, [x16, #0x110]\n" + "fmla z23.h, p3/M, z7.h, z11.h\n" + "fmla z26.h, p3/M, z5.h, z11.h\n" + "fmla z31.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z19.h, p3/M, z8.h, z12.h\n" + "ldr x11, [x16, #0x118]\n" + "fmla z27.h, p3/M, z2.h, z12.h\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z20.h, p3/M, z6.h, z10.h\n" + "fmla z24.h, p3/M, z3.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z23.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x27, x15, LSL #1]\n" + "fmla z25.h, p3/M, z7.h, z11.h\n" + "fmla z26.h, p3/M, z6.h, z11.h\n" + "fmla z28.h, p3/M, z5.h, z11.h\n" + "fmla z24.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z27.h, p3/M, z5.h, z12.h\n" + "fmla z31.h, p3/M, z2.h, z12.h\n" + "fmla z29.h, p3/M, z7.h, z10.h\n" + "fmla z30.h, p3/M, z6.h, z10.h\n" + "fmla z23.h, p3/M, z8.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z28.h, p3/M, z8.h, z10.h\n" + "fmla z25.h, p3/M, z8.h, z11.h\n" + "ld1h { z10.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z26.h, p3/M, z7.h, z11.h\n" + "fmla z27.h, p3/M, z6.h, z11.h\n" + "fmla z29.h, p3/M, z5.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z11.h\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z16.h, p3/M, z4.h, z10.h\n" + "fmla z17.h, p3/M, z3.h, z10.h\n" + "fmla z20.h, p3/M, z1.h, z10.h\n" + "fmla z21.h, p3/M, z0.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z18.h, p3/M, z5.h, z11.h\n" + "fmla z19.h, p3/M, z4.h, z11.h\n" + "fmla z29.h, p3/M, z8.h, z12.h\n" + "fmla z30.h, p3/M, z7.h, z12.h\n" + "fmla z31.h, p3/M, z6.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x12, x15, LSL #1]\n" + "fmla z22.h, p3/M, z2.h, z11.h\n" + "fmla z23.h, p3/M, z1.h, z11.h\n" + "fmla z26.h, p3/M, z8.h, z10.h\n" + "fmla z27.h, p3/M, z7.h, z10.h\n" + ".inst 0xc16dc9f0 // fclamp { z16.h-z19.h }, z15.h, z13.h\n" + "fmla z24.h, p3/M, z7.h, z12.h\n" + "fmla z25.h, p3/M, z6.h, z12.h\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + ".inst 0xc16dc9f4 // fclamp { z20.h-z23.h }, z15.h, z13.h\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z30.h, p3/M, z5.h, z10.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "st1h { z16.h }, p1, [x23, x28, LSL #1]\n" + "ldr x23, [x9, #0x20]\n" + "st1h { z17.h }, p1, [x22, x28, LSL #1]\n" + "ldr x22, [x9, #0x28]\n" + "st1h { z18.h }, p1, [x21, x28, LSL #1]\n" + "ldr x21, [x9, #0x30]\n" + ".inst 0xc16dc9f8 // fclamp { z24.h-z27.h }, z15.h, z13.h\n" + "st1h { z19.h }, p1, [x20, x28, LSL #1]\n" + "ldr x20, [x9, #0x38]\n" + "st1h { z20.h }, p1, [x23, x28, LSL #1]\n" + "ldr x23, [x9, #0x40]\n" + ".inst 0xc16dc9fc // fclamp { z28.h-z31.h }, z15.h, z13.h\n" + "st1h { z21.h }, p1, [x22, x28, LSL #1]\n" + "ldr x22, [x9, #0x48]\n" + "st1h { z22.h }, p1, [x21, x28, LSL #1]\n" + "ldr x21, [x9, #0x50]\n" + "st1h { z23.h }, p1, [x20, x28, LSL #1]\n" + "ldr x20, [x9, #0x58]\n" + "st1h { z24.h }, p1, [x23, x28, LSL #1]\n" + "ldr x23, [x9, #0x60]\n" + "st1h { z25.h }, p1, [x22, x28, LSL #1]\n" + "ldr x22, [x9, #0x68]\n" + "st1h { z26.h }, p1, [x21, x28, LSL #1]\n" + "ldr x21, [x9, #0x70]\n" + "st1h { z27.h }, p1, [x20, x28, LSL #1]\n" + "ldr x20, [x9, #0x78]\n" + "st1h { z28.h }, p1, [x23, x28, LSL #1]\n" + "st1h { z29.h }, p1, [x22, x28, LSL #1]\n" + "st1h { z30.h }, p1, [x21, x28, LSL #1]\n" + "st1h { z31.h }, p1, [x20, x28, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp new file mode 100644 index 0000000000..27fcb2e6d2 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst.hpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/core/NEON/kernels/arm_gemm/utils.hpp" + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl(const __fp16 *const *const input_ptrs, __fp16 *const *const outptrs, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); +void sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl(const unsigned int n_tile_rows, const unsigned int n_tile_cols, const __fp16 *inptr, int64_t ld_input_row, int64_t ld_input_col, __fp16 *outptr, int64_t ld_output_row, int64_t ld_output_col, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); + +class sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16> +{ + private: + using Parent = DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16>; + Parent::IndirectKernelType m_indirect_kernel = sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl; + Parent::DirectKernelType m_direct_kernel = sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl; + + public: + using return_type = __fp16; + constexpr static auto vl_type = arm_gemm::VLType::SME; + + constexpr static unsigned int kernel_rows = 3; + constexpr static unsigned int kernel_cols = 3; + + constexpr static unsigned int stride_rows = 2; + constexpr static unsigned int stride_cols = 2; + + constexpr static unsigned int output_rows = 2; + constexpr static unsigned int output_cols = 2; + + sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst(const CPUInfo *) + : Parent(output_rows, output_cols, kernel_rows, kernel_cols, stride_rows, stride_cols) {} + + arm_gemm::VLType get_vl_type(void) const override { return vl_type; } + + Parent::IndirectKernelType get_indirect_kernel() const override { return m_indirect_kernel; } + Parent::DirectKernelType get_direct_kernel() const override { return m_direct_kernel; } +}; + +} // namespace depthwise +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp new file mode 100644 index 0000000000..066ce06aa6 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_direct.cpp @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst_direct_impl( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + const uint64_t n_tile_rows, n_tile_cols; + const __fp16 *inptr; + const uint64_t ld_input_row; + const uint64_t ld_input_col; + __fp16 *outptr; + const uint64_t ld_output_row; + const uint64_t ld_output_col; + const void *params; + const __fp16 min, max; + + uint64_t tile_i = 0, tile_j = 0; + + Args( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + const float activation_min, + const float activation_max + ) : n_tile_rows(n_tile_rows), n_tile_cols(n_tile_cols), inptr(inptr), + ld_input_row(ld_input_row), ld_input_col(ld_input_col), outptr(outptr), + ld_output_row(ld_output_row), ld_output_col(ld_output_col), + params(params), min(activation_min), max(activation_max) + { + } + }; + + Args params_struct( + n_tile_rows, n_tile_cols, + inptr, ld_input_row, ld_input_col, + outptr, ld_output_row, ld_output_col, + params, activation_min, activation_max + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x2, #0x0\n" + "mov x3, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "1:" // Tile loop + "str x2, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "mov x22, #0x4\n" + "str x3, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" + "ldr x4, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" + "ldr x5, [%x[params_struct], %[offsetof_args_inptr]]\n" + "mul x20, x2, x21\n" // offset = tile_i * ld_input_row + "ldr x6, [%x[params_struct], %[offsetof_args_params]]\n" + "madd x20, x3, x4, x20\n" // offset += tile_j * ld_input_col + "mul x20, x20, x22\n" // offset *= kernel_stride * output_size + "add x7, x4, x4\n" + "add x5, x5, x20, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) + "add x8, x5, x21, LSL #1\n" + "add x17, x7, x4\n" + "add x16, x8, x21, LSL #1\n" + "add x15, x17, x4\n" + "add x14, x16, x21, LSL #1\n" + "add x13, x14, x21, LSL #1\n" + "cbnz x3, 2f\n" + "ldr x24, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "lsl x12, %x[n_channels], #0x1\n" + "mov x28, #0x8\n" + "mul x28, x28, x4\n" + "add x27, x16, x7, LSL #1\n" + "add x26, x5, x4, LSL #1\n" + "add x25, x5, x17, LSL #1\n" + "sub x20, x24, x3\n" + "add x24, x5, x15, LSL #1\n" + "sub x20, x20, #0x1\n" + "add x23, x8, x4, LSL #1\n" + "and x20, x20, #0x3fffff\n" + "add x22, x5, x7, LSL #1\n" + "orr x12, x12, x20, LSL #22\n" + "add x21, x8, x17, LSL #1\n" + "orr x12, x12, x28, LSL #38\n" + "add x20, x8, x15, LSL #1\n" + "add x11, x8, x7, LSL #1\n" + "add x10, x14, x4, LSL #1\n" + "add x9, x16, x4, LSL #1\n" + "add x28, x14, x17, LSL #1\n" + ".inst 0xf8ac4b7a // rprfm pldonce, x12, [x27]\n" + "add x27, x16, x17, LSL #1\n" + ".inst 0xf8ac48ba // rprfm pldonce, x12, [x5]\n" + ".inst 0xf8ac4b5a // rprfm pldonce, x12, [x26]\n" + "add x26, x14, x15, LSL #1\n" + ".inst 0xf8ac4b3a // rprfm pldonce, x12, [x25]\n" + "add x25, x16, x15, LSL #1\n" + ".inst 0xf8ac4b1a // rprfm pldonce, x12, [x24]\n" + "add x24, x13, x4, LSL #1\n" + ".inst 0xf8ac491a // rprfm pldonce, x12, [x8]\n" + ".inst 0xf8ac4afa // rprfm pldonce, x12, [x23]\n" + "add x23, x14, x7, LSL #1\n" + ".inst 0xf8ac4ada // rprfm pldonce, x12, [x22]\n" + "add x22, x13, x17, LSL #1\n" + ".inst 0xf8ac4aba // rprfm pldonce, x12, [x21]\n" + "add x21, x13, x7, LSL #1\n" + ".inst 0xf8ac4a9a // rprfm pldonce, x12, [x20]\n" + "add x20, x13, x15, LSL #1\n" + ".inst 0xf8ac497a // rprfm pldonce, x12, [x11]\n" + ".inst 0xf8ac49da // rprfm pldonce, x12, [x14]\n" + ".inst 0xf8ac4a1a // rprfm pldonce, x12, [x16]\n" + ".inst 0xf8ac495a // rprfm pldonce, x12, [x10]\n" + ".inst 0xf8ac493a // rprfm pldonce, x12, [x9]\n" + ".inst 0xf8ac4b9a // rprfm pldonce, x12, [x28]\n" + ".inst 0xf8ac4b7a // rprfm pldonce, x12, [x27]\n" + ".inst 0xf8ac4b5a // rprfm pldonce, x12, [x26]\n" + ".inst 0xf8ac49ba // rprfm pldonce, x12, [x13]\n" + ".inst 0xf8ac4b3a // rprfm pldonce, x12, [x25]\n" + ".inst 0xf8ac4b1a // rprfm pldonce, x12, [x24]\n" + ".inst 0xf8ac4afa // rprfm pldonce, x12, [x23]\n" + ".inst 0xf8ac4ada // rprfm pldonce, x12, [x22]\n" + ".inst 0xf8ac4aba // rprfm pldonce, x12, [x21]\n" + ".inst 0xf8ac4a9a // rprfm pldonce, x12, [x20]\n" + "2:" // Tile loop: Prefetch input rows: End + "ldr x26, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" + "mov x20, #0x2\n" + "ld1h { z19.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + "ldr x25, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" + "cnth x24\n" + ".inst 0xa040a0c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "ldr x23, [%x[params_struct], %[offsetof_args_outptr]]\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + ".inst 0xa040a0c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "mul x22, x2, x26\n" // offset = tile_i * ld_output_row + "cmp x24, %x[n_channels]\n" + "ld1rh { z18.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "madd x22, x3, x25, x22\n" // offset += tile_j * ld_output_col + "ld1rh { z17.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "mov x21, #0x0\n" + "mul x22, x22, x20\n" // offset *= output_tile_size + "sub x20, XZR, x24\n" + "ld1h { z8.h }, p3/Z, [x6]\n" + "add x23, x23, x22, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) + "ld1h { z9.h }, p2/Z, [x16, x7, LSL #1]\n" + "addvl x6, x6, #1\n" + "add x22, x23, x26, LSL #1\n" + "ld1h { z10.h }, p2/Z, [x5]\n" + "ld1h { z11.h }, p2/Z, [x5, x4, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x5, x17, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x5, x15, LSL #1]\n" + "ld1h { z14.h }, p2/Z, [x8]\n" + "ld1h { z15.h }, p2/Z, [x8, x4, LSL #1]\n" + "ld1h { z16.h }, p2/Z, [x5, x7, LSL #1]\n" + "bge 4f\n" + "3:" // Tile loop: Channel loop + "movprfx z28, z19\n fmla z28.h, p3/M, z8.h, z9.h\n" + "movprfx z29, z19\n fmla z29.h, p3/M, z6.h, z9.h\n" + "whilelt p1.h, x24, %x[n_channels]\n" + "inch x21\n" + "movprfx z30, z19\n fmla z30.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z19\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ld1h { z19.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + "inch x24\n" + "mov p0.b, p2.b\n" + "addvl x5, x5, #1\n" + "inch x20\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z29.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x8, x15, LSL #1]\n" + "ld1h { z10.h }, p1/Z, [x5]\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x8, x17, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x8, x7, LSL #1]\n" + "addvl x8, x8, #1\n" + "fmla z28.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x14]\n" + "fmla z29.h, p3/M, z0.h, z16.h\n" + "fmla z28.h, p3/M, z4.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x16]\n" + "fmla z30.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x4, LSL #1]\n" + "fmla z28.h, p3/M, z2.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x16, x4, LSL #1]\n" + "fmla z30.h, p3/M, z0.h, z15.h\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x16, x17, LSL #1]\n" + "fmla z28.h, p3/M, z5.h, z13.h\n" + "fmla z29.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16, x15, LSL #1]\n" + "addvl x16, x16, #1\n" + "ld1h { z9.h }, p1/Z, [x16, x7, LSL #1]\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "fmla z28.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x13]\n" + "fmla z29.h, p3/M, z7.h, z12.h\n" + "fmla z30.h, p3/M, z1.h, z16.h\n" + "ld1h { z13.h }, p2/Z, [x13, x4, LSL #1]\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p1/Z, [x5, x17, LSL #1]\n" + "fmla z28.h, p3/M, z7.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x14, x7, LSL #1]\n" + "addvl x14, x14, #1\n" + "fmla z30.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x13, x7, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x13, x17, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "ld1h { z13.h }, p1/Z, [x5, x15, LSL #1]\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "whilelt p2.h, x21, %x[n_channels]\n" + "cmp x24, %x[n_channels]\n" + "addvl x13, x13, #1\n" + "fmla z30.h, p3/M, z5.h, z16.h\n" + "fmla z31.h, p3/M, z3.h, z16.h\n" + ".inst 0xa040a0c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "ld1h { z16.h }, p1/Z, [x5, x7, LSL #1]\n" + "fmla z31.h, p3/M, z7.h, z14.h\n" + "ld1h { z14.h }, p1/Z, [x8]\n" + "fmla z30.h, p3/M, z8.h, z15.h\n" + "fmla z31.h, p3/M, z6.h, z15.h\n" + ".inst 0xa040a0c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "ld1h { z15.h }, p1/Z, [x8, x4, LSL #1]\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p1/Z, [x5, x4, LSL #1]\n" + "ld1h { z8.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + ".inst 0xc171ca5c // fclamp { z28.h-z31.h }, z18.h, z17.h\n" + "st1h { z28.h }, p0, [x23]\n" + "st1h { z29.h }, p0, [x23, x25, LSL #1]\n" + "addvl x23, x23, #1\n" + "st1h { z30.h }, p0, [x22]\n" + "st1h { z31.h }, p0, [x22, x25, LSL #1]\n" + "addvl x22, x22, #1\n" + "blt 3b\n" + "4:" // Tile loop: Channel tail + "movprfx z28, z19\n fmla z28.h, p3/M, z8.h, z9.h\n" + "movprfx z29, z19\n fmla z29.h, p3/M, z6.h, z9.h\n" + "ldr x3, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "mov p0.b, p2.b\n" + "movprfx z30, z19\n fmla z30.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z19\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ldr x2, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "ldr x24, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" + "add x3, x3, #0x1\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z29.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x8, x15, LSL #1]\n" + "add x20, x2, #0x1\n" + "cmp x3, x24\n" + "csel x2, x2, x20, LT\n" + "csel x3, x3, XZR, LT\n" + "cmp x2, x21\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x8, x17, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x8, x7, LSL #1]\n" + "fmla z28.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x14]\n" + "fmla z29.h, p3/M, z0.h, z16.h\n" + "fmla z28.h, p3/M, z4.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x16]\n" + "fmla z30.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x4, LSL #1]\n" + "fmla z28.h, p3/M, z2.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x16, x4, LSL #1]\n" + "fmla z30.h, p3/M, z0.h, z15.h\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x16, x17, LSL #1]\n" + "fmla z28.h, p3/M, z5.h, z13.h\n" + "fmla z29.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16, x15, LSL #1]\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x13, x4, LSL #1]\n" + "fmla z28.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x13]\n" + "fmla z29.h, p3/M, z7.h, z12.h\n" + "fmla z30.h, p3/M, z1.h, z16.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "fmla z28.h, p3/M, z7.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x14, x7, LSL #1]\n" + "fmla z30.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x13, x7, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x13, x17, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x13, x15, LSL #1]\n" + "fmla z30.h, p3/M, z5.h, z16.h\n" + "fmla z31.h, p3/M, z3.h, z16.h\n" + "fmla z30.h, p3/M, z8.h, z15.h\n" + "fmla z31.h, p3/M, z7.h, z14.h\n" + "fmla z31.h, p3/M, z6.h, z15.h\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + ".inst 0xc171ca5c // fclamp { z28.h-z31.h }, z18.h, z17.h\n" + "st1h { z28.h }, p0, [x23]\n" + "st1h { z29.h }, p0, [x23, x25, LSL #1]\n" + "st1h { z30.h }, p0, [x22]\n" + "st1h { z31.h }, p0, [x22, x25, LSL #1]\n" + "blt 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp new file mode 100644 index 0000000000..1bf3a84959 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst/generic_indirect.cpp @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_3x3_s2_output2x2_mla_depthfirst_indirect_impl( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + __fp16 *const *outptrs; + const void *params; + const __fp16 min, max; + const __fp16 *inptrs[25]; + + Args( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *const params, + const __fp16 min, + const __fp16 max + ) : outptrs(outptrs), params(params), min(min), max(max) + { + inptrs[0] = input_ptrs[12]; + inptrs[1] = input_ptrs[0]; + inptrs[2] = input_ptrs[1]; + inptrs[3] = input_ptrs[3]; + inptrs[4] = input_ptrs[4]; + inptrs[5] = input_ptrs[5]; + inptrs[6] = input_ptrs[6]; + inptrs[7] = input_ptrs[2]; + inptrs[8] = input_ptrs[8]; + inptrs[9] = input_ptrs[9]; + inptrs[10] = input_ptrs[7]; + inptrs[11] = input_ptrs[15]; + inptrs[12] = input_ptrs[10]; + inptrs[13] = input_ptrs[16]; + inptrs[14] = input_ptrs[11]; + inptrs[15] = input_ptrs[18]; + inptrs[16] = input_ptrs[13]; + inptrs[17] = input_ptrs[19]; + inptrs[18] = input_ptrs[20]; + inptrs[19] = input_ptrs[14]; + inptrs[20] = input_ptrs[21]; + inptrs[21] = input_ptrs[17]; + inptrs[22] = input_ptrs[23]; + inptrs[23] = input_ptrs[22]; + inptrs[24] = input_ptrs[24]; + + } + }; + + Args params_struct(input_ptrs, outptrs, params, + activation_min, activation_max); + + __asm__ __volatile__( + "ldr x20, [%x[params_struct], %[offsetof_args_outptrs]]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "add x16, %x[params_struct], %[offsetof_Args_inptrs]\n" + "mov x15, #0x0\n" + "ldr x14, [%x[params_struct], %[offsetof_args_params]]\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "cnth x13\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + "ld1rh { z19.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "ldp x12, x11, [x20, #0x0]\n" + "ldp x10, x9, [x20, #0x10]\n" + "cmp x13, %x[n_channels]\n" + "ld1rh { z18.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "sub x28, XZR, x13\n" + "ld1h { z17.h }, p3/Z, [x14]\n" + "addvl x14, x14, #1\n" + "ldp x27, x26, [x16, #0x0]\n" + "ldp x25, x24, [x16, #0x10]\n" + ".inst 0xa040a1c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "ldp x23, x22, [x16, #0x20]\n" + ".inst 0xa040a1c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "ldp x21, x20, [x16, #0x30]\n" + "ld1h { z8.h }, p3/Z, [x14]\n" + "addvl x14, x14, #1\n" + "ld1h { z9.h }, p2/Z, [x27, x15, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x26, x15, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x25, x15, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x24, x15, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x23, x15, LSL #1]\n" + "ld1h { z14.h }, p2/Z, [x22, x15, LSL #1]\n" + "ld1h { z15.h }, p2/Z, [x21, x15, LSL #1]\n" + "ld1h { z16.h }, p2/Z, [x20, x15, LSL #1]\n" + "bge 2f\n" + "1:" // Channel loop + "movprfx z28, z17\n fmla z28.h, p3/M, z8.h, z9.h\n" + "movprfx z29, z17\n fmla z29.h, p3/M, z6.h, z9.h\n" + "ldr x27, [x16, #0x40]\n" + "whilelt p1.h, x13, %x[n_channels]\n" + "ldr x26, [x16, #0x48]\n" + "movprfx z30, z17\n fmla z30.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z17\n fmla z31.h, p3/M, z0.h, z9.h\n" + "ld1h { z17.h }, p3/Z, [x14]\n" + "ldr x25, [x16, #0x50]\n" + "addvl x14, x14, #1\n" + "inch x28\n" + "ldr x24, [x16, #0x58]\n" + "mov p0.b, p2.b\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z29.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x20, [x16, #0x78]\n" + "ldr x23, [x16, #0x60]\n" + "ldr x22, [x16, #0x68]\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x27, x15, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x27, [x16, #0x80]\n" + "ldr x26, [x16, #0x88]\n" + "ldr x21, [x16, #0x70]\n" + "fmla z28.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z16.h\n" + "ldr x24, [x16, #0x98]\n" + "ldr x25, [x16, #0x90]\n" + "fmla z30.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z28.h, p3/M, z4.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x23, x15, LSL #1]\n" + "ldr x23, [x16, #0xa0]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x22, x15, LSL #1]\n" + "ldr x22, [x16, #0xa8]\n" + "fmla z28.h, p3/M, z2.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x21, x15, LSL #1]\n" + "ldr x21, [x16, #0xb0]\n" + "fmla z30.h, p3/M, z0.h, z15.h\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xc0]\n" + "fmla z28.h, p3/M, z5.h, z13.h\n" + "fmla z29.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x20, x15, LSL #1]\n" + "ldr x20, [x16, #0xb8]\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x23, x15, LSL #1]\n" + "fmla z28.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z29.h, p3/M, z7.h, z12.h\n" + "fmla z30.h, p3/M, z1.h, z16.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "fmla z28.h, p3/M, z7.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x22, x15, LSL #1]\n" + "fmla z30.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x20, x15, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x21, x15, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldp x27, x26, [x16, #0x0]\n" + "inch x15\n" + "ldp x25, x24, [x16, #0x10]\n" + "whilelt p2.h, x15, %x[n_channels]\n" + "ldp x23, x22, [x16, #0x20]\n" + "fmla z30.h, p3/M, z5.h, z16.h\n" + "ldp x21, x20, [x16, #0x30]\n" + "ld1h { z9.h }, p1/Z, [x27, x13, LSL #1]\n" + "fmla z31.h, p3/M, z3.h, z16.h\n" + "ld1h { z10.h }, p1/Z, [x26, x13, LSL #1]\n" + "ld1h { z12.h }, p1/Z, [x24, x13, LSL #1]\n" + "fmla z30.h, p3/M, z8.h, z15.h\n" + "ld1h { z13.h }, p1/Z, [x23, x13, LSL #1]\n" + "fmla z31.h, p3/M, z7.h, z14.h\n" + "ld1h { z14.h }, p1/Z, [x22, x13, LSL #1]\n" + "ld1h { z16.h }, p1/Z, [x20, x13, LSL #1]\n" + ".inst 0xa040a1c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "fmla z31.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p1/Z, [x21, x13, LSL #1]\n" + ".inst 0xa040a1c4 // ld1h { z4.h-z7.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + "ld1h { z11.h }, p1/Z, [x25, x13, LSL #1]\n" + "inch x13\n" + "cmp x13, %x[n_channels]\n" + "ld1h { z8.h }, p3/Z, [x14]\n" + "addvl x14, x14, #1\n" + ".inst 0xc172ca7c // fclamp { z28.h-z31.h }, z19.h, z18.h\n" + "st1h { z28.h }, p0, [x12, x28, LSL #1]\n" + "st1h { z29.h }, p0, [x11, x28, LSL #1]\n" + "st1h { z30.h }, p0, [x10, x28, LSL #1]\n" + "st1h { z31.h }, p0, [x9, x28, LSL #1]\n" + "blt 1b\n" + "2:" // Channel tail + "movprfx z28, z17\n fmla z28.h, p3/M, z8.h, z9.h\n" + "movprfx z29, z17\n fmla z29.h, p3/M, z6.h, z9.h\n" + "ldr x27, [x16, #0x40]\n" + "inch x28\n" + "ldr x26, [x16, #0x48]\n" + "movprfx z30, z17\n fmla z30.h, p3/M, z2.h, z9.h\n" + "movprfx z31, z17\n fmla z31.h, p3/M, z0.h, z9.h\n" + "mov p0.b, p2.b\n" + "ldr x25, [x16, #0x50]\n" + "ldr x24, [x16, #0x58]\n" + "fmla z28.h, p3/M, z0.h, z10.h\n" + "fmla z29.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x26, x15, LSL #1]\n" + "ldr x20, [x16, #0x78]\n" + "ldr x23, [x16, #0x60]\n" + "ldr x22, [x16, #0x68]\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x27, x15, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x25, x15, LSL #1]\n" + "ldr x27, [x16, #0x80]\n" + "ldr x26, [x16, #0x88]\n" + "ldr x21, [x16, #0x70]\n" + "fmla z28.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z16.h\n" + "ldr x24, [x16, #0x98]\n" + "ldr x25, [x16, #0x90]\n" + "fmla z30.h, p3/M, z3.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x26, x15, LSL #1]\n" + "fmla z28.h, p3/M, z4.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x23, x15, LSL #1]\n" + "ldr x23, [x16, #0xa0]\n" + "fmla z29.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x22, x15, LSL #1]\n" + "ldr x22, [x16, #0xa8]\n" + "fmla z28.h, p3/M, z2.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x21, x15, LSL #1]\n" + "ldr x21, [x16, #0xb0]\n" + "fmla z30.h, p3/M, z0.h, z15.h\n" + "fmla z29.h, p3/M, z5.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xc0]\n" + "fmla z28.h, p3/M, z5.h, z13.h\n" + "fmla z29.h, p3/M, z3.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x20, x15, LSL #1]\n" + "ldr x20, [x16, #0xb8]\n" + "fmla z30.h, p3/M, z4.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x24, x15, LSL #1]\n" + "fmla z31.h, p3/M, z4.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x23, x15, LSL #1]\n" + "fmla z28.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x25, x15, LSL #1]\n" + "fmla z29.h, p3/M, z7.h, z12.h\n" + "fmla z30.h, p3/M, z1.h, z16.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "fmla z28.h, p3/M, z7.h, z16.h\n" + "ld1h { z16.h }, p2/Z, [x22, x15, LSL #1]\n" + "fmla z30.h, p3/M, z6.h, z15.h\n" + "ld1h { z15.h }, p2/Z, [x20, x15, LSL #1]\n" + "fmla z29.h, p3/M, z8.h, z11.h\n" + "fmla z31.h, p3/M, z5.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x21, x15, LSL #1]\n" + "fmla z30.h, p3/M, z7.h, z13.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x27, x15, LSL #1]\n" + "fmla z30.h, p3/M, z5.h, z16.h\n" + "fmla z31.h, p3/M, z3.h, z16.h\n" + "fmla z30.h, p3/M, z8.h, z15.h\n" + "fmla z31.h, p3/M, z7.h, z14.h\n" + "fmla z31.h, p3/M, z6.h, z15.h\n" + "fmla z31.h, p3/M, z8.h, z11.h\n" + ".inst 0xc172ca7c // fclamp { z28.h-z31.h }, z19.h, z18.h\n" + "st1h { z28.h }, p0, [x12, x28, LSL #1]\n" + "st1h { z29.h }, p0, [x11, x28, LSL #1]\n" + "st1h { z30.h }, p0, [x10, x28, LSL #1]\n" + "st1h { z31.h }, p0, [x9, x28, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp new file mode 100644 index 0000000000..84263cb564 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst.hpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "src/core/NEON/kernels/arm_gemm/utils.hpp" + +#include <cstdint> + +#pragma once + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst_indirect_impl(const __fp16 *const *const input_ptrs, __fp16 *const *const outptrs, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); +void sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst_direct_impl(const unsigned int n_tile_rows, const unsigned int n_tile_cols, const __fp16 *inptr, int64_t ld_input_row, int64_t ld_input_col, __fp16 *outptr, int64_t ld_output_row, int64_t ld_output_col, const void *params, unsigned int n_channels, const __fp16 activation_min, const __fp16 activation_max); + +class sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst : public DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16> +{ + private: + using Parent = DepthwiseDepthfirstStrategy<__fp16, __fp16, __fp16, __fp16>; + Parent::IndirectKernelType m_indirect_kernel = sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst_indirect_impl; + Parent::DirectKernelType m_direct_kernel = sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst_direct_impl; + + public: + using return_type = __fp16; + constexpr static auto vl_type = arm_gemm::VLType::SME; + + constexpr static unsigned int kernel_rows = 5; + constexpr static unsigned int kernel_cols = 5; + + constexpr static unsigned int stride_rows = 1; + constexpr static unsigned int stride_cols = 1; + + constexpr static unsigned int output_rows = 2; + constexpr static unsigned int output_cols = 2; + + sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst(const CPUInfo *) + : Parent(output_rows, output_cols, kernel_rows, kernel_cols, stride_rows, stride_cols) {} + + arm_gemm::VLType get_vl_type(void) const override { return vl_type; } + + Parent::IndirectKernelType get_indirect_kernel() const override { return m_indirect_kernel; } + Parent::DirectKernelType get_direct_kernel() const override { return m_direct_kernel; } +}; + +} // namespace depthwise +} // namespace arm_conv diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst/generic_direct.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst/generic_direct.cpp new file mode 100644 index 0000000000..58b7824b98 --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst/generic_direct.cpp @@ -0,0 +1,586 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst_direct_impl( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + const uint64_t n_tile_rows, n_tile_cols; + const __fp16 *inptr; + const uint64_t ld_input_row; + const uint64_t ld_input_col; + __fp16 *outptr; + const uint64_t ld_output_row; + const uint64_t ld_output_col; + const void *params; + const __fp16 min, max; + + uint64_t tile_i = 0, tile_j = 0; + + Args( + const unsigned int n_tile_rows, + const unsigned int n_tile_cols, + const __fp16 *inptr, + int64_t ld_input_row, + int64_t ld_input_col, + __fp16 *outptr, + int64_t ld_output_row, + int64_t ld_output_col, + const void *params, + const float activation_min, + const float activation_max + ) : n_tile_rows(n_tile_rows), n_tile_cols(n_tile_cols), inptr(inptr), + ld_input_row(ld_input_row), ld_input_col(ld_input_col), outptr(outptr), + ld_output_row(ld_output_row), ld_output_col(ld_output_col), + params(params), min(activation_min), max(activation_max) + { + } + }; + + Args params_struct( + n_tile_rows, n_tile_cols, + inptr, ld_input_row, ld_input_col, + outptr, ld_output_row, ld_output_col, + params, activation_min, activation_max + ); + + __asm__ __volatile__( + ".inst 0xd503477f // SMSTART ZA\n" + "mov x2, #0x0\n" + "mov x3, #0x0\n" + "ptrue p3.b\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "1:" // Tile loop + "str x2, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "mov x22, #0x2\n" + "str x3, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "ldr x21, [%x[params_struct], %[offsetof_args_ld_input_row]]\n" + "ldr x4, [%x[params_struct], %[offsetof_args_ld_input_col]]\n" + "ldr x5, [%x[params_struct], %[offsetof_args_inptr]]\n" + "mul x20, x2, x21\n" // offset = tile_i * ld_input_row + "ldr x6, [%x[params_struct], %[offsetof_args_params]]\n" + "madd x20, x3, x4, x20\n" // offset += tile_j * ld_input_col + "mul x20, x20, x22\n" // offset *= kernel_stride * output_size + "add x7, x4, x4\n" + "add x5, x5, x20, LSL #1\n" // inptr[0] += offset * sizeof(__fp16) + "add x8, x5, x21, LSL #1\n" + "add x17, x7, x4\n" + "add x16, x8, x21, LSL #1\n" + "add x15, x17, x4\n" + "add x14, x16, x21, LSL #1\n" + "add x13, x15, x4\n" + "add x12, x14, x21, LSL #1\n" + "add x11, x12, x21, LSL #1\n" + "cbnz x3, 2f\n" + "ldr x25, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "lsl x10, %x[n_channels], #0x1\n" + "mov x21, #0x4\n" + "mul x21, x21, x4\n" + "add x9, x5, x4, LSL #1\n" + "add x28, x8, x4, LSL #1\n" + "add x27, x5, x7, LSL #1\n" + "sub x20, x25, x3\n" + "add x26, x8, x7, LSL #1\n" + "sub x20, x20, #0x1\n" + "add x25, x5, x17, LSL #1\n" + "and x20, x20, #0x3fffff\n" + "add x24, x5, x15, LSL #1\n" + "orr x10, x10, x20, LSL #22\n" + "add x23, x8, x13, LSL #1\n" + "orr x10, x10, x21, LSL #38\n" + "add x22, x8, x17, LSL #1\n" + "add x21, x8, x15, LSL #1\n" + "add x20, x5, x13, LSL #1\n" + ".inst 0xf8aa48ba // rprfm pldonce, x10, [x5]\n" + ".inst 0xf8aa493a // rprfm pldonce, x10, [x9]\n" + "add x9, x16, x4, LSL #1\n" + ".inst 0xf8aa491a // rprfm pldonce, x10, [x8]\n" + ".inst 0xf8aa4b9a // rprfm pldonce, x10, [x28]\n" + "add x28, x16, x7, LSL #1\n" + ".inst 0xf8aa4b7a // rprfm pldonce, x10, [x27]\n" + "add x27, x16, x17, LSL #1\n" + ".inst 0xf8aa4b5a // rprfm pldonce, x10, [x26]\n" + "add x26, x16, x15, LSL #1\n" + ".inst 0xf8aa4b3a // rprfm pldonce, x10, [x25]\n" + "add x25, x16, x13, LSL #1\n" + ".inst 0xf8aa4b1a // rprfm pldonce, x10, [x24]\n" + "add x24, x14, x4, LSL #1\n" + ".inst 0xf8aa4afa // rprfm pldonce, x10, [x23]\n" + "add x23, x14, x7, LSL #1\n" + ".inst 0xf8aa4a1a // rprfm pldonce, x10, [x16]\n" + ".inst 0xf8aa4ada // rprfm pldonce, x10, [x22]\n" + "add x22, x14, x17, LSL #1\n" + ".inst 0xf8aa4aba // rprfm pldonce, x10, [x21]\n" + "add x21, x14, x15, LSL #1\n" + ".inst 0xf8aa4a9a // rprfm pldonce, x10, [x20]\n" + "add x20, x14, x13, LSL #1\n" + ".inst 0xf8aa493a // rprfm pldonce, x10, [x9]\n" + "add x9, x12, x4, LSL #1\n" + ".inst 0xf8aa4b9a // rprfm pldonce, x10, [x28]\n" + "add x28, x12, x7, LSL #1\n" + ".inst 0xf8aa4b7a // rprfm pldonce, x10, [x27]\n" + "add x27, x12, x17, LSL #1\n" + ".inst 0xf8aa4b5a // rprfm pldonce, x10, [x26]\n" + "add x26, x12, x15, LSL #1\n" + ".inst 0xf8aa4b3a // rprfm pldonce, x10, [x25]\n" + "add x25, x12, x13, LSL #1\n" + ".inst 0xf8aa49da // rprfm pldonce, x10, [x14]\n" + ".inst 0xf8aa4b1a // rprfm pldonce, x10, [x24]\n" + "add x24, x11, x4, LSL #1\n" + ".inst 0xf8aa4afa // rprfm pldonce, x10, [x23]\n" + "add x23, x11, x7, LSL #1\n" + ".inst 0xf8aa4ada // rprfm pldonce, x10, [x22]\n" + "add x22, x11, x17, LSL #1\n" + ".inst 0xf8aa4aba // rprfm pldonce, x10, [x21]\n" + "add x21, x11, x15, LSL #1\n" + ".inst 0xf8aa4a9a // rprfm pldonce, x10, [x20]\n" + "add x20, x11, x13, LSL #1\n" + ".inst 0xf8aa499a // rprfm pldonce, x10, [x12]\n" + ".inst 0xf8aa493a // rprfm pldonce, x10, [x9]\n" + ".inst 0xf8aa4b9a // rprfm pldonce, x10, [x28]\n" + ".inst 0xf8aa4b7a // rprfm pldonce, x10, [x27]\n" + ".inst 0xf8aa4b5a // rprfm pldonce, x10, [x26]\n" + ".inst 0xf8aa4b3a // rprfm pldonce, x10, [x25]\n" + ".inst 0xf8aa497a // rprfm pldonce, x10, [x11]\n" + ".inst 0xf8aa4b1a // rprfm pldonce, x10, [x24]\n" + ".inst 0xf8aa4afa // rprfm pldonce, x10, [x23]\n" + ".inst 0xf8aa4ada // rprfm pldonce, x10, [x22]\n" + ".inst 0xf8aa4aba // rprfm pldonce, x10, [x21]\n" + ".inst 0xf8aa4a9a // rprfm pldonce, x10, [x20]\n" + "2:" // Tile loop: Prefetch input rows: End + "ldr x27, [%x[params_struct], %[offsetof_args_ld_output_row]]\n" + "mov x26, #0x2\n" + "cnth x25\n" + "ld1h { z18.h }, p3/Z, [x6]\n" + "ldr x24, [%x[params_struct], %[offsetof_args_ld_output_col]]\n" + "addvl x6, x6, #1\n" + "whilelt p2.h, XZR, %x[n_channels]\n" + "ld1rh { z17.h }, p3/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "ldr x23, [%x[params_struct], %[offsetof_args_outptr]]\n" + ".inst 0xa040a0c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "cmp x25, %x[n_channels]\n" + "mul x22, x2, x27\n" // offset = tile_i * ld_output_row + "ld1rh { z16.h }, p3/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "mov x21, #0x0\n" + "madd x22, x3, x24, x22\n" // offset += tile_j * ld_output_col + "sub x20, XZR, x25\n" + "ld1h { z4.h }, p3/Z, [x6]\n" + "mul x22, x22, x26\n" // offset *= output_tile_size + "ld1h { z5.h }, p2/Z, [x5]\n" + "addvl x6, x6, #1\n" + "add x23, x23, x22, LSL #1\n" // outptrs[0] += offset * sizeof(__fp16) + "ld1h { z6.h }, p2/Z, [x5, x4, LSL #1]\n" + "add x22, x23, x27, LSL #1\n" + "ld1h { z7.h }, p2/Z, [x8]\n" + "ld1h { z8.h }, p2/Z, [x8, x4, LSL #1]\n" + "ld1h { z9.h }, p2/Z, [x5, x7, LSL #1]\n" + "ld1h { z13.h }, p2/Z, [x8, x7, LSL #1]\n" + "ld1h { z11.h }, p2/Z, [x5, x17, LSL #1]\n" + "ld1h { z12.h }, p2/Z, [x5, x15, LSL #1]\n" + "ld1h { z10.h }, p2/Z, [x8, x13, LSL #1]\n" + "ld1h { z14.h }, p2/Z, [x16]\n" + "bge 4f\n" + "3:" // Tile loop: Channel loop + "movprfx z28, z18\n fmla z28.h, p3/M, z0.h, z5.h\n" + "movprfx z29, z18\n fmla z29.h, p3/M, z0.h, z6.h\n" + "ld1h { z5.h }, p2/Z, [x8, x17, LSL #1]\n" + "whilelt p1.h, x25, %x[n_channels]\n" + "movprfx z30, z18\n fmla z30.h, p3/M, z0.h, z7.h\n" + "movprfx z31, z18\n fmla z31.h, p3/M, z0.h, z8.h\n" + "ld1h { z0.h }, p3/Z, [x6]\n" + "inch x21\n" + "inch x25\n" + "mov p0.b, p2.b\n" + "inch x20\n" + "fmla z28.h, p3/M, z1.h, z6.h\n" + "ld1h { z6.h }, p2/Z, [x8, x15, LSL #1]\n" + "addvl x8, x8, #1\n" + "fmla z29.h, p3/M, z1.h, z9.h\n" + "fmla z30.h, p3/M, z1.h, z8.h\n" + "fmla z31.h, p3/M, z1.h, z13.h\n" + "ld1h { z1.h }, p3/Z, [x6, #1, MUL VL]\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x5, x13, LSL #1]\n" + "addvl x5, x5, #1\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "fmla z30.h, p3/M, z2.h, z13.h\n" + "fmla z31.h, p3/M, z2.h, z5.h\n" + "ld1h { z2.h }, p3/Z, [x6, #2, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16, x4, LSL #1]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z30.h, p3/M, z3.h, z5.h\n" + "fmla z31.h, p3/M, z3.h, z6.h\n" + "ld1h { z3.h }, p3/Z, [x6, #3, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x16, x7, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x16, x17, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z6.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "ld1h { z4.h }, p3/Z, [x6, #4, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z7.h\n" + "ld1h { z7.h }, p1/Z, [x8]\n" + "fmla z29.h, p3/M, z0.h, z8.h\n" + "fmla z30.h, p3/M, z0.h, z14.h\n" + "fmla z31.h, p3/M, z0.h, z11.h\n" + "ld1h { z0.h }, p3/Z, [x6, #5, MUL VL]\n" + "fmla z28.h, p3/M, z1.h, z8.h\n" + "ld1h { z8.h }, p2/Z, [x16, x13, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z13.h\n" + "fmla z30.h, p3/M, z1.h, z11.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "ld1h { z1.h }, p3/Z, [x6, #6, MUL VL]\n" + "fmla z28.h, p3/M, z2.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x16, x15, LSL #1]\n" + "addvl x16, x16, #1\n" + "fmla z29.h, p3/M, z2.h, z5.h\n" + "fmla z30.h, p3/M, z2.h, z12.h\n" + "fmla z31.h, p3/M, z2.h, z9.h\n" + "ld1h { z2.h }, p3/Z, [x6, #7, MUL VL]\n" + "addvl x6, x6, #16\n" + "ld1h { z18.h }, p3/Z, [x6, #4, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z5.h\n" + "ld1h { z5.h }, p2/Z, [x14]\n" + "fmla z29.h, p3/M, z3.h, z6.h\n" + "fmla z30.h, p3/M, z3.h, z9.h\n" + "fmla z31.h, p3/M, z3.h, z13.h\n" + "ld1h { z3.h }, p3/Z, [x6, #-8, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z6.h\n" + "ld1h { z6.h }, p2/Z, [x14, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x7, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z13.h\n" + "fmla z31.h, p3/M, z4.h, z8.h\n" + "ld1h { z4.h }, p3/Z, [x6, #-7, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x14, x13, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z11.h\n" + "fmla z30.h, p3/M, z0.h, z5.h\n" + "fmla z31.h, p3/M, z0.h, z6.h\n" + "ld1h { z0.h }, p3/Z, [x6, #-6, MUL VL]\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z12.h\n" + "fmla z30.h, p3/M, z1.h, z6.h\n" + "fmla z31.h, p3/M, z1.h, z10.h\n" + "ld1h { z1.h }, p3/Z, [x6, #-5, MUL VL]\n" + "fmla z28.h, p3/M, z2.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x15, LSL #1]\n" + "addvl x14, x14, #1\n" + "fmla z29.h, p3/M, z2.h, z9.h\n" + "fmla z30.h, p3/M, z2.h, z10.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ld1h { z2.h }, p3/Z, [x6, #-4, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x12]\n" + "fmla z29.h, p3/M, z3.h, z13.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z12.h\n" + "ld1h { z3.h }, p3/Z, [x6, #-3, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x12, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z8.h\n" + "ld1h { z8.h }, p2/Z, [x12, x15, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z12.h\n" + "fmla z31.h, p3/M, z4.h, z14.h\n" + "ld1h { z4.h }, p3/Z, [x6, #-2, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z5.h\n" + "ld1h { z5.h }, p2/Z, [x12, x7, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z6.h\n" + "fmla z30.h, p3/M, z0.h, z9.h\n" + "fmla z31.h, p3/M, z0.h, z13.h\n" + "ld1h { z0.h }, p3/Z, [x6, #-1, MUL VL]\n" + "fmla z28.h, p3/M, z1.h, z6.h\n" + "ld1h { z6.h }, p2/Z, [x12, x17, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z10.h\n" + "fmla z30.h, p3/M, z1.h, z13.h\n" + "fmla z31.h, p3/M, z1.h, z5.h\n" + "ld1h { z1.h }, p3/Z, [x6]\n" + "fmla z28.h, p3/M, z2.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x12, x13, LSL #1]\n" + "addvl x12, x12, #1\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "fmla z30.h, p3/M, z2.h, z5.h\n" + "fmla z31.h, p3/M, z2.h, z6.h\n" + "ld1h { z2.h }, p3/Z, [x6, #1, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x11]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z30.h, p3/M, z3.h, z6.h\n" + "fmla z31.h, p3/M, z3.h, z8.h\n" + "ld1h { z3.h }, p3/Z, [x6, #2, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z14.h\n" + "ld1h { z14.h }, p1/Z, [x16]\n" + "fmla z30.h, p3/M, z4.h, z8.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "ld1h { z4.h }, p3/Z, [x6, #3, MUL VL]\n" + "addvl x6, x6, #5\n" + "fmla z28.h, p3/M, z0.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x11, x7, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z13.h\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x11, x17, LSL #1]\n" + "fmla z31.h, p3/M, z0.h, z12.h\n" + "fmla z28.h, p3/M, z1.h, z13.h\n" + "ld1h { z13.h }, p1/Z, [x8, x7, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z5.h\n" + "fmla z30.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z31.h, p3/M, z1.h, z9.h\n" + "fmla z28.h, p3/M, z2.h, z5.h\n" + "ld1h { z5.h }, p1/Z, [x5]\n" + "fmla z29.h, p3/M, z2.h, z6.h\n" + "fmla z30.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x11, x13, LSL #1]\n" + "whilelt p2.h, x21, %x[n_channels]\n" + "cmp x25, %x[n_channels]\n" + "addvl x11, x11, #1\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "fmla z28.h, p3/M, z3.h, z6.h\n" + "ld1h { z6.h }, p1/Z, [x5, x4, LSL #1]\n" + "fmla z29.h, p3/M, z3.h, z8.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p1/Z, [x5, x17, LSL #1]\n" + "fmla z31.h, p3/M, z3.h, z12.h\n" + ".inst 0xa040a0c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x6]\n" + "addvl x6, x6, #4\n" + "fmla z28.h, p3/M, z4.h, z8.h\n" + "ld1h { z8.h }, p1/Z, [x8, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z10.h\n" + "ld1h { z10.h }, p1/Z, [x8, x13, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p1/Z, [x5, x15, LSL #1]\n" + "fmla z31.h, p3/M, z4.h, z9.h\n" + "ld1h { z9.h }, p1/Z, [x5, x7, LSL #1]\n" + "ld1h { z4.h }, p3/Z, [x6]\n" + "addvl x6, x6, #1\n" + ".inst 0xc170ca3c // fclamp { z28.h-z31.h }, z17.h, z16.h\n" + "st1h { z28.h }, p0, [x23]\n" + "st1h { z29.h }, p0, [x23, x24, LSL #1]\n" + "addvl x23, x23, #1\n" + "st1h { z30.h }, p0, [x22]\n" + "st1h { z31.h }, p0, [x22, x24, LSL #1]\n" + "addvl x22, x22, #1\n" + "blt 3b\n" + "4:" // Tile loop: Channel tail + "movprfx z28, z18\n fmla z28.h, p3/M, z0.h, z5.h\n" + "movprfx z29, z18\n fmla z29.h, p3/M, z0.h, z6.h\n" + "ld1h { z5.h }, p2/Z, [x8, x17, LSL #1]\n" + "ldr x3, [%x[params_struct], %[offsetof_args_tile_j]]\n" + "movprfx z30, z18\n fmla z30.h, p3/M, z0.h, z7.h\n" + "movprfx z31, z18\n fmla z31.h, p3/M, z0.h, z8.h\n" + "ld1h { z0.h }, p3/Z, [x6]\n" + "ldr x2, [%x[params_struct], %[offsetof_args_tile_i]]\n" + "ldr x25, [%x[params_struct], %[offsetof_args_n_tile_cols]]\n" + "mov p0.b, p2.b\n" + "ldr x21, [%x[params_struct], %[offsetof_args_n_tile_rows]]\n" + "add x3, x3, #0x1\n" + "fmla z28.h, p3/M, z1.h, z6.h\n" + "ld1h { z6.h }, p2/Z, [x8, x15, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z9.h\n" + "add x20, x2, #0x1\n" + "fmla z30.h, p3/M, z1.h, z8.h\n" + "fmla z31.h, p3/M, z1.h, z13.h\n" + "ld1h { z1.h }, p3/Z, [x6, #1, MUL VL]\n" + "cmp x3, x25\n" + "csel x2, x2, x20, LT\n" + "csel x3, x3, XZR, LT\n" + "cmp x2, x21\n" + "fmla z28.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x5, x13, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "fmla z30.h, p3/M, z2.h, z13.h\n" + "fmla z31.h, p3/M, z2.h, z5.h\n" + "ld1h { z2.h }, p3/Z, [x6, #2, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x16, x4, LSL #1]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z30.h, p3/M, z3.h, z5.h\n" + "fmla z31.h, p3/M, z3.h, z6.h\n" + "ld1h { z3.h }, p3/Z, [x6, #3, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x16, x7, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x16, x17, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z6.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "ld1h { z4.h }, p3/Z, [x6, #4, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z7.h\n" + "fmla z29.h, p3/M, z0.h, z8.h\n" + "fmla z30.h, p3/M, z0.h, z14.h\n" + "fmla z31.h, p3/M, z0.h, z11.h\n" + "ld1h { z0.h }, p3/Z, [x6, #5, MUL VL]\n" + "fmla z28.h, p3/M, z1.h, z8.h\n" + "ld1h { z8.h }, p2/Z, [x16, x13, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z13.h\n" + "fmla z30.h, p3/M, z1.h, z11.h\n" + "fmla z31.h, p3/M, z1.h, z12.h\n" + "ld1h { z1.h }, p3/Z, [x6, #6, MUL VL]\n" + "fmla z28.h, p3/M, z2.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x16, x15, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z5.h\n" + "fmla z30.h, p3/M, z2.h, z12.h\n" + "fmla z31.h, p3/M, z2.h, z9.h\n" + "ld1h { z2.h }, p3/Z, [x6, #7, MUL VL]\n" + "addvl x6, x6, #16\n" + "fmla z28.h, p3/M, z3.h, z5.h\n" + "ld1h { z5.h }, p2/Z, [x14]\n" + "fmla z29.h, p3/M, z3.h, z6.h\n" + "fmla z30.h, p3/M, z3.h, z9.h\n" + "fmla z31.h, p3/M, z3.h, z13.h\n" + "ld1h { z3.h }, p3/Z, [x6, #-8, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z6.h\n" + "ld1h { z6.h }, p2/Z, [x14, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x14, x7, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z13.h\n" + "fmla z31.h, p3/M, z4.h, z8.h\n" + "ld1h { z4.h }, p3/Z, [x6, #-7, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z14.h\n" + "ld1h { z14.h }, p2/Z, [x14, x13, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z11.h\n" + "fmla z30.h, p3/M, z0.h, z5.h\n" + "fmla z31.h, p3/M, z0.h, z6.h\n" + "ld1h { z0.h }, p3/Z, [x6, #-6, MUL VL]\n" + "fmla z28.h, p3/M, z1.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x14, x17, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z12.h\n" + "fmla z30.h, p3/M, z1.h, z6.h\n" + "fmla z31.h, p3/M, z1.h, z10.h\n" + "ld1h { z1.h }, p3/Z, [x6, #-5, MUL VL]\n" + "fmla z28.h, p3/M, z2.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x14, x15, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z9.h\n" + "fmla z30.h, p3/M, z2.h, z10.h\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "ld1h { z2.h }, p3/Z, [x6, #-4, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x12]\n" + "fmla z29.h, p3/M, z3.h, z13.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z12.h\n" + "ld1h { z3.h }, p3/Z, [x6, #-3, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z13.h\n" + "ld1h { z13.h }, p2/Z, [x12, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z8.h\n" + "ld1h { z8.h }, p2/Z, [x12, x15, LSL #1]\n" + "fmla z30.h, p3/M, z4.h, z12.h\n" + "fmla z31.h, p3/M, z4.h, z14.h\n" + "ld1h { z4.h }, p3/Z, [x6, #-2, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z5.h\n" + "ld1h { z5.h }, p2/Z, [x12, x7, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z6.h\n" + "fmla z30.h, p3/M, z0.h, z9.h\n" + "fmla z31.h, p3/M, z0.h, z13.h\n" + "ld1h { z0.h }, p3/Z, [x6, #-1, MUL VL]\n" + "fmla z28.h, p3/M, z1.h, z6.h\n" + "ld1h { z6.h }, p2/Z, [x12, x17, LSL #1]\n" + "fmla z29.h, p3/M, z1.h, z10.h\n" + "fmla z30.h, p3/M, z1.h, z13.h\n" + "fmla z31.h, p3/M, z1.h, z5.h\n" + "ld1h { z1.h }, p3/Z, [x6]\n" + "fmla z28.h, p3/M, z2.h, z10.h\n" + "ld1h { z10.h }, p2/Z, [x12, x13, LSL #1]\n" + "fmla z29.h, p3/M, z2.h, z11.h\n" + "fmla z30.h, p3/M, z2.h, z5.h\n" + "fmla z31.h, p3/M, z2.h, z6.h\n" + "ld1h { z2.h }, p3/Z, [x6, #1, MUL VL]\n" + "fmla z28.h, p3/M, z3.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x11]\n" + "fmla z29.h, p3/M, z3.h, z12.h\n" + "fmla z30.h, p3/M, z3.h, z6.h\n" + "fmla z31.h, p3/M, z3.h, z8.h\n" + "ld1h { z3.h }, p3/Z, [x6, #2, MUL VL]\n" + "fmla z28.h, p3/M, z4.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x4, LSL #1]\n" + "fmla z29.h, p3/M, z4.h, z14.h\n" + "fmla z30.h, p3/M, z4.h, z8.h\n" + "fmla z31.h, p3/M, z4.h, z10.h\n" + "ld1h { z4.h }, p3/Z, [x6, #3, MUL VL]\n" + "fmla z28.h, p3/M, z0.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x11, x7, LSL #1]\n" + "fmla z29.h, p3/M, z0.h, z13.h\n" + "fmla z30.h, p3/M, z0.h, z11.h\n" + "ld1h { z11.h }, p2/Z, [x11, x17, LSL #1]\n" + "fmla z31.h, p3/M, z0.h, z12.h\n" + "fmla z28.h, p3/M, z1.h, z13.h\n" + "fmla z29.h, p3/M, z1.h, z5.h\n" + "fmla z30.h, p3/M, z1.h, z12.h\n" + "ld1h { z12.h }, p2/Z, [x11, x15, LSL #1]\n" + "fmla z31.h, p3/M, z1.h, z9.h\n" + "fmla z28.h, p3/M, z2.h, z5.h\n" + "fmla z29.h, p3/M, z2.h, z6.h\n" + "fmla z30.h, p3/M, z2.h, z9.h\n" + "ld1h { z9.h }, p2/Z, [x11, x13, LSL #1]\n" + "fmla z31.h, p3/M, z2.h, z11.h\n" + "fmla z28.h, p3/M, z3.h, z6.h\n" + "fmla z29.h, p3/M, z3.h, z8.h\n" + "fmla z30.h, p3/M, z3.h, z11.h\n" + "fmla z31.h, p3/M, z3.h, z12.h\n" + "fmla z28.h, p3/M, z4.h, z8.h\n" + "fmla z29.h, p3/M, z4.h, z10.h\n" + "fmla z30.h, p3/M, z4.h, z12.h\n" + "fmla z31.h, p3/M, z4.h, z9.h\n" + ".inst 0xc170ca3c // fclamp { z28.h-z31.h }, z17.h, z16.h\n" + "st1h { z28.h }, p0, [x23]\n" + "st1h { z29.h }, p0, [x23, x24, LSL #1]\n" + "st1h { z30.h }, p0, [x22]\n" + "st1h { z31.h }, p0, [x22, x24, LSL #1]\n" + "blt 1b\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_args_inptr] "I" (offsetof(Args, inptr)), [offsetof_args_ld_input_col] "I" (offsetof(Args, ld_input_col)), [offsetof_args_ld_input_row] "I" (offsetof(Args, ld_input_row)), [offsetof_args_ld_output_col] "I" (offsetof(Args, ld_output_col)), [offsetof_args_ld_output_row] "I" (offsetof(Args, ld_output_row)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_n_tile_cols] "I" (offsetof(Args, n_tile_cols)), [offsetof_args_n_tile_rows] "I" (offsetof(Args, n_tile_rows)), [offsetof_args_outptr] "I" (offsetof(Args, outptr)), [offsetof_args_params] "I" (offsetof(Args, params)), [offsetof_args_tile_i] "I" (offsetof(Args, tile_i)), [offsetof_args_tile_j] "I" (offsetof(Args, tile_j)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst/generic_indirect.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst/generic_indirect.cpp new file mode 100644 index 0000000000..313036876e --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst/generic_indirect.cpp @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include <cstddef> +#include <cstdint> + +#if defined(ARM_COMPUTE_ENABLE_SME2) + +namespace arm_conv { +namespace depthwise { + +void sme2_fp16_nhwc_5x5_s1_output2x2_mla_depthfirst_indirect_impl( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *params, + unsigned int n_channels, + const __fp16 activation_min, + const __fp16 activation_max +) +{ + struct Args + { + __fp16 *const *outptrs; + const void *params; + const __fp16 min, max; + const __fp16 *inptrs[36]; + + Args( + const __fp16 *const *const input_ptrs, + __fp16 *const *const outptrs, + const void *const params, + const __fp16 min, + const __fp16 max + ) : outptrs(outptrs), params(params), min(min), max(max) + { + inptrs[0] = input_ptrs[0]; + inptrs[1] = input_ptrs[1]; + inptrs[2] = input_ptrs[6]; + inptrs[3] = input_ptrs[7]; + inptrs[4] = input_ptrs[2]; + inptrs[5] = input_ptrs[8]; + inptrs[6] = input_ptrs[3]; + inptrs[7] = input_ptrs[4]; + inptrs[8] = input_ptrs[11]; + inptrs[9] = input_ptrs[12]; + inptrs[10] = input_ptrs[9]; + inptrs[11] = input_ptrs[10]; + inptrs[12] = input_ptrs[5]; + inptrs[13] = input_ptrs[13]; + inptrs[14] = input_ptrs[14]; + inptrs[15] = input_ptrs[15]; + inptrs[16] = input_ptrs[16]; + inptrs[17] = input_ptrs[17]; + inptrs[18] = input_ptrs[18]; + inptrs[19] = input_ptrs[19]; + inptrs[20] = input_ptrs[20]; + inptrs[21] = input_ptrs[21]; + inptrs[22] = input_ptrs[22]; + inptrs[23] = input_ptrs[23]; + inptrs[24] = input_ptrs[24]; + inptrs[25] = input_ptrs[25]; + inptrs[26] = input_ptrs[26]; + inptrs[27] = input_ptrs[27]; + inptrs[28] = input_ptrs[28]; + inptrs[29] = input_ptrs[29]; + inptrs[30] = input_ptrs[30]; + inptrs[31] = input_ptrs[31]; + inptrs[32] = input_ptrs[32]; + inptrs[33] = input_ptrs[33]; + inptrs[34] = input_ptrs[34]; + inptrs[35] = input_ptrs[35]; + + } + }; + + Args params_struct(input_ptrs, outptrs, params, + activation_min, activation_max); + + __asm__ __volatile__( + "ldr x20, [%x[params_struct], %[offsetof_args_outptrs]]\n" + "add x16, %x[params_struct], %[offsetof_Args_inptrs]\n" + ".inst 0xd503477f // SMSTART ZA\n" + "mov x15, #0x0\n" + "ldr x14, [%x[params_struct], %[offsetof_args_params]]\n" + ".inst 0x25207810 // ptrue pn8.b\n" + "whilelt p3.h, XZR, %x[n_channels]\n" + "ptrue p2.b\n" + "cnth x13\n" + "ldp x12, x11, [x20, #0x0]\n" + "ldp x10, x9, [x20, #0x10]\n" + "cmp x13, %x[n_channels]\n" + "ld1rh { z18.h }, p2/Z, [%x[params_struct], %[offsetof_args_min]]\n" + "sub x28, XZR, x13\n" + "ldp x27, x26, [x16, #0x0]\n" + "ld1h { z17.h }, p2/Z, [x14]\n" + "addvl x14, x14, #1\n" + "ldp x25, x24, [x16, #0x10]\n" + ".inst 0xa040a1c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "ldp x23, x22, [x16, #0x20]\n" + "ld1rh { z16.h }, p2/Z, [%x[params_struct], %[offsetof_args_max]]\n" + "ld1h { z5.h }, p3/Z, [x27, x15, LSL #1]\n" + "ldp x21, x20, [x16, #0x30]\n" + "ld1h { z6.h }, p3/Z, [x26, x15, LSL #1]\n" + "ldp x27, x26, [x16, #0x40]\n" + "ld1h { z4.h }, p2/Z, [x14]\n" + "addvl x14, x14, #1\n" + "ld1h { z7.h }, p3/Z, [x25, x15, LSL #1]\n" + "ld1h { z8.h }, p3/Z, [x24, x15, LSL #1]\n" + "ld1h { z9.h }, p3/Z, [x23, x15, LSL #1]\n" + "ld1h { z13.h }, p3/Z, [x22, x15, LSL #1]\n" + "ld1h { z11.h }, p3/Z, [x21, x15, LSL #1]\n" + "ld1h { z12.h }, p3/Z, [x20, x15, LSL #1]\n" + "ld1h { z10.h }, p3/Z, [x27, x15, LSL #1]\n" + "ld1h { z14.h }, p3/Z, [x26, x15, LSL #1]\n" + "bge 2f\n" + "1:" // Channel loop + "movprfx z28, z17\n fmla z28.h, p2/M, z0.h, z5.h\n" + "movprfx z29, z17\n fmla z29.h, p2/M, z0.h, z6.h\n" + "ldr x25, [x16, #0x50]\n" + "whilelt p1.h, x13, %x[n_channels]\n" + "movprfx z30, z17\n fmla z30.h, p2/M, z0.h, z7.h\n" + "movprfx z31, z17\n fmla z31.h, p2/M, z0.h, z8.h\n" + "ldr x24, [x16, #0x58]\n" + "ld1h { z0.h }, p2/Z, [x14]\n" + "ldr x23, [x16, #0x60]\n" + "inch x28\n" + "mov p0.b, p3.b\n" + "ld1h { z5.h }, p3/Z, [x25, x15, LSL #1]\n" + "ldr x22, [x16, #0x68]\n" + "fmla z28.h, p2/M, z1.h, z6.h\n" + "fmla z29.h, p2/M, z1.h, z9.h\n" + "ld1h { z6.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldr x21, [x16, #0x70]\n" + "fmla z30.h, p2/M, z1.h, z8.h\n" + "fmla z31.h, p2/M, z1.h, z13.h\n" + "ld1h { z1.h }, p2/Z, [x14, #1, MUL VL]\n" + "ldr x20, [x16, #0x78]\n" + "ldr x27, [x16, #0x80]\n" + "fmla z28.h, p2/M, z2.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x23, x15, LSL #1]\n" + "fmla z29.h, p2/M, z2.h, z11.h\n" + "ldr x26, [x16, #0x88]\n" + "fmla z30.h, p2/M, z2.h, z13.h\n" + "fmla z31.h, p2/M, z2.h, z5.h\n" + "ld1h { z2.h }, p2/Z, [x14, #2, MUL VL]\n" + "ldr x25, [x16, #0x90]\n" + "ldr x24, [x16, #0x98]\n" + "fmla z28.h, p2/M, z3.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x22, x15, LSL #1]\n" + "fmla z29.h, p2/M, z3.h, z12.h\n" + "ldr x23, [x16, #0xa0]\n" + "fmla z30.h, p2/M, z3.h, z5.h\n" + "fmla z31.h, p2/M, z3.h, z6.h\n" + "ld1h { z3.h }, p2/Z, [x14, #3, MUL VL]\n" + "ldr x22, [x16, #0xa8]\n" + "fmla z28.h, p2/M, z4.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x21, x15, LSL #1]\n" + "ldr x21, [x16, #0xb0]\n" + "fmla z29.h, p2/M, z4.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x20, x15, LSL #1]\n" + "ldr x20, [x16, #0xb8]\n" + "fmla z30.h, p2/M, z4.h, z6.h\n" + "fmla z31.h, p2/M, z4.h, z10.h\n" + "ld1h { z4.h }, p2/Z, [x14, #4, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z7.h\n" + "fmla z29.h, p2/M, z0.h, z8.h\n" + "fmla z30.h, p2/M, z0.h, z14.h\n" + "fmla z31.h, p2/M, z0.h, z11.h\n" + "ld1h { z0.h }, p2/Z, [x14, #5, MUL VL]\n" + "fmla z28.h, p2/M, z1.h, z8.h\n" + "ld1h { z8.h }, p3/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xc8]\n" + "fmla z29.h, p2/M, z1.h, z13.h\n" + "fmla z30.h, p2/M, z1.h, z11.h\n" + "fmla z31.h, p2/M, z1.h, z12.h\n" + "ld1h { z1.h }, p2/Z, [x14, #6, MUL VL]\n" + "fmla z28.h, p2/M, z2.h, z13.h\n" + "ld1h { z13.h }, p3/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xc0]\n" + "fmla z29.h, p2/M, z2.h, z5.h\n" + "fmla z30.h, p2/M, z2.h, z12.h\n" + "fmla z31.h, p2/M, z2.h, z9.h\n" + "ld1h { z2.h }, p2/Z, [x14, #7, MUL VL]\n" + "addvl x14, x14, #16\n" + "ld1h { z17.h }, p2/Z, [x14, #4, MUL VL]\n" + "fmla z28.h, p2/M, z3.h, z5.h\n" + "ld1h { z5.h }, p3/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0xd0]\n" + "fmla z29.h, p2/M, z3.h, z6.h\n" + "fmla z30.h, p2/M, z3.h, z9.h\n" + "fmla z31.h, p2/M, z3.h, z13.h\n" + "ld1h { z3.h }, p2/Z, [x14, #-8, MUL VL]\n" + "fmla z28.h, p2/M, z4.h, z6.h\n" + "ld1h { z6.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0xd8]\n" + "fmla z29.h, p2/M, z4.h, z10.h\n" + "ld1h { z10.h }, p3/Z, [x23, x15, LSL #1]\n" + "ldr x23, [x16, #0xe0]\n" + "fmla z30.h, p2/M, z4.h, z13.h\n" + "fmla z31.h, p2/M, z4.h, z8.h\n" + "ld1h { z4.h }, p2/Z, [x14, #-7, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z14.h\n" + "ld1h { z14.h }, p3/Z, [x20, x15, LSL #1]\n" + "ldr x20, [x16, #0xf8]\n" + "fmla z29.h, p2/M, z0.h, z11.h\n" + "fmla z30.h, p2/M, z0.h, z5.h\n" + "fmla z31.h, p2/M, z0.h, z6.h\n" + "ld1h { z0.h }, p2/Z, [x14, #-6, MUL VL]\n" + "fmla z28.h, p2/M, z1.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x22, x15, LSL #1]\n" + "ldr x22, [x16, #0xe8]\n" + "fmla z29.h, p2/M, z1.h, z12.h\n" + "fmla z30.h, p2/M, z1.h, z6.h\n" + "fmla z31.h, p2/M, z1.h, z10.h\n" + "ld1h { z1.h }, p2/Z, [x14, #-5, MUL VL]\n" + "fmla z28.h, p2/M, z2.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x21, x15, LSL #1]\n" + "ldr x21, [x16, #0xf0]\n" + "fmla z29.h, p2/M, z2.h, z9.h\n" + "fmla z30.h, p2/M, z2.h, z10.h\n" + "fmla z31.h, p2/M, z2.h, z11.h\n" + "ld1h { z2.h }, p2/Z, [x14, #-4, MUL VL]\n" + "fmla z28.h, p2/M, z3.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0x100]\n" + "fmla z29.h, p2/M, z3.h, z13.h\n" + "fmla z30.h, p2/M, z3.h, z11.h\n" + "fmla z31.h, p2/M, z3.h, z12.h\n" + "ld1h { z3.h }, p2/Z, [x14, #-3, MUL VL]\n" + "fmla z28.h, p2/M, z4.h, z13.h\n" + "ld1h { z13.h }, p3/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0x108]\n" + "fmla z29.h, p2/M, z4.h, z8.h\n" + "ld1h { z8.h }, p3/Z, [x23, x15, LSL #1]\n" + "fmla z30.h, p2/M, z4.h, z12.h\n" + "fmla z31.h, p2/M, z4.h, z14.h\n" + "ld1h { z4.h }, p2/Z, [x14, #-2, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z5.h\n" + "ld1h { z5.h }, p3/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0x110]\n" + "fmla z29.h, p2/M, z0.h, z6.h\n" + "fmla z30.h, p2/M, z0.h, z9.h\n" + "fmla z31.h, p2/M, z0.h, z13.h\n" + "ld1h { z0.h }, p2/Z, [x14, #-1, MUL VL]\n" + "fmla z28.h, p2/M, z1.h, z6.h\n" + "ld1h { z6.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0x118]\n" + "fmla z29.h, p2/M, z1.h, z10.h\n" + "fmla z30.h, p2/M, z1.h, z13.h\n" + "fmla z31.h, p2/M, z1.h, z5.h\n" + "ld1h { z1.h }, p2/Z, [x14]\n" + "fmla z28.h, p2/M, z2.h, z10.h\n" + "ld1h { z10.h }, p3/Z, [x22, x15, LSL #1]\n" + "fmla z29.h, p2/M, z2.h, z11.h\n" + "fmla z30.h, p2/M, z2.h, z5.h\n" + "fmla z31.h, p2/M, z2.h, z6.h\n" + "ld1h { z2.h }, p2/Z, [x14, #1, MUL VL]\n" + "fmla z28.h, p2/M, z3.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x21, x15, LSL #1]\n" + "fmla z29.h, p2/M, z3.h, z12.h\n" + "fmla z30.h, p2/M, z3.h, z6.h\n" + "fmla z31.h, p2/M, z3.h, z8.h\n" + "ld1h { z3.h }, p2/Z, [x14, #2, MUL VL]\n" + "fmla z28.h, p2/M, z4.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x20, x15, LSL #1]\n" + "fmla z29.h, p2/M, z4.h, z14.h\n" + "fmla z30.h, p2/M, z4.h, z8.h\n" + "fmla z31.h, p2/M, z4.h, z10.h\n" + "ld1h { z4.h }, p2/Z, [x14, #3, MUL VL]\n" + "addvl x14, x14, #5\n" + "fmla z28.h, p2/M, z0.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x27, x15, LSL #1]\n" + "fmla z29.h, p2/M, z0.h, z13.h\n" + "fmla z30.h, p2/M, z0.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x26, x15, LSL #1]\n" + "ldp x27, x26, [x16, #0x0]\n" + "fmla z31.h, p2/M, z0.h, z12.h\n" + "fmla z28.h, p2/M, z1.h, z13.h\n" + "fmla z29.h, p2/M, z1.h, z5.h\n" + "fmla z30.h, p2/M, z1.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x25, x15, LSL #1]\n" + "fmla z31.h, p2/M, z1.h, z9.h\n" + "fmla z28.h, p2/M, z2.h, z5.h\n" + "ld1h { z5.h }, p1/Z, [x27, x13, LSL #1]\n" + "fmla z29.h, p2/M, z2.h, z6.h\n" + "fmla z30.h, p2/M, z2.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldp x25, x24, [x16, #0x10]\n" + "ldp x23, x22, [x16, #0x20]\n" + "inch x15\n" + "ldp x21, x20, [x16, #0x30]\n" + "whilelt p3.h, x15, %x[n_channels]\n" + "fmla z31.h, p2/M, z2.h, z11.h\n" + "fmla z28.h, p2/M, z3.h, z6.h\n" + "ld1h { z6.h }, p1/Z, [x26, x13, LSL #1]\n" + "ldp x27, x26, [x16, #0x40]\n" + "fmla z29.h, p2/M, z3.h, z8.h\n" + "fmla z30.h, p2/M, z3.h, z11.h\n" + "ld1h { z7.h }, p1/Z, [x25, x13, LSL #1]\n" + "ld1h { z13.h }, p1/Z, [x22, x13, LSL #1]\n" + "fmla z31.h, p2/M, z3.h, z12.h\n" + "fmla z28.h, p2/M, z4.h, z8.h\n" + "ld1h { z8.h }, p1/Z, [x24, x13, LSL #1]\n" + "fmla z29.h, p2/M, z4.h, z10.h\n" + "fmla z30.h, p2/M, z4.h, z12.h\n" + "ld1h { z11.h }, p1/Z, [x21, x13, LSL #1]\n" + "ld1h { z12.h }, p1/Z, [x20, x13, LSL #1]\n" + "fmla z31.h, p2/M, z4.h, z9.h\n" + "ld1h { z9.h }, p1/Z, [x23, x13, LSL #1]\n" + "ld1h { z10.h }, p1/Z, [x27, x13, LSL #1]\n" + "ld1h { z14.h }, p1/Z, [x26, x13, LSL #1]\n" + "inch x13\n" + ".inst 0xa040a1c0 // ld1h { z0.h-z3.h }, pn8.b/Z, [x14]\n" + "addvl x14, x14, #4\n" + "cmp x13, %x[n_channels]\n" + ".inst 0xc170ca5c // fclamp { z28.h-z31.h }, z18.h, z16.h\n" + "ld1h { z4.h }, p2/Z, [x14]\n" + "addvl x14, x14, #1\n" + "st1h { z28.h }, p0, [x12, x28, LSL #1]\n" + "st1h { z29.h }, p0, [x11, x28, LSL #1]\n" + "st1h { z30.h }, p0, [x10, x28, LSL #1]\n" + "st1h { z31.h }, p0, [x9, x28, LSL #1]\n" + "blt 1b\n" + "2:" // Channel tail + "movprfx z28, z17\n fmla z28.h, p2/M, z0.h, z5.h\n" + "movprfx z29, z17\n fmla z29.h, p2/M, z0.h, z6.h\n" + "ldr x25, [x16, #0x50]\n" + "inch x28\n" + "movprfx z30, z17\n fmla z30.h, p2/M, z0.h, z7.h\n" + "movprfx z31, z17\n fmla z31.h, p2/M, z0.h, z8.h\n" + "ldr x24, [x16, #0x58]\n" + "ld1h { z0.h }, p2/Z, [x14]\n" + "ldr x23, [x16, #0x60]\n" + "mov p0.b, p3.b\n" + "ld1h { z5.h }, p3/Z, [x25, x15, LSL #1]\n" + "ldr x22, [x16, #0x68]\n" + "fmla z28.h, p2/M, z1.h, z6.h\n" + "fmla z29.h, p2/M, z1.h, z9.h\n" + "ld1h { z6.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldr x21, [x16, #0x70]\n" + "fmla z30.h, p2/M, z1.h, z8.h\n" + "fmla z31.h, p2/M, z1.h, z13.h\n" + "ld1h { z1.h }, p2/Z, [x14, #1, MUL VL]\n" + "ldr x20, [x16, #0x78]\n" + "ldr x27, [x16, #0x80]\n" + "fmla z28.h, p2/M, z2.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x23, x15, LSL #1]\n" + "fmla z29.h, p2/M, z2.h, z11.h\n" + "ldr x26, [x16, #0x88]\n" + "fmla z30.h, p2/M, z2.h, z13.h\n" + "fmla z31.h, p2/M, z2.h, z5.h\n" + "ld1h { z2.h }, p2/Z, [x14, #2, MUL VL]\n" + "ldr x25, [x16, #0x90]\n" + "ldr x24, [x16, #0x98]\n" + "fmla z28.h, p2/M, z3.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x22, x15, LSL #1]\n" + "fmla z29.h, p2/M, z3.h, z12.h\n" + "ldr x23, [x16, #0xa0]\n" + "fmla z30.h, p2/M, z3.h, z5.h\n" + "fmla z31.h, p2/M, z3.h, z6.h\n" + "ld1h { z3.h }, p2/Z, [x14, #3, MUL VL]\n" + "ldr x22, [x16, #0xa8]\n" + "fmla z28.h, p2/M, z4.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x21, x15, LSL #1]\n" + "ldr x21, [x16, #0xb0]\n" + "fmla z29.h, p2/M, z4.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x20, x15, LSL #1]\n" + "ldr x20, [x16, #0xb8]\n" + "fmla z30.h, p2/M, z4.h, z6.h\n" + "fmla z31.h, p2/M, z4.h, z10.h\n" + "ld1h { z4.h }, p2/Z, [x14, #4, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z7.h\n" + "fmla z29.h, p2/M, z0.h, z8.h\n" + "fmla z30.h, p2/M, z0.h, z14.h\n" + "fmla z31.h, p2/M, z0.h, z11.h\n" + "ld1h { z0.h }, p2/Z, [x14, #5, MUL VL]\n" + "fmla z28.h, p2/M, z1.h, z8.h\n" + "ld1h { z8.h }, p3/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0xc8]\n" + "fmla z29.h, p2/M, z1.h, z13.h\n" + "fmla z30.h, p2/M, z1.h, z11.h\n" + "fmla z31.h, p2/M, z1.h, z12.h\n" + "ld1h { z1.h }, p2/Z, [x14, #6, MUL VL]\n" + "fmla z28.h, p2/M, z2.h, z13.h\n" + "ld1h { z13.h }, p3/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0xc0]\n" + "fmla z29.h, p2/M, z2.h, z5.h\n" + "fmla z30.h, p2/M, z2.h, z12.h\n" + "fmla z31.h, p2/M, z2.h, z9.h\n" + "ld1h { z2.h }, p2/Z, [x14, #7, MUL VL]\n" + "addvl x14, x14, #16\n" + "fmla z28.h, p2/M, z3.h, z5.h\n" + "ld1h { z5.h }, p3/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0xd0]\n" + "fmla z29.h, p2/M, z3.h, z6.h\n" + "fmla z30.h, p2/M, z3.h, z9.h\n" + "fmla z31.h, p2/M, z3.h, z13.h\n" + "ld1h { z3.h }, p2/Z, [x14, #-8, MUL VL]\n" + "fmla z28.h, p2/M, z4.h, z6.h\n" + "ld1h { z6.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0xd8]\n" + "fmla z29.h, p2/M, z4.h, z10.h\n" + "ld1h { z10.h }, p3/Z, [x23, x15, LSL #1]\n" + "ldr x23, [x16, #0xe0]\n" + "fmla z30.h, p2/M, z4.h, z13.h\n" + "fmla z31.h, p2/M, z4.h, z8.h\n" + "ld1h { z4.h }, p2/Z, [x14, #-7, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z14.h\n" + "ld1h { z14.h }, p3/Z, [x20, x15, LSL #1]\n" + "ldr x20, [x16, #0xf8]\n" + "fmla z29.h, p2/M, z0.h, z11.h\n" + "fmla z30.h, p2/M, z0.h, z5.h\n" + "fmla z31.h, p2/M, z0.h, z6.h\n" + "ld1h { z0.h }, p2/Z, [x14, #-6, MUL VL]\n" + "fmla z28.h, p2/M, z1.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x22, x15, LSL #1]\n" + "ldr x22, [x16, #0xe8]\n" + "fmla z29.h, p2/M, z1.h, z12.h\n" + "fmla z30.h, p2/M, z1.h, z6.h\n" + "fmla z31.h, p2/M, z1.h, z10.h\n" + "ld1h { z1.h }, p2/Z, [x14, #-5, MUL VL]\n" + "fmla z28.h, p2/M, z2.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x21, x15, LSL #1]\n" + "ldr x21, [x16, #0xf0]\n" + "fmla z29.h, p2/M, z2.h, z9.h\n" + "fmla z30.h, p2/M, z2.h, z10.h\n" + "fmla z31.h, p2/M, z2.h, z11.h\n" + "ld1h { z2.h }, p2/Z, [x14, #-4, MUL VL]\n" + "fmla z28.h, p2/M, z3.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x27, x15, LSL #1]\n" + "ldr x27, [x16, #0x100]\n" + "fmla z29.h, p2/M, z3.h, z13.h\n" + "fmla z30.h, p2/M, z3.h, z11.h\n" + "fmla z31.h, p2/M, z3.h, z12.h\n" + "ld1h { z3.h }, p2/Z, [x14, #-3, MUL VL]\n" + "fmla z28.h, p2/M, z4.h, z13.h\n" + "ld1h { z13.h }, p3/Z, [x26, x15, LSL #1]\n" + "ldr x26, [x16, #0x108]\n" + "fmla z29.h, p2/M, z4.h, z8.h\n" + "ld1h { z8.h }, p3/Z, [x23, x15, LSL #1]\n" + "fmla z30.h, p2/M, z4.h, z12.h\n" + "fmla z31.h, p2/M, z4.h, z14.h\n" + "ld1h { z4.h }, p2/Z, [x14, #-2, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z5.h\n" + "ld1h { z5.h }, p3/Z, [x25, x15, LSL #1]\n" + "ldr x25, [x16, #0x110]\n" + "fmla z29.h, p2/M, z0.h, z6.h\n" + "fmla z30.h, p2/M, z0.h, z9.h\n" + "fmla z31.h, p2/M, z0.h, z13.h\n" + "ld1h { z0.h }, p2/Z, [x14, #-1, MUL VL]\n" + "fmla z28.h, p2/M, z1.h, z6.h\n" + "ld1h { z6.h }, p3/Z, [x24, x15, LSL #1]\n" + "ldr x24, [x16, #0x118]\n" + "fmla z29.h, p2/M, z1.h, z10.h\n" + "fmla z30.h, p2/M, z1.h, z13.h\n" + "fmla z31.h, p2/M, z1.h, z5.h\n" + "ld1h { z1.h }, p2/Z, [x14]\n" + "fmla z28.h, p2/M, z2.h, z10.h\n" + "ld1h { z10.h }, p3/Z, [x22, x15, LSL #1]\n" + "fmla z29.h, p2/M, z2.h, z11.h\n" + "fmla z30.h, p2/M, z2.h, z5.h\n" + "fmla z31.h, p2/M, z2.h, z6.h\n" + "ld1h { z2.h }, p2/Z, [x14, #1, MUL VL]\n" + "fmla z28.h, p2/M, z3.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x21, x15, LSL #1]\n" + "fmla z29.h, p2/M, z3.h, z12.h\n" + "fmla z30.h, p2/M, z3.h, z6.h\n" + "fmla z31.h, p2/M, z3.h, z8.h\n" + "ld1h { z3.h }, p2/Z, [x14, #2, MUL VL]\n" + "fmla z28.h, p2/M, z4.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x20, x15, LSL #1]\n" + "fmla z29.h, p2/M, z4.h, z14.h\n" + "fmla z30.h, p2/M, z4.h, z8.h\n" + "fmla z31.h, p2/M, z4.h, z10.h\n" + "ld1h { z4.h }, p2/Z, [x14, #3, MUL VL]\n" + "fmla z28.h, p2/M, z0.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x27, x15, LSL #1]\n" + "fmla z29.h, p2/M, z0.h, z13.h\n" + "fmla z30.h, p2/M, z0.h, z11.h\n" + "ld1h { z11.h }, p3/Z, [x26, x15, LSL #1]\n" + "fmla z31.h, p2/M, z0.h, z12.h\n" + "fmla z28.h, p2/M, z1.h, z13.h\n" + "fmla z29.h, p2/M, z1.h, z5.h\n" + "fmla z30.h, p2/M, z1.h, z12.h\n" + "ld1h { z12.h }, p3/Z, [x25, x15, LSL #1]\n" + "fmla z31.h, p2/M, z1.h, z9.h\n" + "fmla z28.h, p2/M, z2.h, z5.h\n" + "fmla z29.h, p2/M, z2.h, z6.h\n" + "fmla z30.h, p2/M, z2.h, z9.h\n" + "ld1h { z9.h }, p3/Z, [x24, x15, LSL #1]\n" + "fmla z31.h, p2/M, z2.h, z11.h\n" + "fmla z28.h, p2/M, z3.h, z6.h\n" + "fmla z29.h, p2/M, z3.h, z8.h\n" + "fmla z30.h, p2/M, z3.h, z11.h\n" + "fmla z31.h, p2/M, z3.h, z12.h\n" + "fmla z28.h, p2/M, z4.h, z8.h\n" + "fmla z29.h, p2/M, z4.h, z10.h\n" + "fmla z30.h, p2/M, z4.h, z12.h\n" + "fmla z31.h, p2/M, z4.h, z9.h\n" + ".inst 0xc170ca5c // fclamp { z28.h-z31.h }, z18.h, z16.h\n" + "st1h { z28.h }, p0, [x12, x28, LSL #1]\n" + "st1h { z29.h }, p0, [x11, x28, LSL #1]\n" + "st1h { z30.h }, p0, [x10, x28, LSL #1]\n" + "st1h { z31.h }, p0, [x9, x28, LSL #1]\n" + ".inst 0xd503467f // SMSTOP\n" + : + : [n_channels] "r" ((unsigned long) n_channels), [offsetof_Args_inptrs] "I" (offsetof(Args, inptrs)), [offsetof_args_max] "I" (offsetof(Args, max)), [offsetof_args_min] "I" (offsetof(Args, min)), [offsetof_args_outptrs] "I" (offsetof(Args, outptrs)), [offsetof_args_params] "I" (offsetof(Args, params)), [params_struct] "r" (¶ms_struct) + : "cc", "memory", "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31" + ); +} + +} // namespace depthwise +} // namespace arm_conv + +#endif // defined(ARM_COMPUTE_ENABLE_SME2) |