Update CPU kernels and add mixed sign GEMM support

 - Add support for mixed sign quantized convolution.
 - Add support for mixed sign dequantized GEMM.
 - Add SME FP16 GEMV kernel.
 - Change SME vector length function to use RDSVL instead of static variable.
 - Add GEMM dilation support internally (not exposed yet).
 - Remove unused "get_default_activation_values" functions.
 - Add SVE fixed format interleaved BF16 DOT kernel.
 - Updates and optimizations to assembly kernels.

Resolves COMPMID-6926

Change-Id: I227f502502611d4cc4111c89e30c53ce94079544
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11570
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp b/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp
index 3e1fc491f1..890f82537c 100644
--- a/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp
+++ b/src/core/NEON/kernels/convolution/winograd/input_transforms/arm_fp32_1x8.cpp
@@ -31,11 +31,11 @@ namespace input_transform {
 
 void arm_fp32_1x8(
   const unsigned int n_channels,
-  const float * input_base,
+  const float *const input_base,
   size_t,  // We don't need to stride over rows
-  size_t input_col_stride,
+  const size_t input_col_stride,
   float *outptr,
-  size_t matrix_stride
+  const size_t matrix_stride
 )
 {
   constexpr int inner_tile_cols = 8;