COMPMID-1166: Fixed alpha/beta mixup for some merges.

The default templated merge, and the specialised S8 12x8 merge, were
using alpha and beta the wrong way round.  Fixed.

Change-Id: Ie559b665edf1eb012e8cb54ea0bca31612bcc072
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/131309
Tested-by: Jenkins <bsgcomp@arm.com>
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>

2 files changed, 49 insertions, 49 deletions

diff --git a/src/core/NEON/kernels/arm_gemm/mergeresults.hpp b/src/core/NEON/kernels/arm_gemm/mergeresults.hpp
index 2ab01d680c..4a6da3d21c 100644
--- a/src/core/NEON/kernels/arm_gemm/mergeresults.hpp
+++ b/src/core/NEON/kernels/arm_gemm/mergeresults.hpp
@@ -61,7 +61,7 @@ inline void MergeResults(Tout *out, const Tin *in, int ldc, int y0, int ymax, in
                 {
                     Tout &p = out[(ybase + row) * ldc + xbase + col];
 
-                    p = (p * alpha) + (beta * in[row * width + col]);
+                    p = (p * beta) + (alpha * in[row * width + col]);
                 }
             }
 
diff --git a/src/core/NEON/kernels/arm_gemm/merges/a64_merge_int32_12x8.hpp b/src/core/NEON/kernels/arm_gemm/merges/a64_merge_int32_12x8.hpp
index dc247aad37..79dd1f07e3 100644
--- a/src/core/NEON/kernels/arm_gemm/merges/a64_merge_int32_12x8.hpp
+++ b/src/core/NEON/kernels/arm_gemm/merges/a64_merge_int32_12x8.hpp
@@ -123,140 +123,140 @@ inline void MergeResults<12, 8>(int32_t *out, const int32_t *in, const int ldout
                     "ldr q3, [%x[outptr0]]\n"
                     "ldr q4, [%x[outptr0], #0x10]\n"
                     "ldr q5, [%x[outptr0], #0x20]\n"
-                    "mul v3.4s, v3.4s, %[alpha_value].4s\n"
+                    "mul v3.4s, v3.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr]]\n"
-                    "mul v4.4s, v4.4s, %[alpha_value].4s\n"
+                    "mul v4.4s, v4.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0x10]\n"
-                    "mul v5.4s, v5.4s, %[alpha_value].4s\n"
+                    "mul v5.4s, v5.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0x20]\n"
-                    "mla v3.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v3.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q0, [%x[outptr1]]\n"
-                    "mla v4.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v4.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q1, [%x[outptr1], #0x10]\n"
-                    "mla v5.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v5.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q2, [%x[outptr1], #0x20]\n"
 
                     // Row 1
                     ASM_PREFETCH("[%x[outptr2], #192]")
-                    "mul v0.4s, v0.4s, %[alpha_value].4s\n"
+                    "mul v0.4s, v0.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0x30]\n"
                     "str q3, [%x[outptr0]], #0x10\n"
-                    "mul v1.4s, v1.4s, %[alpha_value].4s\n"
+                    "mul v1.4s, v1.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0x40]\n"
                     "str q4, [%x[outptr0]], #0x10\n"
-                    "mul v2.4s, v2.4s, %[alpha_value].4s\n"
+                    "mul v2.4s, v2.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0x50]\n"
                     "str q5, [%x[outptr0]], #0x10\n"
-                    "mla v0.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v0.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q3, [%x[outptr2]]\n"
-                    "mla v1.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v1.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q4, [%x[outptr2], #0x10]\n"
-                    "mla v2.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v2.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q5, [%x[outptr2], #0x20]\n"
 
                     // Row 2
                     ASM_PREFETCH("[%x[outptr3], #192]")
-                    "mul v3.4s, v3.4s, %[alpha_value].4s\n"
+                    "mul v3.4s, v3.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0x60]\n"
                     "str q0, [%x[outptr1]], #0x10\n"
-                    "mul v4.4s, v4.4s, %[alpha_value].4s\n"
+                    "mul v4.4s, v4.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0x70]\n"
                     "str q1, [%x[outptr1]], #0x10\n"
-                    "mul v5.4s, v5.4s, %[alpha_value].4s\n"
+                    "mul v5.4s, v5.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0x80]\n"
                     "str q2, [%x[outptr1]], #0x10\n"
-                    "mla v3.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v3.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q0, [%x[outptr3]]\n"
-                    "mla v4.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v4.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q1, [%x[outptr3], #0x10]\n"
-                    "mla v5.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v5.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q2, [%x[outptr3], #0x20]\n"
 
                     // Row 3
                     ASM_PREFETCH("[%x[outptr4], #192]")
-                    "mul v0.4s, v0.4s, %[alpha_value].4s\n"
+                    "mul v0.4s, v0.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0x90]\n"
                     "str q3, [%x[outptr2]], #0x10\n"
-                    "mul v1.4s, v1.4s, %[alpha_value].4s\n"
+                    "mul v1.4s, v1.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0xa0]\n"
                     "str q4, [%x[outptr2]], #0x10\n"
-                    "mul v2.4s, v2.4s, %[alpha_value].4s\n"
+                    "mul v2.4s, v2.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0xb0]\n"
                     "str q5, [%x[outptr2]], #0x10\n"
-                    "mla v0.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v0.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q3, [%x[outptr4]]\n"
-                    "mla v1.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v1.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q4, [%x[outptr4], #0x10]\n"
-                    "mla v2.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v2.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q5, [%x[outptr4], #0x20]\n"
 
                     // Row 4
                     ASM_PREFETCH("[%x[outptr5], #192]")
-                    "mul v3.4s, v3.4s, %[alpha_value].4s\n"
+                    "mul v3.4s, v3.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0xc0]\n"
                     "str q0, [%x[outptr3]], #0x10\n"
-                    "mul v4.4s, v4.4s, %[alpha_value].4s\n"
+                    "mul v4.4s, v4.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0xd0]\n"
                     "str q1, [%x[outptr3]], #0x10\n"
-                    "mul v5.4s, v5.4s, %[alpha_value].4s\n"
+                    "mul v5.4s, v5.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0xe0]\n"
                     "str q2, [%x[outptr3]], #0x10\n"
-                    "mla v3.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v3.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q0, [%x[outptr5]]\n"
-                    "mla v4.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v4.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q1, [%x[outptr5], #0x10]\n"
-                    "mla v5.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v5.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q2, [%x[outptr5], #0x20]\n"
 
                     // Row 5
                     ASM_PREFETCH("[%x[outptr6], #192]")
-                    "mul v0.4s, v0.4s, %[alpha_value].4s\n"
+                    "mul v0.4s, v0.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0xf0]\n"
                     "str q3, [%x[outptr4]], #0x10\n"
-                    "mul v1.4s, v1.4s, %[alpha_value].4s\n"
+                    "mul v1.4s, v1.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0x100]\n"
                     "str q4, [%x[outptr4]], #0x10\n"
-                    "mul v2.4s, v2.4s, %[alpha_value].4s\n"
+                    "mul v2.4s, v2.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0x110]\n"
                     "str q5, [%x[outptr4]], #0x10\n"
-                    "mla v0.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v0.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q3, [%x[outptr6]]\n"
-                    "mla v1.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v1.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q4, [%x[outptr6], #0x10]\n"
-                    "mla v2.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v2.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q5, [%x[outptr6], #0x20]\n"
 
                     // Row 6
                     ASM_PREFETCH("[%x[outptr7], #192]")
-                    "mul v3.4s, v3.4s, %[alpha_value].4s\n"
+                    "mul v3.4s, v3.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0x120]\n"
                     "str q0, [%x[outptr5]], #0x10\n"
-                    "mul v4.4s, v4.4s, %[alpha_value].4s\n"
+                    "mul v4.4s, v4.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0x130]\n"
                     "str q1, [%x[outptr5]], #0x10\n"
-                    "mul v5.4s, v5.4s, %[alpha_value].4s\n"
+                    "mul v5.4s, v5.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0x140]\n"
                     "str q2, [%x[outptr5]], #0x10\n"
-                    "mla v3.4s, v6.4s, %[beta_value].4s\n"
+                    "mla v3.4s, v6.4s, %[alpha_value].4s\n"
                     "ldr q0, [%x[outptr7]]\n"
-                    "mla v4.4s, v7.4s, %[beta_value].4s\n"
+                    "mla v4.4s, v7.4s, %[alpha_value].4s\n"
                     "ldr q1, [%x[outptr7], #0x10]\n"
-                    "mla v5.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v5.4s, v8.4s, %[alpha_value].4s\n"
                     "ldr q2, [%x[outptr7], #0x20]\n"
 
                     // Row 7
-                    "mul v0.4s, v0.4s, %[alpha_value].4s\n"
+                    "mul v0.4s, v0.4s, %[beta_value].4s\n"
                     "ldr q6, [%x[inptr], #0x150]\n"
                     "str q3, [%x[outptr6]], #0x10\n"
-                    "mul v1.4s, v1.4s, %[alpha_value].4s\n"
+                    "mul v1.4s, v1.4s, %[beta_value].4s\n"
                     "ldr q7, [%x[inptr], #0x160]\n"
                     "str q4, [%x[outptr6]], #0x10\n"
-                    "mul v2.4s, v2.4s, %[alpha_value].4s\n"
+                    "mul v2.4s, v2.4s, %[beta_value].4s\n"
                     "ldr q8, [%x[inptr], #0x170]\n"
                     "str q5, [%x[outptr6]], #0x10\n"
-                    "mla v0.4s, v6.4s, %[beta_value].4s\n"
-                    "mla v1.4s, v7.4s, %[beta_value].4s\n"
-                    "mla v2.4s, v8.4s, %[beta_value].4s\n"
+                    "mla v0.4s, v6.4s, %[alpha_value].4s\n"
+                    "mla v1.4s, v7.4s, %[alpha_value].4s\n"
+                    "mla v2.4s, v8.4s, %[alpha_value].4s\n"
                     "str q0, [%x[outptr7]], #0x10\n"
                     "str q1, [%x[outptr7]], #0x10\n"
                     "str q2, [%x[outptr7]], #0x10\n"