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author | Michael Tyler <michael.tyler@arm.com> | 2023-04-12 17:43:17 +0100 |
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committer | michael.tyler <michael.tyler@arm.com> | 2023-06-05 15:57:58 +0000 |
commit | 74921eee924625426429044decefe3673561b174 (patch) | |
tree | 654da1a95e3d42d6af8ad1ff27bb40d77b1fd8c5 /src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp | |
parent | df5d9878008be9b60586df97ebfff197abb5195e (diff) | |
download | ComputeLibrary-74921eee924625426429044decefe3673561b174.tar.gz |
Update CPU kernel implementations and guard directives
Resolves COMPMID-6023
Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp')
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp index 49d2acf1cd..252152e3da 100644 --- a/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp +++ b/src/core/NEON/kernels/arm_gemm/indirect-interleaves/sme_interleave4VL_block4_u8_u8_summing.hpp @@ -22,7 +22,7 @@ * SOFTWARE. */ -#if defined(__ARM_FEATURE_SVE) +#if defined(ARM_COMPUTE_ENABLE_SME) template <> void interleave_block<4, 4, VLType::SME, true>( @@ -112,22 +112,22 @@ void interleave_block<4, 4, VLType::SME, true>( ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xe0bf8120 // st1w { za0v.s[x12] }, p0/Z, [x9, XZR, LSL #2]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" - ".inst 0xc0828813 // mova z19.s, p2/M, za0v.s[x12]\n" + ".inst 0xc0828810 // mova z16.s, p2/M, za0v.s[x12]\n" ".inst 0xe0af8124 // st1w { za1v.s[x12] }, p0/Z, [x9, x15, LSL #2]\n" ".inst 0x25306d21 // psel p1.s, p11.s/Z, p9.s[w12]\n" ".inst 0x25306d20 // psel p0.s, p11.s/Z, p9.s[w12]\n" ".inst 0xc0828891 // mova z17.s, p2/M, za1v.s[x12]\n" ".inst 0xe0ae8528 // st1w { za2v.s[x12] }, p1/Z, [x9, x14, LSL #2]\n" - ".inst 0xc0828912 // mova z18.s, p2/M, za2v.s[x12]\n" - "udot z23.s, z19.b, z24.b\n" + ".inst 0xc0828913 // mova z19.s, p2/M, za2v.s[x12]\n" + "udot z23.s, z16.b, z24.b\n" ".inst 0xe0ad812c // st1w { za3v.s[x12] }, p0/Z, [x9, x13, LSL #2]\n" - ".inst 0xc0828990 // mova z16.s, p2/M, za3v.s[x12]\n" + ".inst 0xc0828992 // mova z18.s, p2/M, za3v.s[x12]\n" "add x12, x12, #0x1\n" "cmp x12, x20\n" "udot z22.s, z17.b, z24.b\n" - "udot z21.s, z18.b, z24.b\n" + "udot z21.s, z19.b, z24.b\n" "addvl x9, x9, #4\n" - "udot z20.s, z16.b, z24.b\n" + "udot z20.s, z18.b, z24.b\n" "blt 5b\n" "incb x28\n" "whilelt p9.b, x28, %x[width]\n" @@ -147,4 +147,4 @@ void interleave_block<4, 4, VLType::SME, true>( ); } -#endif // defined(__ARM_FEATURE_SVE) +#endif // defined(ARM_COMPUTE_ENABLE_SME) |