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author | Michael Tyler <michael.tyler@arm.com> | 2024-06-04 15:47:37 +0100 |
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committer | Michael Tyler <michael.tyler@arm.com> | 2024-06-25 09:10:13 +0000 |
commit | fc94f4d23abd4bc427b701f54ad85282e9ec7872 (patch) | |
tree | 5e2980599256e2b2f4374e5beb61596fc95c9d5a /src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp | |
parent | c2237ec4094c7824f8f7e61bc89504d01c5b59ff (diff) | |
download | ComputeLibrary-fc94f4d23abd4bc427b701f54ad85282e9ec7872.tar.gz |
Update CPU kernels and add mixed sign GEMM support
- Add support for mixed sign quantized convolution.
- Add support for mixed sign dequantized GEMM.
- Add SME FP16 GEMV kernel.
- Change SME vector length function to use RDSVL instead of static variable.
- Add GEMM dilation support internally (not exposed yet).
- Remove unused "get_default_activation_values" functions.
- Add SVE fixed format interleaved BF16 DOT kernel.
- Updates and optimizations to assembly kernels.
Resolves COMPMID-6926
Change-Id: I227f502502611d4cc4111c89e30c53ce94079544
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11570
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp')
-rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp b/src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp index d0e8639229..a553f1be9e 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp +++ b/src/core/NEON/kernels/arm_conv/pooling/depthfirst_driver.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 Arm Limited. + * Copyright (c) 2022-2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -64,10 +64,10 @@ class DepthfirstDriver : public PoolingCommon<TInput, TOutput> std::unique_ptr<const IDepthfirstStrategy> m_strat; /* Compute the amount of working space required for a single thread. */ - virtual size_t get_working_size_per_thread() const = 0; + virtual size_t get_working_size_per_thread(unsigned int) const = 0; /* Initialise the working space for a thread. */ - virtual void initialise_working_space(void *) const = 0; + virtual void initialise_working_space(void *, unsigned int) const = 0; /* Compute a portion of the output tensor with padding. */ virtual void compute_tile_padded( @@ -148,8 +148,8 @@ class DepthfirstDriver : public PoolingCommon<TInput, TOutput> { // Get and initialise the working space for this thread. void *thread_working_space = - static_cast<uint8_t *>(working_space) + thread_id * this->get_working_size_per_thread(); - this->initialise_working_space(thread_working_space); + static_cast<uint8_t *>(working_space) + thread_id * this->get_working_size_per_thread(n_channels); + this->initialise_working_space(thread_working_space, n_channels); // Construct convenient representations of the input/output tensors. TensorSpec<const TInput *> input_tensor(reinterpret_cast<const TInput *>(input), ld_input_row, ld_input_col); @@ -289,9 +289,14 @@ class DepthfirstDriver : public PoolingCommon<TInput, TOutput> { } - size_t get_working_size(unsigned int n_threads) const override final + size_t get_working_size(unsigned int n_threads) const override { - return n_threads * this->get_working_size_per_thread(); + return this->get_working_size(n_threads, this->m_args.n_channels); + } + + size_t get_working_size(unsigned int n_threads, unsigned int n_channels) const override final + { + return n_threads * this->get_working_size_per_thread(n_channels); } }; |