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| author | ramelg01 <ramy.elgammal@arm.com> | 2022-05-04 15:12:21 +0100 |
|---|---|---|
| committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2022-05-05 08:54:15 +0000 |
| commit | 638b7e4f6b1125b74f27f90dea2cd23eca52bfe8 (patch) | |
| tree | 68cf88a73c990ad580f200b6ddff76d50860c1ea /src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp | |
| parent | facd9dd4c75feb886240a2b55cefe55ccf773f63 (diff) | |
| download | ComputeLibrary-638b7e4f6b1125b74f27f90dea2cd23eca52bfe8.tar.gz | |
Fix for Neon™ Depthwise Android P VTS test failure
Resolves: COMPMID-5237
Signed-off-by: ramy.elgammal@arm.com
Change-Id: Ib1f5e262030e915a038cef587001708bbaf14c56
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7508
Reviewed-by: David Mansell
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp index 22f95746fc..96cde40e04 100644 --- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst/generic.cpp @@ -267,24 +267,24 @@ void a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( "smlal2 v23.4s, v29.8h, v6.8h\n" "smlal v13.4s, v31.4h, v6.4h\n" "smlal v19.4s, v30.4h, v8.4h\n" - "sqdmulh v13.4s, v13.4s, v21.4s\n" + "sqrdmulh v13.4s, v13.4s, v21.4s\n" "smlal v18.4s, v28.4h, v8.4h\n" "smlal v9.4s, v28.4h, v7.4h\n" - "sqdmulh v19.4s, v19.4s, v21.4s\n" + "sqrdmulh v19.4s, v19.4s, v21.4s\n" "smlal2 v26.4s, v31.8h, v6.8h\n" "smlal2 v11.4s, v30.8h, v8.8h\n" - "sqdmulh v18.4s, v18.4s, v21.4s\n" + "sqrdmulh v18.4s, v18.4s, v21.4s\n" "smlal2 v24.4s, v28.8h, v8.8h\n" "smlal2 v23.4s, v28.8h, v7.8h\n" - "sqdmulh v9.4s, v9.4s, v21.4s\n" + "sqrdmulh v9.4s, v9.4s, v21.4s\n" "and v7.16b, v13.16b, v25.16b\n" - "sqdmulh v26.4s, v26.4s, v10.4s\n" + "sqrdmulh v26.4s, v26.4s, v10.4s\n" "and v4.16b, v19.16b, v25.16b\n" - "sqdmulh v11.4s, v11.4s, v10.4s\n" + "sqrdmulh v11.4s, v11.4s, v10.4s\n" "and v21.16b, v18.16b, v25.16b\n" - "sqdmulh v24.4s, v24.4s, v10.4s\n" + "sqrdmulh v24.4s, v24.4s, v10.4s\n" "and v20.16b, v9.16b, v25.16b\n" - "sqdmulh v23.4s, v23.4s, v10.4s\n" + "sqrdmulh v23.4s, v23.4s, v10.4s\n" "sshr v7.4s, v7.4s, #0x1f\n" "and v29.16b, v26.16b, v16.16b\n" "sshr v4.4s, v4.4s, #0x1f\n" @@ -493,24 +493,24 @@ void a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( "smlal2 v23.4s, v29.8h, v6.8h\n" "smlal v13.4s, v31.4h, v6.4h\n" "smlal v19.4s, v30.4h, v8.4h\n" - "sqdmulh v13.4s, v13.4s, v21.4s\n" + "sqrdmulh v13.4s, v13.4s, v21.4s\n" "smlal v18.4s, v28.4h, v8.4h\n" "smlal v9.4s, v28.4h, v7.4h\n" - "sqdmulh v19.4s, v19.4s, v21.4s\n" + "sqrdmulh v19.4s, v19.4s, v21.4s\n" "smlal2 v26.4s, v31.8h, v6.8h\n" "smlal2 v11.4s, v30.8h, v8.8h\n" - "sqdmulh v18.4s, v18.4s, v21.4s\n" + "sqrdmulh v18.4s, v18.4s, v21.4s\n" "smlal2 v24.4s, v28.8h, v8.8h\n" "smlal2 v23.4s, v28.8h, v7.8h\n" - "sqdmulh v9.4s, v9.4s, v21.4s\n" + "sqrdmulh v9.4s, v9.4s, v21.4s\n" "and v7.16b, v13.16b, v25.16b\n" - "sqdmulh v26.4s, v26.4s, v10.4s\n" + "sqrdmulh v26.4s, v26.4s, v10.4s\n" "and v4.16b, v19.16b, v25.16b\n" - "sqdmulh v11.4s, v11.4s, v10.4s\n" + "sqrdmulh v11.4s, v11.4s, v10.4s\n" "and v21.16b, v18.16b, v25.16b\n" - "sqdmulh v24.4s, v24.4s, v10.4s\n" + "sqrdmulh v24.4s, v24.4s, v10.4s\n" "and v20.16b, v9.16b, v25.16b\n" - "sqdmulh v23.4s, v23.4s, v10.4s\n" + "sqrdmulh v23.4s, v23.4s, v10.4s\n" "sshr v7.4s, v7.4s, #0x1f\n" "and v29.16b, v26.16b, v16.16b\n" "sshr v4.4s, v4.4s, #0x1f\n" @@ -1043,22 +1043,22 @@ void a64_u8s8u8q_nhwc_3x3_s1_output2x2_mla_depthfirst_impl( "ld1 { v21.s }[0], [x13]\n" "ld1 { v25.s }[0], [x11]\n" "59:" // Oddments: Load requant params: Bit 2: End - "sqdmulh v13.4s, v13.4s, v21.4s\n" - "sqdmulh v19.4s, v19.4s, v21.4s\n" + "sqrdmulh v13.4s, v13.4s, v21.4s\n" + "sqrdmulh v19.4s, v19.4s, v21.4s\n" "add x10, x10, x14\n" "add x9, x9, x14\n" - "sqdmulh v18.4s, v18.4s, v21.4s\n" - "sqdmulh v9.4s, v9.4s, v21.4s\n" + "sqrdmulh v18.4s, v18.4s, v21.4s\n" + "sqrdmulh v9.4s, v9.4s, v21.4s\n" "add x28, x28, x14\n" "add x27, x27, x14\n" "and v7.16b, v13.16b, v25.16b\n" - "sqdmulh v26.4s, v26.4s, v10.4s\n" + "sqrdmulh v26.4s, v26.4s, v10.4s\n" "and v4.16b, v19.16b, v25.16b\n" - "sqdmulh v11.4s, v11.4s, v10.4s\n" + "sqrdmulh v11.4s, v11.4s, v10.4s\n" "and v21.16b, v18.16b, v25.16b\n" - "sqdmulh v24.4s, v24.4s, v10.4s\n" + "sqrdmulh v24.4s, v24.4s, v10.4s\n" "and v20.16b, v9.16b, v25.16b\n" - "sqdmulh v23.4s, v23.4s, v10.4s\n" + "sqrdmulh v23.4s, v23.4s, v10.4s\n" "sshr v7.4s, v7.4s, #0x1f\n" "and v29.16b, v26.16b, v16.16b\n" "sshr v4.4s, v4.4s, #0x1f\n" |