Revert "Update CPU kernels to remove x19"

This reverts commit 3c59f01c209d2732a15d97d65565ead964787a8b.

Resolves: COMPMID-5817
Change-Id: Ie2443a21854a95db1e3d0cafa2121c0187a5e237
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8974
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>

1 files changed, 142 insertions, 141 deletions

diff --git a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst/generic.cpp
index 69b3865a65..04a7abd3bd 100644
--- a/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst/generic.cpp
+++ b/src/core/NEON/kernels/arm_conv/depthwise/kernels/a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst/generic.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, 2023 Arm Limited.
+ * Copyright (c) 2021 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -41,59 +41,59 @@ void a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst_imp
   const float minmax_vals[2] = { activation_min, activation_max };
 
   __asm__ __volatile__(
-    "ld1r { v24.4s }, [%x[clamps]]\n"
+    "ldp x14, x13, [%x[outptrs], #0x0]\n"
+    "add x12, %x[clamps], #0x4\n"
+    "ldp x11, x10, [%x[outptrs], #0x10]\n"
+    "mov x9, #0x0\n"
+    "ldp x28, x27, [%x[outptrs], #0x20]\n"
+    "mov x26, #0x0\n"
+    "ldp x25, x24, [%x[outptrs], #0x30]\n"
+    "lsr x23, %x[channel_multiplier], #0x2\n"
+    "ldr x22, [%x[outptrs], #0x40]\n"
     "ldr x21, [%x[inptrs], #0x0]\n"
-    "lsr x22, %x[channel_multiplier], #0x2\n"
-    "add x20, %x[clamps], #0x4\n"
+    "ldr x20, [%x[inptrs], #0x8]\n"
+    "ldr x19, [%x[inptrs], #0x10]\n"
     "ldr q0, [x21, #0x0]\n"
     "ldr q1, [x21, #0x10]\n"
-    "mov x21, #0x0\n"
-    "mov x14, #0x0\n"
-    "ld1r { v23.4s }, [x20]\n"
-    "ldr x20, [%x[inptrs], #0x8]\n"
     "ldr q2, [x20, #0x0]\n"
     "ldr q3, [x20, #0x10]\n"
-    "ldr x20, [%x[inptrs], #0x10]\n"
-    "ldr q4, [x20, #0x0]\n"
-    "ldr q5, [x20, #0x10]\n"
-    "ldr x20, [%x[inptrs], #0x18]\n"
-    "ldr q6, [x20, #0x0]\n"
-    "ldr q7, [x20, #0x10]\n"
+    "ldr q4, [x19, #0x0]\n"
+    "ldr q5, [x19, #0x10]\n"
+    "ldr x21, [%x[inptrs], #0x18]\n"
     "ldr x20, [%x[inptrs], #0x20]\n"
+    "ldr x19, [%x[inptrs], #0x28]\n"
+    "ldr q6, [x21, #0x0]\n"
+    "ldr q7, [x21, #0x10]\n"
     "ldr q8, [x20, #0x0]\n"
     "ldr q9, [x20, #0x10]\n"
-    "ldr x20, [%x[inptrs], #0x28]\n"
-    "ldr q10, [x20, #0x0]\n"
-    "ldr q11, [x20, #0x10]\n"
-    "ldr x20, [%x[inptrs], #0x30]\n"
-    "ldr q12, [x20, #0x0]\n"
-    "ldr q13, [x20, #0x10]\n"
-    "ldp x13, x12, [%x[outptrs], #0x0]\n"
-    "ldp x11, x10, [%x[outptrs], #0x10]\n"
-    "ldp x9, x28, [%x[outptrs], #0x20]\n"
-    "ldp x27, x26, [%x[outptrs], #0x30]\n"
-    "ldr x25, [%x[outptrs], #0x40]\n"
-    "cbz x22, 3f\n"
+    "ldr q10, [x19, #0x0]\n"
+    "ldr q11, [x19, #0x10]\n"
+    "ldr x19, [%x[inptrs], #0x30]\n"
+    "ld1r { v24.4s }, [%x[clamps]]\n"
+    "ld1r { v23.4s }, [x12]\n"
+    "ldr q12, [x19, #0x0]\n"
+    "ldr q13, [x19, #0x10]\n"
+    "cbz x23, 3f\n"
     "ldr q14, [%x[params], #0x0]\n"
-    "ldr q31, [%x[params], #0x10]\n"
-    "subs x22, x22, #0x1\n"
     "mov v15.16b, v14.16b\n"
-    "ldr q30, [%x[params], #0x20]\n"
-    "ldr q29, [%x[params], #0x30]\n"
+    "ldr q31, [%x[params], #0x10]\n"
+    "subs x23, x23, #0x1\n"
     "mov v16.16b, v14.16b\n"
+    "ldr q30, [%x[params], #0x20]\n"
     "mov v17.16b, v14.16b\n"
+    "ldr q29, [%x[params], #0x30]\n"
+    "add %x[params], %x[params], #0x40\n"
     "mov v18.16b, v14.16b\n"
     "mov v19.16b, v14.16b\n"
-    "add %x[params], %x[params], #0x40\n"
     "mov v20.16b, v14.16b\n"
     "mov v21.16b, v14.16b\n"
     "mov v22.16b, v14.16b\n"
     "beq 2f\n"
     "1:"  // Output channel complete vector loop
     "fmla v14.4s, v31.4s, v0.s[0]\n"
+    "add x9, x9, #0x4\n"
     "fmla v15.4s, v31.4s, v0.s[2]\n"
-    "subs x22, x22, #0x1\n"
-    "add x21, x21, #0x4\n"
+    "subs x23, x23, #0x1\n"
     "fmla v16.4s, v31.4s, v1.s[0]\n"
     "fmla v17.4s, v31.4s, v4.s[0]\n"
     "fmla v18.4s, v31.4s, v4.s[2]\n"
@@ -174,51 +174,51 @@ void a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst_imp
     "ldr q30, [%x[params], #0x80]\n"
     "fmla v14.4s, v29.4s, v4.s[2]\n"
     "fmla v15.4s, v29.4s, v5.s[0]\n"
-    "fmin v14.4s, v14.4s, v23.4s\n"
     "fmla v16.4s, v29.4s, v5.s[2]\n"
     "fmla v17.4s, v29.4s, v8.s[2]\n"
-    "fmax v14.4s, v14.4s, v24.4s\n"
-    "str q14, [x13, x14]\n"
-    "ldr q14, [%x[params], #0x60]\n"
     "fmla v18.4s, v29.4s, v9.s[0]\n"
     "fmla v19.4s, v29.4s, v9.s[2]\n"
-    "fmin v15.4s, v15.4s, v23.4s\n"
     "fmla v20.4s, v29.4s, v12.s[2]\n"
     "fmla v21.4s, v29.4s, v13.s[0]\n"
-    "fmin v16.4s, v16.4s, v23.4s\n"
     "fmla v22.4s, v29.4s, v13.s[2]\n"
     "ldr q29, [%x[params], #0x90]\n"
-    "fmin v17.4s, v17.4s, v23.4s\n"
+    "fmin v14.4s, v14.4s, v23.4s\n"
+    "fmin v15.4s, v15.4s, v23.4s\n"
+    "fmin v16.4s, v16.4s, v23.4s\n"
+    "fmax v14.4s, v14.4s, v24.4s\n"
+    "str q14, [x14, x26]\n"
+    "fmax v15.4s, v15.4s, v24.4s\n"
+    "fmax v16.4s, v16.4s, v24.4s\n"
+    "ldr q14, [%x[params], #0x60]\n"
     "add %x[params], %x[params], #0xa0\n"
+    "fmin v17.4s, v17.4s, v23.4s\n"
+    "str q15, [x13, x26]\n"
     "fmin v18.4s, v18.4s, v23.4s\n"
     "fmin v19.4s, v19.4s, v23.4s\n"
+    "str q16, [x11, x26]\n"
     "fmin v20.4s, v20.4s, v23.4s\n"
-    "fmin v21.4s, v21.4s, v23.4s\n"
-    "fmin v22.4s, v22.4s, v23.4s\n"
-    "fmax v15.4s, v15.4s, v24.4s\n"
-    "str q15, [x12, x14]\n"
-    "fmax v16.4s, v16.4s, v24.4s\n"
     "fmax v17.4s, v17.4s, v24.4s\n"
-    "str q16, [x11, x14]\n"
+    "str q17, [x10, x26]\n"
     "fmax v18.4s, v18.4s, v24.4s\n"
     "fmax v19.4s, v19.4s, v24.4s\n"
-    "str q17, [x10, x14]\n"
+    "str q18, [x28, x26]\n"
     "fmax v20.4s, v20.4s, v24.4s\n"
+    "fmin v21.4s, v21.4s, v23.4s\n"
+    "str q19, [x27, x26]\n"
+    "fmin v22.4s, v22.4s, v23.4s\n"
+    "str q20, [x25, x26]\n"
     "fmax v21.4s, v21.4s, v24.4s\n"
-    "str q18, [x9, x14]\n"
-    "fmax v22.4s, v22.4s, v24.4s\n"
-    "str q19, [x28, x14]\n"
     "mov v15.16b, v14.16b\n"
-    "str q20, [x27, x14]\n"
+    "str q21, [x24, x26]\n"
+    "fmax v22.4s, v22.4s, v24.4s\n"
     "mov v16.16b, v14.16b\n"
+    "str q22, [x22, x26]\n"
     "mov v17.16b, v14.16b\n"
-    "str q21, [x26, x14]\n"
+    "add x26, x26, #0x10\n"
     "mov v18.16b, v14.16b\n"
     "mov v19.16b, v14.16b\n"
-    "str q22, [x25, x14]\n"
     "mov v20.16b, v14.16b\n"
     "mov v21.16b, v14.16b\n"
-    "add x14, x14, #0x10\n"
     "mov v22.16b, v14.16b\n"
     "bgt 1b\n"
     "2:"  // Output channel complete vector tail
@@ -303,58 +303,58 @@ void a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst_imp
     "fmla v22.4s, v30.4s, v13.s[1]\n"
     "fmla v14.4s, v29.4s, v4.s[2]\n"
     "fmla v15.4s, v29.4s, v5.s[0]\n"
-    "fmin v14.4s, v14.4s, v23.4s\n"
     "fmla v16.4s, v29.4s, v5.s[2]\n"
     "fmla v17.4s, v29.4s, v8.s[2]\n"
-    "fmin v15.4s, v15.4s, v23.4s\n"
     "fmla v18.4s, v29.4s, v9.s[0]\n"
     "fmla v19.4s, v29.4s, v9.s[2]\n"
-    "fmin v16.4s, v16.4s, v23.4s\n"
     "fmla v20.4s, v29.4s, v12.s[2]\n"
     "fmla v21.4s, v29.4s, v13.s[0]\n"
-    "fmin v17.4s, v17.4s, v23.4s\n"
     "fmla v22.4s, v29.4s, v13.s[2]\n"
-    "fmin v18.4s, v18.4s, v23.4s\n"
-    "fmin v19.4s, v19.4s, v23.4s\n"
-    "fmin v20.4s, v20.4s, v23.4s\n"
-    "fmin v21.4s, v21.4s, v23.4s\n"
-    "fmin v22.4s, v22.4s, v23.4s\n"
+    "fmin v14.4s, v14.4s, v23.4s\n"
+    "fmin v15.4s, v15.4s, v23.4s\n"
+    "fmin v16.4s, v16.4s, v23.4s\n"
     "fmax v14.4s, v14.4s, v24.4s\n"
+    "str q14, [x14, x26]\n"
     "fmax v15.4s, v15.4s, v24.4s\n"
-    "str q14, [x13, x14]\n"
     "fmax v16.4s, v16.4s, v24.4s\n"
+    "str q15, [x13, x26]\n"
+    "fmin v17.4s, v17.4s, v23.4s\n"
+    "fmin v18.4s, v18.4s, v23.4s\n"
+    "str q16, [x11, x26]\n"
+    "fmin v19.4s, v19.4s, v23.4s\n"
+    "fmin v20.4s, v20.4s, v23.4s\n"
     "fmax v17.4s, v17.4s, v24.4s\n"
-    "str q15, [x12, x14]\n"
+    "str q17, [x10, x26]\n"
     "fmax v18.4s, v18.4s, v24.4s\n"
     "fmax v19.4s, v19.4s, v24.4s\n"
-    "str q16, [x11, x14]\n"
+    "str q18, [x28, x26]\n"
     "fmax v20.4s, v20.4s, v24.4s\n"
+    "fmin v21.4s, v21.4s, v23.4s\n"
+    "str q19, [x27, x26]\n"
+    "fmin v22.4s, v22.4s, v23.4s\n"
+    "str q20, [x25, x26]\n"
     "fmax v21.4s, v21.4s, v24.4s\n"
-    "str q17, [x10, x14]\n"
     "fmax v22.4s, v22.4s, v24.4s\n"
-    "str q18, [x9, x14]\n"
-    "str q19, [x28, x14]\n"
-    "str q20, [x27, x14]\n"
-    "str q21, [x26, x14]\n"
-    "str q22, [x25, x14]\n"
-    "add x14, x14, #0x10\n"
+    "str q21, [x24, x26]\n"
+    "str q22, [x22, x26]\n"
+    "add x26, x26, #0x10\n"
     "3:"  // Output channel oddments
     "tst %x[channel_multiplier], #0x3\n"
     "beq 6f\n"
     "ldr q14, [%x[params], #0x0]\n"
-    "ldr q31, [%x[params], #0x10]\n"
     "mov v15.16b, v14.16b\n"
+    "ldr q31, [%x[params], #0x10]\n"
     "mov v16.16b, v14.16b\n"
     "ldr q30, [%x[params], #0x20]\n"
-    "ldr q29, [%x[params], #0x30]\n"
     "mov v17.16b, v14.16b\n"
+    "ldr q29, [%x[params], #0x30]\n"
     "mov v18.16b, v14.16b\n"
     "mov v19.16b, v14.16b\n"
     "mov v20.16b, v14.16b\n"
-    "fmla v15.4s, v31.4s, v0.s[2]\n"
     "mov v21.16b, v14.16b\n"
     "mov v22.16b, v14.16b\n"
     "fmla v14.4s, v31.4s, v0.s[0]\n"
+    "fmla v15.4s, v31.4s, v0.s[2]\n"
     "fmla v16.4s, v31.4s, v1.s[0]\n"
     "fmla v17.4s, v31.4s, v4.s[0]\n"
     "fmla v18.4s, v31.4s, v4.s[2]\n"
@@ -434,97 +434,98 @@ void a64_fp32_packed_to_nhwc_3x3_s2_with_multiplier_output3x3_mla_depthfirst_imp
     "fmla v22.4s, v30.4s, v13.s[1]\n"
     "fmla v14.4s, v29.4s, v4.s[2]\n"
     "fmla v15.4s, v29.4s, v5.s[0]\n"
-    "fmin v14.4s, v14.4s, v23.4s\n"
     "fmla v16.4s, v29.4s, v5.s[2]\n"
     "fmla v17.4s, v29.4s, v8.s[2]\n"
-    "fmin v15.4s, v15.4s, v23.4s\n"
     "fmla v18.4s, v29.4s, v9.s[0]\n"
     "fmla v19.4s, v29.4s, v9.s[2]\n"
-    "fmin v16.4s, v16.4s, v23.4s\n"
     "fmla v20.4s, v29.4s, v12.s[2]\n"
     "fmla v21.4s, v29.4s, v13.s[0]\n"
-    "fmin v17.4s, v17.4s, v23.4s\n"
     "fmla v22.4s, v29.4s, v13.s[2]\n"
-    "fmin v18.4s, v18.4s, v23.4s\n"
-    "fmin v19.4s, v19.4s, v23.4s\n"
-    "fmin v20.4s, v20.4s, v23.4s\n"
-    "fmin v21.4s, v21.4s, v23.4s\n"
-    "fmin v22.4s, v22.4s, v23.4s\n"
+    "fmin v14.4s, v14.4s, v23.4s\n"
+    "fmin v15.4s, v15.4s, v23.4s\n"
+    "fmin v16.4s, v16.4s, v23.4s\n"
     "fmax v14.4s, v14.4s, v24.4s\n"
     "fmax v15.4s, v15.4s, v24.4s\n"
     "fmax v16.4s, v16.4s, v24.4s\n"
+    "fmin v17.4s, v17.4s, v23.4s\n"
+    "fmin v18.4s, v18.4s, v23.4s\n"
+    "fmin v19.4s, v19.4s, v23.4s\n"
     "fmax v17.4s, v17.4s, v24.4s\n"
     "fmax v18.4s, v18.4s, v24.4s\n"
     "fmax v19.4s, v19.4s, v24.4s\n"
+    "fmin v20.4s, v20.4s, v23.4s\n"
+    "fmin v21.4s, v21.4s, v23.4s\n"
+    "fmin v22.4s, v22.4s, v23.4s\n"
     "fmax v20.4s, v20.4s, v24.4s\n"
     "fmax v21.4s, v21.4s, v24.4s\n"
     "fmax v22.4s, v22.4s, v24.4s\n"
     "tbz %x[channel_multiplier], #1, 4f\n"
-    "add x20, x13, x14\n"
-    "add x22, x12, x14\n"
-    "st1 { v14.d }[0], [x20]\n"
-    "add x21, x11, x14\n"
-    "add x20, x10, x14\n"
-    "st1 { v15.d }[0], [x22]\n"
-    "add x24, x9, x14\n"
-    "add x23, x28, x14\n"
-    "st1 { v16.d }[0], [x21]\n"
-    "add x22, x27, x14\n"
-    "add x21, x26, x14\n"
-    "st1 { v17.d }[0], [x20]\n"
-    "add x20, x25, x14\n"
-    "st1 { v18.d }[0], [x24]\n"
-    "add x14, x14, #0x8\n"
-    "st1 { v19.d }[0], [x23]\n"
-    "st1 { v20.d }[0], [x22]\n"
-    "st1 { v21.d }[0], [x21]\n"
-    "st1 { v22.d }[0], [x20]\n"
+    "add x19, x14, x26\n"
+    "st1 { v14.d }[0], [x19]\n"
+    "add x19, x13, x26\n"
+    "st1 { v15.d }[0], [x19]\n"
+    "add x19, x11, x26\n"
+    "st1 { v16.d }[0], [x19]\n"
+    "add x19, x10, x26\n"
+    "st1 { v17.d }[0], [x19]\n"
+    "add x19, x28, x26\n"
+    "st1 { v18.d }[0], [x19]\n"
+    "add x19, x27, x26\n"
+    "st1 { v19.d }[0], [x19]\n"
+    "add x19, x25, x26\n"
+    "st1 { v20.d }[0], [x19]\n"
+    "add x19, x24, x26\n"
+    "st1 { v21.d }[0], [x19]\n"
+    "add x19, x22, x26\n"
+    "st1 { v22.d }[0], [x19]\n"
+    "add x26, x26, #0x8\n"
     "tbz %x[channel_multiplier], #0, 5f\n"
-    "add x20, x13, x14\n"
-    "add x22, x12, x14\n"
-    "st1 { v14.s }[2], [x20]\n"
-    "add x21, x11, x14\n"
-    "add x20, x10, x14\n"
-    "st1 { v15.s }[2], [x22]\n"
-    "add x24, x9, x14\n"
-    "add x23, x28, x14\n"
-    "st1 { v16.s }[2], [x21]\n"
-    "add x22, x27, x14\n"
-    "add x21, x26, x14\n"
-    "st1 { v17.s }[2], [x20]\n"
-    "add x20, x25, x14\n"
-    "st1 { v18.s }[2], [x24]\n"
-    "st1 { v19.s }[2], [x23]\n"
-    "st1 { v20.s }[2], [x22]\n"
-    "st1 { v21.s }[2], [x21]\n"
-    "st1 { v22.s }[2], [x20]\n"
+    "add x19, x14, x26\n"
+    "st1 { v14.s }[2], [x19]\n"
+    "add x19, x13, x26\n"
+    "st1 { v15.s }[2], [x19]\n"
+    "add x19, x11, x26\n"
+    "st1 { v16.s }[2], [x19]\n"
+    "add x19, x10, x26\n"
+    "st1 { v17.s }[2], [x19]\n"
+    "add x19, x28, x26\n"
+    "st1 { v18.s }[2], [x19]\n"
+    "add x19, x27, x26\n"
+    "st1 { v19.s }[2], [x19]\n"
+    "add x19, x25, x26\n"
+    "st1 { v20.s }[2], [x19]\n"
+    "add x19, x24, x26\n"
+    "st1 { v21.s }[2], [x19]\n"
+    "add x19, x22, x26\n"
+    "st1 { v22.s }[2], [x19]\n"
     "b 5f\n"
     "4:"  // Output channel oddments: Store: Bit 1: Unset
-    "add x20, x13, x14\n"
-    "add x22, x12, x14\n"
-    "st1 { v14.s }[0], [x20]\n"
-    "add x21, x11, x14\n"
-    "add x20, x10, x14\n"
-    "st1 { v15.s }[0], [x22]\n"
-    "add x24, x9, x14\n"
-    "add x23, x28, x14\n"
-    "st1 { v16.s }[0], [x21]\n"
-    "add x22, x27, x14\n"
-    "add x21, x26, x14\n"
-    "st1 { v17.s }[0], [x20]\n"
-    "add x20, x25, x14\n"
-    "st1 { v18.s }[0], [x24]\n"
-    "st1 { v19.s }[0], [x23]\n"
-    "st1 { v20.s }[0], [x22]\n"
-    "st1 { v21.s }[0], [x21]\n"
-    "st1 { v22.s }[0], [x20]\n"
+    "tbz %x[channel_multiplier], #0, 5f\n"
+    "add x19, x14, x26\n"
+    "st1 { v14.s }[0], [x19]\n"
+    "add x19, x13, x26\n"
+    "st1 { v15.s }[0], [x19]\n"
+    "add x19, x11, x26\n"
+    "st1 { v16.s }[0], [x19]\n"
+    "add x19, x10, x26\n"
+    "st1 { v17.s }[0], [x19]\n"
+    "add x19, x28, x26\n"
+    "st1 { v18.s }[0], [x19]\n"
+    "add x19, x27, x26\n"
+    "st1 { v19.s }[0], [x19]\n"
+    "add x19, x25, x26\n"
+    "st1 { v20.s }[0], [x19]\n"
+    "add x19, x24, x26\n"
+    "st1 { v21.s }[0], [x19]\n"
+    "add x19, x22, x26\n"
+    "st1 { v22.s }[0], [x19]\n"
     "5:"  // Output channel oddments: Store: Bit 1: End
 
     "6:"  // End
 
     : [params] "+&r" (params)
     : [channel_multiplier] "r" (n_output_channels), [clamps] "r" (minmax_vals), [inptrs] "r" (inptrs), [outptrs] "r" (outptrs)
-    : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
+    : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v29", "v30", "v31", "x9", "x10", "x11", "x12", "x13", "x14", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
   );
 }