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authorViet-Hoa Do <viet-hoa.do@arm.com>2022-06-01 11:47:14 +0100
committerViet-Hoa Do <viet-hoa.do@arm.com>2022-11-28 16:57:42 +0000
commit03b2971ac69a86f10a1566938d1a25afee15746c (patch)
treeaec7cfc047e1da278b4b71a706cda7b1b0faa158 /src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp
parent7dc0234331f2150a6b4ac5c2b49de419870f7cf5 (diff)
downloadComputeLibrary-03b2971ac69a86f10a1566938d1a25afee15746c.tar.gz
Integrate SME2 kernels
* Add SME/SME2 detection. * Integrate SME2 implementation for: - Normal convolution - Winograd - Depthwise convolution - Pooling Resolves: COMPMID-5700 Signed-off-by: Viet-Hoa Do <viet-hoa.do@arm.com> Change-Id: I2f1ca1d05f8cfeee9309ed1c0a36096a4a6aad5c Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8692 Reviewed-by: Gunes Bayir <gunes.bayir@arm.com> Tested-by: Arm Jenkins <bsgcomp@arm.com> Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp')
-rw-r--r--src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp
index 78b6aec388..1ba7694f1e 100644
--- a/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp
+++ b/src/core/NEON/kernels/arm_conv/depthwise/depthwise_implementation_constraints.hpp
@@ -85,6 +85,18 @@ bool cpu_has_dot_product(const DepthwiseArgs &args, const void *)
return args.cpu_info->has_dotprod();
}
+bool cpu_has_sme(const DepthwiseArgs &args, const void *) __attribute__ ((unused));
+bool cpu_has_sme(const DepthwiseArgs &args, const void *)
+{
+ return args.cpu_info->has_sme();
+}
+
+bool cpu_has_sme2(const DepthwiseArgs &args, const void *) __attribute__ ((unused));
+bool cpu_has_sme2(const DepthwiseArgs &args, const void *)
+{
+ return args.cpu_info->has_sme2();
+}
+
bool cpu_has_sve(const DepthwiseArgs &args, const void *) __attribute__ ((unused));
bool cpu_has_sve(const DepthwiseArgs &args, const void *)
{
@@ -115,6 +127,15 @@ bool has_channel_multiplier(const DepthwiseArgs &args, const void *)
return args.channel_multiplier > 1;
}
+// Planar kernels require a "priming" step before the main processing loop. The kernels can prime with left padding
+// or input data, but not right padding - which could be needed in some extreme cases such as a 5x5 kernel, width 1
+// padding 2. These are rare enough and can be handled with other kernels anyway, so filter them out with this.
+bool no_prime_right_pad(const DepthwiseArgs &args, const void *) __attribute__ ((unused));
+bool no_prime_right_pad(const DepthwiseArgs &args, const void *)
+{
+ return (args.input_cols + args.padding.left) >= (args.kernel_cols - 1);
+}
+
bool qp_has_no_left_shift(const DepthwiseArgs &args, const void *_qp) __attribute__ ((unused));
bool qp_has_no_left_shift(const DepthwiseArgs &, const void *_qp)
{