IVGCVSW-820: Add QASYMM8 support to NeonActivationLayerKernel

Change-Id: Ic3881e97b4fcbae0ac287a1e010cfc6f0fd8d7d1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/112139
Tested-by: BSG Visual Compute Jenkins server to access repositories on http://mpd-gerrit.cambridge.arm.com <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>

3 files changed, 61 insertions, 2 deletions

diff --git a/arm_compute/core/NEON/NEAsymm.h b/arm_compute/core/NEON/NEAsymm.h
index d227d3ccbe..f0d7439d40 100644
--- a/arm_compute/core/NEON/NEAsymm.h
+++ b/arm_compute/core/NEON/NEAsymm.h
@@ -28,6 +28,12 @@
 
 namespace arm_compute
 {
+using qasymm8x8_t   = uint8x8_t;   /**< 8 bit quantized asymmetric vector with 8 elements */
+using qasymm8x8x2_t = uint8x8x2_t; /**< 8 bit quantized asymmetric vector with 16 elements */
+using qasymm8x8x3_t = uint8x8x3_t; /**< 8 bit quantized asymmetric vector with 24 elements */
+using qasymm8x8x4_t = uint8x8x4_t; /**< 8 bit quantized asymmetric vector with 32 elements */
+using qasymm8x16_t  = uint8x16_t;  /**< 8 bit quantized asymmetric vector with 16 elements */
+
 /** Round to the nearest division by a power-of-two using exponent
  *
  * @note This function calculates the following expression: (x + 2^n -1 ) / 2^n where n = exponent
@@ -38,6 +44,18 @@ namespace arm_compute
  * @return the nearest division by a power-of-two using exponent
  */
 int32x4_t rounding_divide_by_pow2(int32x4_t x, int exponent);
+
+/** Perform a multiply-accumulate on all 16 components of a QASYMM8 vector
+ *
+ * vd*vs + vo
+ *
+ * @param[in] vd Input vector value in QASYMM8 format
+ * @param[in] vs Vector multiplier in F32 format. The multiplier value must be duplicated across all four lanes.
+ * @param[in] vo Vector addend in F32 format. The addend value must be duplicated across all four lanes.
+ *
+ * @return A 16-component vector in QASYMM8 format, saturated to fit
+ */
+uint8x16_t vmlaq_qasymm8(qasymm8x16_t vd, float32x4_t vs, float32x4_t vo);
 } // namespace arm_compute
 #include "arm_compute/core/NEON/NEAsymm.inl"
-#endif // __ARM_COMPUTE_NEASYMM_H__
\ No newline at end of file
+#endif // __ARM_COMPUTE_NEASYMM_H__
diff --git a/arm_compute/core/NEON/NEAsymm.inl b/arm_compute/core/NEON/NEAsymm.inl
index bbce308b35..ce999a5413 100644
--- a/arm_compute/core/NEON/NEAsymm.inl
+++ b/arm_compute/core/NEON/NEAsymm.inl
@@ -30,4 +30,38 @@ inline int32x4_t rounding_divide_by_pow2(int32x4_t x, int exponent)
     const int32x4_t fixed_up_x = vqaddq_s32(x, fixup);
     return vrshlq_s32(fixed_up_x, shift_vec);
 }
-} // namespace arm_compute
\ No newline at end of file
+
+inline qasymm8x16_t vmlaq_qasymm8(qasymm8x16_t vd, float32x4_t vs, float32x4_t vo)
+{
+    // Convert uint8 vectors to uint16 vectors
+    const uint8x8_t vd_low        = vget_low_u8(vd);
+    const uint8x8_t vd_high       = vget_high_u8(vd);
+    uint16x8_t      vd_low_u16x8  = vmovl_u8(vd_low);
+    uint16x8_t      vd_high_u16x8 = vmovl_u8(vd_high);
+    // Convert uint16 vectors to uint32 vectors
+    uint32x4_t A_u32x4 = vmovl_u16(vget_low_u16(vd_low_u16x8));
+    uint32x4_t B_u32x4 = vmovl_u16(vget_high_u16(vd_low_u16x8));
+    uint32x4_t C_u32x4 = vmovl_u16(vget_low_u16(vd_high_u16x8));
+    uint32x4_t D_u32x4 = vmovl_u16(vget_high_u16(vd_high_u16x8));
+    // Convert uint32 vectors to float32 vectors
+    float32x4_t A_f32x4 = vcvtq_f32_u32(A_u32x4);
+    float32x4_t B_f32x4 = vcvtq_f32_u32(B_u32x4);
+    float32x4_t C_f32x4 = vcvtq_f32_u32(C_u32x4);
+    float32x4_t D_f32x4 = vcvtq_f32_u32(D_u32x4);
+    // vd = vd*vs + vo
+    A_f32x4 = vmlaq_f32(vo, A_f32x4, vs);
+    B_f32x4 = vmlaq_f32(vo, B_f32x4, vs);
+    C_f32x4 = vmlaq_f32(vo, C_f32x4, vs);
+    D_f32x4 = vmlaq_f32(vo, D_f32x4, vs);
+    // Convert float32 vectors to uint32 vectors
+    A_u32x4 = vcvtq_u32_f32(A_f32x4);
+    B_u32x4 = vcvtq_u32_f32(B_f32x4);
+    C_u32x4 = vcvtq_u32_f32(C_f32x4);
+    D_u32x4 = vcvtq_u32_f32(D_f32x4);
+    // Convert uint32 vectors to uint16 vectors (with saturation)
+    vd_low_u16x8  = vcombine_u16(vqmovn_u32(A_u32x4), vqmovn_u32(B_u32x4));
+    vd_high_u16x8 = vcombine_u16(vqmovn_u32(C_u32x4), vqmovn_u32(D_u32x4));
+    // convert uint16 vectors to uint8 vectors (with saturation)
+    return vcombine_u8(vqmovn_u16(vd_low_u16x8), vqmovn_u16(vd_high_u16x8));
+}
+} // namespace arm_compute
diff --git a/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h b/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h
index e8c032aaeb..1edda843de 100644
--- a/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h
+++ b/arm_compute/core/NEON/kernels/NEActivationLayerKernel.h
@@ -26,6 +26,7 @@
 
 #include "arm_compute/core/FixedPoint.h"
 #include "arm_compute/core/NEON/INEKernel.h"
+#include "arm_compute/core/QAsymm8.h"
 
 #ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
 #include <arm_fp16.h>
@@ -105,6 +106,12 @@ private:
      * @param[in] window Region on which to execute the kernel
      */
     template <ActivationLayerInfo::ActivationFunction F, typename T>
+    typename std::enable_if<std::is_same<T, qasymm8_t>::value, void>::type activation(const Window &window);
+    /** Function to apply an activation function on a tensor.
+     *
+     * @param[in] window Region on which to execute the kernel
+     */
+    template <ActivationLayerInfo::ActivationFunction F, typename T>
     typename std::enable_if<std::is_same<T, qint16_t>::value, void>::type activation(const Window &window);
 
 private: