COMPMID-791: Adds support of QASYMM8 in NEDepthwiseConvolution3x3

Change-Id: I1a9ed6c3420ddf8978aeaad48d9915333b006b49
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/116374
Tested-by: Jenkins <bsgcomp@arm.com>
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>

1 files changed, 16 insertions, 8 deletions

diff --git a/arm_compute/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h b/arm_compute/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h
index 46d52fc182..c42e5c43b5 100644
--- a/arm_compute/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h
+++ b/arm_compute/core/NEON/kernels/NEDirectConvolutionLayerOutputStageKernel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited.
+ * Copyright (c) 2017-2018 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -50,13 +50,17 @@ public:
     ~NEDirectConvolutionLayerOutputStageKernel() = default;
     /** Set the accumulate buffer and the biases of the kernel.
      *
-     * @param[in, out] input  Input to add the bias to. If @p output is not specified then accumulation is done in-place.
-     *                        Data type supported: QS16/QS32/F16/F32
-     * @param[in]      bias   (Optional) The shared bias tensor to add. It must be 1D Tensor. Data type supported: Same as @p input
-     * @param[out]     output (Optional) If the output tensor is specified the accumulation is done out-of-place. (Defaults to nullptr)
-     *                         Data type supported: QS8/QS16/F16/F32
+     * @param[in, out] input                        Input to add the bias to. If @p output is not specified then accumulation is done in-place.
+     *                                              Data type supported: QS16/QS32/F16/F32
+     * @param[in]      bias                         (Optional) The shared bias tensor to add. It must be 1D Tensor. Data type supported: Same as @p input
+     * @param[out]     output                       (Optional) If the output tensor is specified the accumulation is done out-of-place. (Defaults to nullptr)
+     *                                              Data type supported: QS8/QS16/F16/F32
+     * @param[in]      result_fixedpoint_multiplier (Optional)Fixed point value to be multiplied to each element of the input matrix when once the result_offset has been add
+     * @param[in]      result_shift                 (Optional)Integer value used to round to nearest division by a power-of-two the result after the fixed point multiplication
+     * @param[in]      result_offset_after_shift    (Optional)Offset to be applied to result before converting it back to QASYMM8
      */
-    void configure(ITensor *input, const ITensor *bias = nullptr, ITensor *output = nullptr);
+    void configure(ITensor *input, const ITensor *bias = nullptr, ITensor *output = nullptr,
+                   int result_fixedpoint_multiplier = 0, int result_shift = 0, int result_offset_after_shift = 0);
     /** Static function to check if given info will lead to a valid configuration of @ref NEDirectConvolutionLayerOutputStageKernel
      *
      * @param[in] input  Input to add the bias to. If @p output is not specified then accumulation is done in-place.
@@ -72,13 +76,17 @@ public:
     void run(const Window &window, const ThreadInfo &info) override;
 
 private:
-    using OutputStageKernel = void(ITensor *input, const ITensor *bias, const Window window, ITensor *output);
+    using OutputStageKernel = void(ITensor *input, const ITensor *bias, const Window &window, ITensor *output,
+                                   int result_fixedpoint_multiplier, int result_shift, int result_offset_after_shift);
 
 private:
     OutputStageKernel *_func;
     ITensor           *_input;
     const ITensor     *_bias;
     ITensor           *_output;
+    int                _result_fixedpoint_multiplier;
+    int                _result_shift;
+    int                _result_offset_after_shift;
 };
 } // namespace arm_compute
 #endif /*__ARM_COMPUTE_NEDIRECTCONVOLUTIONLAYEROUTPUTSTAGEKERNEL_H__ */