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| author | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-10-18 11:34:23 +0200 |
|---|---|---|
| committer | Kristofer Jonsson <kristofer.jonsson@arm.com> | 2022-10-18 11:56:26 +0200 |
| commit | 01c32d4768d8176a32c193f44069da1f43fbf513 (patch) | |
| tree | 881b81e57e5370190da098226c17e182e7b85bd4 /targets | |
| parent | 5f2200d06aa096fd707d87ff5bdf0d01c44009c7 (diff) | |
| download | ethos-u-core-platform-01c32d4768d8176a32c193f44069da1f43fbf513.tar.gz | |
Configure write-through caching for Corstone-310 BRAM
Change-Id: I5e0fc2ecbbf416ca07be6b9d65e989c1c116b219
Diffstat (limited to 'targets')
| -rw-r--r-- | targets/corstone-310/target.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/targets/corstone-310/target.cpp b/targets/corstone-310/target.cpp index 3b2820f..a91bc67 100644 --- a/targets/corstone-310/target.cpp +++ b/targets/corstone-310/target.cpp @@ -389,7 +389,7 @@ void targetSetup() { 1, // Non-Privileged 0), // eXecute Never disabled ARM_MPU_RLAR(0x213fffff, // Limit - Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + Mpu::WTWARA_index) // Attribute index - Write-Through, Write-Allocate, Read-allocate }, { // SSE-300 internal SRAM (S) @@ -399,7 +399,7 @@ void targetSetup() { 1, // Non-Privileged 0), // eXecute Never disabled ARM_MPU_RLAR(0x313fffff, // Limit - Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + Mpu::WTWARA_index) // Attribute index - Write-Through, Write-Allocate, Read-allocate }, { // DDR (NS) |