From 01c32d4768d8176a32c193f44069da1f43fbf513 Mon Sep 17 00:00:00 2001 From: Kristofer Jonsson Date: Tue, 18 Oct 2022 11:34:23 +0200 Subject: Configure write-through caching for Corstone-310 BRAM Change-Id: I5e0fc2ecbbf416ca07be6b9d65e989c1c116b219 --- targets/corstone-310/target.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'targets') diff --git a/targets/corstone-310/target.cpp b/targets/corstone-310/target.cpp index 3b2820f..a91bc67 100644 --- a/targets/corstone-310/target.cpp +++ b/targets/corstone-310/target.cpp @@ -389,7 +389,7 @@ void targetSetup() { 1, // Non-Privileged 0), // eXecute Never disabled ARM_MPU_RLAR(0x213fffff, // Limit - Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + Mpu::WTWARA_index) // Attribute index - Write-Through, Write-Allocate, Read-allocate }, { // SSE-300 internal SRAM (S) @@ -399,7 +399,7 @@ void targetSetup() { 1, // Non-Privileged 0), // eXecute Never disabled ARM_MPU_RLAR(0x313fffff, // Limit - Mpu::WBWARA_index) // Attribute index - Write-Back, Write-Allocate, Read-allocate + Mpu::WTWARA_index) // Attribute index - Write-Through, Write-Allocate, Read-allocate }, { // DDR (NS) -- cgit v1.2.1