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| author | James Ward <james.ward@arm.com> | 2023-02-28 10:27:11 +0000 |
|---|---|---|
| committer | Eric Kunze <eric.kunze@arm.com> | 2023-03-01 18:52:54 +0000 |
| commit | fc537fb8a2ac9fa4101cbb996e9949d9d8fc0026 (patch) | |
| tree | f13fd20aeb116830fa59b34438e59b6049646e76 /operators/tensor/conv2d_1x3/conv2d_1x3_1x65535x3x1_i8xi8_acci32_st11_pad1110_dilat11/test.json | |
| parent | b48e5e1067571c4f391db1830fdbcaedc3bd14b4 (diff) | |
| download | conformance_tests-fc537fb8a2ac9fa4101cbb996e9949d9d8fc0026.tar.gz | |
Updating CONV2D_1X3 tests for ofm_depth fix Regen
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I03cd90e8b7b701074e2d2e1a1b978e5427a5134e
Diffstat (limited to 'operators/tensor/conv2d_1x3/conv2d_1x3_1x65535x3x1_i8xi8_acci32_st11_pad1110_dilat11/test.json')
| -rw-r--r-- | operators/tensor/conv2d_1x3/conv2d_1x3_1x65535x3x1_i8xi8_acci32_st11_pad1110_dilat11/test.json | 154 |
1 files changed, 154 insertions, 0 deletions
diff --git a/operators/tensor/conv2d_1x3/conv2d_1x3_1x65535x3x1_i8xi8_acci32_st11_pad1110_dilat11/test.json b/operators/tensor/conv2d_1x3/conv2d_1x3_1x65535x3x1_i8xi8_acci32_st11_pad1110_dilat11/test.json new file mode 100644 index 000000000..6192bbd64 --- /dev/null +++ b/operators/tensor/conv2d_1x3/conv2d_1x3_1x65535x3x1_i8xi8_acci32_st11_pad1110_dilat11/test.json @@ -0,0 +1,154 @@ +{ + version: { + _major: 0, + _minor: 51, + _patch: 0, + _draft: true + }, + regions: [ + { + name: "main", + blocks: [ + { + name: "main", + operators: [ + { + op: "CONST", + attribute_type: "NONE", + inputs: [ + + ], + outputs: [ + "const-1" + ] + }, + { + op: "CONST", + attribute_type: "NONE", + inputs: [ + + ], + outputs: [ + "const-2" + ] + }, + { + op: "CONV2D", + attribute_type: "ConvAttribute", + attribute: { + pad: [ + 1, + 1, + 1, + 0 + ], + stride: [ + 1, + 1 + ], + dilation: [ + 1, + 1 + ], + input_zp: 53, + weight_zp: -38 + }, + inputs: [ + "input-0", + "const-1", + "const-2" + ], + outputs: [ + "result-0" + ] + } + ], + tensors: [ + { + name: "input-0", + shape: [ + 1, + 65535, + 3, + 1 + ], + type: "INT8" + }, + { + name: "const-1", + shape: [ + 5, + 1, + 3, + 1 + ], + type: "INT8", + data: [ + 20, + 163, + 120, + 145, + 161, + 134, + 77, + 118, + 40, + 204, + 177, + 198, + 207, + 148, + 213 + ] + }, + { + name: "const-2", + shape: [ + 5 + ], + type: "INT32", + data: [ + 202, + 175, + 56, + 116, + 129, + 66, + 132, + 247, + 235, + 103, + 162, + 192, + 113, + 140, + 6, + 188, + 193, + 163, + 182, + 157 + ] + }, + { + name: "result-0", + shape: [ + 1, + 65537, + 2, + 5 + ], + type: "INT32" + } + ], + inputs: [ + "input-0" + ], + outputs: [ + "result-0" + ] + } + ] + } + ] +} |