diff options
| author | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-10-21 15:42:22 +0300 |
|---|---|---|
| committer | Nir Ekhauz <nir.ekhauz@arm.com> | 2021-10-24 07:35:37 +0300 |
| commit | 1a9693920e6dc05e047bb56f2f2b7a7620485e45 (patch) | |
| tree | 3733ba9406aa95173cd9ed14f1a7a1938883ab66 /targets | |
| parent | 64f37cde5db1576056abe8940f73992ba3128bee (diff) | |
| download | ethos-u-core-platform-1a9693920e6dc05e047bb56f2f2b7a7620485e45.tar.gz | |
Verify Corstone-300 AN552
Set BRAM size to 1MB and SRAM size to 2MB for corstone-300 target in gcc and armclang.
Change-Id: I5728948ba64fa69459f9a28d8b6459f7d63bd4d0
Diffstat (limited to 'targets')
| -rw-r--r-- | targets/corstone-300/platform.ld | 9 | ||||
| -rw-r--r-- | targets/corstone-300/platform.scatter | 11 |
2 files changed, 14 insertions, 6 deletions
diff --git a/targets/corstone-300/platform.ld b/targets/corstone-300/platform.ld index ec58acc..d373970 100644 --- a/targets/corstone-300/platform.ld +++ b/targets/corstone-300/platform.ld @@ -48,12 +48,14 @@ * +-----------------------+-------------+-------------+----+--------------------------------------+ * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | - * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0040_0000 | NS | 0x0040_0000; 2 MiB | - * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0040_0000 | S | Secure alias for NS BRAM | + * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0010_0000 | NS | 0x0100_0000; 1 MiB | + * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0010_0000 | S | Secure alias for NS BRAM | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | + * | QSPI external flash | 0x2800_0000 | 0x0080_0000 | NS | 8MB | + * | QSPI external flash | 0x3800_0000 | 0x0080_0000 | S | 8MB | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | * +-----------------------+-------------+-------------+----+--------------------------------------+ @@ -81,9 +83,10 @@ __HEAP_SIZE = 0x00008000; MEMORY { ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 - BRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x00400000 + BRAM (rw) : ORIGIN = 0x11000000, LENGTH = 0x00100000 DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 0x00080000 SRAM (rw) : ORIGIN = 0x31000000, LENGTH = 0x00200000 + QSPI (rw) : ORIGIN = 0x38000000, LENGTH = 0x00800000 DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x60000000 } diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter index fab12d1..e115c0f 100644 --- a/targets/corstone-300/platform.scatter +++ b/targets/corstone-300/platform.scatter @@ -48,12 +48,14 @@ * +-----------------------+-------------+-------------+----+--------------------------------------+ * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | - * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0020_0000 | NS | 0x0100_0000; 2 MiB | - * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | + * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0010_0000 | NS | 0x0100_0000; 1 MiB | + * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0010_0000 | S | Secure alias for NS BRAM | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | + * | QSPI external flash | 0x2800_0000 | 0x0080_0000 | NS | 8MB | + * | QSPI external flash | 0x3800_0000 | 0x0080_0000 | S | 8MB | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | * +-----------------------+-------------+-------------+----+--------------------------------------+ @@ -102,7 +104,7 @@ #define ITCM_SIZE 0x00080000 #define BRAM_START 0x11000000 -#define BRAM_SIZE 0x00200000 +#define BRAM_SIZE 0x00100000 #define DTCM_START 0x30000000 #define DTCM_SIZE 0x00080000 @@ -110,6 +112,9 @@ #define SRAM_START 0x31000000 #define SRAM_SIZE 0x00200000 +#define QSPI_START 0x38000000 +#define QSPI_SIZE 0x00800000 + #define DDR_START 0x70000000 #define DDR_SIZE 0x02000000 |