diff options
Diffstat (limited to 'targets/corstone-300/platform.scatter')
| -rw-r--r-- | targets/corstone-300/platform.scatter | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/targets/corstone-300/platform.scatter b/targets/corstone-300/platform.scatter index fab12d1..e115c0f 100644 --- a/targets/corstone-300/platform.scatter +++ b/targets/corstone-300/platform.scatter @@ -48,12 +48,14 @@ * +-----------------------+-------------+-------------+----+--------------------------------------+ * | ITCM | 0x0000_0000 | 0x0008_0000 | NS | 0x0000_0000; 512 kiB | * | ITCM | 0x1000_0000 | 0x0008_0000 | S | Secure alias for NS ITCM | - * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0020_0000 | NS | 0x0100_0000; 2 MiB | - * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0020_0000 | S | Secure alias for NS BRAM | + * | FPGA Data SRAM; BRAM | 0x0100_0000 | 0x0010_0000 | NS | 0x0100_0000; 1 MiB | + * | FPGA data SRAM; BRAM | 0x1100_0000 | 0x0010_0000 | S | Secure alias for NS BRAM | * | DTCM | 0x2000_0000 | 0x0008_0000 | NS | 512 kiB; 4 banks of 128k each | * | DTCM | 0x3000_0000 | 0x0008_0000 | S | Secure alias for NS DTCM | * | SSE-300 internal SRAM | 0x2100_0000 | 0x0020_0000 | NS | 1 bank of 2 MiB; 3cc latency) | * | SSE-300 internal SRAM | 0x3100_0000 | 0x0020_0000 | S | Secure alias for NS internal SRAM | + * | QSPI external flash | 0x2800_0000 | 0x0080_0000 | NS | 8MB | + * | QSPI external flash | 0x3800_0000 | 0x0080_0000 | S | 8MB | * | DDR | 0x6000_0000 | 0x1000_0000 | NS | 0x0800_0000; 256 MiB bank | * | DDR | 0x7000_0000 | 0x1000_0000 | S | 0x0C00_0000; 256 MiB bank | * +-----------------------+-------------+-------------+----+--------------------------------------+ @@ -102,7 +104,7 @@ #define ITCM_SIZE 0x00080000 #define BRAM_START 0x11000000 -#define BRAM_SIZE 0x00200000 +#define BRAM_SIZE 0x00100000 #define DTCM_START 0x30000000 #define DTCM_SIZE 0x00080000 @@ -110,6 +112,9 @@ #define SRAM_START 0x31000000 #define SRAM_SIZE 0x00200000 +#define QSPI_START 0x38000000 +#define QSPI_SIZE 0x00800000 + #define DDR_START 0x70000000 #define DDR_SIZE 0x02000000 |