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| author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2022-11-01 15:59:50 +0000 |
|---|---|---|
| committer | TeresaARM <teresa.charlinreyes@arm.com> | 2023-05-08 13:16:01 +0000 |
| commit | 1fe6c8170ae2fe90b53fb71b7570aec9dfe75c45 (patch) | |
| tree | bbb846edda64445c1e033b182e5a079c8d5728d8 /docs | |
| parent | c52190a7e80cf238ba1d8630e5cc36ec7c7849e2 (diff) | |
| download | armnn-1fe6c8170ae2fe90b53fb71b7570aec9dfe75c45.tar.gz | |
IVGCVSW-7307 Add CpuAcc Batch MatMul Workload
* Call dedicated MatMul kernel in ACL
* Add int8 tests
* Add int8 to documentation
* Force tensors to be dynamic (nonConst) as per request of ACL
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I992ae9aae1174214607bf29305f21cdeaf3fdc1b
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/02_operator_list.dox | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/docs/02_operator_list.dox b/docs/02_operator_list.dox index 007d4f5e35..791565a985 100644 --- a/docs/02_operator_list.dox +++ b/docs/02_operator_list.dox @@ -1,4 +1,4 @@ -/// Copyright (c) 2021 ARM Limited and Contributors. All rights reserved. +/// Copyright (c) 2021, 2023 ARM Limited and Contributors. All rights reserved. /// /// SPDX-License-Identifier: MIT /// @@ -299,6 +299,7 @@ where N = batches, C = channels, H = height, W = width <table> <tr><th> <tr><td>FLOAT32 + <tr><td>QASYMMS8 </table> <tr> <td>GpuAcc |