diff options
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp | 284 |
1 files changed, 142 insertions, 142 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp index 60135a42d5..2c517695c4 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -141,9 +141,9 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v0.4s, #0x0\n" "cbz x23, 4f\n" "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" "add x22, x22, #0x10\n" - "ldr q31, [x21, x27]\n" "ldr q30, [x20, x27]\n" "ldr q29, [x21, x26]\n" "ldr q28, [x20, x26]\n" @@ -156,26 +156,26 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddl v23.8h, v31.8b, v30.8b\n" "saddl2 v22.8h, v31.16b, v30.16b\n" "ldp x21, x20, [x22, #0x0]\n" - "subs x23, x23, #0x1\n" - "saddl v21.8h, v29.8b, v28.8b\n" - "saddl2 v20.8h, v29.16b, v28.16b\n" - "add x22, x22, #0x10\n" - "saddl v19.8h, v27.8b, v26.8b\n" - "saddl2 v18.8h, v27.16b, v26.16b\n" "ldr q31, [x21, x27]\n" "ldr q30, [x20, x27]\n" + "saddl v21.8h, v29.8b, v28.8b\n" + "saddl2 v20.8h, v29.16b, v28.16b\n" "ldr q29, [x21, x26]\n" "ldr q28, [x20, x26]\n" - "saddl v17.8h, v25.8b, v24.8b\n" - "saddl2 v16.8h, v25.16b, v24.16b\n" + "saddl v19.8h, v27.8b, v26.8b\n" + "saddl2 v18.8h, v27.16b, v26.16b\n" "ldr q27, [x21, x25]\n" "ldr q26, [x20, x25]\n" - "saddw v15.4s, v15.4s, v23.4h\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" + "saddl v17.8h, v25.8b, v24.8b\n" + "saddl2 v16.8h, v25.16b, v24.16b\n" "ldr q25, [x21, x24]\n" "ldr q24, [x20, x24]\n" + "subs x23, x23, #0x1\n" + "saddw v15.4s, v15.4s, v23.4h\n" + "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" + "add x22, x22, #0x10\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" "saddw v9.4s, v9.4s, v20.4h\n" @@ -219,17 +219,17 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "beq 6f\n" "5:" // 4-vectors of channels: Single input loop "ldr x20, [x22], #0x8\n" - "subs x23, x23, #0x1\n" - "ldr q19, [x20, x27]\n" - "ldr q18, [x20, x26]\n" + "ldr q16, [x20, x27]\n" + "sxtl v23.8h, v16.8b\n" + "sxtl2 v22.8h, v16.16b\n" + "ldr q16, [x20, x26]\n" "ldr q17, [x20, x25]\n" + "sxtl v21.8h, v16.8b\n" + "sxtl2 v20.8h, v16.16b\n" "ldr q16, [x20, x24]\n" - "sxtl v23.8h, v19.8b\n" - "sxtl2 v22.8h, v19.16b\n" - "sxtl v21.8h, v18.8b\n" - "sxtl2 v20.8h, v18.16b\n" "sxtl v19.8h, v17.8b\n" "sxtl2 v18.8h, v17.16b\n" + "subs x23, x23, #0x1\n" "sxtl v17.8h, v16.8b\n" "sxtl2 v16.8h, v16.16b\n" "saddw v15.4s, v15.4s, v23.4h\n" @@ -250,61 +250,61 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw2 v0.4s, v0.4s, v16.8h\n" "bgt 5b\n" "6:" // 4-vectors of channels: Single input loop: End - "ld1r { v20.4s }, [%x[left_shift]]\n" - "ld1r { v19.4s }, [%x[combined_rescale_value]]\n" - "movi v18.4s, #0x7f\n" + "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" + "srshl v15.4s, v15.4s, v18.4s\n" + "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" + "srshl v13.4s, v13.4s, v18.4s\n" + "srshl v12.4s, v12.4s, v18.4s\n" "sub %x[n_channels], %x[n_channels], #0x40\n" - "ld1r { v17.4s }, [%x[right_shift]]\n" + "srshl v11.4s, v11.4s, v18.4s\n" + "srshl v10.4s, v10.4s, v18.4s\n" "cmp %x[n_channels], #0x40\n" - "not v16.16b, v18.16b\n" - "srshl v15.4s, v15.4s, v20.4s\n" - "srshl v14.4s, v14.4s, v20.4s\n" - "srshl v13.4s, v13.4s, v20.4s\n" - "srshl v12.4s, v12.4s, v20.4s\n" - "srshl v11.4s, v11.4s, v20.4s\n" - "srshl v10.4s, v10.4s, v20.4s\n" - "srshl v9.4s, v9.4s, v20.4s\n" - "srshl v8.4s, v8.4s, v20.4s\n" - "srshl v7.4s, v7.4s, v20.4s\n" - "srshl v6.4s, v6.4s, v20.4s\n" - "srshl v5.4s, v5.4s, v20.4s\n" - "srshl v4.4s, v4.4s, v20.4s\n" - "srshl v3.4s, v3.4s, v20.4s\n" - "srshl v2.4s, v2.4s, v20.4s\n" - "srshl v1.4s, v1.4s, v20.4s\n" - "srshl v0.4s, v0.4s, v20.4s\n" - "sqrdmulh v15.4s, v15.4s, v19.4s\n" - "sqrdmulh v14.4s, v14.4s, v19.4s\n" - "sqrdmulh v13.4s, v13.4s, v19.4s\n" - "sqrdmulh v12.4s, v12.4s, v19.4s\n" - "sqrdmulh v11.4s, v11.4s, v19.4s\n" - "sqrdmulh v10.4s, v10.4s, v19.4s\n" - "sqrdmulh v9.4s, v9.4s, v19.4s\n" - "sqrdmulh v8.4s, v8.4s, v19.4s\n" - "sqrdmulh v7.4s, v7.4s, v19.4s\n" - "sqrdmulh v6.4s, v6.4s, v19.4s\n" - "sqrdmulh v5.4s, v5.4s, v19.4s\n" - "sqrdmulh v4.4s, v4.4s, v19.4s\n" - "sqrdmulh v3.4s, v3.4s, v19.4s\n" - "sqrdmulh v2.4s, v2.4s, v19.4s\n" - "sqrdmulh v1.4s, v1.4s, v19.4s\n" - "sqrdmulh v0.4s, v0.4s, v19.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" - "srshl v11.4s, v11.4s, v17.4s\n" - "srshl v10.4s, v10.4s, v17.4s\n" - "srshl v9.4s, v9.4s, v17.4s\n" - "srshl v8.4s, v8.4s, v17.4s\n" - "srshl v7.4s, v7.4s, v17.4s\n" - "srshl v6.4s, v6.4s, v17.4s\n" - "srshl v5.4s, v5.4s, v17.4s\n" - "srshl v4.4s, v4.4s, v17.4s\n" - "srshl v3.4s, v3.4s, v17.4s\n" - "srshl v2.4s, v2.4s, v17.4s\n" - "srshl v1.4s, v1.4s, v17.4s\n" - "srshl v0.4s, v0.4s, v17.4s\n" + "srshl v9.4s, v9.4s, v18.4s\n" + "srshl v8.4s, v8.4s, v18.4s\n" + "srshl v7.4s, v7.4s, v18.4s\n" + "srshl v6.4s, v6.4s, v18.4s\n" + "srshl v5.4s, v5.4s, v18.4s\n" + "srshl v4.4s, v4.4s, v18.4s\n" + "srshl v3.4s, v3.4s, v18.4s\n" + "srshl v2.4s, v2.4s, v18.4s\n" + "srshl v1.4s, v1.4s, v18.4s\n" + "srshl v0.4s, v0.4s, v18.4s\n" + "sqrdmulh v15.4s, v15.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v13.4s, v13.4s, v17.4s\n" + "sqrdmulh v12.4s, v12.4s, v17.4s\n" + "sqrdmulh v11.4s, v11.4s, v17.4s\n" + "sqrdmulh v10.4s, v10.4s, v17.4s\n" + "sqrdmulh v9.4s, v9.4s, v17.4s\n" + "sqrdmulh v8.4s, v8.4s, v17.4s\n" + "sqrdmulh v7.4s, v7.4s, v17.4s\n" + "sqrdmulh v6.4s, v6.4s, v17.4s\n" + "sqrdmulh v5.4s, v5.4s, v17.4s\n" + "sqrdmulh v4.4s, v4.4s, v17.4s\n" + "sqrdmulh v3.4s, v3.4s, v17.4s\n" + "sqrdmulh v2.4s, v2.4s, v17.4s\n" + "sqrdmulh v1.4s, v1.4s, v17.4s\n" + "sqrdmulh v0.4s, v0.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "srshl v11.4s, v11.4s, v16.4s\n" + "srshl v10.4s, v10.4s, v16.4s\n" + "srshl v9.4s, v9.4s, v16.4s\n" + "srshl v8.4s, v8.4s, v16.4s\n" + "srshl v7.4s, v7.4s, v16.4s\n" + "srshl v6.4s, v6.4s, v16.4s\n" + "srshl v5.4s, v5.4s, v16.4s\n" + "srshl v4.4s, v4.4s, v16.4s\n" + "srshl v3.4s, v3.4s, v16.4s\n" + "srshl v2.4s, v2.4s, v16.4s\n" + "srshl v1.4s, v1.4s, v16.4s\n" + "srshl v0.4s, v0.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" @@ -321,36 +321,36 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "smax v2.4s, v2.4s, v16.4s\n" "smax v1.4s, v1.4s, v16.4s\n" "smax v0.4s, v0.4s, v16.4s\n" - "smin v15.4s, v15.4s, v18.4s\n" - "smin v14.4s, v14.4s, v18.4s\n" - "smin v13.4s, v13.4s, v18.4s\n" - "smin v12.4s, v12.4s, v18.4s\n" - "smin v11.4s, v11.4s, v18.4s\n" - "smin v10.4s, v10.4s, v18.4s\n" - "smin v9.4s, v9.4s, v18.4s\n" - "smin v8.4s, v8.4s, v18.4s\n" - "smin v7.4s, v7.4s, v18.4s\n" - "smin v6.4s, v6.4s, v18.4s\n" - "smin v5.4s, v5.4s, v18.4s\n" - "smin v4.4s, v4.4s, v18.4s\n" - "smin v3.4s, v3.4s, v18.4s\n" - "smin v2.4s, v2.4s, v18.4s\n" - "smin v1.4s, v1.4s, v18.4s\n" - "smin v0.4s, v0.4s, v18.4s\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" + "smin v11.4s, v11.4s, v17.4s\n" + "smin v10.4s, v10.4s, v17.4s\n" + "smin v9.4s, v9.4s, v17.4s\n" + "smin v8.4s, v8.4s, v17.4s\n" + "smin v7.4s, v7.4s, v17.4s\n" + "smin v6.4s, v6.4s, v17.4s\n" + "smin v5.4s, v5.4s, v17.4s\n" + "smin v4.4s, v4.4s, v17.4s\n" + "smin v3.4s, v3.4s, v17.4s\n" + "smin v2.4s, v2.4s, v17.4s\n" + "smin v1.4s, v1.4s, v17.4s\n" + "smin v0.4s, v0.4s, v17.4s\n" "uzp1 v23.16b, v15.16b, v14.16b\n" - "uzp1 v19.16b, v13.16b, v12.16b\n" + "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v22.16b, v11.16b, v10.16b\n" "uzp1 v18.16b, v9.16b, v8.16b\n" "uzp1 v21.16b, v7.16b, v6.16b\n" "uzp1 v17.16b, v5.16b, v4.16b\n" "uzp1 v20.16b, v3.16b, v2.16b\n" - "uzp1 v16.16b, v1.16b, v0.16b\n" - "uzp1 v19.16b, v23.16b, v19.16b\n" + "uzp1 v19.16b, v1.16b, v0.16b\n" + "uzp1 v16.16b, v23.16b, v16.16b\n" "uzp1 v18.16b, v22.16b, v18.16b\n" - "uzp1 v17.16b, v21.16b, v17.16b\n" - "uzp1 v16.16b, v20.16b, v16.16b\n" - "str q19, [%x[outptr], x27]\n" + "str q16, [%x[outptr], x27]\n" "add x27, x27, #0x40\n" + "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v20.16b, v19.16b\n" "str q18, [%x[outptr], x26]\n" "add x26, x26, #0x40\n" "str q17, [%x[outptr], x25]\n" @@ -371,23 +371,23 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v12.4s, #0x0\n" "cbz x23, 11f\n" "ldp x21, x20, [x22, #0x0]\n" + "ldr q31, [x21, x27]\n" "subs x23, x23, #0x1\n" "add x22, x22, #0x10\n" - "ldr q31, [x21, x27]\n" "ldr q30, [x20, x27]\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop "saddl v17.8h, v31.8b, v30.8b\n" "saddl2 v16.8h, v31.16b, v30.16b\n" "ldp x21, x20, [x22, #0x0]\n" - "subs x23, x23, #0x1\n" - "add x22, x22, #0x10\n" "ldr q31, [x21, x27]\n" "ldr q30, [x20, x27]\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v17.4h\n" "saddw2 v14.4s, v14.4s, v17.8h\n" "saddw v13.4s, v13.4s, v16.4h\n" "saddw2 v12.4s, v12.4s, v16.8h\n" + "add x22, x22, #0x10\n" "bgt 9b\n" "10:" // Single vector of channels: Loop: 2 inputs tail "saddl v17.8h, v31.8b, v30.8b\n" @@ -401,43 +401,43 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "beq 13f\n" "12:" // Single vector of channels: Loop: Single input loop "ldr x20, [x22], #0x8\n" - "subs x23, x23, #0x1\n" "ldr q16, [x20, x27]\n" "sxtl v17.8h, v16.8b\n" "sxtl2 v16.8h, v16.16b\n" + "subs x23, x23, #0x1\n" "saddw v15.4s, v15.4s, v17.4h\n" "saddw2 v14.4s, v14.4s, v17.8h\n" "saddw v13.4s, v13.4s, v16.4h\n" "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 12b\n" "13:" // Single vector of channels: Loop: Single input loop: End - "ld1r { v20.4s }, [%x[left_shift]]\n" - "ld1r { v19.4s }, [%x[combined_rescale_value]]\n" - "movi v18.4s, #0x7f\n" + "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" + "srshl v15.4s, v15.4s, v18.4s\n" + "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" + "srshl v13.4s, v13.4s, v18.4s\n" + "srshl v12.4s, v12.4s, v18.4s\n" "sub %x[n_channels], %x[n_channels], #0x10\n" - "ld1r { v17.4s }, [%x[right_shift]]\n" + "sqrdmulh v15.4s, v15.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" "cmp %x[n_channels], #0x10\n" - "not v16.16b, v18.16b\n" - "srshl v15.4s, v15.4s, v20.4s\n" - "srshl v14.4s, v14.4s, v20.4s\n" - "srshl v13.4s, v13.4s, v20.4s\n" - "srshl v12.4s, v12.4s, v20.4s\n" - "sqrdmulh v15.4s, v15.4s, v19.4s\n" - "sqrdmulh v14.4s, v14.4s, v19.4s\n" - "sqrdmulh v13.4s, v13.4s, v19.4s\n" - "sqrdmulh v12.4s, v12.4s, v19.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" + "sqrdmulh v13.4s, v13.4s, v17.4s\n" + "sqrdmulh v12.4s, v12.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v15.4s, v15.4s, v18.4s\n" - "smin v14.4s, v14.4s, v18.4s\n" - "smin v13.4s, v13.4s, v18.4s\n" - "smin v12.4s, v12.4s, v18.4s\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v16.16b, v17.16b, v16.16b\n" @@ -457,10 +457,10 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "15:" // Oddments: 2 inputs loop "ldp x21, x20, [x22, #0x0]\n" "add x22, x22, #0x10\n" - "movi v31.16b, #0x0\n" - "movi v30.16b, #0x0\n" "add x21, x21, x27\n" + "movi v31.16b, #0x0\n" "add x20, x20, x27\n" + "movi v30.16b, #0x0\n" "tbz %x[n_channels], #3, 19f\n" "ldr d31, [x21], #0x8\n" "ldr d30, [x20], #0x8\n" @@ -534,8 +534,8 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "beq 34f\n" "25:" // Oddments: Single input loop "ldr x21, [x22], #0x8\n" - "movi v31.16b, #0x0\n" "add x21, x21, x27\n" + "movi v31.16b, #0x0\n" "tbz %x[n_channels], #3, 29f\n" "ldr d31, [x21], #0x8\n" "tbz %x[n_channels], #2, 27f\n" @@ -590,31 +590,31 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "saddw2 v12.4s, v12.4s, v16.8h\n" "bgt 25b\n" "34:" // Oddments: Single input loop: End - "ld1r { v20.4s }, [%x[left_shift]]\n" - "ld1r { v19.4s }, [%x[combined_rescale_value]]\n" - "movi v18.4s, #0x7f\n" - "ld1r { v17.4s }, [%x[right_shift]]\n" - "not v16.16b, v18.16b\n" - "srshl v15.4s, v15.4s, v20.4s\n" - "srshl v14.4s, v14.4s, v20.4s\n" - "srshl v13.4s, v13.4s, v20.4s\n" - "srshl v12.4s, v12.4s, v20.4s\n" - "sqrdmulh v15.4s, v15.4s, v19.4s\n" - "sqrdmulh v14.4s, v14.4s, v19.4s\n" - "sqrdmulh v13.4s, v13.4s, v19.4s\n" - "sqrdmulh v12.4s, v12.4s, v19.4s\n" - "srshl v15.4s, v15.4s, v17.4s\n" - "srshl v14.4s, v14.4s, v17.4s\n" - "srshl v13.4s, v13.4s, v17.4s\n" - "srshl v12.4s, v12.4s, v17.4s\n" + "ld1r { v18.4s }, [%x[left_shift]]\n" + "ld1r { v17.4s }, [%x[combined_rescale_value]]\n" + "srshl v15.4s, v15.4s, v18.4s\n" + "srshl v14.4s, v14.4s, v18.4s\n" + "ld1r { v16.4s }, [%x[right_shift]]\n" + "srshl v13.4s, v13.4s, v18.4s\n" + "srshl v12.4s, v12.4s, v18.4s\n" + "sqrdmulh v15.4s, v15.4s, v17.4s\n" + "sqrdmulh v14.4s, v14.4s, v17.4s\n" + "sqrdmulh v13.4s, v13.4s, v17.4s\n" + "sqrdmulh v12.4s, v12.4s, v17.4s\n" + "movi v17.4s, #0x7f\n" + "srshl v15.4s, v15.4s, v16.4s\n" + "srshl v14.4s, v14.4s, v16.4s\n" + "srshl v13.4s, v13.4s, v16.4s\n" + "srshl v12.4s, v12.4s, v16.4s\n" + "not v16.16b, v17.16b\n" "smax v15.4s, v15.4s, v16.4s\n" "smax v14.4s, v14.4s, v16.4s\n" "smax v13.4s, v13.4s, v16.4s\n" "smax v12.4s, v12.4s, v16.4s\n" - "smin v15.4s, v15.4s, v18.4s\n" - "smin v14.4s, v14.4s, v18.4s\n" - "smin v13.4s, v13.4s, v18.4s\n" - "smin v12.4s, v12.4s, v18.4s\n" + "smin v15.4s, v15.4s, v17.4s\n" + "smin v14.4s, v14.4s, v17.4s\n" + "smin v13.4s, v13.4s, v17.4s\n" + "smin v12.4s, v12.4s, v17.4s\n" "uzp1 v17.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v16.16b, v17.16b, v16.16b\n" |