Align kernel/operator header layout

- Redirect validate documentation to configure
- Align header names
- Align class layout

Signed-off-by: Georgios Pinitas <georgios.pinitas@arm.com>
Change-Id: Ia40f67383826a66e9f9a33745d66805551e31a3a
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5897
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>

1 files changed, 5 insertions, 5 deletions

diff --git a/src/core/cpu/kernels/CpuDepthwiseConv2dNativeKernel.cpp b/src/core/cpu/kernels/CpuDepthwiseConv2dNativeKernel.cpp
index eac9baaf01..5530eba9f1 100644
--- a/src/core/cpu/kernels/CpuDepthwiseConv2dNativeKernel.cpp
+++ b/src/core/cpu/kernels/CpuDepthwiseConv2dNativeKernel.cpp
@@ -803,11 +803,6 @@ Status validate_arguments(const ITensorInfo *src, const ITensorInfo *weights, co
 }
 } // namespace
 
-CpuDepthwiseConv2dNativeKernel::CpuDepthwiseConv2dNativeKernel()
-    : _func(), _conv_info(), _depth_multiplier(1), _dilation(), _output_multiplier(), _output_shift(), _has_biases()
-{
-}
-
 void CpuDepthwiseConv2dNativeKernel::configure(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, ITensorInfo *dst, const ConvolutionInfo &info)
 {
     ARM_COMPUTE_ERROR_ON_NULLPTR(src, weights, dst);
@@ -945,6 +940,11 @@ void CpuDepthwiseConv2dNativeKernel::run_op(ITensorPack &tensors, const Window &
     auto       dst     = tensors.get_tensor(TensorType::ACL_DST);
     (this->*_func)(src, weights, biases, dst, window, _has_biases);
 }
+
+const char *CpuDepthwiseConv2dNativeKernel::name() const
+{
+    return "CpuDepthwiseConv2dNativeKernel";
+}
 } // namespace kernels
 } // namespace cpu
 } // namespace arm_compute