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author | Michael Tyler <michael.tyler@arm.com> | 2023-04-12 17:43:17 +0100 |
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committer | michael.tyler <michael.tyler@arm.com> | 2023-06-05 15:57:58 +0000 |
commit | 74921eee924625426429044decefe3673561b174 (patch) | |
tree | 654da1a95e3d42d6af8ad1ff27bb40d77b1fd8c5 /src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp | |
parent | df5d9878008be9b60586df97ebfff197abb5195e (diff) | |
download | ComputeLibrary-74921eee924625426429044decefe3673561b174.tar.gz |
Update CPU kernel implementations and guard directives
Resolves COMPMID-6023
Change-Id: I868975d14c4f98af6716726feda22405a6a4c891
Signed-off-by: Michael Tyler <michael.tyler@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp')
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp | 120 |
1 files changed, 62 insertions, 58 deletions
diff --git a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp index 1ac2ac075e..3b16c97e2c 100644 --- a/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp +++ b/src/core/NEON/kernels/arm_gemm/kernels/sve_interleaved_fp16_mla_8x3VL/generic.cpp @@ -28,8 +28,12 @@ namespace arm_gemm { void sve_interleaved_fp16_mla_8x3VL( - const __fp16 *Apanel, const __fp16 *Bpanel, - __fp16 *Cpanel, int ablocks, int bblocks, int K) { + const __fp16 *Apanel, + const __fp16 *Bpanel, + __fp16 *Cpanel, + int ablocks, + int bblocks, + int K) { struct KernelArgs { size_t K = {}; @@ -83,16 +87,16 @@ void sve_interleaved_fp16_mla_8x3VL( "3:" // main loop head "fmla z8.h, z2.h, z0.h[0]\n" "fmla z11.h, z2.h, z0.h[1]\n" - "ld1rqh { z1.h }, p0/Z, [%x[Apanel], #16]\n" + "ld1rqh { z7.h }, p0/Z, [%x[Apanel], #16]\n" "fmla z14.h, z2.h, z0.h[2]\n" "fmla z17.h, z2.h, z0.h[3]\n" - "ld1h { z5.h }, p0/Z, [x22, #3, MUL VL]\n" + "ld1h { z6.h }, p0/Z, [x22, #3, MUL VL]\n" "fmla z20.h, z2.h, z0.h[4]\n" "fmla z23.h, z2.h, z0.h[5]\n" - "ld1h { z6.h }, p0/Z, [x22, #4, MUL VL]\n" + "ld1h { z5.h }, p0/Z, [x22, #4, MUL VL]\n" "fmla z26.h, z2.h, z0.h[6]\n" "fmla z29.h, z2.h, z0.h[7]\n" - "ld1h { z7.h }, p0/Z, [x22, #5, MUL VL]\n" + "ld1h { z1.h }, p0/Z, [x22, #5, MUL VL]\n" "fmla z9.h, z3.h, z0.h[0]\n" "fmla z12.h, z3.h, z0.h[1]\n" "addvl x22, x22, #6\n" @@ -116,31 +120,31 @@ void sve_interleaved_fp16_mla_8x3VL( "fmla z28.h, z4.h, z0.h[6]\n" "fmla z31.h, z4.h, z0.h[7]\n" "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" - "fmla z8.h, z5.h, z1.h[0]\n" - "fmla z11.h, z5.h, z1.h[1]\n" + "fmla z8.h, z6.h, z7.h[0]\n" + "fmla z11.h, z6.h, z7.h[1]\n" "ld1h { z4.h }, p0/Z, [x22, #2, MUL VL]\n" - "fmla z14.h, z5.h, z1.h[2]\n" - "fmla z17.h, z5.h, z1.h[3]\n" - "fmla z20.h, z5.h, z1.h[4]\n" - "fmla z23.h, z5.h, z1.h[5]\n" - "fmla z26.h, z5.h, z1.h[6]\n" - "fmla z29.h, z5.h, z1.h[7]\n" - "fmla z9.h, z6.h, z1.h[0]\n" - "fmla z12.h, z6.h, z1.h[1]\n" - "fmla z15.h, z6.h, z1.h[2]\n" - "fmla z18.h, z6.h, z1.h[3]\n" - "fmla z21.h, z6.h, z1.h[4]\n" - "fmla z24.h, z6.h, z1.h[5]\n" - "fmla z27.h, z6.h, z1.h[6]\n" - "fmla z30.h, z6.h, z1.h[7]\n" - "fmla z10.h, z7.h, z1.h[0]\n" - "fmla z13.h, z7.h, z1.h[1]\n" - "fmla z16.h, z7.h, z1.h[2]\n" - "fmla z19.h, z7.h, z1.h[3]\n" - "fmla z22.h, z7.h, z1.h[4]\n" - "fmla z25.h, z7.h, z1.h[5]\n" - "fmla z28.h, z7.h, z1.h[6]\n" - "fmla z31.h, z7.h, z1.h[7]\n" + "fmla z14.h, z6.h, z7.h[2]\n" + "fmla z17.h, z6.h, z7.h[3]\n" + "fmla z20.h, z6.h, z7.h[4]\n" + "fmla z23.h, z6.h, z7.h[5]\n" + "fmla z26.h, z6.h, z7.h[6]\n" + "fmla z29.h, z6.h, z7.h[7]\n" + "fmla z9.h, z5.h, z7.h[0]\n" + "fmla z12.h, z5.h, z7.h[1]\n" + "fmla z15.h, z5.h, z7.h[2]\n" + "fmla z18.h, z5.h, z7.h[3]\n" + "fmla z21.h, z5.h, z7.h[4]\n" + "fmla z24.h, z5.h, z7.h[5]\n" + "fmla z27.h, z5.h, z7.h[6]\n" + "fmla z30.h, z5.h, z7.h[7]\n" + "fmla z10.h, z1.h, z7.h[0]\n" + "fmla z13.h, z1.h, z7.h[1]\n" + "fmla z16.h, z1.h, z7.h[2]\n" + "fmla z19.h, z1.h, z7.h[3]\n" + "fmla z22.h, z1.h, z7.h[4]\n" + "fmla z25.h, z1.h, z7.h[5]\n" + "fmla z28.h, z1.h, z7.h[6]\n" + "fmla z31.h, z1.h, z7.h[7]\n" "bge 3b\n" "4:" // main loop skip "fmla z8.h, z2.h, z0.h[0]\n" @@ -170,36 +174,36 @@ void sve_interleaved_fp16_mla_8x3VL( "fmla z28.h, z4.h, z0.h[6]\n" "fmla z31.h, z4.h, z0.h[7]\n" "cbz x20, 5f\n" - "ld1rqh { z0.h }, p0/Z, [%x[Apanel]]\n" - "ld1h { z5.h }, p0/Z, [x22]\n" - "fmla z8.h, z5.h, z0.h[0]\n" - "ld1h { z6.h }, p0/Z, [x22, #1, MUL VL]\n" - "ld1h { z7.h }, p0/Z, [x22, #2, MUL VL]\n" - "fmla z11.h, z5.h, z0.h[1]\n" - "fmla z14.h, z5.h, z0.h[2]\n" - "fmla z17.h, z5.h, z0.h[3]\n" + "ld1rqh { z3.h }, p0/Z, [%x[Apanel]]\n" + "ld1h { z2.h }, p0/Z, [x22]\n" + "fmla z8.h, z2.h, z3.h[0]\n" + "ld1h { z1.h }, p0/Z, [x22, #1, MUL VL]\n" + "ld1h { z0.h }, p0/Z, [x22, #2, MUL VL]\n" + "fmla z11.h, z2.h, z3.h[1]\n" + "fmla z14.h, z2.h, z3.h[2]\n" + "fmla z17.h, z2.h, z3.h[3]\n" "add %x[Apanel], %x[Apanel], #0x10\n" - "fmla z20.h, z5.h, z0.h[4]\n" - "fmla z23.h, z5.h, z0.h[5]\n" + "fmla z20.h, z2.h, z3.h[4]\n" + "fmla z23.h, z2.h, z3.h[5]\n" "addvl x22, x22, #3\n" - "fmla z26.h, z5.h, z0.h[6]\n" - "fmla z29.h, z5.h, z0.h[7]\n" - "fmla z9.h, z6.h, z0.h[0]\n" - "fmla z12.h, z6.h, z0.h[1]\n" - "fmla z15.h, z6.h, z0.h[2]\n" - "fmla z18.h, z6.h, z0.h[3]\n" - "fmla z21.h, z6.h, z0.h[4]\n" - "fmla z24.h, z6.h, z0.h[5]\n" - "fmla z27.h, z6.h, z0.h[6]\n" - "fmla z30.h, z6.h, z0.h[7]\n" - "fmla z10.h, z7.h, z0.h[0]\n" - "fmla z13.h, z7.h, z0.h[1]\n" - "fmla z16.h, z7.h, z0.h[2]\n" - "fmla z19.h, z7.h, z0.h[3]\n" - "fmla z22.h, z7.h, z0.h[4]\n" - "fmla z25.h, z7.h, z0.h[5]\n" - "fmla z28.h, z7.h, z0.h[6]\n" - "fmla z31.h, z7.h, z0.h[7]\n" + "fmla z26.h, z2.h, z3.h[6]\n" + "fmla z29.h, z2.h, z3.h[7]\n" + "fmla z9.h, z1.h, z3.h[0]\n" + "fmla z12.h, z1.h, z3.h[1]\n" + "fmla z15.h, z1.h, z3.h[2]\n" + "fmla z18.h, z1.h, z3.h[3]\n" + "fmla z21.h, z1.h, z3.h[4]\n" + "fmla z24.h, z1.h, z3.h[5]\n" + "fmla z27.h, z1.h, z3.h[6]\n" + "fmla z30.h, z1.h, z3.h[7]\n" + "fmla z10.h, z0.h, z3.h[0]\n" + "fmla z13.h, z0.h, z3.h[1]\n" + "fmla z16.h, z0.h, z3.h[2]\n" + "fmla z19.h, z0.h, z3.h[3]\n" + "fmla z22.h, z0.h, z3.h[4]\n" + "fmla z25.h, z0.h, z3.h[5]\n" + "fmla z28.h, z0.h, z3.h[6]\n" + "fmla z31.h, z0.h, z3.h[7]\n" "5:" // multiply loop done "st1h { z8.h }, p0, [%x[Cpanel]]\n" "subs x23, x23, #0x1\n" |